AM64x MCU+ SDK  08.06.00
ECC : Error Correcting Code

Table of Contents

To increase functional and system reliability, the memories in many device modules and subsystems are protected by Error Correcting Code (ECC), which performs Single Error Correction (SEC) and Double Error Detection (DED). Detected errors are reported via ESM. Single bit errors are corrected, and double bit errors are detected. The ECC Aggregator is connected to these memory and interconnect components which have the ECC. The ECC aggregator provides access to control and monitor the ECC protected memories in a module or subsystem.

SDL provides support for ECC aggregator configuration. Each ECC aggregator instance can be independently configured through the same SDL API by passing a different instance. The safety manual also defines test-for-diagnostics for the various IPs with ECC/parity support. The SDL also provides the support for executing ECC aggregator self-tests, using the error injection feature of the ECC aggregator. The ECC aggregators should be configured at startup, after running BIST.

Features Supported

The SDL provides support for the ECC through:

  • ECC Configuration API
  • ECC self-test API
  • ECC error injection API
  • ECC static register readback API

  • ECC error status APIs

    The SDL ECC module requires a mapping of certain aggregator registers into the address space of the R5F Core. In these cases, the ECC module will use the DPL API SDL_DPL_addrTranslate() to get the address. The application must provide the mapped address through this call. This mapping is required for any ECC aggregator that is used which has an address which is not in the 32-bit address space. The mapping is expected to always be valid because it may be needed at runtime to get information about ECC errors that may be encountered.

There are over 40 ECC aggregators on the device each supporting multiple memories and interconnects.

Error Injection for Various RAM ID types

There are two types of ECC aggregator RAM IDs supported on the device (wrapper and interconnect). The wrapper types are used for memories where local computations are performed for particular processing cores in the device, and the interconnect types are utilized for interconnect bus signals between cores or to/from peripherals.

For wrapper RAM ID types, after injecting an error, the memory associated with that RAM ID needs to be accessed in order to trigger the error interrupt event. It is the application's responsibility to trigger the error event through memory access after injecting the error.

SysConfig Features

  • None

Features NOT Supported

  • None

Important Usage Guidelines

  • None

Example Usage of R5F ATCM0

The following shows an example of SDL R5F ECC API usage by the application for Error Injection Tests and Exception handling.

Include the below file to access the APIs

#include <sdl/sdl_ecc.h>
#include <sdl/sdl_exception.h>
#include <sdl/r5/v0/interrupt.h>
#include "ecc_main.h"

Below are the macros specifies the RAM address, ECC aggregator and ECC aggregator RAMID for inject the ECC error

#define SDL_EXAMPLE_ECC_RAM_ADDR (0x00000510u) // R5F ATCM0 RAM address
#define SDL_EXAMPLE_ECC_AGGR SDL_R5FSS0_CORE0_ECC_AGGR
#define SDL_EXAMPLE_ECC_RAM_ID SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_ATCM0_BANK0_RAM_ID

ESM callback function

This is the list of exception handle and the parameters

const SDL_R5ExptnHandlers ECC_Test_R5ExptnHandlers =
{
.udefExptnHandler = &SDL_EXCEPTION_undefInstructionExptnHandler,
.swiExptnHandler = &SDL_EXCEPTION_swIntrExptnHandler,
.pabtExptnHandler = &SDL_EXCEPTION_prefetchAbortExptnHandler,
.dabtExptnHandler = &SDL_EXCEPTION_dataAbortExptnHandler,
.irqExptnHandler = &SDL_EXCEPTION_irqExptnHandler,
.fiqExptnHandler = &SDL_EXCEPTION_fiqExptnHandler,
.udefExptnHandlerArgs = ((void *)0u),
.swiExptnHandlerArgs = ((void *)0u),
.pabtExptnHandlerArgs = ((void *)0u),
.dabtExptnHandlerArgs = ((void *)0u),
.irqExptnHandlerArgs = ((void *)0u),
};

Below are the functions used to print the which exception is occured

void ECC_Test_undefInstructionExptnCallback(void)
{
printf("\r\nUndefined Instruction exception\r\n");
}
void ECC_Test_swIntrExptnCallback(void)
{
printf("\r\nSoftware interrupt exception\r\n");
}
void ECC_Test_prefetchAbortExptnCallback(void)
{
printf("\r\nPrefetch Abort exception\r\n");
}
void ECC_Test_dataAbortExptnCallback(void)
{
printf("\r\nData Abort exception\r\n");
}
void ECC_Test_irqExptnCallback(void)
{
printf("\r\nIrq exception\r\n");
}
void ECC_Test_fiqExptnCallback(void)
{
printf("\r\nFiq exception\r\n");
}

Initilize Exception handler

void ECC_Test_exceptionInit(void)
{
SDL_EXCEPTION_CallbackFunctions_t exceptionCallbackFunctions =
{
.udefExptnCallback = ECC_Test_undefInstructionExptnCallback,
.swiExptnCallback = ECC_Test_swIntrExptnCallback,
.pabtExptnCallback = ECC_Test_prefetchAbortExptnCallback,
.dabtExptnCallback = ECC_Test_dataAbortExptnCallback,
.irqExptnCallback = ECC_Test_irqExptnCallback,
.fiqExptnCallback = ECC_Test_fiqExptnCallback,
};
/* Initialize SDL exception handler */
SDL_EXCEPTION_init(&exceptionCallbackFunctions);
/* Register SDL exception handler */
Intc_RegisterExptnHandlers(&ECC_Test_R5ExptnHandlers);
return;
}

This structure defines the elements of ECC Init configuration

static SDL_ECC_MemSubType ECC_Test_R5FSS0_CORE0_subMemTypeList[SDL_R5FSS0_CORE0_MAX_MEM_SECTIONS] =
{
SDL_EXAMPLE_ECC_RAM_ID,
};
static SDL_ECC_InitConfig_t ECC_Test_R5FSS0_CORE0_ECCInitConfig =
{
.numRams = SDL_R5FSS0_CORE0_MAX_MEM_SECTIONS,
.pMemSubTypeList = &(ECC_Test_R5FSS0_CORE0_subMemTypeList[0]),
};

Enabling the ECC module

SDL_ECC_UTILS_enableECCATCM();

Enabling the Event bus

SDL_UTILS_enable_event_bus();

Initialize ECC memory for the ECC aggregator

result = SDL_ECC_initMemory(SDL_EXAMPLE_ECC_AGGR, SDL_EXAMPLE_ECC_RAM_ID);

Initialize ECC parameters for single and double bit error injection

result = SDL_ECC_init(SDL_EXAMPLE_ECC_AGGR, &ECC_Test_R5FSS0_CORE0_ECCInitConfig);

Execute ECC R5F ATCM0 single bit inject test

int32_t ECC_Test_run_R5FSS0_CORE0_ATCM0_BANK0_1BitInjectTest(void)
{
SDL_ErrType_t result;
int32_t retVal=0;
SDL_ECC_InjectErrorConfig_t injectErrorConfig;
volatile uint32_t testLocationValue;
DebugP_log("\r\nR5FSS0 CORE0 ATCM0 BANK0 Single bit error inject: starting \r\n");
/* Note the address is relative to start of ram */
injectErrorConfig.pErrMem = (uint32_t *)(SDL_EXAMPLE_ECC_RAM_ADDR);
/* Run one shot test for R5FSS0 CORE0 ATCM0 BANK0 1 bit error */
injectErrorConfig.flipBitMask = 0x02;
result = SDL_ECC_injectError(SDL_EXAMPLE_ECC_AGGR,
SDL_EXAMPLE_ECC_RAM_ID,
SDL_INJECT_ECC_ERROR_FORCING_1BIT_ONCE,
&injectErrorConfig);
if (result != SDL_PASS ) {
retVal = -1;
} else {
/* Access the memory where injection is expected */
testLocationValue = injectErrorConfig.pErrMem[0];
DebugP_log("\r\nR5FSS0 CORE0 ATCM0 BANK0 Single bit error inject at pErrMem = 0x%p and the value of pErrMem is 0x%p :test complete\r\n",
injectErrorConfig.pErrMem, testLocationValue);
}
return retVal;
}

Execute ECC R5F ATCM0 double bit inject test

int32_t ECC_Test_run_R5FSS0_CORE0_ATCM0_BANK0_2BitInjectTest(void)
{
SDL_ErrType_t result;
int32_t retVal=0;
SDL_ECC_InjectErrorConfig_t injectErrorConfig;
volatile uint32_t testLocationValue;
DebugP_log("\r\nR5FSS0 CORE0 ATCM0 BANK0 Double bit error inject: starting \r\n");
/* Run one shot test for R5FSS0 CORE0 ATCM0 BANK0 2 bit error */
/* Note the address is relative to start of ram */
injectErrorConfig.pErrMem = (uint32_t *)(SDL_EXAMPLE_ECC_RAM_ADDR);
injectErrorConfig.flipBitMask = 0x30002;
result = SDL_ECC_injectError(SDL_EXAMPLE_ECC_AGGR,
SDL_EXAMPLE_ECC_RAM_ID,
SDL_INJECT_ECC_ERROR_FORCING_2BIT_ONCE,
&injectErrorConfig);
if (result != SDL_PASS ) {
retVal = -1;
} else {
/* Access the memory where injection is expected */
testLocationValue = injectErrorConfig.pErrMem[0];
DebugP_log("\r\nR5FSS0 CORE0 ATCM0 BANK0 Double bit error inject: pErrMem fixed location = 0x%p once test complete: the value of pErrMem is 0x%p\r\n",
injectErrorConfig.pErrMem, testLocationValue);
}
return retVal;
}

Example Usage of R5F BTCM

The following shows an example of SDL R5F ECC API usage by the application for Error Injection Tests and Exception handling.

Include the below file to access the APIs

#include <sdl/sdl_ecc.h>
#include <sdl/sdl_exception.h>
#include <sdl/r5/v0/interrupt.h>
#include "ecc_main.h"

Below are the macros specifies the RAM address, ECC aggregator and ECC aggregator RAMID for inject the ECC error

#if SDL_B0TCM0_BANK0
#define SDL_R5FSS0_CORE0_MAX_MEM_SECTIONS (1u)
#define SDL_EXAMPLE_ECC_RAM_ADDR (0x00080010u) /* R5F BTCM RAM address */
#define SDL_EXAMPLE_ECC_AGGR SDL_R5FSS0_CORE0_ECC_AGGR
#define SDL_EXAMPLE_ECC_RAM_ID SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B0TCM0_BANK0_RAM_ID
#endif
#if SDL_B0TCM0_BANK1
#define SDL_R5FSS0_CORE0_MAX_MEM_SECTIONS (1u)
#define SDL_EXAMPLE_ECC_RAM_ADDR (0x00081510u) /* R5F BTCM RAM address */
#define SDL_EXAMPLE_ECC_AGGR SDL_R5FSS0_CORE0_ECC_AGGR
#define SDL_EXAMPLE_ECC_RAM_ID SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B0TCM0_BANK1_RAM_ID
#endif
#if SDL_B1TCM0_BANK0
#define SDL_R5FSS0_CORE0_MAX_MEM_SECTIONS (1u)
#define SDL_EXAMPLE_ECC_RAM_ADDR (0x00082510u) /* R5F BTCM RAM address */
#define SDL_EXAMPLE_ECC_AGGR SDL_R5FSS0_CORE0_ECC_AGGR
#define SDL_EXAMPLE_ECC_RAM_ID SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B1TCM0_BANK0_RAM_ID
#endif
#if SDL_B1TCM0_BANK1
#define SDL_R5FSS0_CORE0_MAX_MEM_SECTIONS (1u)
#define SDL_EXAMPLE_ECC_RAM_ADDR (0x00083510u) /* R5F BTCM RAM address */
#define SDL_EXAMPLE_ECC_AGGR SDL_R5FSS0_CORE0_ECC_AGGR
#define SDL_EXAMPLE_ECC_RAM_ID SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B1TCM0_BANK1_RAM_ID
#endif

ESM callback function

This is the list of exception handle and the parameters

const SDL_R5ExptnHandlers ECC_Test_R5ExptnHandlers =
{
.udefExptnHandler = &SDL_EXCEPTION_undefInstructionExptnHandler,
.swiExptnHandler = &SDL_EXCEPTION_swIntrExptnHandler,
.pabtExptnHandler = &SDL_EXCEPTION_prefetchAbortExptnHandler,
.dabtExptnHandler = &SDL_EXCEPTION_dataAbortExptnHandler,
.irqExptnHandler = &SDL_EXCEPTION_irqExptnHandler,
.fiqExptnHandler = &SDL_EXCEPTION_fiqExptnHandler,
.udefExptnHandlerArgs = ((void *)0u),
.swiExptnHandlerArgs = ((void *)0u),
.pabtExptnHandlerArgs = ((void *)0u),
.dabtExptnHandlerArgs = ((void *)0u),
.irqExptnHandlerArgs = ((void *)0u),
};

Below are the functions used to print the which exception is occured

void ECC_Test_undefInstructionExptnCallback(void)
{
printf("\r\nUndefined Instruction exception\r\n");
}
void ECC_Test_swIntrExptnCallback(void)
{
printf("\r\nSoftware interrupt exception\r\n");
}
void ECC_Test_prefetchAbortExptnCallback(void)
{
printf("\r\nPrefetch Abort exception\r\n");
}
void ECC_Test_dataAbortExptnCallback(void)
{
printf("\r\nData Abort exception\r\n");
}
void ECC_Test_irqExptnCallback(void)
{
printf("\r\nIrq exception\r\n");
}
void ECC_Test_fiqExptnCallback(void)
{
printf("\r\nFiq exception\r\n");
}

Initilize Exception handler

void ECC_Test_exceptionInit(void)
{
SDL_EXCEPTION_CallbackFunctions_t exceptionCallbackFunctions =
{
.udefExptnCallback = ECC_Test_undefInstructionExptnCallback,
.swiExptnCallback = ECC_Test_swIntrExptnCallback,
.pabtExptnCallback = ECC_Test_prefetchAbortExptnCallback,
.dabtExptnCallback = ECC_Test_dataAbortExptnCallback,
.irqExptnCallback = ECC_Test_irqExptnCallback,
.fiqExptnCallback = ECC_Test_fiqExptnCallback,
};
/* Initialize SDL exception handler */
SDL_EXCEPTION_init(&exceptionCallbackFunctions);
/* Register SDL exception handler */
Intc_RegisterExptnHandlers(&ECC_Test_R5ExptnHandlers);
return;
}

This structure defines the elements of ECC Init configuration

static SDL_ECC_MemSubType ECC_Test_R5FSS0_CORE0_subMemTypeList[SDL_R5FSS0_CORE0_MAX_MEM_SECTIONS] =
{
SDL_EXAMPLE_ECC_RAM_ID,
};
static SDL_ECC_InitConfig_t ECC_Test_R5FSS0_CORE0_ECCInitConfig =
{
.numRams = SDL_R5FSS0_CORE0_MAX_MEM_SECTIONS,
.pMemSubTypeList = &(ECC_Test_R5FSS0_CORE0_subMemTypeList[0]),
};

Enabling the ECC module

#if (SDL_B0TCM0_BANK0) || (SDL_B0TCM0_BANK1)
/*Enabling the B0TCM ECC module*/
SDL_ECC_UTILS_enableECCB0TCM();
#endif
#if (SDL_B1TCM0_BANK0) || (SDL_B1TCM0_BANK1)
/*Enabling the B0TCM ECC module*/
SDL_ECC_UTILS_enableECCB1TCM();
#endif

Enabling the Event bus

SDL_UTILS_enable_event_bus();

Initialize ECC memory for the ECC aggregator

result = SDL_ECC_initMemory(SDL_EXAMPLE_ECC_AGGR, SDL_EXAMPLE_ECC_RAM_ID);

Initialize ECC parameters for single and double bit error injection

result = SDL_ECC_init(SDL_EXAMPLE_ECC_AGGR, &ECC_Test_R5FSS0_CORE0_ECCInitConfig);

Execute ECC R5F BTCM single bit inject test

int32_t ECC_Test_run_R5FSS0_CORE0_BTCM_1BitInjectTest(void)
{
SDL_ErrType_t result;
int32_t retVal=0;
SDL_ECC_InjectErrorConfig_t injectErrorConfig;
volatile uint32_t testLocationValue;
DebugP_log("\r\nR5FSS0 CORE0 BTCM Single bit error inject: starting \r\n");
/* Note the address is relative to start of ram */
injectErrorConfig.pErrMem = (uint32_t *)(SDL_EXAMPLE_ECC_RAM_ADDR);
/* Run one shot test for R5FSS0 CORE0 BTCM 1 bit error */
injectErrorConfig.flipBitMask = 0x02;
result = SDL_ECC_injectError(SDL_EXAMPLE_ECC_AGGR,
SDL_EXAMPLE_ECC_RAM_ID,
SDL_INJECT_ECC_ERROR_FORCING_1BIT_ONCE,
&injectErrorConfig);
if (result != SDL_PASS ) {
retVal = -1;
} else {
/* Access the memory where injection is expected */
testLocationValue = injectErrorConfig.pErrMem[0];
DebugP_log("\r\nR5FSS0 CORE0 BTCM Single bit error inject at pErrMem = 0x%p and the value of pErrMem is 0x%p :test complete\r\n",
injectErrorConfig.pErrMem, testLocationValue);
}
return retVal;
}

Execute ECC R5F BTCM double bit inject test

int32_t ECC_Test_run_R5FSS0_CORE0_BTCM_2BitInjectTest(void)
{
SDL_ErrType_t result;
int32_t retVal=0;
SDL_ECC_InjectErrorConfig_t injectErrorConfig;
volatile uint32_t testLocationValue;
DebugP_log("\r\nR5FSS0 CORE0 BTCM Double bit error inject: starting \r\n");
/* Run one shot test for R5FSS0 CORE0 BTCM 2 bit error */
/* Note the address is relative to start of ram */
injectErrorConfig.pErrMem = (uint32_t *)(SDL_EXAMPLE_ECC_RAM_ADDR);
injectErrorConfig.flipBitMask = 0x03;
result = SDL_ECC_injectError(SDL_EXAMPLE_ECC_AGGR,
SDL_EXAMPLE_ECC_RAM_ID,
SDL_INJECT_ECC_ERROR_FORCING_2BIT_ONCE,
&injectErrorConfig);
if (result != SDL_PASS ) {
retVal = -1;
} else {
/* Access the memory where injection is expected */
testLocationValue = injectErrorConfig.pErrMem[0];
DebugP_log("\r\nR5FSS0 CORE0 BTCM Double bit error inject: pErrMem fixed location = 0x%p once test complete: the value of pErrMem is 0x%p\r\n",
injectErrorConfig.pErrMem, testLocationValue);
}
return retVal;
}

Example Usage of MSS L2

The following shows an example of SDL MSS L2 API usage by the application for Error Injection Tests and Exception handling.

Include the below file to access the APIs

#include <sdl/sdl_ecc.h>
#include "ecc_main.h"

Below are the macros specifies the RAM address, ECC aggregator and ECC aggregator RAMID for inject the ECC error

ESM callback function

This structure defines the elements of ECC Init configuration

static SDL_ECC_MemSubType ECC_Test_MSS_L2_subMemTypeList[SDL_MSS_L2_MAX_MEM_SECTIONS] =
{
SDL_EXAMPLE_ECC_RAM_ID,
};
static SDL_ECC_InitConfig_t ECC_Test_MSS_L2_ECCInitConfig =
{
.numRams = SDL_MSS_L2_MAX_MEM_SECTIONS,
.pMemSubTypeList = &(ECC_Test_MSS_L2_subMemTypeList[0]),
};

Event BitMap for ECC ESM callback for MSS

Initialization of MSS L2 memory

Clearing any old interrupt presented

SDL_REG32_WR(SDL_ECC_AGGR_ERROR_STATUS1_ADDR, 0xF0Fu);

Initialize ECC memory for the ECC aggregator

result = SDL_ECC_initMemory(SDL_EXAMPLE_ECC_AGGR, SDL_EXAMPLE_ECC_RAM_ID);

Initialize ECC parameters for single and double bit error injection

result = SDL_ECC_init(SDL_EXAMPLE_ECC_AGGR, &ECC_Test_MSS_ECCInitConfig);

Execute ECC MSS L2 single bit inject test

int32_t ECC_Test_run_MSS_L2RAMB_1BitInjectTest(void)
{
SDL_ErrType_t result;
int32_t retVal=0;
SDL_ECC_InjectErrorConfig_t injectErrorConfig;
volatile uint32_t testLocationValue;
DebugP_log("\r\nMSS L2 RAMB Single bit error inject: starting \r\n");
/* Note the address is relative to start of ram */
injectErrorConfig.pErrMem = (uint32_t *)(SDL_EXAMPLE_ECC_RAM_ADDR);
/* Run one shot test for MSS L2 RAMB 1 bit error */
injectErrorConfig.flipBitMask = 0x002;
result = SDL_ECC_injectError(SDL_EXAMPLE_ECC_AGGR,
SDL_EXAMPLE_ECC_RAM_ID,
SDL_INJECT_ECC_ERROR_FORCING_1BIT_ONCE,
&injectErrorConfig);
if (result != SDL_PASS ) {
retVal = -1;
} else {
/* Access the memory where injection is expected */
testLocationValue = injectErrorConfig.pErrMem[0];
DebugP_log("\r\nMSS L2 RAMB Single bit error inject at pErrMem = 0x%p and the value of pErrMem is 0x%p :test complete\r\n",
injectErrorConfig.pErrMem, testLocationValue);
}
return retVal;
}

Initialization of MSS L2 memory

SDL_REG32_WR(SDL_MSS_L2_MEM_INIT_ADDR, SDL_ECC_MSS_L2_BANK_MEM_INIT);
while(SDL_REG32_RD(SDL_MSS_L2_MEM_INIT_DONE_ADDR)!=SDL_ECC_MSS_L2_BANK_MEM_INIT);
/* Clear Done memory after MEM init*/
SDL_REG32_WR(SDL_MSS_L2_MEM_INIT_DONE_ADDR, SDL_ECC_MSS_L2_BANK_MEM_INIT);

Clearing any old interrupt presented

SDL_REG32_WR(SDL_ECC_AGGR_ERROR_STATUS1_ADDR, 0xF0Fu);

Execute ECC MSS L2 double bit inject test

int32_t ECC_Test_run_MSS_L2RAMB_2BitInjectTest(void)
{
SDL_ErrType_t result;
int32_t retVal=0;
SDL_ECC_InjectErrorConfig_t injectErrorConfig;
volatile uint32_t testLocationValue;
DebugP_log("\r\nMSS L2 RAMB Double bit error inject: starting \r\n");
/* Run one shot test for MSS L2 RAMB 2 bit error */
/* Note the address is relative to start of ram */
injectErrorConfig.pErrMem = (uint32_t *)(SDL_EXAMPLE_ECC_RAM_ADDR);
injectErrorConfig.flipBitMask = 0x30002;
result = SDL_ECC_injectError(SDL_EXAMPLE_ECC_AGGR,
SDL_EXAMPLE_ECC_RAM_ID,
SDL_INJECT_ECC_ERROR_FORCING_2BIT_ONCE,
&injectErrorConfig);
/* Access the memory where injection is expected */
testLocationValue = injectErrorConfig.pErrMem[0];
if (result != SDL_PASS ) {
retVal = -1;
} else {
DebugP_log("\r\nMSS L2 RAMB Double bit error inject: pErrMem fixed location = 0x%p once test complete: the value of pErrMem is 0x%p\r\n",
injectErrorConfig.pErrMem, testLocationValue);
}
return retVal;
}

Example Usage of MSS TPTC

The following shows an example of SDL MSS TPTC API usage by the application for Error Injection Tests and Exception handling.

Include the below file to access the APIs

#include <drivers/edma.h>
#include "ti_drivers_config.h"
#include "ti_drivers_open_close.h"
#include "ti_board_open_close.h"
#include <sdl/sdl_ecc.h>
#include "ecc_main.h"

Below are the macros specifies the ECC aggregator and ECC aggregator RAMID for inject the ECC error

ESM callback function

This structure defines the elements of ECC Init configuration

static SDL_ECC_MemSubType ECC_Test_MSS_subMemTypeList[SDL_MSS_MAX_MEM_SECTIONS] =
{
SDL_EXAMPLE_ECC_RAM_ID,
};
static SDL_ECC_InitConfig_t ECC_Test_MSS_ECCInitConfig =
{
.numRams = SDL_MSS_MAX_MEM_SECTIONS,
.pMemSubTypeList = &(ECC_Test_MSS_subMemTypeList[0]),
};

Event BitMap for ECC ESM callback for MSS

Initialization of EDMA and ECC injection

/* EDMA transfer with ECC single bit injection*/
testResult = edma_interrupt_transfer(CONFIG_EDMA0, SDL_ECC_SEC, 0u, EDMA_MSS_TPCC_A_EVT_FREE_0);

Initialize EDMA

EDMA_Init();
DebugP_log("\r\n[EDMA] Interrupt Transfer Test Started...\r\n");
baseAddr = EDMA_getBaseAddr(gEdmaHandle[edmaConfigNum]);
regionId = EDMA_getRegionId(gEdmaHandle[edmaConfigNum]);
dmaCh = channelEvent;
status = EDMA_allocDmaChannel(gEdmaHandle[edmaConfigNum], &dmaCh);
tcc = channelEvent;
status = EDMA_allocTcc(gEdmaHandle[edmaConfigNum], &tcc);
param = channelEvent;
status = EDMA_allocParam(gEdmaHandle[edmaConfigNum], &param);

Initialize ECC memory for the ECC aggregator

result = SDL_ECC_initMemory(SDL_EXAMPLE_ECC_AGGR, SDL_EXAMPLE_ECC_RAM_ID);

Initialize ECC parameters for single and double bit error injection

result = SDL_ECC_init(SDL_EXAMPLE_ECC_AGGR, &ECC_Test_MSS_ECCInitConfig);

Execute ECC MSS TPTC single bit inject test

int32_t ECC_Test_run_MSS_TPTC_A0_1Bit_InjectTest(void)
{
SDL_ErrType_t result;
int32_t retVal=0;
SDL_ECC_InjectErrorConfig_t injectErrorConfig;
DebugP_log("\n MSS TPTC_A0 Single bit error inject: test starting");
injectErrorConfig.pErrMem = (uint32_t *)(0x0u);
/* Run one shot test for MSS TPTC_A0 1 bit error */
injectErrorConfig.flipBitMask = 0x02;
result = SDL_ECC_injectError(SDL_EXAMPLE_ECC_AGGR,
SDL_EXAMPLE_ECC_RAM_ID,
SDL_INJECT_ECC_ERROR_FORCING_1BIT_ONCE,
&injectErrorConfig);
if (result != SDL_PASS ) {
DebugP_log("\n MSS TPTC_A0 Single bit error inject at pErrMem 0x%p test failed",
injectErrorConfig.pErrMem);
retVal = -1;
} else {
DebugP_log("\n MSS TPTC_A0 Single bit error inject at pErrMem 0x%p",
injectErrorConfig.pErrMem);
}
return retVal;
}

Execute ECC MSS TPTC double bit inject test

int32_t ECC_Test_run_MSS_TPTC_A0_2Bit_InjectTest(void)
{
SDL_ErrType_t result;
int32_t retVal=0;
SDL_ECC_InjectErrorConfig_t injectErrorConfig;
DebugP_log("\n MSS TPTC_A0 Double bit error inject: starting");
/* Run one shot test for MSS TPTC_A0 2 bit error */
/* Note the address is relative to start of ram */
injectErrorConfig.pErrMem = (uint32_t *)(0x0u);
injectErrorConfig.flipBitMask = 0x03;
result = SDL_ECC_injectError(SDL_EXAMPLE_ECC_AGGR,
SDL_EXAMPLE_ECC_RAM_ID,
SDL_INJECT_ECC_ERROR_FORCING_2BIT_ONCE,
&injectErrorConfig);
if (result != SDL_PASS ) {
DebugP_log("\n MSS TPTC_A0 Double bit error inject: at pErrMem 0x%p: fixed location once test failed",
injectErrorConfig.pErrMem);
retVal = -1;
} else {
DebugP_log("\n MSS TPTC_A0 Double bit error inject at pErrMem 0x%p ",
injectErrorConfig.pErrMem);
}
return retVal;
}

Initialize the source address with a pattern and initialize dst address with zero/another pattern (optional)

srcBuffPtr = (uint8_t *) gEdmaTestSrcBuff;
dstBuffPtr = (uint8_t *) gEdmaTestDstBuff;
for(loopCnt = 0U; loopCnt < EDMA_TEST_BUFFER_SIZE; loopCnt++)
{
srcBuffPtr[loopCnt] = (uint8_t)loopCnt;
dstBuffPtr[loopCnt] = 0;
}
CacheP_wb((void *)srcBuffPtr, EDMA_TEST_BUFFER_SIZE, CacheP_TYPE_ALL);
CacheP_wb((void *)dstBuffPtr, EDMA_TEST_BUFFER_SIZE, CacheP_TYPE_ALL);
/* Request channel */
EDMA_configureChannelRegion(baseAddr, regionId, EDMA_CHANNEL_TYPE_DMA,
dmaCh, tcc, param, queueType);
/* Program Param Set */
EDMA_ccPaRAMEntry_init(&edmaParam);
edmaParam.srcAddr = (uint32_t) SOC_virtToPhy(srcBuffPtr);
edmaParam.destAddr = (uint32_t) SOC_virtToPhy(dstBuffPtr);
edmaParam.aCnt = (uint16_t) EDMA_TEST_A_COUNT;
edmaParam.bCnt = (uint16_t) EDMA_TEST_B_COUNT;
edmaParam.cCnt = (uint16_t) EDMA_TEST_C_COUNT;
edmaParam.bCntReload = (uint16_t) EDMA_TEST_B_COUNT;
edmaParam.srcBIdx = (int16_t) EDMA_PARAM_BIDX(EDMA_TEST_A_COUNT);
edmaParam.destBIdx = (int16_t) EDMA_PARAM_BIDX(EDMA_TEST_A_COUNT);
edmaParam.srcCIdx = (int16_t) EDMA_TEST_A_COUNT;
edmaParam.destCIdx = (int16_t) EDMA_TEST_A_COUNT;
edmaParam.linkAddr = 0xFFFFU;
edmaParam.srcBIdxExt = (int8_t) EDMA_PARAM_BIDX_EXT(EDMA_TEST_A_COUNT);
edmaParam.destBIdxExt = (int8_t) EDMA_PARAM_BIDX_EXT(EDMA_TEST_A_COUNT);
edmaParam.opt |=
(EDMA_OPT_TCINTEN_MASK | EDMA_OPT_ITCINTEN_MASK |
((((uint32_t)tcc) << EDMA_OPT_TCC_SHIFT) & EDMA_OPT_TCC_MASK));
EDMA_setPaRAM(baseAddr, param, &edmaParam);
status = SemaphoreP_constructBinary(&gEdmaTestDoneSem, 0);
/* Register interrupt */
intrObj.tccNum = tcc;
intrObj.cbFxn = &EDMA_regionIsrFxn;
intrObj.appData = (void *) &gEdmaTestDoneSem;
status = EDMA_registerIntr(gEdmaHandle[edmaConfigNum], &intrObj);
/*
* Transfer is done in A sync mode
* Number of triggers required are B_COUNT * C_COUNT
*/
for(loopCnt = 0; loopCnt < (EDMA_TEST_B_COUNT * EDMA_TEST_C_COUNT); loopCnt++)
{
EDMA_enableTransferRegion(
baseAddr, regionId, dmaCh, EDMA_TRIG_MODE_MANUAL);
SemaphoreP_pend(&gEdmaTestDoneSem, SystemP_WAIT_FOREVER);
}
/* Invalidate destination buffer and compare with src buffer */
CacheP_inv((void *)dstBuffPtr, EDMA_TEST_BUFFER_SIZE, CacheP_TYPE_ALL);
for(loopCnt = 0; loopCnt < EDMA_TEST_BUFFER_SIZE; loopCnt++)
{
if(srcBuffPtr[loopCnt] != dstBuffPtr[loopCnt])
{
DebugP_log("Error matching value at src and dst address %d\r\n", loopCnt);
status = SystemP_FAILURE;
result = SDL_EFAIL;
break;
}
}
status = EDMA_unregisterIntr(gEdmaHandle[edmaConfigNum], &intrObj);
SemaphoreP_destruct(&gEdmaTestDoneSem);
/* Free channel */
EDMA_freeChannelRegion(baseAddr, regionId, EDMA_CHANNEL_TYPE_DMA,
dmaCh, EDMA_TRIG_MODE_MANUAL, tcc, EDMA_TEST_EVT_QUEUE_NO);
/* Free the EDMA resources managed by driver. */
status = EDMA_freeDmaChannel(gEdmaHandle[edmaConfigNum], &dmaCh);
status = EDMA_freeTcc(gEdmaHandle[edmaConfigNum], &tcc);
status = EDMA_freeParam(gEdmaHandle[edmaConfigNum], &param);
if(status == SystemP_SUCCESS)
{
DebugP_log("\r\n[EDMA] Interrupt Transfer Test Completed!!\r\n");
if(esmError == TRUE)
{
DebugP_log("\r\nAll tests have passed!!\r\n");
esmError = false;
}
else
{
result = SDL_EFAIL;
DebugP_log("\r\nESM interrupt is not occurred.... Test is failed!!\r\n");
}
}
else
{
result = SDL_EFAIL;
DebugP_log("\r\nSome tests have failed!!\r\n");
}
EDMA_Deinit();

Example Usage of MCAN

Include the below file to access the APIs

#include "ecc_main.h"

Below are the macros specifies the RAM address, ECC aggregator and ECC aggregator RAMID for inject the ECC error

This structure defines the elements of ECC Init configuration

static SDL_ECC_MemSubType ECC_Test_MCANA_subMemTypeList[SDL_MCANA_MAX_MEM_SECTIONS] =
{
SDL_EXAMPLE_ECC_RAM_ID,
};
static SDL_ECC_InitConfig_t ECC_Test_MCANA_ECCInitConfig =
{
.numRams = SDL_MCANA_MAX_MEM_SECTIONS,
.pMemSubTypeList = &(ECC_Test_MCANA_subMemTypeList[0]),
};

ESM callback function

Event BitMap for ECC ESM callback for MCAN

Initialize ECC memory for the ECC aggregator

result = SDL_ECC_initMemory(SDL_EXAMPLE_ECC_AGGR, SDL_EXAMPLE_ECC_RAM_ID);

Initialize ECC parameters for single and double bit error injection

result = SDL_ECC_init(SDL_EXAMPLE_ECC_AGGR, &ECC_Test_MCANA_ECCInitConfig);

Write some data to the RAM memory before injecting

for(i=1;i<=num_of_iterations;i++){
wr_data = (i)<<24 | (i)<<16 | (i)<<8 | i;
SDL_REG32_WR(addr+i*16, wr_data);
}

Execute ECC MCAN single bit inject test

int32_t ECC_Test_run_MCANA_1BitInjectTest(void)
{
SDL_ErrType_t result;
int32_t retVal=0;
SDL_ECC_InjectErrorConfig_t injectErrorConfig;
volatile uint32_t testLocationValue;
DebugP_log("\r\nMCANA Single bit error inject: starting \r\n");
/* Note the address is relative to start of ram */
injectErrorConfig.pErrMem = (uint32_t *)(SDL_EXAMPLE_ECC_RAM_ADDR);
/* Run one shot test for MCANA 1 bit error */
injectErrorConfig.flipBitMask = 0x002;
result = SDL_ECC_injectError(SDL_EXAMPLE_ECC_AGGR,
SDL_EXAMPLE_ECC_RAM_ID,
SDL_INJECT_ECC_ERROR_FORCING_1BIT_ONCE,
&injectErrorConfig);
if (result != SDL_PASS ) {
retVal = -1;
} else {
/* Access the memory where injection is expected */
testLocationValue = injectErrorConfig.pErrMem[0];
DebugP_log("\r\nMCANA Single bit error inject at pErrMem = 0x%p and the value of pErrMem is 0x%p :test complete\r\n",
injectErrorConfig.pErrMem, testLocationValue);
}
return retVal;
}

Read data from the RAM memory after injecting

for(i=1;i<=num_of_iterations;i++){
rd_data = SDL_REG32_RD(addr+i*16);
DebugP_log("\r\nRead data = 0x%p\r\n",rd_data);
}

Write some data to the RAM memory before injecting

for(i=1;i<=num_of_iterations;i++){
wr_data = (i)<<24 | (i)<<16 | (i)<<8 | i;
SDL_REG32_WR(addr+i*16, wr_data);
}

Execute ECC MCAN double bit inject test

int32_t ECC_Test_run_MCANA_2BitInjectTest(void)
{
SDL_ErrType_t result;
int32_t retVal=0;
SDL_ECC_InjectErrorConfig_t injectErrorConfig;
volatile uint32_t testLocationValue;
DebugP_log("\r\nMCANA double bit error inject: starting \r\n");
/* Run one shot test for MCANA 2 bit error */
/* Note the address is relative to start of ram */
injectErrorConfig.pErrMem = (uint32_t *)(SDL_EXAMPLE_ECC_RAM_ADDR);
injectErrorConfig.flipBitMask = 0x03;
result = SDL_ECC_injectError(SDL_EXAMPLE_ECC_AGGR,
SDL_EXAMPLE_ECC_RAM_ID,
SDL_INJECT_ECC_ERROR_FORCING_2BIT_ONCE,
&injectErrorConfig);
/* Access the memory where injection is expected */
testLocationValue = injectErrorConfig.pErrMem[0];
if (result != SDL_PASS ) {
retVal = -1;
} else {
DebugP_log("\r\nMCANA Double bit error inject: pErrMem fixed location = 0x%p once test complete: the value of pErrMem is 0x%p\r\n",
injectErrorConfig.pErrMem, testLocationValue);
}
return retVal;
}

Read data from the RAM memory after injecting

for(i=1;i<=num_of_iterations;i++){
rd_data = SDL_REG32_RD(addr+i*16);
DebugP_log("\r\nRead data = 0x%p\r\n",rd_data);
}

Example Usage of TCM Parity

Include the below file to access the APIs

#include "parity_main.h"

Below are the macros specifies the values need to set for TCM parity Error forcing

ESM callback function

Event BitMap for ESM callback for TCM Parity

Execute TCM Parity Error injection for B0TCM0 for R5FSS0 core 0

Example Usage of DMA Parity

Include the below file to access the APIs

#include "parity_main.h"

ESM callback function

Event BitMap for ESM callback for TCM Parity

Execute TPCC Parity Error injection

API

APIs for SDL ECC (ECC_AGGR)

SDL_ECC_InitConfig_t
Definition: sdl_ecc.h:294
SDL_ECC_InitConfig_t::numRams
uint32_t numRams
Definition: sdl_ecc.h:295
SDL_R5ExptnHandlers
Structure containing the Exception Handlers. If application does not want register an exception handl...
Definition: sdl_interrupt.h:111
SOC_virtToPhy
uint64_t SOC_virtToPhy(void *virtAddr)
SOC Virtual (CPU) to Physical address translation function.
SDL_ECC_initMemory
int32_t SDL_ECC_initMemory(SDL_ECC_MemType eccMemType, SDL_ECC_MemSubType memSubType)
Initializes Memory to be ready for ECC error detection. Assumes ECC is already enabled.
SDL_ECC_injectError
int32_t SDL_ECC_injectError(SDL_ECC_MemType eccMemType, SDL_ECC_MemSubType memSubType, SDL_ECC_InjectErrorType errorType, const SDL_ECC_InjectErrorConfig_t *pECCErrorConfig)
Injects ECC error at specified location Assumes ECC is already enabled.
SDL_EXCEPTION_swIntrExptnHandler
void SDL_EXCEPTION_swIntrExptnHandler(void *param)
SW Interrupt Exception Handler.
SDL_ECC_MemSubType
uint32_t SDL_ECC_MemSubType
This enumerator indicate ECC memory Sub Type.
Definition: sdl_ecc.h:280
SDL_EXCEPTION_undefInstructionExptnHandler
void SDL_EXCEPTION_undefInstructionExptnHandler(void *param)
Undefined Instruction Exception Handler.
SDL_EXCEPTION_prefetchAbortExptnHandler
void SDL_EXCEPTION_prefetchAbortExptnHandler(void *param)
Prefetch Abort Exception Handler.
Intc_RegisterExptnHandlers
void Intc_RegisterExptnHandlers(const SDL_R5ExptnHandlers *handlers)
This function registers handlers for various exceptions.
SystemP_WAIT_FOREVER
#define SystemP_WAIT_FOREVER
Value to use when needing a timeout of infinity or wait forver until resource is available.
Definition: SystemP.h:83
SDL_ECC_UTILS_enableECCB0TCM
void SDL_ECC_UTILS_enableECCB0TCM(void)
SDL_REG32_WR
#define SDL_REG32_WR(p, v)
This macro writes a 32-bit value to a hardware register.
Definition: sdlr.h:127
addr
uint64_t addr
Definition: csl_udmap_tr.h:3
DebugP_log
#define DebugP_log(format,...)
Function to log a string to the enabled console.
Definition: DebugP.h:225
SDL_ECC_InjectErrorConfig_t
Definition: sdl_ecc.h:307
SDL_ECC_UTILS_enableECCATCM
void SDL_ECC_UTILS_enableECCATCM(void)
SDL_ECC_InjectErrorConfig_t::pErrMem
uint32_t * pErrMem
Definition: sdl_ecc.h:308
SemaphoreP_destruct
void SemaphoreP_destruct(SemaphoreP_Object *obj)
Cleanup, delete, destruct a semaphore object.
CacheP_inv
void CacheP_inv(void *addr, uint32_t size, uint32_t type)
Cache invalidate for a specified region.
SDL_EXCEPTION_irqExptnHandler
void SDL_EXCEPTION_irqExptnHandler(void *param)
IRQ Exception Handler.
SystemP_SUCCESS
#define SystemP_SUCCESS
Return status when the API execution was successful.
Definition: SystemP.h:56
SDL_ECC_InjectErrorConfig_t::flipBitMask
uint32_t flipBitMask
Definition: sdl_ecc.h:310
sdl_exception.h
Header file contains enumerations, structure definitions and function declarations for SDL EXCEPTION ...
SDL_EXCEPTION_init
void SDL_EXCEPTION_init(const SDL_EXCEPTION_CallbackFunctions_t *callbackFunctions)
Initialise Exception module.
SDL_EXCEPTION_CallbackFunctions_t
Structure of call back functions for various exception events.
Definition: sdl_exception.h:74
sdl_ecc.h
Header file contains enumerations, structure definitions and function.
SystemP_FAILURE
#define SystemP_FAILURE
Return status when the API execution was not successful due to a failure.
Definition: SystemP.h:61
SDL_INJECT_ECC_ERROR_FORCING_2BIT_ONCE
@ SDL_INJECT_ECC_ERROR_FORCING_2BIT_ONCE
Definition: sdl_ecc.h:92
CacheP_TYPE_ALL
#define CacheP_TYPE_ALL
Definition: CacheP.h:78
SDL_REG32_RD
#define SDL_REG32_RD(p)
This macro reads a 32-bit value from a hardware register and returns the value.
Definition: sdlr.h:118
SDL_UTILS_enable_event_bus
void SDL_UTILS_enable_event_bus(void)
SDL_R5ExptnHandlers::udefExptnHandler
exptnHandlerPtr udefExptnHandler
Definition: sdl_interrupt.h:112
SDL_ECC_init
int32_t SDL_ECC_init(SDL_ECC_MemType eccMemType, const SDL_ECC_InitConfig_t *pECCInitConfig)
Initializes ECC module for ECC detection.
SemaphoreP_constructBinary
int32_t SemaphoreP_constructBinary(SemaphoreP_Object *obj, uint32_t initValue)
Create a binary semaphore object.
CacheP_wb
void CacheP_wb(void *addr, uint32_t size, uint32_t type)
Cache writeback for a specified region.
SDL_ECC_UTILS_enableECCB1TCM
void SDL_ECC_UTILS_enableECCB1TCM(void)
SDL_INJECT_ECC_ERROR_FORCING_1BIT_ONCE
@ SDL_INJECT_ECC_ERROR_FORCING_1BIT_ONCE
Definition: sdl_ecc.h:90
SDL_EXCEPTION_fiqExptnHandler
void SDL_EXCEPTION_fiqExptnHandler(void *param)
FIQ Exception Handler.
SDL_EXCEPTION_dataAbortExptnHandler
void SDL_EXCEPTION_dataAbortExptnHandler(void *param)
Data Abort Exception Handler.
SemaphoreP_pend
int32_t SemaphoreP_pend(SemaphoreP_Object *obj, uint32_t timeToWaitInTicks)
Pend on a semaphore object or lock a mutex.
SDL_EXCEPTION_CallbackFunctions_t::udefExptnCallback
SDL_EXCEPTION_Callback_t udefExptnCallback
Definition: sdl_exception.h:75