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AM64x MCU+ SDK
08.05.00
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51 #ifndef SOC_TISCI_DEVICES_H
52 #define SOC_TISCI_DEVICES_H
60 #define TISCI_DEV_ADC0 0
61 #define TISCI_DEV_CMP_EVENT_INTROUTER0 1
62 #define TISCI_DEV_DBGSUSPENDROUTER0 2
63 #define TISCI_DEV_MAIN_GPIOMUX_INTROUTER0 3
64 #define TISCI_DEV_MCU_MCU_GPIOMUX_INTROUTER0 5
65 #define TISCI_DEV_TIMESYNC_EVENT_INTROUTER0 6
66 #define TISCI_DEV_MCU_M4FSS0 7
67 #define TISCI_DEV_MCU_M4FSS0_CBASS_0 8
68 #define TISCI_DEV_MCU_M4FSS0_CORE0 9
69 #define TISCI_DEV_CPSW0 13
70 #define TISCI_DEV_CPT2_AGGR0 14
71 #define TISCI_DEV_STM0 15
72 #define TISCI_DEV_DCC0 16
73 #define TISCI_DEV_DCC1 17
74 #define TISCI_DEV_DCC2 18
75 #define TISCI_DEV_DCC3 19
76 #define TISCI_DEV_DCC4 20
77 #define TISCI_DEV_DCC5 21
78 #define TISCI_DEV_DMSC0 22
79 #define TISCI_DEV_MCU_DCC0 23
80 #define TISCI_DEV_DEBUGSS_WRAP0 24
81 #define TISCI_DEV_DMASS0 25
82 #define TISCI_DEV_DMASS0_BCDMA_0 26
83 #define TISCI_DEV_DMASS0_CBASS_0 27
84 #define TISCI_DEV_DMASS0_INTAGGR_0 28
85 #define TISCI_DEV_DMASS0_IPCSS_0 29
86 #define TISCI_DEV_DMASS0_PKTDMA_0 30
87 #define TISCI_DEV_DMASS0_RINGACC_0 33
88 #define TISCI_DEV_MCU_TIMER0 35
89 #define TISCI_DEV_TIMER0 36
90 #define TISCI_DEV_TIMER1 37
91 #define TISCI_DEV_TIMER2 38
92 #define TISCI_DEV_TIMER3 39
93 #define TISCI_DEV_TIMER4 40
94 #define TISCI_DEV_TIMER5 41
95 #define TISCI_DEV_TIMER6 42
96 #define TISCI_DEV_TIMER7 43
97 #define TISCI_DEV_TIMER8 44
98 #define TISCI_DEV_TIMER9 45
99 #define TISCI_DEV_TIMER10 46
100 #define TISCI_DEV_TIMER11 47
101 #define TISCI_DEV_MCU_TIMER1 48
102 #define TISCI_DEV_MCU_TIMER2 49
103 #define TISCI_DEV_MCU_TIMER3 50
104 #define TISCI_DEV_ECAP0 51
105 #define TISCI_DEV_ECAP1 52
106 #define TISCI_DEV_ECAP2 53
107 #define TISCI_DEV_ELM0 54
108 #define TISCI_DEV_EMIF_DATA_0_VD 55
109 #define TISCI_DEV_MMCSD0 57
110 #define TISCI_DEV_MMCSD1 58
111 #define TISCI_DEV_EQEP0 59
112 #define TISCI_DEV_EQEP1 60
113 #define TISCI_DEV_GTC0 61
114 #define TISCI_DEV_EQEP2 62
115 #define TISCI_DEV_ESM0 63
116 #define TISCI_DEV_MCU_ESM0 64
117 #define TISCI_DEV_FSIRX0 65
118 #define TISCI_DEV_FSIRX1 66
119 #define TISCI_DEV_FSIRX2 67
120 #define TISCI_DEV_FSIRX3 68
121 #define TISCI_DEV_FSIRX4 69
122 #define TISCI_DEV_FSIRX5 70
123 #define TISCI_DEV_FSITX0 71
124 #define TISCI_DEV_FSITX1 72
125 #define TISCI_DEV_FSS0 73
126 #define TISCI_DEV_FSS0_FSAS_0 74
127 #define TISCI_DEV_FSS0_OSPI_0 75
128 #define TISCI_DEV_GICSS0 76
129 #define TISCI_DEV_GPIO0 77
130 #define TISCI_DEV_GPIO1 78
131 #define TISCI_DEV_MCU_GPIO0 79
132 #define TISCI_DEV_GPMC0 80
133 #define TISCI_DEV_PRU_ICSSG0 81
134 #define TISCI_DEV_PRU_ICSSG1 82
135 #define TISCI_DEV_LED0 83
136 #define TISCI_DEV_CPTS0 84
137 #define TISCI_DEV_DDPA0 85
138 #define TISCI_DEV_EPWM0 86
139 #define TISCI_DEV_EPWM1 87
140 #define TISCI_DEV_EPWM2 88
141 #define TISCI_DEV_EPWM3 89
142 #define TISCI_DEV_EPWM4 90
143 #define TISCI_DEV_EPWM5 91
144 #define TISCI_DEV_EPWM6 92
145 #define TISCI_DEV_EPWM7 93
146 #define TISCI_DEV_EPWM8 94
147 #define TISCI_DEV_VTM0 95
148 #define TISCI_DEV_MAILBOX0 96
149 #define TISCI_DEV_MAIN2MCU_VD 97
150 #define TISCI_DEV_MCAN0 98
151 #define TISCI_DEV_MCAN1 99
152 #define TISCI_DEV_MCU_MCRC64_0 100
153 #define TISCI_DEV_MCU2MAIN_VD 101
154 #define TISCI_DEV_I2C0 102
155 #define TISCI_DEV_I2C1 103
156 #define TISCI_DEV_I2C2 104
157 #define TISCI_DEV_I2C3 105
158 #define TISCI_DEV_MCU_I2C0 106
159 #define TISCI_DEV_MCU_I2C1 107
160 #define TISCI_DEV_PCIE0 114
161 #define TISCI_DEV_R5FSS0 119
162 #define TISCI_DEV_R5FSS1 120
163 #define TISCI_DEV_R5FSS0_CORE0 121
164 #define TISCI_DEV_R5FSS0_CORE1 122
165 #define TISCI_DEV_R5FSS1_CORE0 123
166 #define TISCI_DEV_R5FSS1_CORE1 124
167 #define TISCI_DEV_RTI0 125
168 #define TISCI_DEV_RTI1 126
169 #define TISCI_DEV_RTI8 127
170 #define TISCI_DEV_RTI9 128
171 #define TISCI_DEV_RTI10 130
172 #define TISCI_DEV_RTI11 131
173 #define TISCI_DEV_MCU_RTI0 132
174 #define TISCI_DEV_SA2_UL0 133
175 #define TISCI_DEV_COMPUTE_CLUSTER0 134
176 #define TISCI_DEV_A53SS0_CORE_0 135
177 #define TISCI_DEV_A53SS0_CORE_1 136
178 #define TISCI_DEV_A53SS0 137
179 #define TISCI_DEV_DDR16SS0 138
180 #define TISCI_DEV_PSC0 139
181 #define TISCI_DEV_MCU_PSC0 140
182 #define TISCI_DEV_MCSPI0 141
183 #define TISCI_DEV_MCSPI1 142
184 #define TISCI_DEV_MCSPI2 143
185 #define TISCI_DEV_MCSPI3 144
186 #define TISCI_DEV_MCSPI4 145
187 #define TISCI_DEV_UART0 146
188 #define TISCI_DEV_MCU_MCSPI0 147
189 #define TISCI_DEV_MCU_MCSPI1 148
190 #define TISCI_DEV_MCU_UART0 149
191 #define TISCI_DEV_SPINLOCK0 150
192 #define TISCI_DEV_TIMERMGR0 151
193 #define TISCI_DEV_UART1 152
194 #define TISCI_DEV_UART2 153
195 #define TISCI_DEV_UART3 154
196 #define TISCI_DEV_UART4 155
197 #define TISCI_DEV_UART5 156
198 #define TISCI_DEV_BOARD0 157
199 #define TISCI_DEV_UART6 158
200 #define TISCI_DEV_MCU_UART1 160
201 #define TISCI_DEV_USB0 161
202 #define TISCI_DEV_SERDES_10G0 162
203 #define TISCI_DEV_PBIST0 163
204 #define TISCI_DEV_PBIST1 164
205 #define TISCI_DEV_PBIST2 165
206 #define TISCI_DEV_PBIST3 166
207 #define TISCI_DEV_COMPUTE_CLUSTER0_PBIST_0 167