pcie/pcie.h

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/*
 *  Copyright (C) 2022 Texas Instruments Incorporated
 *
 *  Redistribution and use in source and binary forms, with or without
 *  modification, are permitted provided that the following conditions
 *  are met:
 *
 *    Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 *
 *    Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the
 *    distribution.
 *
 *    Neither the name of Texas Instruments Incorporated nor the names of
 *    its contributors may be used to endorse or promote products derived
 *    from this software without specific prior written permission.
 *
 *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
 *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
 *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
 *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
 *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */
 
#ifndef PCIE_H_
#define PCIE_H_
 
#ifdef __cplusplus
extern "C" {
#endif
 
#include <stdint.h>
 
/* ========================================================================== */
/*                             Macros                                         */
/* ========================================================================== */
 
#define PCIE_MAX_PERIPHS    (4U)
 
#define PCIE_MAX_MSI_IRQ    (32U)
 
#define PCIE_MAX_MSIX_IRQ   (2048U)
 
/* ========================================================================== */
/*                         Structures and Enums                               */
/* ========================================================================== */
 
typedef enum
{
    PCIE_EP_MODE = 0,    
    PCIE_LEGACY_EP_MODE, 
    PCIE_RC_MODE         
} Pcie_Mode;
 
typedef enum
{
    PCIE_GEN1 = 1,      
    PCIE_GEN2 = 2,      
    PCIE_GEN3 = 3,      
} Pcie_Gen;
 
typedef void *Pcie_Handle;
 
typedef struct
{
    void              *cfgBase;
    void              *dataBase;
    uint32_t           dataReserved;
    void              *devParams;
} Pcie_DeviceCfgBaseAddr;
 
typedef enum
{
    PCIE_BAR_NON_PREF = 0,    
    PCIE_BAR_PREF             
} Pcie_BarPref;
 
typedef enum
{
  PCIE_BAR_TYPE32 = 0,    
  PCIE_BAR_RSVD,          
  PCIE_BAR_TYPE64         
} Pcie_BarType;
 
typedef enum
{
    PCIE_BAR_MEM_MEM = 0,    
    PCIE_BAR_MEM_IO          
} Pcie_BarMem;
 
typedef enum Pcie_AtuRegionDir
{
    PCIE_ATU_REGION_DIR_OUTBOUND, 
    PCIE_ATU_REGION_DIR_INBOUND   
} Pcie_AtuRegionDir;
 
typedef enum Pcie_TlpType
{
    PCIE_TLP_TYPE_MEM, 
    PCIE_TLP_TYPE_IO,  
    PCIE_TLP_TYPE_CFG  
} Pcie_TlpType;
 
typedef enum Pcie_AtuRegionMatchMode
{
    PCIE_ATU_REGION_MATCH_MODE_ADDR, 
    PCIE_ATU_REGION_MATCH_MODE_BAR   
} Pcie_AtuRegionMatchMode;
 
typedef struct
{
    uint32_t regionIndex;
    Pcie_TlpType tlpType;
    uint32_t lowerBaseAddr;
    uint32_t upperBaseAddr;
    uint32_t regionWindowSize;
    uint32_t lowerTargetAddr;
    uint32_t upperTargetAddr;
} Pcie_ObAtuCfg;
 
typedef struct
{
    uint32_t regionIndex;
    Pcie_TlpType tlpType;
    uint32_t lowerBaseAddr;
    uint32_t upperBaseAddr;
    uint32_t regionWindowSize;
    uint32_t lowerTargetAddr;
    uint32_t upperTargetAddr;
    uint32_t barAperture;
    uint32_t barCfg;
} Pcie_IbAtuCfg;
 
typedef void (*Pcie_MsiIsr)(void *arg, uint32_t msiData);
 
typedef void (*Pcie_MsixIsr)(void *arg, uint32_t msixData);
 
typedef struct {
    Pcie_MsiIsr isr;
    void *arg;
    uint32_t intNum;
} Pcie_RegisterMsiIsrParams;
 
typedef struct {
    Pcie_MsixIsr isr;
    void *arg;
    uint32_t intNum;
} Pcie_RegisterMsixIsrParams;
 
typedef struct {
    Pcie_MsiIsr isr[PCIE_MAX_MSI_IRQ];
    void *isrArgs[PCIE_MAX_MSI_IRQ];
} Pcie_MsiIsrCtrl;
 
typedef struct {
    Pcie_MsixIsr isr[PCIE_MAX_MSIX_IRQ];
    void *isrArgs[PCIE_MAX_MSIX_IRQ];
} Pcie_MsixIsrCtrl;
 
typedef struct {
    /* Address to write to for MSIx interrupt */
    uintptr_t addr;
    /* Data to write to for MSIx interrupt */
    uint32_t data;
    /* Indentifies if a function is restricted from sending MSIx */
    uint32_t vector_ctrl;
} Pcie_MsixTblEntry;
 
typedef struct
{
    Pcie_MsixTblEntry tbl[PCIE_MAX_MSIX_IRQ];
} Pcie_MsixTbl;
 
typedef struct
{
    uint32_t deviceNum;
    Pcie_Mode operationMode;
    Pcie_Gen gen;
    uint32_t numLanes;
    Pcie_ObAtuCfg *obAtu;
    uint32_t obAtuNum;
    Pcie_IbAtuCfg *ibAtu;
    uint32_t ibAtuNum;
    uint32_t msiGlobalEventNum;
    uint32_t msiRingNum;
    uint32_t msiIntNum;
    uint32_t msiIrqEnableFlag;
    Pcie_MsiIsrCtrl *msiIsrCtrl;
    uint8_t *msiRingMem;
    uint32_t msixGlobalEventNum;
    uint32_t msixRingNum;
    uint32_t msixIntNum;
    uint32_t msixIrqEnableFlag;
    Pcie_MsixTbl *epMsixTbl;
    Pcie_MsixIsrCtrl *msixIsrCtrl;
    uint8_t *msixRingMem;
} Pcie_Attrs;
 
typedef struct
{
    Pcie_Handle handle;
    Pcie_DeviceCfgBaseAddr *bases;
    uint32_t cfgDone;
} Pcie_Object;
 
typedef struct
{
    Pcie_DeviceCfgBaseAddr *basesPtr[PCIE_MAX_PERIPHS];
} Pcie_DeviceCfg;
 
typedef struct
{
    Pcie_DeviceCfg dev;
} Pcie_InitCfg;
 
 
typedef struct
{
    Pcie_Object *object;
    Pcie_Attrs *attrs;
} Pcie_Config;
 
typedef enum
{
    PCIE_LOCATION_LOCAL,     
    PCIE_LOCATION_REMOTE     
} Pcie_Location;
 
typedef enum
{
    PCIE_LTSSM_DETECT_QUIET=0,      
    PCIE_LTSSM_DETECT_ACT,          
    PCIE_LTSSM_POLL_ACTIVE,         
    PCIE_LTSSM_POLL_COMPLIANCE,     
    PCIE_LTSSM_POLL_CONFIG,         
    PCIE_LTSSM_PRE_DETECT_QUIET,    
    PCIE_LTSSM_DETECT_WAIT,         
    PCIE_LTSSM_CFG_LINKWD_START,    
    PCIE_LTSSM_CFG_LINKWD_ACEPT,    
    PCIE_LTSSM_CFG_LANENUM_WAIT,    
    PCIE_LTSSM_CFG_LANENUM_ACEPT,   
    PCIE_LTSSM_CFG_COMPLETE,        
    PCIE_LTSSM_CFG_IDLE,            
    PCIE_LTSSM_RCVRY_LOCK,          
    PCIE_LTSSM_RCVRY_SPEED,         
    PCIE_LTSSM_RCVRY_RCVRCFG,       
    PCIE_LTSSM_RCVRY_IDLE,          
    PCIE_LTSSM_L0,                  
    PCIE_LTSSM_L0S,                 
    PCIE_LTSSM_L123_SEND_EIDLE,     
    PCIE_LTSSM_L1_IDLE,             
    PCIE_LTSSM_L2_IDLE,             
    PCIE_LTSSM_L2_WAKE,             
    PCIE_LTSSM_DISABLED_ENTRY,      
    PCIE_LTSSM_DISABLED_IDLE,       
    PCIE_LTSSM_DISABLED,            
    PCIE_LTSSM_LPBK_ENTRY,          
    PCIE_LTSSM_LPBK_ACTIVE,         
    PCIE_LTSSM_LPBK_EXIT,           
    PCIE_LTSSM_LPBK_EXIT_TIMEOUT,   
    PCIE_LTSSM_HOT_RESET_ENTRY,     
    PCIE_LTSSM_HOT_RESET,           
    PCIE_LTSSM_RCVRY_EQ0,           
    PCIE_LTSSM_RCVRY_EQ1,           
    PCIE_LTSSM_RCVRY_EQ2,           
    PCIE_LTSSM_RCVRY_EQ3            
} Pcie_LtssmState;
 
typedef struct Pcie_BarCfg_s {
    Pcie_Location location;
    Pcie_Mode mode;
    uint32_t base;
    Pcie_BarPref prefetch;
    Pcie_BarType type;
    Pcie_BarMem memSpace;
    uint8_t idx;
    uint8_t barxc;
    uint8_t barxa;
} Pcie_BarCfg;
 
typedef struct Pcie_IbTransCfg_s {
    uint8_t    ibBar;
    uint32_t   ibStartAddrLo;
    uint32_t   ibStartAddrHi;
    uint32_t   ibOffsetAddr;
    uint8_t    region;
} Pcie_IbTransCfg;
 
typedef struct Pcie_AtuRegionParams_s
{
    Pcie_AtuRegionDir       regionDir;
    Pcie_TlpType            tlpType;
    uint32_t                 enableRegion;
    Pcie_AtuRegionMatchMode matchMode;
    uint32_t                 barNumber;
    uint32_t                 lowerBaseAddr;
    uint32_t                 upperBaseAddr;
    uint32_t                 regionWindowSize;
    uint32_t                 lowerTargetAddr;
    uint32_t                 upperTargetAddr;
} Pcie_AtuRegionParams;
 
extern Pcie_Config gPcieConfig[];
extern uint32_t gPcieConfigNum;
 
/* ========================================================================== */
/*                          Function Declarations                             */
/* ========================================================================== */
 
void Pcie_init(void);
 
Pcie_Handle Pcie_open(uint32_t index);
 
void Pcie_close(Pcie_Handle handle);
 
Pcie_DeviceCfgBaseAddr *Pcie_handleGetBases (Pcie_Handle handle);
 
int32_t Pcie_setInterfaceMode (Pcie_Handle handle, Pcie_Mode mode);
 
int32_t Pcie_getMemSpaceReserved (Pcie_Handle handle, uint32_t *resSize);
 
int32_t Pcie_getMemSpaceRange (Pcie_Handle handle, void **base, uint32_t *size);
 
int32_t Pcie_cfgBar (Pcie_Handle handle, const Pcie_BarCfg *barCfg);
 
int32_t Pcie_atuRegionConfig (Pcie_Handle handle, Pcie_Location location,
            uint32_t atuRegionIndex, const Pcie_AtuRegionParams *atuRegionParams);
 
int32_t Pcie_getVendorId(Pcie_Handle handle, Pcie_Location location,
                                        uint32_t *vendorId, uint32_t *deviceId);
 
int32_t Pcie_waitLinkUp(Pcie_Handle handle);
 
int32_t Pcie_checkLinkParams(Pcie_Handle handle);
 
int32_t Pcie_LtssmCtrl (Pcie_Handle handle, uint8_t enable);
 
int32_t Pcie_setLanes (Pcie_Handle handle);
 
int32_t Pcie_cfgEP (Pcie_Handle handle);
 
int32_t Pcie_cfgRC (Pcie_Handle handle);
 
#ifdef __cplusplus
}
#endif
 
#endif  /* PCIE_H_ */