AM64x MCU+ SDK  08.05.00
ddr/v0/ddr.h
Go to the documentation of this file.
1 /******************************************************************************
2  * Copyright (c) 2021-2022 Texas Instruments Incorporated - https://www.ti.com
3  *
4  * Redistribution and use in source and binary forms, with or without
5  * modification, are permitted provided that the following conditions
6  * are met:
7  *
8  * Redistributions of source code must retain the above copyright
9  * notice, this list of conditions and the following disclaimer.
10  *
11  * Redistributions in binary form must reproduce the above copyright
12  * notice, this list of conditions and the following disclaimer in the
13  * documentation and/or other materials provided with the
14  * distribution.
15  *
16  * Neither the name of Texas Instruments Incorporated nor the names of
17  * its contributors may be used to endorse or promote products derived
18  * from this software without specific prior written permission.
19  *
20  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
21  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
22  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
23  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
24  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
25  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
26  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
27  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
28  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
29  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
30  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31  *
32  *****************************************************************************/
33 
49 #ifndef DDR_DRIVER_H_
50 #define DDR_DRIVER_H_
51 
52 /* ========================================================================== */
53 /* Include Files */
54 /* ========================================================================== */
55 
56 #include <stdint.h>
57 
58 #ifdef __cplusplus
59 extern "C" {
60 #endif
61 
62 /* ========================================================================== */
63 /* Macros & Typedefs */
64 /* ========================================================================== */
65 
72 #define DDR_ECC_1B_ERROR (0U)
73 #define DDR_ECC_2B_ERROR (1U)
74 #define DDR_ECC_ERR_ALL (2U)
75 
77 /* ========================================================================== */
78 /* Structures and Enums */
79 /* ========================================================================== */
80 
85 typedef struct
86 {
87  uint32_t ddrEccStart0;
88  uint32_t ddrEccEnd0;
90  uint32_t ddrEccStart1;
91  uint32_t ddrEccEnd1;
93  uint32_t ddrEccStart2;
94  uint32_t ddrEccEnd2;
96 
105 typedef struct
106 {
107  uint64_t clk1Freq;
108  uint64_t clk2Freq;
110  uint32_t *ddrssCtlReg;
111  uint32_t *ddrssPhyIndepReg;
112  uint32_t *ddrssPhyReg;
114  uint16_t *ddrssCtlRegNum;
116  uint16_t *ddrssPhyRegNum;
118  uint16_t ddrssCtlRegCount;
120  uint16_t ddrssPhyRegCount;
122  uint8_t fshcount;
124  uint8_t enableEccFlag;
127 } DDR_Params;
128 
134 typedef struct
135 {
140 
141 /* ========================================================================== */
142 /* Function Declarations */
143 /* ========================================================================== */
144 
152 
165 int32_t DDR_init(DDR_Params *prms);
166 
173 void DDR_enableInlineECC (uint8_t enableFlag);
174 
183 int32_t DDR_clearECCError (uint8_t errorType);
184 
193 int32_t DDR_getECCErrorInfo (DDR_ECCErrorInfo *ECCErrorInfo);
194 
195 #ifdef __cplusplus
196 }
197 #endif /* __cplusplus */
198 
199 #endif /* DDR_DRIVER_H_ */
200 
DDR_EccRegion::ddrEccEnd1
uint32_t ddrEccEnd1
Definition: ddr/v0/ddr.h:91
DDR_EccRegion::ddrEccStart2
uint32_t ddrEccStart2
Definition: ddr/v0/ddr.h:93
DDR_Params::ddrssCtlRegCount
uint16_t ddrssCtlRegCount
Definition: ddr/v0/ddr.h:118
DDR_ECCErrorInfo::doublebitErrorAddress
uintptr_t doublebitErrorAddress
Definition: ddr/v0/ddr.h:137
DDR_ECCErrorInfo
Emif ECC Error Information structure.
Definition: ddr/v0/ddr.h:135
DDR_Params::ddrssPhyRegNum
uint16_t * ddrssPhyRegNum
Definition: ddr/v0/ddr.h:116
DDR_EccRegion::ddrEccStart0
uint32_t ddrEccStart0
Definition: ddr/v0/ddr.h:87
DDR_Params::ddrssPhyReg
uint32_t * ddrssPhyReg
Definition: ddr/v0/ddr.h:112
DDR_Params::ddrssPhyRegCount
uint16_t ddrssPhyRegCount
Definition: ddr/v0/ddr.h:120
DDR_Params_init
void DDR_Params_init(DDR_Params *prms)
Set default values to DDR_Params.
DDR_enableInlineECC
void DDR_enableInlineECC(uint8_t enableFlag)
Enable/Disable DDR inline ECC.
DDR_ECCErrorInfo::singlebitErrorAddress
uintptr_t singlebitErrorAddress
Definition: ddr/v0/ddr.h:136
DDR_EccRegion
DDR Inline ECC region The structure specifies the DDR inline ECC region start and End address.
Definition: ddr/v0/ddr.h:86
DDR_Params::clk2Freq
uint64_t clk2Freq
Definition: ddr/v0/ddr.h:108
DDR_Params::ddrssPhyIndepReg
uint32_t * ddrssPhyIndepReg
Definition: ddr/v0/ddr.h:111
DDR_Params::enableEccFlag
uint8_t enableEccFlag
Definition: ddr/v0/ddr.h:124
DDR_Params::ddrssPhyIndepRegCount
uint16_t ddrssPhyIndepRegCount
Definition: ddr/v0/ddr.h:119
DDR_Params::fshcount
uint8_t fshcount
Definition: ddr/v0/ddr.h:122
DDR_getECCErrorInfo
int32_t DDR_getECCErrorInfo(DDR_ECCErrorInfo *ECCErrorInfo)
Get ECC error status.
DDR_Params::ddrssPhyIndepRegNum
uint16_t * ddrssPhyIndepRegNum
Definition: ddr/v0/ddr.h:115
DDR_clearECCError
int32_t DDR_clearECCError(uint8_t errorType)
Clear ECC errors for DDR.
DDR_init
int32_t DDR_init(DDR_Params *prms)
DDR4 Initialization function.
DDR_Params::clk1Freq
uint64_t clk1Freq
Definition: ddr/v0/ddr.h:107
DDR_Params
DDR config structure.
Definition: ddr/v0/ddr.h:106
DDR_EccRegion::ddrEccEnd2
uint32_t ddrEccEnd2
Definition: ddr/v0/ddr.h:94
DDR_Params::ddrssCtlRegNum
uint16_t * ddrssCtlRegNum
Definition: ddr/v0/ddr.h:114
DDR_Params::eccRegion
DDR_EccRegion * eccRegion
Definition: ddr/v0/ddr.h:125
DDR_ECCErrorInfo::singlebitErrorCount
uint32_t singlebitErrorCount
Definition: ddr/v0/ddr.h:138
DDR_EccRegion::ddrEccStart1
uint32_t ddrEccStart1
Definition: ddr/v0/ddr.h:90
DDR_EccRegion::ddrEccEnd0
uint32_t ddrEccEnd0
Definition: ddr/v0/ddr.h:88
DDR_Params::ddrssCtlReg
uint32_t * ddrssCtlReg
Definition: ddr/v0/ddr.h:110