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AM64x MCU+ SDK
08.04.00
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Go to the documentation of this file.
60 #include <drivers/hw_include/cslr_soc.h>
62 #include <drivers/hw_include/hw_types.h>
65 #define MAX_WAIT 20000
67 (*((volatile uint32_t *)(x)))
69 (*((volatile uint8_t *)(x)))
71 (*((volatile uint16_t *)(x)))
76 #define SYNCEVENT_INTRTR_IN_27 27
80 #define SYNCEVT_RTR_SYNC28_EVT 0x64
82 #define SYNCEVT_RTR_SYNC29_EVT 0x68
84 #define SYNCEVT_RTR_SYNC30_EVT 0x6C
86 #define SYNCEVT_RTR_SYNC31_EVT 0x70
88 #define SYNCEVT_RTR_SYNC10_EVT 0x2C
226 void HDSL_set_pc_addr(uint8_t gPc_addrh,uint8_t gPc_addrl,uint8_t gPc_offh,uint8_t gPc_offl);
250 void HDSL_write_pc_buffer(uint8_t gPc_buf0,uint8_t gPc_buf1,uint8_t gPc_buf2,uint8_t gPc_buf3,uint8_t gPc_buf4,uint8_t gPc_buf5,uint8_t gPc_buf6,uint8_t gPc_buf7);
uint16_t HDSL_get_events()
taking values of High bytes event(EVENT_H),Low bytes event(EVENT_L)
uint8_t HDSL_get_edges()
read Cable bit sampling time control
void HDSL_write_pc_buffer(uint8_t gPc_buf0, uint8_t gPc_buf1, uint8_t gPc_buf2, uint8_t gPc_buf3, uint8_t gPc_buf4, uint8_t gPc_buf5, uint8_t gPc_buf6, uint8_t gPc_buf7)
Write Parameters channel buffer for different bytes(bytes 0-7)
void HDSL_generate_memory_image(void)
@ MENU_SAFE_POSITION
Definition: hdsl_drv.h:92
uint8_t HDSL_get_qm()
Taking quality monitoring value.
@ MENU_HDSL_REG_INTO_DDR_GPIO
Definition: hdsl_drv.h:102
uint8_t HDSL_get_acc_err_cnt()
Acceleration error counter.
@ MENU_DIRECT_READ_RID81_LENGTH8
Definition: hdsl_drv.h:104
int HDSL_enable_sync_signal(uint8_t ES, uint32_t period)
Enable IEP *Enable SYNC0 and program pulse width Enable cyclic mod Program CMP1 TSR configura...
uint8_t HDSL_get_delay()
read Run time delay of system cable and signal strength
uint32_t HDSL_get_length()
@ MENU_PC_SHORT_MSG_WRITE
Definition: hdsl_drv.h:98
uint8_t HDSL_get_sum()
Getting Summarized slave status.
uint32_t HDSL_read_pc_short_msg(uint32_t gPc_addr)
Read Response of Short message parameters channel Read for safe1 channel(S_PC_DATA) and write Short m...
int HDSL_write_pc_short_msg(uint32_t gPc_addr, uint32_t gPc_data)
Write Response of Short message parameters channel Read for safe1 channel(S_PC_DATA) with gPc_data an...
@ MENU_HDSL_REG_INTO_DDR
Definition: hdsl_drv.h:101
@ MENU_PC_LONG_MSG_WRITE
Definition: hdsl_drv.h:100
@ MENU_DIRECT_READ_RID0_LENGTH8
Definition: hdsl_drv.h:103
@ MENU_EVENTS
Definition: hdsl_drv.h:94
uint8_t HDSL_get_sync_ctrl()
read Synchronization control value
@ MENU_INVALID
Definition: hdsl_drv.h:110
uint32_t value
Definition: tisci_otp_revision.h:2
@ MENU_INDIRECT_WRITE_RID0_LENGTH8
Definition: hdsl_drv.h:107
void * HDSL_get_src_loc()
@ MENU_INDIRECT_WRITE_RID0_LENGTH8_OFFSET0
Definition: hdsl_drv.h:106
@ MENU_DIRECT_READ_RID0_LENGTH8_OFFSET6
Definition: hdsl_drv.h:108
void HDSL_set_pc_ctrl(uint8_t value)
To set the direction read/write for long message communication.
uint8_t HDSL_get_rssi()
Read RSSI value.
uint8_t HDSL_get_master_qm()
read Quality monitoring value
uint8_t HDSL_get_enc_id(int byte)
Read encoder id bytes(byte no. 0-2)
void HDSL_set_sync_ctrl(uint8_t val)
write Synchronization control value
uint64_t HDSL_get_pos(int position_id)
Calculate fast position,safe position1,safe position2.
void HDSL_set_pc_addr(uint8_t gPc_addrh, uint8_t gPc_addrl, uint8_t gPc_offh, uint8_t gPc_offl)
Write PC_AAD_L ,PC_ADD_H ,PC_OFF_L,PC_OFF_H and PC_CTRL values in hdsl interface.
@ MENU_SUMMARY
Definition: hdsl_drv.h:95
@ MENU_LIMIT
Definition: hdsl_drv.h:109
@ MENU_DIRECT_READ_RID81_LENGTH2
Definition: hdsl_drv.h:105
@ MENU_RSSI
Definition: hdsl_drv.h:97
@ MENU_QUALITY_MONITORING
Definition: hdsl_drv.h:93
@ MENU_ACC_ERR_CNT
Definition: hdsl_drv.h:96
uint8_t HDSL_read_pc_buffer(uint8_t buff_off)
read Parameters channel buffer for different bytes(bytes 0-7)
struct PRUICSS_Config_s * PRUICSS_Handle
A handle that is returned from a PRUICSS_open() call. This handle is required for calling other APIs.
Definition: pruicss/g_v0/pruicss.h:235
@ MENU_PC_SHORT_MSG_READ
Definition: hdsl_drv.h:99
void HDSL_iep_init(PRUICSS_Handle gPruIcss0Handle, void *gPru_cfg, void *gPru_dramx)
Initialize IEP and Use OCP as IEP CLK src.