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AM64x MCU+ SDK
08.03.00
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51 #ifndef SOC_TISCI_DEVICES_H
52 #define SOC_TISCI_DEVICES_H
60 #define TISCI_DEV_ADC0 0
61 #define TISCI_DEV_CMP_EVENT_INTROUTER0 1
62 #define TISCI_DEV_DBGSUSPENDROUTER0 2
63 #define TISCI_DEV_MAIN_GPIOMUX_INTROUTER0 3
64 #define TISCI_DEV_MCU_MCU_GPIOMUX_INTROUTER0 5
65 #define TISCI_DEV_TIMESYNC_EVENT_INTROUTER0 6
66 #define TISCI_DEV_MCU_M4FSS0 7
67 #define TISCI_DEV_MCU_M4FSS0_CORE0 9
68 #define TISCI_DEV_CPSW0 13
69 #define TISCI_DEV_CPT2_AGGR0 14
70 #define TISCI_DEV_STM0 15
71 #define TISCI_DEV_DCC0 16
72 #define TISCI_DEV_DCC1 17
73 #define TISCI_DEV_DCC2 18
74 #define TISCI_DEV_DCC3 19
75 #define TISCI_DEV_DCC4 20
76 #define TISCI_DEV_DCC5 21
77 #define TISCI_DEV_DMSC0 22
78 #define TISCI_DEV_MCU_DCC0 23
79 #define TISCI_DEV_DEBUGSS_WRAP0 24
80 #define TISCI_DEV_DMASS0 25
81 #define TISCI_DEV_DMASS0_BCDMA_0 26
82 #define TISCI_DEV_DMASS0_CBASS_0 27
83 #define TISCI_DEV_DMASS0_INTAGGR_0 28
84 #define TISCI_DEV_DMASS0_IPCSS_0 29
85 #define TISCI_DEV_DMASS0_PKTDMA_0 30
86 #define TISCI_DEV_DMASS0_PSILCFG_0 31
87 #define TISCI_DEV_DMASS0_PSILSS_0 32
88 #define TISCI_DEV_DMASS0_RINGACC_0 33
89 #define TISCI_DEV_MCU_TIMER0 35
90 #define TISCI_DEV_TIMER0 36
91 #define TISCI_DEV_TIMER1 37
92 #define TISCI_DEV_TIMER2 38
93 #define TISCI_DEV_TIMER3 39
94 #define TISCI_DEV_TIMER4 40
95 #define TISCI_DEV_TIMER5 41
96 #define TISCI_DEV_TIMER6 42
97 #define TISCI_DEV_TIMER7 43
98 #define TISCI_DEV_TIMER8 44
99 #define TISCI_DEV_TIMER9 45
100 #define TISCI_DEV_TIMER10 46
101 #define TISCI_DEV_TIMER11 47
102 #define TISCI_DEV_MCU_TIMER1 48
103 #define TISCI_DEV_MCU_TIMER2 49
104 #define TISCI_DEV_MCU_TIMER3 50
105 #define TISCI_DEV_ECAP0 51
106 #define TISCI_DEV_ECAP1 52
107 #define TISCI_DEV_ECAP2 53
108 #define TISCI_DEV_ELM0 54
109 #define TISCI_DEV_EMIF_DATA_0_VD 55
110 #define TISCI_DEV_MMCSD0 57
111 #define TISCI_DEV_MMCSD1 58
112 #define TISCI_DEV_EQEP0 59
113 #define TISCI_DEV_EQEP1 60
114 #define TISCI_DEV_GTC0 61
115 #define TISCI_DEV_EQEP2 62
116 #define TISCI_DEV_ESM0 63
117 #define TISCI_DEV_MCU_ESM0 64
118 #define TISCI_DEV_FSIRX0 65
119 #define TISCI_DEV_FSIRX1 66
120 #define TISCI_DEV_FSIRX2 67
121 #define TISCI_DEV_FSIRX3 68
122 #define TISCI_DEV_FSIRX4 69
123 #define TISCI_DEV_FSIRX5 70
124 #define TISCI_DEV_FSITX0 71
125 #define TISCI_DEV_FSITX1 72
126 #define TISCI_DEV_FSS0 73
127 #define TISCI_DEV_FSS0_FSAS_0 74
128 #define TISCI_DEV_FSS0_OSPI_0 75
129 #define TISCI_DEV_GICSS0 76
130 #define TISCI_DEV_GPIO0 77
131 #define TISCI_DEV_GPIO1 78
132 #define TISCI_DEV_MCU_GPIO0 79
133 #define TISCI_DEV_GPMC0 80
134 #define TISCI_DEV_PRU_ICSSG0 81
135 #define TISCI_DEV_PRU_ICSSG1 82
136 #define TISCI_DEV_LED0 83
137 #define TISCI_DEV_CPTS0 84
138 #define TISCI_DEV_DDPA0 85
139 #define TISCI_DEV_EPWM0 86
140 #define TISCI_DEV_EPWM1 87
141 #define TISCI_DEV_EPWM2 88
142 #define TISCI_DEV_EPWM3 89
143 #define TISCI_DEV_EPWM4 90
144 #define TISCI_DEV_EPWM5 91
145 #define TISCI_DEV_EPWM6 92
146 #define TISCI_DEV_EPWM7 93
147 #define TISCI_DEV_EPWM8 94
148 #define TISCI_DEV_VTM0 95
149 #define TISCI_DEV_MAILBOX0 96
150 #define TISCI_DEV_MAIN2MCU_VD 97
151 #define TISCI_DEV_MCAN0 98
152 #define TISCI_DEV_MCAN1 99
153 #define TISCI_DEV_MCU_MCRC64_0 100
154 #define TISCI_DEV_MCU2MAIN_VD 101
155 #define TISCI_DEV_I2C0 102
156 #define TISCI_DEV_I2C1 103
157 #define TISCI_DEV_I2C2 104
158 #define TISCI_DEV_I2C3 105
159 #define TISCI_DEV_MCU_I2C0 106
160 #define TISCI_DEV_MCU_I2C1 107
161 #define TISCI_DEV_MSRAM_256K0 108
162 #define TISCI_DEV_MSRAM_256K1 109
163 #define TISCI_DEV_MSRAM_256K2 110
164 #define TISCI_DEV_MSRAM_256K3 111
165 #define TISCI_DEV_MSRAM_256K4 112
166 #define TISCI_DEV_MSRAM_256K5 113
167 #define TISCI_DEV_PCIE0 114
168 #define TISCI_DEV_POSTDIV1_16FFT1 115
169 #define TISCI_DEV_POSTDIV4_16FF0 116
170 #define TISCI_DEV_POSTDIV4_16FF2 117
171 #define TISCI_DEV_PSRAMECC0 118
172 #define TISCI_DEV_R5FSS0 119
173 #define TISCI_DEV_R5FSS1 120
174 #define TISCI_DEV_R5FSS0_CORE0 121
175 #define TISCI_DEV_R5FSS0_CORE1 122
176 #define TISCI_DEV_R5FSS1_CORE0 123
177 #define TISCI_DEV_R5FSS1_CORE1 124
178 #define TISCI_DEV_RTI0 125
179 #define TISCI_DEV_RTI1 126
180 #define TISCI_DEV_RTI8 127
181 #define TISCI_DEV_RTI9 128
182 #define TISCI_DEV_RTI10 130
183 #define TISCI_DEV_RTI11 131
184 #define TISCI_DEV_MCU_RTI0 132
185 #define TISCI_DEV_SA2_UL0 133
186 #define TISCI_DEV_COMPUTE_CLUSTER0 134
187 #define TISCI_DEV_A53SS0_CORE_0 135
188 #define TISCI_DEV_A53SS0_CORE_1 136
189 #define TISCI_DEV_A53SS0 137
190 #define TISCI_DEV_DDR16SS0 138
191 #define TISCI_DEV_PSC0 139
192 #define TISCI_DEV_MCU_PSC0 140
193 #define TISCI_DEV_MCSPI0 141
194 #define TISCI_DEV_MCSPI1 142
195 #define TISCI_DEV_MCSPI2 143
196 #define TISCI_DEV_MCSPI3 144
197 #define TISCI_DEV_MCSPI4 145
198 #define TISCI_DEV_UART0 146
199 #define TISCI_DEV_MCU_MCSPI0 147
200 #define TISCI_DEV_MCU_MCSPI1 148
201 #define TISCI_DEV_MCU_UART0 149
202 #define TISCI_DEV_SPINLOCK0 150
203 #define TISCI_DEV_TIMERMGR0 151
204 #define TISCI_DEV_UART1 152
205 #define TISCI_DEV_UART2 153
206 #define TISCI_DEV_UART3 154
207 #define TISCI_DEV_UART4 155
208 #define TISCI_DEV_UART5 156
209 #define TISCI_DEV_BOARD0 157
210 #define TISCI_DEV_UART6 158
211 #define TISCI_DEV_MCU_UART1 160
212 #define TISCI_DEV_USB0 161
213 #define TISCI_DEV_SERDES_10G0 162
214 #define TISCI_DEV_PBIST0 163
215 #define TISCI_DEV_PBIST1 164
216 #define TISCI_DEV_PBIST2 165
217 #define TISCI_DEV_PBIST3 166
218 #define TISCI_DEV_COMPUTE_CLUSTER0_PBIST_0 167