AM64x MCU+ SDK  08.03.00
Introduction

Table of Contents

PRU_ICSSG Subsystem

The Programmable Real-Time Unit Subsystem and Industrial Communication Subsystem (PRU_ICSSG) consists of:

  • Two 32-bit load/store RISC CPU cores — Programmable Real-Time Units (PRU0 and PRU1)
  • Two auxiliary 32-bit load/store RISC CPU cores — Auxiliary Programmable Real-Time Units (RTU_PRU0 and RTU_PRU1)
  • Two 32-bit load/store RISC CPU cores — Transmit Programmable Real-Time Units (TX_PRU0 and TX_PRU1)
  • Data RAMs per PRU core
  • Instruction RAMs per PRU, per RTU_PRU and per TX_PRU cores
  • Shared RAM
  • Peripheral modules: UART0, ECAP0, PWM, IEP0 and IEP1
  • Interrupt controller (INTC) and Task Manager per core

The programmable nature of the PRU cores, along with their access to pins, events and all device resources, provides flexibility in implementing fast real-time responses, specialized data handling operations, custom peripheral interfaces, and in offloading tasks from the other processor cores of the device. The PRU cores are programmed with a small, deterministic instruction set. Each PRU can operate independently or in coordination with each other and can also work in coordination with the device-level host CPU. This interaction between processors is determined by the nature of the firmware loaded into the PRU’s instruction memory.

PRU-ICSSG Sub-System Block Diagram

Refer to latest AM64x TRM (Technical Reference Manual) for complete details. (Can be found here: https://www.ti.com/product/AM6442)

PRU Core

PRU core is optimized for low latency and jitter. It contains:

  • Non pipelined CPU which is 100% deterministic – no jitter in real-time execution
  • Broadside interface with 1024 bit wide data bus supports lowest latency transfers
  • Register mapped IOs and bit-wise addressing provide max interface flexibility
  • Programmed in assembly or C language (or mixed C and inline assembly) with full support in CCS for source level debugging

PRU Instruction Set

  • Arithmetic Operations (green)
  • Logic Operations (blue)
  • IO Operations (black)
  • Program Flow Control (red)
ADD ADC SUB SUC RSB RSC
LSL LSR AND OR XOR NOT MIN MAX CLR SET LMBD
MOV LDI LDI32 LBBO SBBO LBCO SBCO MVIB MVIW MVID ZERO FILL XIN XOUT TSEN
JAL JMP CALL RET QBGT QBGE QBLT QBLE QBEQ QBNE QBA QBBS QBBC WBS WBC HALT SLP

Refer for usage details: PRU Assembly Instruction User Guide

PRU Register Addressing

Possible Addressability in Instructions: Bit, Byte (8-bit), Half-word (16-bit), Word (32-bit), Pointer

Sample assembly code instructions:

ldi r0.b0, 0x18 ; Load Immediate - loads 0x18 value into r0.b0
ldi r0.b2, 0x24 ; Load Immediate - loads 0x24 value into r0.b2
mov r0.w1, r1.w0 ; Copy Value - copies r1.w0 into r0.w1
set r1.b1, r1.b0, 5 ; Set Bit - copies value of r1.b0 into r1.b1 after setting it's 5th bit (0 indexing)
lbbo &r3, r1, r2.w0, b0 ; Load Byte Burst - Copy "r0.b0" bytes into r3 from the memory address r1+r2.w0

PRU Broadside Accelerators

PRU_ICSSG supports a broadside interface, which uses the XFR (XIN, XOUT, or XCHG) instruction to transfer the contents of PRUn, RTU_PRUn or TX_PRUn (where n = 0 or 1) registers to or from accelerators. This interface enables up to 31 registers (R0-R30, or 124 bytes) to be transferred in a single instruction.

PRU I/O Control Modes

Each slice is directly connected to 20 GPIO pins which can be controlled by the PRUs using R30 register and pin values can be read using R31 register. By default PRU0 and PRU1 cores are able to control the respective GPIO pins (after they have been correctly pinmuxed). Overall:

  • PRU has full input and output control on all interfaces
  • RTU_PRU and TX_PRU see R31 input and can process receive in parallel (If PRU_ICSSG slice is in GPIO mode, then RTU_PRU and TX_PRU both get the same r31_status (R31 register value) as PRU, but, only PRU core has control over pins, RTU_PRU/TX_PRU only have observation or input. RTU_PRU and TX_PRU has no support for GPO)
  • PRU/RTU_PRU supports load sharing option for sigma-delta and encoder interface (Load sharing across 3 PRU cores per slice of ICSSG which enables RTU (SD0-SD2), PRU (SD3-SD5), TX_PRU (SD6-SD8) control 3 channels each).

GPIO Connection
Direct Output 20 GPOs R30[19-0]
Direct Input 20 GPIs R31[19-0]
16 bit parallel capture 16 GPIs R31[15-0], CLK R31[16]
Serial shift out mode DATAOUT GPO0, CLKOUT GPO1, two 16 bit shadow register, core_clock based
Serial shift in mode DATAIN GPO0, 28 bit shift register, CNT_16 flag, core_clock with two fractional divider 1, 1.5, 2 …
9 x Sigma Delta sinc1/2/3 accumulators, OSR4..256, fast detect
3 x Peripheral Interface encoder (RS-485) interface

Real-Time Task Manager

The PRU_ICSSG system integrates 6 Task Managers used for efficient switching between tasks. There is one dedicated task manager for each PRU, RTU and TX_PRU core (PRU0/ PRU1, RTU_PRU0/ RTU_PRU1 and TX_PRU0/ TX_PRU1 cores), which are described in the subsequent sections. Each task manager works independently from the others.

  • Allows change of Program Counter in 2 cycles
  • Flexible context save/restore using SPAD register banks
  • 2 levels of pre-emption, 5 sub-tasks per level
  • 151 triggers from internal and external events
    • Ethernet receive/transmit/link states
    • IEP timer capture/compare/SYNC_OUT
    • INTC HOST_OUT[7:0], HOST_TASKMGR[7:0]
    • SPINLOCK_FEED_REQ[63:0]
    • PRU_INTR_IN[2:0]
    • xfr2vbus DMA data ready

Task Manager Block Diagram