AM64x MCU+ SDK  08.02.00
sciclient_irq_rm.h
Go to the documentation of this file.
1 /*
2  * Copyright (C) 2020 Texas Instruments Incorporated
3  *
4  * Redistribution and use in source and binary forms, with or without
5  * modification, are permitted provided that the following conditions
6  * are met:
7  *
8  * Redistributions of source code must retain the above copyright
9  * notice, this list of conditions and the following disclaimer.
10  *
11  * Redistributions in binary form must reproduce the above copyright
12  * notice, this list of conditions and the following disclaimer in the
13  * documentation and/or other materials provided with the
14  * distribution.
15  *
16  * Neither the name of Texas Instruments Incorporated nor the names of
17  * its contributors may be used to endorse or promote products derived
18  * from this software without specific prior written permission.
19  *
20  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
21  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
22  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
23  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
24  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
25  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
26  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
27  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
28  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
29  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
30  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31  *
32  */
39 #ifndef SCICLIENT_IRQ_RM_H_
40 #define SCICLIENT_IRQ_RM_H_
41 
42 /* ========================================================================== */
43 /* Include Files */
44 /* ========================================================================== */
45 
46 #include <stdint.h>
47 
48 /* ========================================================================== */
49 /* Macros & Typedefs */
50 /* ========================================================================== */
51 
52 #define SCICLIENT_RM_IA_NUM_INST 1
53 
54 #define SCICLIENT_RM_IR_NUM_INST 4
55 
56 #define SCICLIENT_IRQ_MAX_ROUTE_DEPTH 3
57 
58 /* ========================================================================== */
59 /* Structure Declarations */
60 /* ========================================================================== */
61 
62 /* None */
63 
64 /* ========================================================================== */
65 /* Global Variables */
66 /* ========================================================================== */
67 
68 /* None */
69 
70 #endif /* SCICLIENT_IRQ_RM_H_ */
TISCI_DEV_EPWM0
#define TISCI_DEV_EPWM0
Definition: tisci_devices.h:133
sciclient.h
This file contains prototypes for APIs contained as a part of SCICLIENT as well as the structures of ...
TISCI_SEC_PROXY_MAIN_1_R5_2_WRITE_LOW_PRIORITY_THREAD_ID
#define TISCI_SEC_PROXY_MAIN_1_R5_2_WRITE_LOW_PRIORITY_THREAD_ID
Definition: tisci_sec_proxy.h:222
DMASS0_INTAGGR_0_intaggr_vintr_pend_72_79_to_R5FSS0_CORE0_intr_8_15
const struct Sciclient_rmIrqIf DMASS0_INTAGGR_0_intaggr_vintr_pend_72_79_to_R5FSS0_CORE0_intr_8_15
Definition: sciclient_irq_rm.c:589
PRU_ICSSG0_pr1_edc0_sync0_out_0_0_to_TIMESYNC_EVENT_INTROUTER0_in_25_25
const struct Sciclient_rmIrqIf PRU_ICSSG0_pr1_edc0_sync0_out_0_0_to_TIMESYNC_EVENT_INTROUTER0_in_25_25
Definition: sciclient_irq_rm.c:841
tisci_if_EPWM0
const struct Sciclient_rmIrqIf *const tisci_if_EPWM0[]
Definition: sciclient_irq_rm.c:1028
TIMESYNC_EVENT_INTROUTER0_outl_22_22_to_CPTS0_cpts_hw7_push_6_6
const struct Sciclient_rmIrqIf TIMESYNC_EVENT_INTROUTER0_outl_22_22_to_CPTS0_cpts_hw7_push_6_6
Definition: sciclient_irq_rm.c:445
DMASS0_INTAGGR_0_intaggr_vintr_pend_160_167_to_PRU_ICSSG1_pr1_slv_intr_16_23
const struct Sciclient_rmIrqIf DMASS0_INTAGGR_0_intaggr_vintr_pend_160_167_to_PRU_ICSSG1_pr1_slv_intr_16_23
Definition: sciclient_irq_rm.c:643
CPSW0_cpts_sync_3_3_to_TIMESYNC_EVENT_INTROUTER0_in_34_34
const struct Sciclient_rmIrqIf CPSW0_cpts_sync_3_3_to_TIMESYNC_EVENT_INTROUTER0_in_34_34
Definition: sciclient_irq_rm.c:564
TIMESYNC_EVENT_INTROUTER0_outl_20_20_to_CPTS0_cpts_hw5_push_4_4
const struct Sciclient_rmIrqIf TIMESYNC_EVENT_INTROUTER0_outl_20_20_to_CPTS0_cpts_hw5_push_4_4
Definition: sciclient_irq_rm.c:433
MAIN_GPIOMUX_INTROUTER0_outp_16_17_to_DMASS0_INTAGGR_0_intaggr_levi_pend_24_25
const struct Sciclient_rmIrqIf MAIN_GPIOMUX_INTROUTER0_outp_16_17_to_DMASS0_INTAGGR_0_intaggr_levi_pend_24_25
Definition: sciclient_irq_rm.c:219
MAIN_GPIOMUX_INTROUTER0_outp_0_15_to_R5FSS1_CORE0_intr_32_47
const struct Sciclient_rmIrqIf MAIN_GPIOMUX_INTROUTER0_outp_0_15_to_R5FSS1_CORE0_intr_32_47
Definition: sciclient_irq_rm.c:201
TIMESYNC_EVENT_INTROUTER0_outl_18_18_to_CPTS0_cpts_hw3_push_2_2
const struct Sciclient_rmIrqIf TIMESYNC_EVENT_INTROUTER0_outl_18_18_to_CPTS0_cpts_hw3_push_2_2
Definition: sciclient_irq_rm.c:421
EPWM3_epwm_synco_o_0_0_to_TIMESYNC_EVENT_INTROUTER0_in_40_40
const struct Sciclient_rmIrqIf EPWM3_epwm_synco_o_0_0_to_TIMESYNC_EVENT_INTROUTER0_in_40_40
Definition: sciclient_irq_rm.c:1038
TISCI_SEC_PROXY_A53_1_READ_RESPONSE_THREAD_ID
#define TISCI_SEC_PROXY_A53_1_READ_RESPONSE_THREAD_ID
Definition: tisci_sec_proxy.h:133
tisci_irq_MCU_MCU_GPIOMUX_INTROUTER0
static const struct Sciclient_rmIrqNode tisci_irq_MCU_MCU_GPIOMUX_INTROUTER0
Definition: sciclient_irq_rm.c:348
TISCI_DEV_TIMER1
#define TISCI_DEV_TIMER1
Definition: tisci_devices.h:85
PCIE0_pcie_ptm_valid_pulse_4_4_to_TIMESYNC_EVENT_INTROUTER0_in_38_38
const struct Sciclient_rmIrqIf PCIE0_pcie_ptm_valid_pulse_4_4_to_TIMESYNC_EVENT_INTROUTER0_in_38_38
Definition: sciclient_irq_rm.c:1094
TISCI_HOST_ID_MAIN_0_R5_2
#define TISCI_HOST_ID_MAIN_0_R5_2
Definition: tisci_hosts.h:65
gRmIrInstances
struct Sciclient_rmIrInst gRmIrInstances[SCICLIENT_RM_IR_NUM_INST]
Definition: sciclient_irq_rm.c:89
CPTS0_cpts_genf3_4_4_to_TIMESYNC_EVENT_INTROUTER0_in_19_19
const struct Sciclient_rmIrqIf CPTS0_cpts_genf3_4_4_to_TIMESYNC_EVENT_INTROUTER0_in_19_19
Definition: sciclient_irq_rm.c:981
TISCI_SEC_PROXY_MAIN_1_R5_3_WRITE_LOW_PRIORITY_THREAD_ID
#define TISCI_SEC_PROXY_MAIN_1_R5_3_WRITE_LOW_PRIORITY_THREAD_ID
Definition: tisci_sec_proxy.h:236
tisci_if_GPMC0
const struct Sciclient_rmIrqIf *const tisci_if_GPMC0[]
Definition: sciclient_irq_rm.c:831
MCU_MCU_GPIOMUX_INTROUTER0_outp_0_3_to_R5FSS1_CORE0_intr_104_107
const struct Sciclient_rmIrqIf MCU_MCU_GPIOMUX_INTROUTER0_outp_0_3_to_R5FSS1_CORE0_intr_104_107
Definition: sciclient_irq_rm.c:301
SCICLIENT_CONTEXT_MAX_NUM
#define SCICLIENT_CONTEXT_MAX_NUM
Definition: sciclient_fmwMsgParams.h:115
TISCI_HOST_ID_A53_1
#define TISCI_HOST_ID_A53_1
Definition: tisci_hosts.h:71
TIMESYNC_EVENT_INTROUTER0_outl_10_10_to_PRU_ICSSG0_pr1_edc1_latch0_in_2_2
const struct Sciclient_rmIrqIf TIMESYNC_EVENT_INTROUTER0_outl_10_10_to_PRU_ICSSG0_pr1_edc1_latch0_in_2_2
Definition: sciclient_irq_rm.c:373
CPTS0_cpts_genf0_1_1_to_TIMESYNC_EVENT_INTROUTER0_in_16_16
const struct Sciclient_rmIrqIf CPTS0_cpts_genf0_1_1_to_TIMESYNC_EVENT_INTROUTER0_in_16_16
Definition: sciclient_irq_rm.c:963
tisci_irq_MAIN_GPIOMUX_INTROUTER0
static const struct Sciclient_rmIrqNode tisci_irq_MAIN_GPIOMUX_INTROUTER0
Definition: sciclient_irq_rm.c:276
TISCI_DEV_MCU_MCU_GPIOMUX_INTROUTER0
#define TISCI_DEV_MCU_MCU_GPIOMUX_INTROUTER0
Definition: tisci_devices.h:58
MCU_MCU_GPIOMUX_INTROUTER0_outp_4_7_to_MCU_M4FSS0_CORE0_nvic_0_3
const struct Sciclient_rmIrqIf MCU_MCU_GPIOMUX_INTROUTER0_outp_4_7_to_MCU_M4FSS0_CORE0_nvic_0_3
Definition: sciclient_irq_rm.c:313
GPIO0_gpio_bank_90_98_to_MAIN_GPIOMUX_INTROUTER0_in_190_198
const struct Sciclient_rmIrqIf GPIO0_gpio_bank_90_98_to_MAIN_GPIOMUX_INTROUTER0_in_190_198
Definition: sciclient_irq_rm.c:762
MAIN_GPIOMUX_INTROUTER0_outp_24_29_to_PRU_ICSSG0_pr1_iep1_cap_intr_req_10_15
const struct Sciclient_rmIrqIf MAIN_GPIOMUX_INTROUTER0_outp_24_29_to_PRU_ICSSG0_pr1_iep1_cap_intr_req_10_15
Definition: sciclient_irq_rm.c:231
tisci_irq_TIMER0
static const struct Sciclient_rmIrqNode tisci_irq_TIMER0
Definition: sciclient_irq_rm.c:685
TIMESYNC_EVENT_INTROUTER0_outl_31_31_to_CPSW0_cpts_hw2_push_1_1
const struct Sciclient_rmIrqIf TIMESYNC_EVENT_INTROUTER0_outl_31_31_to_CPSW0_cpts_hw2_push_1_1
Definition: sciclient_irq_rm.c:469
TISCI_SEC_PROXY_MAIN_1_R5_3_READ_RESPONSE_THREAD_ID
#define TISCI_SEC_PROXY_MAIN_1_R5_3_READ_RESPONSE_THREAD_ID
Definition: tisci_sec_proxy.h:231
TIMESYNC_EVENT_INTROUTER0_outl_0_7_to_DMASS0_INTAGGR_0_intaggr_levi_pend_8_15
const struct Sciclient_rmIrqIf TIMESYNC_EVENT_INTROUTER0_outl_0_7_to_DMASS0_INTAGGR_0_intaggr_levi_pend_8_15
Definition: sciclient_irq_rm.c:355
CMP_EVENT_INTROUTER0_outp_32_39_to_DMASS0_INTAGGR_0_intaggr_levi_pend_0_7
const struct Sciclient_rmIrqIf CMP_EVENT_INTROUTER0_outp_32_39_to_DMASS0_INTAGGR_0_intaggr_levi_pend_0_7
Definition: sciclient_irq_rm.c:162
PCIE0_pcie_cpts_hw1_push_2_2_to_TIMESYNC_EVENT_INTROUTER0_in_37_37
const struct Sciclient_rmIrqIf PCIE0_pcie_cpts_hw1_push_2_2_to_TIMESYNC_EVENT_INTROUTER0_in_37_37
Definition: sciclient_irq_rm.c:1088
MAIN_GPIOMUX_INTROUTER0_outp_0_15_to_R5FSS1_CORE1_intr_32_47
const struct Sciclient_rmIrqIf MAIN_GPIOMUX_INTROUTER0_outp_0_15_to_R5FSS1_CORE1_intr_32_47
Definition: sciclient_irq_rm.c:207
tisci_if_TIMER1
const struct Sciclient_rmIrqIf *const tisci_if_TIMER1[]
Definition: sciclient_irq_rm.c:698
TISCI_DEV_EPWM3
#define TISCI_DEV_EPWM3
Definition: tisci_devices.h:136
TISCI_SEC_PROXY_MAIN_0_R5_3_READ_RESPONSE_THREAD_ID
#define TISCI_SEC_PROXY_MAIN_0_R5_3_READ_RESPONSE_THREAD_ID
Definition: tisci_sec_proxy.h:105
MCU_GPIO0_gpio_bank_30_31_to_MCU_MCU_GPIOMUX_INTROUTER0_in_30_31
const struct Sciclient_rmIrqIf MCU_GPIO0_gpio_bank_30_31_to_MCU_MCU_GPIOMUX_INTROUTER0_in_30_31
Definition: sciclient_irq_rm.c:808
PCIE0_pcie_cpts_comp_0_0_to_CMP_EVENT_INTROUTER0_in_81_81
const struct Sciclient_rmIrqIf PCIE0_pcie_cpts_comp_0_0_to_CMP_EVENT_INTROUTER0_in_81_81
Definition: sciclient_irq_rm.c:1070
CPTS0_cpts_genf4_5_5_to_TIMESYNC_EVENT_INTROUTER0_in_20_20
const struct Sciclient_rmIrqIf CPTS0_cpts_genf4_5_5_to_TIMESYNC_EVENT_INTROUTER0_in_20_20
Definition: sciclient_irq_rm.c:987
sciclient_irq_rm.h
Private AM64x specific RM interrupt data.
TISCI_SEC_PROXY_A53_1_WRITE_LOW_PRIORITY_THREAD_ID
#define TISCI_SEC_PROXY_A53_1_WRITE_LOW_PRIORITY_THREAD_ID
Definition: tisci_sec_proxy.h:138
TISCI_DEV_R5FSS0_CORE1
#define TISCI_DEV_R5FSS0_CORE1
Definition: tisci_devices.h:169
MAIN_GPIOMUX_INTROUTER0_outp_24_29_to_PRU_ICSSG1_pr1_iep1_cap_intr_req_10_15
const struct Sciclient_rmIrqIf MAIN_GPIOMUX_INTROUTER0_outp_24_29_to_PRU_ICSSG1_pr1_iep1_cap_intr_req_10_15
Definition: sciclient_irq_rm.c:249
TISCI_DEV_PCIE0
#define TISCI_DEV_PCIE0
Definition: tisci_devices.h:161
MCU_MCU_GPIOMUX_INTROUTER0_outp_8_11_to_MCU_ESM0_esm_pls_event1_92_95
const struct Sciclient_rmIrqIf MCU_MCU_GPIOMUX_INTROUTER0_outp_8_11_to_MCU_ESM0_esm_pls_event1_92_95
Definition: sciclient_irq_rm.c:325
TIMESYNC_EVENT_INTROUTER0_outl_14_14_to_PRU_ICSSG1_pr1_edc1_latch0_in_2_2
const struct Sciclient_rmIrqIf TIMESYNC_EVENT_INTROUTER0_outl_14_14_to_PRU_ICSSG1_pr1_edc1_latch0_in_2_2
Definition: sciclient_irq_rm.c:397
TISCI_HOST_ID_A53_3
#define TISCI_HOST_ID_A53_3
Definition: tisci_hosts.h:75
TISCI_SEC_PROXY_MAIN_0_R5_0_READ_RESPONSE_THREAD_ID
#define TISCI_SEC_PROXY_MAIN_0_R5_0_READ_RESPONSE_THREAD_ID
This file contains:
Definition: tisci_sec_proxy.h:63
TISCI_DEV_CPSW0
#define TISCI_DEV_CPSW0
Definition: tisci_devices.h:62
TIMESYNC_EVENT_INTROUTER0_outl_29_29_to_PCIE0_pcie_cpts_hw2_push_0_0
const struct Sciclient_rmIrqIf TIMESYNC_EVENT_INTROUTER0_outl_29_29_to_PCIE0_pcie_cpts_hw2_push_0_0
Definition: sciclient_irq_rm.c:457
TIMESYNC_EVENT_INTROUTER0_outl_19_19_to_CPTS0_cpts_hw4_push_3_3
const struct Sciclient_rmIrqIf TIMESYNC_EVENT_INTROUTER0_outl_19_19_to_CPTS0_cpts_hw4_push_3_3
Definition: sciclient_irq_rm.c:427
TISCI_HOST_ID_MAIN_0_R5_0
#define TISCI_HOST_ID_MAIN_0_R5_0
Definition: tisci_hosts.h:61
tisci_if_GPIO0
const struct Sciclient_rmIrqIf *const tisci_if_GPIO0[]
Definition: sciclient_irq_rm.c:768
tisci_if_MCU_GPIO0
const struct Sciclient_rmIrqIf *const tisci_if_MCU_GPIO0[]
Definition: sciclient_irq_rm.c:814
TISCI_DEV_DMASS0_INTAGGR_0
#define TISCI_DEV_DMASS0_INTAGGR_0
Definition: tisci_devices.h:77
gRmIrqTreeCount
const uint32_t gRmIrqTreeCount
Definition: sciclient_irq_rm.c:1139
tisci_if_GPIO1
const struct Sciclient_rmIrqIf *const tisci_if_GPIO1[]
Definition: sciclient_irq_rm.c:791
tisci_if_PCIE0
const struct Sciclient_rmIrqIf *const tisci_if_PCIE0[]
Definition: sciclient_irq_rm.c:1100
TISCI_SEC_PROXY_A53_3_READ_RESPONSE_THREAD_ID
#define TISCI_SEC_PROXY_A53_3_READ_RESPONSE_THREAD_ID
Definition: tisci_sec_proxy.h:161
tisci_if_CPTS0
const struct Sciclient_rmIrqIf *const tisci_if_CPTS0[]
Definition: sciclient_irq_rm.c:1005
tisci_irq_CMP_EVENT_INTROUTER0
static const struct Sciclient_rmIrqNode tisci_irq_CMP_EVENT_INTROUTER0
Definition: sciclient_irq_rm.c:176
PRU_ICSSG1_pr1_host_intr_req_4_11_to_CMP_EVENT_INTROUTER0_in_8_15
const struct Sciclient_rmIrqIf PRU_ICSSG1_pr1_host_intr_req_4_11_to_CMP_EVENT_INTROUTER0_in_8_15
Definition: sciclient_irq_rm.c:923
tisci_if_TIMER2
const struct Sciclient_rmIrqIf *const tisci_if_TIMER2[]
Definition: sciclient_irq_rm.c:714
TIMESYNC_EVENT_INTROUTER0_outl_9_9_to_PRU_ICSSG0_pr1_edc0_latch1_in_1_1
const struct Sciclient_rmIrqIf TIMESYNC_EVENT_INTROUTER0_outl_9_9_to_PRU_ICSSG0_pr1_edc0_latch1_in_1_1
Definition: sciclient_irq_rm.c:367
DMASS0_INTAGGR_0_intaggr_vintr_pend_168_183_to_MCU_M4FSS0_CORE0_nvic_32_47
const struct Sciclient_rmIrqIf DMASS0_INTAGGR_0_intaggr_vintr_pend_168_183_to_MCU_M4FSS0_CORE0_nvic_32_47
Definition: sciclient_irq_rm.c:649
CMP_EVENT_INTROUTER0_outp_16_23_to_R5FSS0_CORE1_intr_48_55
const struct Sciclient_rmIrqIf CMP_EVENT_INTROUTER0_outp_16_23_to_R5FSS0_CORE1_intr_48_55
Definition: sciclient_irq_rm.c:144
CPTS0_cpts_comp_0_0_to_CMP_EVENT_INTROUTER0_in_82_82
const struct Sciclient_rmIrqIf CPTS0_cpts_comp_0_0_to_CMP_EVENT_INTROUTER0_in_82_82
Definition: sciclient_irq_rm.c:957
CPSW0_cpts_genf1_2_2_to_TIMESYNC_EVENT_INTROUTER0_in_22_22
const struct Sciclient_rmIrqIf CPSW0_cpts_genf1_2_2_to_TIMESYNC_EVENT_INTROUTER0_in_22_22
Definition: sciclient_irq_rm.c:558
TISCI_HOST_ID_MAIN_1_R5_0
#define TISCI_HOST_ID_MAIN_1_R5_0
Definition: tisci_hosts.h:79
TISCI_DEV_TIMER2
#define TISCI_DEV_TIMER2
Definition: tisci_devices.h:86
TIMER3_timer_pwm_0_0_to_TIMESYNC_EVENT_INTROUTER0_in_3_3
const struct Sciclient_rmIrqIf TIMER3_timer_pwm_0_0_to_TIMESYNC_EVENT_INTROUTER0_in_3_3
Definition: sciclient_irq_rm.c:724
TISCI_SEC_PROXY_A53_0_WRITE_LOW_PRIORITY_THREAD_ID
#define TISCI_SEC_PROXY_A53_0_WRITE_LOW_PRIORITY_THREAD_ID
Definition: tisci_sec_proxy.h:124
DMASS0_INTAGGR_0_intaggr_vintr_pend_120_127_to_R5FSS1_CORE0_intr_8_15
const struct Sciclient_rmIrqIf DMASS0_INTAGGR_0_intaggr_vintr_pend_120_127_to_R5FSS1_CORE0_intr_8_15
Definition: sciclient_irq_rm.c:613
TISCI_SEC_PROXY_MAIN_1_R5_0_WRITE_LOW_PRIORITY_THREAD_ID
#define TISCI_SEC_PROXY_MAIN_1_R5_0_WRITE_LOW_PRIORITY_THREAD_ID
Definition: tisci_sec_proxy.h:194
PRU_ICSSG0_pr1_iep0_cmp_intr_req_12_27_to_CMP_EVENT_INTROUTER0_in_16_31
const struct Sciclient_rmIrqIf PRU_ICSSG0_pr1_iep0_cmp_intr_req_12_27_to_CMP_EVENT_INTROUTER0_in_16_31
Definition: sciclient_irq_rm.c:871
PRU_ICSSG1_pr1_iep1_cmp_intr_req_28_43_to_CMP_EVENT_INTROUTER0_in_64_79
const struct Sciclient_rmIrqIf PRU_ICSSG1_pr1_iep1_cmp_intr_req_28_43_to_CMP_EVENT_INTROUTER0_in_64_79
Definition: sciclient_irq_rm.c:935
tisci_if_PRU_ICSSG1
const struct Sciclient_rmIrqIf *const tisci_if_PRU_ICSSG1[]
Definition: sciclient_irq_rm.c:941
DMASS0_INTAGGR_0_intaggr_vintr_pend_88_119_to_R5FSS1_CORE0_intr_64_95
const struct Sciclient_rmIrqIf DMASS0_INTAGGR_0_intaggr_vintr_pend_88_119_to_R5FSS1_CORE0_intr_64_95
Definition: sciclient_irq_rm.c:619
tisci_irq_GPIO1
static const struct Sciclient_rmIrqNode tisci_irq_GPIO1
Definition: sciclient_irq_rm.c:795
TISCI_SEC_PROXY_M4_0_WRITE_LOW_PRIORITY_THREAD_ID
#define TISCI_SEC_PROXY_M4_0_WRITE_LOW_PRIORITY_THREAD_ID
Definition: tisci_sec_proxy.h:180
TIMESYNC_EVENT_INTROUTER0_outl_17_17_to_CPTS0_cpts_hw2_push_1_1
const struct Sciclient_rmIrqIf TIMESYNC_EVENT_INTROUTER0_outl_17_17_to_CPTS0_cpts_hw2_push_1_1
Definition: sciclient_irq_rm.c:415
TISCI_SEC_PROXY_A53_2_READ_RESPONSE_THREAD_ID
#define TISCI_SEC_PROXY_A53_2_READ_RESPONSE_THREAD_ID
Definition: tisci_sec_proxy.h:147
DMASS0_INTAGGR_0_intaggr_vintr_pend_40_71_to_R5FSS0_CORE0_intr_64_95
const struct Sciclient_rmIrqIf DMASS0_INTAGGR_0_intaggr_vintr_pend_40_71_to_R5FSS0_CORE0_intr_64_95
Definition: sciclient_irq_rm.c:595
TISCI_DEV_R5FSS0_CORE0
#define TISCI_DEV_R5FSS0_CORE0
Definition: tisci_devices.h:168
tisci_if_TIMER0
const struct Sciclient_rmIrqIf *const tisci_if_TIMER0[]
Definition: sciclient_irq_rm.c:682
TISCI_SEC_PROXY_MAIN_1_R5_1_WRITE_LOW_PRIORITY_THREAD_ID
#define TISCI_SEC_PROXY_MAIN_1_R5_1_WRITE_LOW_PRIORITY_THREAD_ID
Definition: tisci_sec_proxy.h:208
EPWM6_epwm_synco_o_0_0_to_TIMESYNC_EVENT_INTROUTER0_in_41_41
const struct Sciclient_rmIrqIf EPWM6_epwm_synco_o_0_0_to_TIMESYNC_EVENT_INTROUTER0_in_41_41
Definition: sciclient_irq_rm.c:1054
MAIN_GPIOMUX_INTROUTER0_outp_46_53_to_PRU_ICSSG1_pr1_slv_intr_46_53
const struct Sciclient_rmIrqIf MAIN_GPIOMUX_INTROUTER0_outp_46_53_to_PRU_ICSSG1_pr1_slv_intr_46_53
Definition: sciclient_irq_rm.c:255
tisci_if_MAIN_GPIOMUX_INTROUTER0
const struct Sciclient_rmIrqIf *const tisci_if_MAIN_GPIOMUX_INTROUTER0[]
Definition: sciclient_irq_rm.c:261
GPMC0_gpmc_sdmareq_0_0_to_DMASS0_INTAGGR_0_intaggr_levi_pend_29_29
const struct Sciclient_rmIrqIf GPMC0_gpmc_sdmareq_0_0_to_DMASS0_INTAGGR_0_intaggr_levi_pend_29_29
Definition: sciclient_irq_rm.c:825
GPIO0_gpio_0_89_to_MAIN_GPIOMUX_INTROUTER0_in_0_89
const struct Sciclient_rmIrqIf GPIO0_gpio_0_89_to_MAIN_GPIOMUX_INTROUTER0_in_0_89
Definition: sciclient_irq_rm.c:756
tisci_irq_CPSW0
static const struct Sciclient_rmIrqNode tisci_irq_CPSW0
Definition: sciclient_irq_rm.c:576
TIMESYNC_EVENT_INTROUTER0_outl_32_32_to_CPSW0_cpts_hw3_push_2_2
const struct Sciclient_rmIrqIf TIMESYNC_EVENT_INTROUTER0_outl_32_32_to_CPSW0_cpts_hw3_push_2_2
Definition: sciclient_irq_rm.c:475
TIMESYNC_EVENT_INTROUTER0_outl_21_21_to_CPTS0_cpts_hw6_push_5_5
const struct Sciclient_rmIrqIf TIMESYNC_EVENT_INTROUTER0_outl_21_21_to_CPTS0_cpts_hw6_push_5_5
Definition: sciclient_irq_rm.c:439
TIMESYNC_EVENT_INTROUTER0_outl_16_16_to_CPTS0_cpts_hw1_push_0_0
const struct Sciclient_rmIrqIf TIMESYNC_EVENT_INTROUTER0_outl_16_16_to_CPTS0_cpts_hw1_push_0_0
Definition: sciclient_irq_rm.c:409
MAIN_GPIOMUX_INTROUTER0_outp_0_15_to_R5FSS0_CORE0_intr_32_47
const struct Sciclient_rmIrqIf MAIN_GPIOMUX_INTROUTER0_outp_0_15_to_R5FSS0_CORE0_intr_32_47
Definition: sciclient_irq_rm.c:189
TISCI_DEV_PRU_ICSSG1
#define TISCI_DEV_PRU_ICSSG1
Definition: tisci_devices.h:129
TISCI_SEC_PROXY_MAIN_1_R5_2_READ_RESPONSE_THREAD_ID
#define TISCI_SEC_PROXY_MAIN_1_R5_2_READ_RESPONSE_THREAD_ID
Definition: tisci_sec_proxy.h:217
CPSW0_cpts_genf0_1_1_to_TIMESYNC_EVENT_INTROUTER0_in_21_21
const struct Sciclient_rmIrqIf CPSW0_cpts_genf0_1_1_to_TIMESYNC_EVENT_INTROUTER0_in_21_21
Definition: sciclient_irq_rm.c:552
tisci_if_CMP_EVENT_INTROUTER0
const struct Sciclient_rmIrqIf *const tisci_if_CMP_EVENT_INTROUTER0[]
Definition: sciclient_irq_rm.c:168
PRU_ICSSG1_pr1_edc1_sync0_out_2_2_to_TIMESYNC_EVENT_INTROUTER0_in_31_31
const struct Sciclient_rmIrqIf PRU_ICSSG1_pr1_edc1_sync0_out_2_2_to_TIMESYNC_EVENT_INTROUTER0_in_31_31
Definition: sciclient_irq_rm.c:911
TISCI_DEV_TIMER0
#define TISCI_DEV_TIMER0
Definition: tisci_devices.h:84
MAIN_GPIOMUX_INTROUTER0_outp_18_23_to_PRU_ICSSG0_pr1_iep0_cap_intr_req_4_9
const struct Sciclient_rmIrqIf MAIN_GPIOMUX_INTROUTER0_outp_18_23_to_PRU_ICSSG0_pr1_iep0_cap_intr_req_4_9
Definition: sciclient_irq_rm.c:225
TISCI_SEC_PROXY_A53_0_READ_RESPONSE_THREAD_ID
#define TISCI_SEC_PROXY_A53_0_READ_RESPONSE_THREAD_ID
Definition: tisci_sec_proxy.h:119
CPTS0_cpts_genf2_3_3_to_TIMESYNC_EVENT_INTROUTER0_in_18_18
const struct Sciclient_rmIrqIf CPTS0_cpts_genf2_3_3_to_TIMESYNC_EVENT_INTROUTER0_in_18_18
Definition: sciclient_irq_rm.c:975
TIMESYNC_EVENT_INTROUTER0_outl_13_13_to_PRU_ICSSG1_pr1_edc0_latch1_in_1_1
const struct Sciclient_rmIrqIf TIMESYNC_EVENT_INTROUTER0_outl_13_13_to_PRU_ICSSG1_pr1_edc0_latch1_in_1_1
Definition: sciclient_irq_rm.c:391
MCU_MCU_GPIOMUX_INTROUTER0_outp_8_11_to_MCU_ESM0_esm_pls_event2_96_99
const struct Sciclient_rmIrqIf MCU_MCU_GPIOMUX_INTROUTER0_outp_8_11_to_MCU_ESM0_esm_pls_event2_96_99
Definition: sciclient_irq_rm.c:331
TIMESYNC_EVENT_INTROUTER0_outl_23_23_to_CPTS0_cpts_hw8_push_7_7
const struct Sciclient_rmIrqIf TIMESYNC_EVENT_INTROUTER0_outl_23_23_to_CPTS0_cpts_hw8_push_7_7
Definition: sciclient_irq_rm.c:451
MAIN_GPIOMUX_INTROUTER0_outp_0_15_to_R5FSS0_CORE1_intr_32_47
const struct Sciclient_rmIrqIf MAIN_GPIOMUX_INTROUTER0_outp_0_15_to_R5FSS0_CORE1_intr_32_47
Definition: sciclient_irq_rm.c:195
DMASS0_INTAGGR_0_intaggr_vintr_pend_40_71_to_R5FSS0_CORE1_intr_64_95
const struct Sciclient_rmIrqIf DMASS0_INTAGGR_0_intaggr_vintr_pend_40_71_to_R5FSS0_CORE1_intr_64_95
Definition: sciclient_irq_rm.c:607
CPTS0_cpts_sync_7_7_to_TIMESYNC_EVENT_INTROUTER0_in_35_35
const struct Sciclient_rmIrqIf CPTS0_cpts_sync_7_7_to_TIMESYNC_EVENT_INTROUTER0_in_35_35
Definition: sciclient_irq_rm.c:999
PRU_ICSSG1_pr1_edc1_sync1_out_3_3_to_TIMESYNC_EVENT_INTROUTER0_in_32_32
const struct Sciclient_rmIrqIf PRU_ICSSG1_pr1_edc1_sync1_out_3_3_to_TIMESYNC_EVENT_INTROUTER0_in_32_32
Definition: sciclient_irq_rm.c:917
TISCI_DEV_MAIN_GPIOMUX_INTROUTER0
#define TISCI_DEV_MAIN_GPIOMUX_INTROUTER0
Definition: tisci_devices.h:57
TIMESYNC_EVENT_INTROUTER0_outl_35_35_to_CPSW0_cpts_hw6_push_5_5
const struct Sciclient_rmIrqIf TIMESYNC_EVENT_INTROUTER0_outl_35_35_to_CPSW0_cpts_hw6_push_5_5
Definition: sciclient_irq_rm.c:493
gRmIrqTree
const struct Sciclient_rmIrqNode *const gRmIrqTree[]
Definition: sciclient_irq_rm.c:1114
tisci_if_EPWM6
const struct Sciclient_rmIrqIf *const tisci_if_EPWM6[]
Definition: sciclient_irq_rm.c:1060
vint_usage_count_DMASS0_INTAGGR_0
uint8_t vint_usage_count_DMASS0_INTAGGR_0[184]
Definition: sciclient_irq_rm.c:50
DMASS0_INTAGGR_0_intaggr_vintr_pend_128_135_to_R5FSS1_CORE1_intr_8_15
const struct Sciclient_rmIrqIf DMASS0_INTAGGR_0_intaggr_vintr_pend_128_135_to_R5FSS1_CORE1_intr_8_15
Definition: sciclient_irq_rm.c:625
PRU_ICSSG1_pr1_edc0_sync1_out_1_1_to_TIMESYNC_EVENT_INTROUTER0_in_30_30
const struct Sciclient_rmIrqIf PRU_ICSSG1_pr1_edc0_sync1_out_1_1_to_TIMESYNC_EVENT_INTROUTER0_in_30_30
Definition: sciclient_irq_rm.c:905
CPTS0_cpts_genf1_2_2_to_TIMESYNC_EVENT_INTROUTER0_in_17_17
const struct Sciclient_rmIrqIf CPTS0_cpts_genf1_2_2_to_TIMESYNC_EVENT_INTROUTER0_in_17_17
Definition: sciclient_irq_rm.c:969
TISCI_SEC_PROXY_ICSSG_0_WRITE_LOW_PRIORITY_THREAD_ID
#define TISCI_SEC_PROXY_ICSSG_0_WRITE_LOW_PRIORITY_THREAD_ID
Definition: tisci_sec_proxy.h:250
TIMESYNC_EVENT_INTROUTER0_outl_34_34_to_CPSW0_cpts_hw5_push_4_4
const struct Sciclient_rmIrqIf TIMESYNC_EVENT_INTROUTER0_outl_34_34_to_CPSW0_cpts_hw5_push_4_4
Definition: sciclient_irq_rm.c:487
tisci_irq_PRU_ICSSG0
static const struct Sciclient_rmIrqNode tisci_irq_PRU_ICSSG0
Definition: sciclient_irq_rm.c:892
MCU_MCU_GPIOMUX_INTROUTER0_outp_0_3_to_R5FSS0_CORE1_intr_104_107
const struct Sciclient_rmIrqIf MCU_MCU_GPIOMUX_INTROUTER0_outp_0_3_to_R5FSS0_CORE1_intr_104_107
Definition: sciclient_irq_rm.c:295
TISCI_DEV_R5FSS1_CORE0
#define TISCI_DEV_R5FSS1_CORE0
Definition: tisci_devices.h:170
tisci_if_EPWM3
const struct Sciclient_rmIrqIf *const tisci_if_EPWM3[]
Definition: sciclient_irq_rm.c:1044
TISCI_SEC_PROXY_MAIN_1_R5_1_READ_RESPONSE_THREAD_ID
#define TISCI_SEC_PROXY_MAIN_1_R5_1_READ_RESPONSE_THREAD_ID
Definition: tisci_sec_proxy.h:203
tisci_if_TIMESYNC_EVENT_INTROUTER0
const struct Sciclient_rmIrqIf *const tisci_if_TIMESYNC_EVENT_INTROUTER0[]
Definition: sciclient_irq_rm.c:511
PRU_ICSSG1_pr1_iep0_cmp_intr_req_12_27_to_CMP_EVENT_INTROUTER0_in_48_63
const struct Sciclient_rmIrqIf PRU_ICSSG1_pr1_iep0_cmp_intr_req_12_27_to_CMP_EVENT_INTROUTER0_in_48_63
Definition: sciclient_irq_rm.c:929
TISCI_DEV_EPWM6
#define TISCI_DEV_EPWM6
Definition: tisci_devices.h:139
tisci_irq_EPWM3
static const struct Sciclient_rmIrqNode tisci_irq_EPWM3
Definition: sciclient_irq_rm.c:1047
TISCI_DEV_CPTS0
#define TISCI_DEV_CPTS0
Definition: tisci_devices.h:131
TISCI_SEC_PROXY_A53_3_WRITE_LOW_PRIORITY_THREAD_ID
#define TISCI_SEC_PROXY_A53_3_WRITE_LOW_PRIORITY_THREAD_ID
Definition: tisci_sec_proxy.h:166
gRmIaInstances
struct Sciclient_rmIaInst gRmIaInstances[SCICLIENT_RM_IA_NUM_INST]
Definition: sciclient_irq_rm.c:74
tisci_if_DMASS0_INTAGGR_0
const struct Sciclient_rmIrqIf *const tisci_if_DMASS0_INTAGGR_0[]
Definition: sciclient_irq_rm.c:655
TISCI_DEV_TIMER3
#define TISCI_DEV_TIMER3
Definition: tisci_devices.h:87
PCIE0_pcie_cpts_sync_3_3_to_TIMESYNC_EVENT_INTROUTER0_in_33_33
const struct Sciclient_rmIrqIf PCIE0_pcie_cpts_sync_3_3_to_TIMESYNC_EVENT_INTROUTER0_in_33_33
Definition: sciclient_irq_rm.c:1082
PRU_ICSSG0_pr1_edc1_sync1_out_3_3_to_TIMESYNC_EVENT_INTROUTER0_in_28_28
const struct Sciclient_rmIrqIf PRU_ICSSG0_pr1_edc1_sync1_out_3_3_to_TIMESYNC_EVENT_INTROUTER0_in_28_28
Definition: sciclient_irq_rm.c:859
TIMESYNC_EVENT_INTROUTER0_outl_37_37_to_CPSW0_cpts_hw8_push_7_7
const struct Sciclient_rmIrqIf TIMESYNC_EVENT_INTROUTER0_outl_37_37_to_CPSW0_cpts_hw8_push_7_7
Definition: sciclient_irq_rm.c:505
TISCI_HOST_ID_MAIN_1_R5_1
#define TISCI_HOST_ID_MAIN_1_R5_1
Definition: tisci_hosts.h:81
tisci_irq_PRU_ICSSG1
static const struct Sciclient_rmIrqNode tisci_irq_PRU_ICSSG1
Definition: sciclient_irq_rm.c:950
GPIO1_gpio_bank_90_98_to_MAIN_GPIOMUX_INTROUTER0_in_180_188
const struct Sciclient_rmIrqIf GPIO1_gpio_bank_90_98_to_MAIN_GPIOMUX_INTROUTER0_in_180_188
Definition: sciclient_irq_rm.c:785
tisci_if_MCU_MCU_GPIOMUX_INTROUTER0
const struct Sciclient_rmIrqIf *const tisci_if_MCU_MCU_GPIOMUX_INTROUTER0[]
Definition: sciclient_irq_rm.c:337
MCU_GPIO0_gpio_0_29_to_MCU_MCU_GPIOMUX_INTROUTER0_in_0_29
const struct Sciclient_rmIrqIf MCU_GPIO0_gpio_0_29_to_MCU_MCU_GPIOMUX_INTROUTER0_in_0_29
Definition: sciclient_irq_rm.c:802
TISCI_SEC_PROXY_MAIN_0_R5_2_WRITE_LOW_PRIORITY_THREAD_ID
#define TISCI_SEC_PROXY_MAIN_0_R5_2_WRITE_LOW_PRIORITY_THREAD_ID
Definition: tisci_sec_proxy.h:96
tisci_irq_CPTS0
static const struct Sciclient_rmIrqNode tisci_irq_CPTS0
Definition: sciclient_irq_rm.c:1015
TISCI_SEC_PROXY_A53_2_WRITE_LOW_PRIORITY_THREAD_ID
#define TISCI_SEC_PROXY_A53_2_WRITE_LOW_PRIORITY_THREAD_ID
Definition: tisci_sec_proxy.h:152
EPWM0_epwm_synco_o_0_0_to_TIMESYNC_EVENT_INTROUTER0_in_39_39
const struct Sciclient_rmIrqIf EPWM0_epwm_synco_o_0_0_to_TIMESYNC_EVENT_INTROUTER0_in_39_39
Definition: sciclient_irq_rm.c:1022
MAIN_GPIOMUX_INTROUTER0_outp_38_45_to_PRU_ICSSG0_pr1_slv_intr_46_53
const struct Sciclient_rmIrqIf MAIN_GPIOMUX_INTROUTER0_outp_38_45_to_PRU_ICSSG0_pr1_slv_intr_46_53
Definition: sciclient_irq_rm.c:237
tisci_irq_EPWM0
static const struct Sciclient_rmIrqNode tisci_irq_EPWM0
Definition: sciclient_irq_rm.c:1031
DMASS0_INTAGGR_0_intaggr_vintr_pend_0_39_to_GICSS0_spi_64_103
const struct Sciclient_rmIrqIf DMASS0_INTAGGR_0_intaggr_vintr_pend_0_39_to_GICSS0_spi_64_103
Definition: sciclient_irq_rm.c:583
tisci_if_GTC0
const struct Sciclient_rmIrqIf *const tisci_if_GTC0[]
Definition: sciclient_irq_rm.c:746
TISCI_SEC_PROXY_MAIN_0_R5_1_WRITE_LOW_PRIORITY_THREAD_ID
#define TISCI_SEC_PROXY_MAIN_0_R5_1_WRITE_LOW_PRIORITY_THREAD_ID
Definition: tisci_sec_proxy.h:82
TISCI_DEV_PRU_ICSSG0
#define TISCI_DEV_PRU_ICSSG0
Definition: tisci_devices.h:128
CMP_EVENT_INTROUTER0_outp_24_31_to_R5FSS1_CORE0_intr_48_55
const struct Sciclient_rmIrqIf CMP_EVENT_INTROUTER0_outp_24_31_to_R5FSS1_CORE0_intr_48_55
Definition: sciclient_irq_rm.c:150
TISCI_DEV_CMP_EVENT_INTROUTER0
#define TISCI_DEV_CMP_EVENT_INTROUTER0
Definition: tisci_devices.h:55
TISCI_HOST_ID_MAIN_0_R5_3
#define TISCI_HOST_ID_MAIN_0_R5_3
Definition: tisci_hosts.h:67
TIMESYNC_EVENT_INTROUTER0_outl_33_33_to_CPSW0_cpts_hw4_push_3_3
const struct Sciclient_rmIrqIf TIMESYNC_EVENT_INTROUTER0_outl_33_33_to_CPSW0_cpts_hw4_push_3_3
Definition: sciclient_irq_rm.c:481
TIMER1_timer_pwm_0_0_to_TIMESYNC_EVENT_INTROUTER0_in_1_1
const struct Sciclient_rmIrqIf TIMER1_timer_pwm_0_0_to_TIMESYNC_EVENT_INTROUTER0_in_1_1
Definition: sciclient_irq_rm.c:692
MAIN_GPIOMUX_INTROUTER0_outp_30_37_to_DMASS0_INTAGGR_0_intaggr_levi_pend_16_23
const struct Sciclient_rmIrqIf MAIN_GPIOMUX_INTROUTER0_outp_30_37_to_DMASS0_INTAGGR_0_intaggr_levi_pend_16_23
Definition: sciclient_irq_rm.c:213
tisci_irq_TIMER3
static const struct Sciclient_rmIrqNode tisci_irq_TIMER3
Definition: sciclient_irq_rm.c:733
TISCI_SEC_PROXY_MAIN_1_R5_0_READ_RESPONSE_THREAD_ID
#define TISCI_SEC_PROXY_MAIN_1_R5_0_READ_RESPONSE_THREAD_ID
Definition: tisci_sec_proxy.h:189
DMASS0_INTAGGR_0_intaggr_vintr_pend_80_87_to_R5FSS0_CORE1_intr_8_15
const struct Sciclient_rmIrqIf DMASS0_INTAGGR_0_intaggr_vintr_pend_80_87_to_R5FSS0_CORE1_intr_8_15
Definition: sciclient_irq_rm.c:601
MCU_MCU_GPIOMUX_INTROUTER0_outp_0_3_to_R5FSS1_CORE1_intr_104_107
const struct Sciclient_rmIrqIf MCU_MCU_GPIOMUX_INTROUTER0_outp_0_3_to_R5FSS1_CORE1_intr_104_107
Definition: sciclient_irq_rm.c:307
tisci_irq_EPWM6
static const struct Sciclient_rmIrqNode tisci_irq_EPWM6
Definition: sciclient_irq_rm.c:1063
TISCI_SEC_PROXY_MAIN_0_R5_1_READ_RESPONSE_THREAD_ID
#define TISCI_SEC_PROXY_MAIN_0_R5_1_READ_RESPONSE_THREAD_ID
Definition: tisci_sec_proxy.h:77
PRU_ICSSG1_pr1_edc0_sync0_out_0_0_to_TIMESYNC_EVENT_INTROUTER0_in_29_29
const struct Sciclient_rmIrqIf PRU_ICSSG1_pr1_edc0_sync0_out_0_0_to_TIMESYNC_EVENT_INTROUTER0_in_29_29
Definition: sciclient_irq_rm.c:899
tisci_irq_TIMESYNC_EVENT_INTROUTER0
static const struct Sciclient_rmIrqNode tisci_irq_TIMESYNC_EVENT_INTROUTER0
Definition: sciclient_irq_rm.c:539
tisci_if_CPSW0
const struct Sciclient_rmIrqIf *const tisci_if_CPSW0[]
Definition: sciclient_irq_rm.c:570
TISCI_SEC_PROXY_ICSSG_0_READ_RESPONSE_THREAD_ID
#define TISCI_SEC_PROXY_ICSSG_0_READ_RESPONSE_THREAD_ID
Definition: tisci_sec_proxy.h:245
MCU_MCU_GPIOMUX_INTROUTER0_outp_8_11_to_MCU_ESM0_esm_pls_event0_88_91
const struct Sciclient_rmIrqIf MCU_MCU_GPIOMUX_INTROUTER0_outp_8_11_to_MCU_ESM0_esm_pls_event0_88_91
Definition: sciclient_irq_rm.c:319
tisci_irq_MCU_GPIO0
static const struct Sciclient_rmIrqNode tisci_irq_MCU_GPIO0
Definition: sciclient_irq_rm.c:818
tisci_irq_GPIO0
static const struct Sciclient_rmIrqNode tisci_irq_GPIO0
Definition: sciclient_irq_rm.c:772
TISCI_HOST_ID_MAIN_1_R5_2
#define TISCI_HOST_ID_MAIN_1_R5_2
Definition: tisci_hosts.h:83
TISCI_DEV_MCU_ESM0
#define TISCI_DEV_MCU_ESM0
Definition: tisci_devices.h:111
TISCI_DEV_TIMESYNC_EVENT_INTROUTER0
#define TISCI_DEV_TIMESYNC_EVENT_INTROUTER0
Definition: tisci_devices.h:59
tisci_irq_GPMC0
static const struct Sciclient_rmIrqNode tisci_irq_GPMC0
Definition: sciclient_irq_rm.c:834
TIMESYNC_EVENT_INTROUTER0_outl_30_30_to_CPSW0_cpts_hw1_push_0_0
const struct Sciclient_rmIrqIf TIMESYNC_EVENT_INTROUTER0_outl_30_30_to_CPSW0_cpts_hw1_push_0_0
Definition: sciclient_irq_rm.c:463
SCICLIENT_RM_IR_NUM_INST
#define SCICLIENT_RM_IR_NUM_INST
Definition: sciclient_irq_rm.h:54
PCIE0_pcie_cpts_genf0_1_1_to_TIMESYNC_EVENT_INTROUTER0_in_23_23
const struct Sciclient_rmIrqIf PCIE0_pcie_cpts_genf0_1_1_to_TIMESYNC_EVENT_INTROUTER0_in_23_23
Definition: sciclient_irq_rm.c:1076
TISCI_HOST_ID_MAIN_0_R5_1
#define TISCI_HOST_ID_MAIN_0_R5_1
Definition: tisci_hosts.h:63
TISCI_SEC_PROXY_MAIN_0_R5_3_WRITE_LOW_PRIORITY_THREAD_ID
#define TISCI_SEC_PROXY_MAIN_0_R5_3_WRITE_LOW_PRIORITY_THREAD_ID
Definition: tisci_sec_proxy.h:110
TISCI_DEV_MCU_GPIO0
#define TISCI_DEV_MCU_GPIO0
Definition: tisci_devices.h:126
MCU_MCU_GPIOMUX_INTROUTER0_outp_0_3_to_GICSS0_spi_104_107
const struct Sciclient_rmIrqIf MCU_MCU_GPIOMUX_INTROUTER0_outp_0_3_to_GICSS0_spi_104_107
Definition: sciclient_irq_rm.c:283
TISCI_HOST_ID_M4_0
#define TISCI_HOST_ID_M4_0
Definition: tisci_hosts.h:77
PRU_ICSSG0_pr1_edc1_sync0_out_2_2_to_TIMESYNC_EVENT_INTROUTER0_in_27_27
const struct Sciclient_rmIrqIf PRU_ICSSG0_pr1_edc1_sync0_out_2_2_to_TIMESYNC_EVENT_INTROUTER0_in_27_27
Definition: sciclient_irq_rm.c:853
PRU_ICSSG0_pr1_iep1_cmp_intr_req_28_43_to_CMP_EVENT_INTROUTER0_in_32_47
const struct Sciclient_rmIrqIf PRU_ICSSG0_pr1_iep1_cmp_intr_req_28_43_to_CMP_EVENT_INTROUTER0_in_32_47
Definition: sciclient_irq_rm.c:877
MAIN_GPIOMUX_INTROUTER0_outp_0_15_to_GICSS0_spi_32_47
const struct Sciclient_rmIrqIf MAIN_GPIOMUX_INTROUTER0_outp_0_15_to_GICSS0_spi_32_47
Definition: sciclient_irq_rm.c:183
TISCI_HOST_ID_A53_0
#define TISCI_HOST_ID_A53_0
Definition: tisci_hosts.h:69
TISCI_DEV_GICSS0
#define TISCI_DEV_GICSS0
Definition: tisci_devices.h:123
GPIO1_gpio_0_89_to_MAIN_GPIOMUX_INTROUTER0_in_90_179
const struct Sciclient_rmIrqIf GPIO1_gpio_0_89_to_MAIN_GPIOMUX_INTROUTER0_in_90_179
Definition: sciclient_irq_rm.c:779
TISCI_DEV_GPIO0
#define TISCI_DEV_GPIO0
Definition: tisci_devices.h:124
tisci_irq_DMASS0_INTAGGR_0
static const struct Sciclient_rmIrqNode tisci_irq_DMASS0_INTAGGR_0
Definition: sciclient_irq_rm.c:669
TIMESYNC_EVENT_INTROUTER0_outl_36_36_to_CPSW0_cpts_hw7_push_6_6
const struct Sciclient_rmIrqIf TIMESYNC_EVENT_INTROUTER0_outl_36_36_to_CPSW0_cpts_hw7_push_6_6
Definition: sciclient_irq_rm.c:499
TIMER0_timer_pwm_0_0_to_TIMESYNC_EVENT_INTROUTER0_in_0_0
const struct Sciclient_rmIrqIf TIMER0_timer_pwm_0_0_to_TIMESYNC_EVENT_INTROUTER0_in_0_0
Definition: sciclient_irq_rm.c:676
TIMESYNC_EVENT_INTROUTER0_outl_11_11_to_PRU_ICSSG0_pr1_edc1_latch1_in_3_3
const struct Sciclient_rmIrqIf TIMESYNC_EVENT_INTROUTER0_outl_11_11_to_PRU_ICSSG0_pr1_edc1_latch1_in_3_3
Definition: sciclient_irq_rm.c:379
tisci_if_PRU_ICSSG0
const struct Sciclient_rmIrqIf *const tisci_if_PRU_ICSSG0[]
Definition: sciclient_irq_rm.c:883
TISCI_HOST_ID_ICSSG_0
#define TISCI_HOST_ID_ICSSG_0
Definition: tisci_hosts.h:87
TISCI_HOST_ID_MAIN_1_R5_3
#define TISCI_HOST_ID_MAIN_1_R5_3
Definition: tisci_hosts.h:85
tisci_irq_TIMER2
static const struct Sciclient_rmIrqNode tisci_irq_TIMER2
Definition: sciclient_irq_rm.c:717
TIMESYNC_EVENT_INTROUTER0_outl_8_8_to_PRU_ICSSG0_pr1_edc0_latch0_in_0_0
const struct Sciclient_rmIrqIf TIMESYNC_EVENT_INTROUTER0_outl_8_8_to_PRU_ICSSG0_pr1_edc0_latch0_in_0_0
Definition: sciclient_irq_rm.c:361
TIMER2_timer_pwm_0_0_to_TIMESYNC_EVENT_INTROUTER0_in_2_2
const struct Sciclient_rmIrqIf TIMER2_timer_pwm_0_0_to_TIMESYNC_EVENT_INTROUTER0_in_2_2
Definition: sciclient_irq_rm.c:708
TISCI_HOST_ID_A53_2
#define TISCI_HOST_ID_A53_2
Definition: tisci_hosts.h:73
DMASS0_INTAGGR_0_intaggr_vintr_pend_88_119_to_R5FSS1_CORE1_intr_64_95
const struct Sciclient_rmIrqIf DMASS0_INTAGGR_0_intaggr_vintr_pend_88_119_to_R5FSS1_CORE1_intr_64_95
Definition: sciclient_irq_rm.c:631
PRU_ICSSG0_pr1_host_intr_req_4_11_to_CMP_EVENT_INTROUTER0_in_0_7
const struct Sciclient_rmIrqIf PRU_ICSSG0_pr1_host_intr_req_4_11_to_CMP_EVENT_INTROUTER0_in_0_7
Definition: sciclient_irq_rm.c:865
CMP_EVENT_INTROUTER0_outp_0_15_to_GICSS0_spi_48_63
const struct Sciclient_rmIrqIf CMP_EVENT_INTROUTER0_outp_0_15_to_GICSS0_spi_48_63
Definition: sciclient_irq_rm.c:132
gSciclientMap
const Sciclient_MapStruct_t gSciclientMap[SCICLIENT_CONTEXT_MAX_NUM]
Definition: sciclient_fmwSecureProxyMap.c:71
tisci_irq_TIMER1
static const struct Sciclient_rmIrqNode tisci_irq_TIMER1
Definition: sciclient_irq_rm.c:701
CMP_EVENT_INTROUTER0_outp_16_23_to_R5FSS0_CORE0_intr_48_55
const struct Sciclient_rmIrqIf CMP_EVENT_INTROUTER0_outp_16_23_to_R5FSS0_CORE0_intr_48_55
Definition: sciclient_irq_rm.c:138
TISCI_DEV_GTC0
#define TISCI_DEV_GTC0
Definition: tisci_devices.h:108
TISCI_SEC_PROXY_MAIN_0_R5_0_WRITE_LOW_PRIORITY_THREAD_ID
#define TISCI_SEC_PROXY_MAIN_0_R5_0_WRITE_LOW_PRIORITY_THREAD_ID
Definition: tisci_sec_proxy.h:68
TISCI_SEC_PROXY_MAIN_0_R5_2_READ_RESPONSE_THREAD_ID
#define TISCI_SEC_PROXY_MAIN_0_R5_2_READ_RESPONSE_THREAD_ID
Definition: tisci_sec_proxy.h:91
rom_usage_DMASS0_INTAGGR_0
static struct Sciclient_rmIaUsedMapping rom_usage_DMASS0_INTAGGR_0[5U]
Definition: sciclient_irq_rm.c:51
TISCI_DEV_R5FSS1_CORE1
#define TISCI_DEV_R5FSS1_CORE1
Definition: tisci_devices.h:171
MAIN_GPIOMUX_INTROUTER0_outp_18_23_to_PRU_ICSSG1_pr1_iep0_cap_intr_req_4_9
const struct Sciclient_rmIrqIf MAIN_GPIOMUX_INTROUTER0_outp_18_23_to_PRU_ICSSG1_pr1_iep0_cap_intr_req_4_9
Definition: sciclient_irq_rm.c:243
GTC0_gtc_push_event_0_0_to_TIMESYNC_EVENT_INTROUTER0_in_36_36
const struct Sciclient_rmIrqIf GTC0_gtc_push_event_0_0_to_TIMESYNC_EVENT_INTROUTER0_in_36_36
Definition: sciclient_irq_rm.c:740
TISCI_DEV_GPMC0
#define TISCI_DEV_GPMC0
Definition: tisci_devices.h:127
TIMESYNC_EVENT_INTROUTER0_outl_12_12_to_PRU_ICSSG1_pr1_edc0_latch0_in_0_0
const struct Sciclient_rmIrqIf TIMESYNC_EVENT_INTROUTER0_outl_12_12_to_PRU_ICSSG1_pr1_edc0_latch0_in_0_0
Definition: sciclient_irq_rm.c:385
PRU_ICSSG0_pr1_edc0_sync1_out_1_1_to_TIMESYNC_EVENT_INTROUTER0_in_26_26
const struct Sciclient_rmIrqIf PRU_ICSSG0_pr1_edc0_sync1_out_1_1_to_TIMESYNC_EVENT_INTROUTER0_in_26_26
Definition: sciclient_irq_rm.c:847
CMP_EVENT_INTROUTER0_outp_24_31_to_R5FSS1_CORE1_intr_48_55
const struct Sciclient_rmIrqIf CMP_EVENT_INTROUTER0_outp_24_31_to_R5FSS1_CORE1_intr_48_55
Definition: sciclient_irq_rm.c:156
CPSW0_cpts_comp_0_0_to_CMP_EVENT_INTROUTER0_in_80_80
const struct Sciclient_rmIrqIf CPSW0_cpts_comp_0_0_to_CMP_EVENT_INTROUTER0_in_80_80
Definition: sciclient_irq_rm.c:546
MCU_MCU_GPIOMUX_INTROUTER0_outp_0_3_to_R5FSS0_CORE0_intr_104_107
const struct Sciclient_rmIrqIf MCU_MCU_GPIOMUX_INTROUTER0_outp_0_3_to_R5FSS0_CORE0_intr_104_107
Definition: sciclient_irq_rm.c:289
TISCI_DEV_MCU_M4FSS0_CORE0
#define TISCI_DEV_MCU_M4FSS0_CORE0
Definition: tisci_devices.h:61
tisci_irq_GTC0
static const struct Sciclient_rmIrqNode tisci_irq_GTC0
Definition: sciclient_irq_rm.c:749
CPTS0_cpts_genf5_6_6_to_TIMESYNC_EVENT_INTROUTER0_in_24_24
const struct Sciclient_rmIrqIf CPTS0_cpts_genf5_6_6_to_TIMESYNC_EVENT_INTROUTER0_in_24_24
Definition: sciclient_irq_rm.c:993
tisci_if_TIMER3
const struct Sciclient_rmIrqIf *const tisci_if_TIMER3[]
Definition: sciclient_irq_rm.c:730
tisci_irq_PCIE0
static const struct Sciclient_rmIrqNode tisci_irq_PCIE0
Definition: sciclient_irq_rm.c:1107
TIMESYNC_EVENT_INTROUTER0_outl_15_15_to_PRU_ICSSG1_pr1_edc1_latch1_in_3_3
const struct Sciclient_rmIrqIf TIMESYNC_EVENT_INTROUTER0_outl_15_15_to_PRU_ICSSG1_pr1_edc1_latch1_in_3_3
Definition: sciclient_irq_rm.c:403
TISCI_SEC_PROXY_M4_0_READ_RESPONSE_THREAD_ID
#define TISCI_SEC_PROXY_M4_0_READ_RESPONSE_THREAD_ID
Definition: tisci_sec_proxy.h:175
DMASS0_INTAGGR_0_intaggr_vintr_pend_152_159_to_PRU_ICSSG0_pr1_slv_intr_16_23
const struct Sciclient_rmIrqIf DMASS0_INTAGGR_0_intaggr_vintr_pend_152_159_to_PRU_ICSSG0_pr1_slv_intr_16_23
Definition: sciclient_irq_rm.c:637
SCICLIENT_RM_IA_NUM_INST
#define SCICLIENT_RM_IA_NUM_INST
Definition: sciclient_irq_rm.h:52
TISCI_DEV_GPIO1
#define TISCI_DEV_GPIO1
Definition: tisci_devices.h:125