adc/v0/adc.h

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/*
 * Copyright (C) 2021 Texas Instruments Incorporated
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 *   Redistributions of source code must retain the above copyright
 *   notice, this list of conditions and the following disclaimer.
 *
 *   Redistributions in binary form must reproduce the above copyright
 *   notice, this list of conditions and the following disclaimer in the
 *   documentation and/or other materials provided with the
 *   distribution.
 *
 *   Neither the name of Texas Instruments Incorporated nor the names of
 *   its contributors may be used to endorse or promote products derived
 *   from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */
 
#ifndef ADC_V0_H_
#define ADC_V0_H_
 
/* ========================================================================== */
/*                             Include Files                                  */
/* ========================================================================== */
 
#include <drivers/hw_include/cslr.h>
#include <drivers/hw_include/cslr_adc.h>
 
#ifdef __cplusplus
extern "C" {
#endif
 
/* ========================================================================== */
/*                             Macros & Typedefs                              */
/* ========================================================================== */
 
#define ADC_INTR_STATUS_ALL     (ADC_IRQSTATUS_END_OF_SEQUENCE_MASK | \
                                 ADC_IRQSTATUS_FIFO0_THR_MASK |       \
                                 ADC_IRQSTATUS_FIFO0_OVERRUN_MASK |   \
                                 ADC_IRQSTATUS_FIFO0_UNDERFLOW_MASK | \
                                 ADC_IRQSTATUS_FIFO1_THR_MASK |       \
                                 ADC_IRQSTATUS_FIFO1_OVERRUN_MASK |   \
                                 ADC_IRQSTATUS_FIFO1_UNDERFLOW_MASK | \
                                 ADC_IRQSTATUS_OUT_OF_RANGE_MASK)
 
#define ADC_INTR_ENABLE_ALL     (ADC_IRQENABLE_SET_END_OF_SEQUENCE_MASK | \
                                 ADC_IRQENABLE_SET_FIFO0_THR_MASK |       \
                                 ADC_IRQENABLE_SET_FIFO0_OVERRUN_MASK |   \
                                 ADC_IRQENABLE_SET_FIFO0_UNDERFLOW_MASK | \
                                 ADC_IRQENABLE_SET_FIFO1_THR_MASK |       \
                                 ADC_IRQENABLE_SET_FIFO1_OVERRUN_MASK |   \
                                 ADC_IRQENABLE_SET_FIFO1_UNDERFLOW_MASK | \
                                 ADC_IRQENABLE_SET_OUT_OF_RANGE_MASK)
 
#define ADC_INTR_DISABLE_ALL    (ADC_IRQENABLE_CLR_END_OF_SEQUENCE_MASK | \
                                 ADC_IRQENABLE_CLR_FIFO0_THR_MASK |       \
                                 ADC_IRQENABLE_CLR_FIFO0_OVERRUN_MASK |   \
                                 ADC_IRQENABLE_CLR_FIFO0_UNDERFLOW_MASK | \
                                 ADC_IRQENABLE_CLR_FIFO1_THR_MASK |       \
                                 ADC_IRQENABLE_CLR_FIFO1_OVERRUN_MASK |   \
                                 ADC_IRQENABLE_CLR_FIFO1_UNDERFLOW_MASK | \
                                 ADC_IRQENABLE_CLR_OUT_OF_RANGE_MASK)
 
#define ADC_INTR_ALL             (ADC_INTR_STATUS_ALL)
 
#define ADC_OPENDELAY_MAX               (0x3FFFFU)
 
#define ADC_SAMPLEDELAY_MAX             (0xFFU)
 
#define ADC_RANGE_MAX                   (0x3FFU)
 
#define ADC_RANGE_MIN                   (0x0U)
 
#define ADC_FIFO_SIZE                   (64U)
 
#define ADC_MAX_NUM_CHN                 (uint32_t)(8U)
 
#define ADC_GET_RANGE(bit)              (((uint32_t) 1U) << (bit))
 
/* ========================================================================== */
/*                         Structures and Enums                               */
/* ========================================================================== */
 
typedef uint32_t adcChannel_t;
 
#define ADC_CHANNEL_1                       (ADC_STEPCONFIG_SEL_INM_SWC_CHANNEL_1)
 
#define ADC_CHANNEL_2                       (ADC_STEPCONFIG_SEL_INM_SWC_CHANNEL_2)
 
#define ADC_CHANNEL_3                       (ADC_STEPCONFIG_SEL_INM_SWC_CHANNEL_3)
 
#define ADC_CHANNEL_4                       (ADC_STEPCONFIG_SEL_INM_SWC_CHANNEL_4)
 
#define ADC_CHANNEL_5                       (ADC_STEPCONFIG_SEL_INM_SWC_CHANNEL_5)
 
#define ADC_CHANNEL_6                       (ADC_STEPCONFIG_SEL_INM_SWC_CHANNEL_6)
 
#define ADC_CHANNEL_7                       (ADC_STEPCONFIG_SEL_INM_SWC_CHANNEL_7)
 
#define ADC_CHANNEL_8                       (ADC_STEPCONFIG_SEL_INM_SWC_CHANNEL_8)
 
typedef uint32_t adcStepId_t;
 
#define ADC_STEP_1                          (ADC_ADCSTAT_STEP_ID_STEP1)
 
#define ADC_STEP_2                          (ADC_ADCSTAT_STEP_ID_STEP2)
 
#define ADC_STEP_3                          (ADC_ADCSTAT_STEP_ID_STEP3)
 
#define ADC_STEP_4                          (ADC_ADCSTAT_STEP_ID_STEP4)
 
#define ADC_STEP_5                          (ADC_ADCSTAT_STEP_ID_STEP5)
 
#define ADC_STEP_6                          (ADC_ADCSTAT_STEP_ID_STEP6)
 
#define ADC_STEP_7                          (ADC_ADCSTAT_STEP_ID_STEP7)
 
#define ADC_STEP_8                          (ADC_ADCSTAT_STEP_ID_STEP8)
 
#define ADC_STEP_9                          (ADC_ADCSTAT_STEP_ID_STEP9)
 
#define ADC_STEP_10                         (ADC_ADCSTAT_STEP_ID_STEP10)
 
#define ADC_STEP_11                         (ADC_ADCSTAT_STEP_ID_STEP11)
 
#define ADC_STEP_12                         (ADC_ADCSTAT_STEP_ID_STEP12)
 
#define ADC_STEP_13                         (ADC_ADCSTAT_STEP_ID_STEP13)
 
#define ADC_STEP_14                         (ADC_ADCSTAT_STEP_ID_STEP14)
 
#define ADC_STEP_15                         (ADC_ADCSTAT_STEP_ID_STEP15)
 
#define ADC_STEP_16                         (ADC_ADCSTAT_STEP_ID_STEP16)
 
typedef uint32_t adcOperationMode_t;
 
#define ADC_OPERATION_MODE_SINGLE_SHOT      (ADC_STEPCONFIG_MODE_SW_EN_ONESHOT)
 
#define ADC_OPERATION_MODE_CONTINUOUS       (ADC_STEPCONFIG_MODE_SW_EN_CONTINUOUS)
 
typedef uint32_t adcAveraging_t;
 
#define ADC_AVERAGING_NONE                  (ADC_STEPCONFIG_AVERAGING_NOAVG)
 
#define ADC_AVERAGING_2_SAMPLES             (ADC_STEPCONFIG_AVERAGING_2_SAMPLESAVG)
 
#define ADC_AVERAGING_4_SAMPLES             (ADC_STEPCONFIG_AVERAGING_4_SAMPLESAVG)
 
#define ADC_AVERAGING_8_SAMPLES             (ADC_STEPCONFIG_AVERAGING_8_SAMPLESAVG)
 
#define ADC_AVERAGING_16_SAMPLES            (ADC_STEPCONFIG_AVERAGING_16_SAMPLESAV)
 
typedef uint32_t adcFIFONum_t;
 
#define ADC_FIFO_NUM_0                      (0x0U)
 
#define ADC_FIFO_NUM_1                      (0x1U)
 
typedef uint32_t adcIntrSrc_t;
 
#define ADC_INTR_SRC_END_OF_SEQUENCE        (ADC_IRQENABLE_SET_END_OF_SEQUENCE_MASK)
 
#define ADC_INTR_SRC_FIFO0_THRESHOLD        (ADC_IRQENABLE_SET_FIFO0_THR_MASK)
 
#define ADC_INTR_SRC_FIFO0_OVERRUN          (ADC_IRQENABLE_SET_FIFO0_OVERRUN_MASK)
 
#define ADC_INTR_SRC_FIFO0_UNDERFLOW        (ADC_IRQENABLE_SET_FIFO0_UNDERFLOW_MASK)
 
#define ADC_INTR_SRC_FIFO1_THRESHOLD        (ADC_IRQENABLE_SET_FIFO1_THR_MASK)
 
#define ADC_INTR_SRC_FIFO1_OVERRUN          (ADC_IRQSTATUS_FIFO1_OVERRUN_MASK)
 
#define ADC_INTR_SRC_FIFO1_UNDERFLOW        (ADC_IRQENABLE_SET_FIFO1_UNDERFLOW_MASK)
 
#define ADC_INTR_SRC_OUT_OF_RANGE           (ADC_IRQENABLE_SET_OUT_OF_RANGE_MASK)
 
typedef uint32_t adcIdleMode_t;
 
#define ADC_IDLE_MODE_FORCE_IDLE            (ADC_SYSCONFIG_IDLEMODE_FORCE)
 
#define ADC_IDLE_MODE_NO_IDLE               (ADC_SYSCONFIG_IDLEMODE_NO_IDLE)
 
#define ADC_IDLE_MODE_SMART_IDLE            (ADC_SYSCONFIG_IDLEMODE_SMART_IDLE)
 
typedef struct adcRevisionId
{
    uint32_t scheme;
    uint32_t func;
    uint32_t rtlRev;
    uint32_t major;
    uint32_t custom;
    uint32_t minor;
}adcRevisionId_t;
 
typedef struct adcStepConfig
{
    uint32_t mode;
    uint32_t channel;
    uint32_t openDelay;
    uint32_t sampleDelay;
    uint32_t rangeCheckEnable;
    uint32_t averaging;
    uint32_t fifoNum;
}adcStepConfig_t;
 
typedef struct adcSequencerStatus
{
    uint32_t afeBusy;
    uint32_t fsmBusy;
    uint32_t stepId;
}adcSequencerStatus_t;
 
/* ========================================================================== */
/*                         Global Variables Declarations                      */
/* ========================================================================== */
 
/* None */
 
/* ========================================================================== */
/*                          Function Declarations                             */
/* ========================================================================== */
 
void ADCPowerUp(uint32_t baseAddr, uint32_t powerUp);
 
uint32_t AdcIsPoweredUp(uint32_t baseAddr);
 
int32_t ADCSetClkDivider(uint32_t baseAddr, uint32_t clkDivider);
 
void ADCInit(uint32_t baseAddr,
             uint32_t errCorrection,
             uint32_t errOffset,
             uint32_t calibration);
 
void ADCFIFODMAAccessEnable(uint32_t baseAddr,
                            uint32_t fifoNum,
                            uint32_t dmaLineEnable);
 
int32_t ADCSetStepParams(uint32_t               baseAddr,
                         uint32_t               stepId,
                         const adcStepConfig_t *configParams);
 
void ADCStepEnable(uint32_t baseAddr,
                   uint32_t stepId,
                   uint32_t stepEnable);
 
void ADCClearAllSteps(uint32_t baseAddr);
 
void ADCStart(uint32_t baseAddr, uint32_t adcEnable);
 
void ADCStepIdTagEnable(uint32_t baseAddr, uint32_t stepIdTag);
 
uint32_t ADCGetFIFOData(uint32_t baseAddr, uint32_t fifoNum);
 
uint32_t ADCGetFIFOWordCount(uint32_t baseAddr, uint32_t fifoNum);
 
int32_t ADCSetCPUFIFOThresholdLevel(uint32_t baseAddr,
                                    uint32_t fifoNum,
                                    uint32_t threshold);
 
uint32_t ADCGetCPUFIFOThresholdLevel(uint32_t baseAddr, uint32_t fifoNum);
 
int32_t ADCSetDMAFIFOThresholdLevel(uint32_t baseAddr,
                                    uint32_t fifoNum,
                                    uint32_t threshold);
 
uint32_t ADCGetDMAFIFOThresholdLevel(uint32_t baseAddr, uint32_t fifoNum);
 
void ADCEnableIntr(uint32_t baseAddr, uint32_t intrMask);
 
void ADCDisableIntr(uint32_t baseAddr, uint32_t intrMask);
 
void ADCWriteEOI(uint32_t baseAddr);
 
uint32_t ADCGetIntrStatus(uint32_t baseAddr);
 
void ADCClearIntrStatus(uint32_t baseAddr, uint32_t intrMask);
 
uint32_t ADCGetIntrRawStatus(uint32_t baseAddr);
 
int32_t ADCSetRange(uint32_t baseAddr, uint32_t highRange, uint32_t lowRange);
 
void ADCGetRange(uint32_t  baseAddr,
                 uint32_t *highRange,
                 uint32_t *lowRange);
 
void ADCGetSequencerStatus(uint32_t              baseAddr,
                           adcSequencerStatus_t *status);
 
void ADCSetIdleMode(uint32_t baseAddr, uint32_t idleMode);
 
void ADCGetRevisionId(uint32_t baseAddr, adcRevisionId_t *revId);
 
/* ========================================================================== */
/*                       Static Function Definitions                          */
/* ========================================================================== */
 
/* None */
 
#ifdef __cplusplus
}
#endif
 
#endif  /* #ifndef ADC_V0_H_ */