AM64x MCU+ SDK  08.01.00
uart/v0/uart.h
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1 /*
2  * Copyright (C) 2021 Texas Instruments Incorporated
3  *
4  * Redistribution and use in source and binary forms, with or without
5  * modification, are permitted provided that the following conditions
6  * are met:
7  *
8  * Redistributions of source code must retain the above copyright
9  * notice, this list of conditions and the following disclaimer.
10  *
11  * Redistributions in binary form must reproduce the above copyright
12  * notice, this list of conditions and the following disclaimer in the
13  * documentation and/or other materials provided with the
14  * distribution.
15  *
16  * Neither the name of Texas Instruments Incorporated nor the names of
17  * its contributors may be used to endorse or promote products derived
18  * from this software without specific prior written permission.
19  *
20  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
21  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
22  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
23  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
24  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
25  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
26  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
27  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
28  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
29  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
30  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31  */
32 
48 #ifndef UART_V0_H_
49 #define UART_V0_H_
50 
51 /* ========================================================================== */
52 /* Include Files */
53 /* ========================================================================== */
54 
55 #include <stdint.h>
56 #include <kernel/dpl/SystemP.h>
57 #include <kernel/dpl/SemaphoreP.h>
58 #include <kernel/dpl/HwiP.h>
59 #include <drivers/hw_include/cslr.h>
60 #include <drivers/hw_include/cslr_uart.h>
61 #include <drivers/hw_include/hw_types.h>
62 
63 #ifdef __cplusplus
64 extern "C" {
65 #endif
66 
67 /* ========================================================================== */
68 /* Macros & Typedefs */
69 /* ========================================================================== */
70 
72 #define UART_FIFO_SIZE (64U)
73 
79 #define UART_TRANSMITEMPTY_TRIALCOUNT (3000U)
80 
82 #define UART_ERROR_COUNT (0x00FFFFFFU)
83 
85 typedef void *UART_Handle;
86 
96 #define UART_TRANSFER_STATUS_SUCCESS (0U)
97 
98 #define UART_TRANSFER_STATUS_TIMEOUT (1U)
99 
100 #define UART_TRANSFER_STATUS_ERROR_BI (2U)
101 
102 #define UART_TRANSFER_STATUS_ERROR_FE (3U)
103 
104 #define UART_TRANSFER_STATUS_ERROR_PE (4U)
105 
106 #define UART_TRANSFER_STATUS_ERROR_OE (5U)
107 
108 #define UART_TRANSFER_STATUS_CANCELLED (6U)
109 
110 #define UART_TRANSFER_STATUS_STARTED (7U)
111 
112 #define UART_TRANSFER_STATUS_READ_TIMEOUT (8U)
113 
114 #define UART_TRANSFER_STATUS_ERROR_INUSE (9U)
115 
116 #define UART_TRANSFER_STATUS_ERROR_OTH (10U)
117 
138 #define UART_TRANSFER_MODE_BLOCKING (0U)
139 
143 #define UART_TRANSFER_MODE_CALLBACK (1U)
144 
166 #define UART_READ_RETURN_MODE_FULL (0U)
167 
170 #define UART_READ_RETURN_MODE_PARTIAL (1U)
171 
181 #define UART_LEN_5 (0U)
182 #define UART_LEN_6 (1U)
183 #define UART_LEN_7 (2U)
184 #define UART_LEN_8 (3U)
185 
195 #define UART_STOPBITS_1 (0U)
196 #define UART_STOPBITS_2 (1U)
197 
207 #define UART_PARITY_NONE (0x00U)
208 #define UART_PARITY_ODD (0x01U)
209 #define UART_PARITY_EVEN (0x03U)
210 #define UART_PARITY_FORCED0 (0x07U)
211 #define UART_PARITY_FORCED1 (0x05U)
212 
222 #define UART_FCTYPE_NONE (0x00U)
223 #define UART_FCTYPE_HW (0x02U)
224 
234 #define UART_FCPARAM_RXNONE (0x00U)
235 #define UART_FCPARAM_RXXONXOFF_2 (0x01U)
236 #define UART_FCPARAM_RXXONXOFF_1 (0x02U)
237 #define UART_FCPARAM_RXXONXOFF_12 (0x03U)
238 #define UART_FCPARAM_AUTO_RTS (0x40U)
239 
249 #define UART_FCPARAM_TXNONE (0x00U)
250 #define UART_FCPARAM_TXXONXOFF_2 (0x04U)
251 #define UART_FCPARAM_TXXONXOFF_1 (0x08U)
252 #define UART_FCPARAM_TXXONXOFF_12 (0x0CU)
253 #define UART_FCPARAM_AUTO_CTS (0x80U)
254 
264 #define UART_RXTRIGLVL_1 (1U)
265 #define UART_RXTRIGLVL_8 (8U)
266 #define UART_RXTRIGLVL_16 (16U)
267 #define UART_RXTRIGLVL_56 (56U)
268 #define UART_RXTRIGLVL_60 (60U)
269 
279 #define UART_TXTRIGLVL_1 (1U)
280 #define UART_TXTRIGLVL_8 (8U)
281 #define UART_TXTRIGLVL_16 (16U)
282 #define UART_TXTRIGLVL_32 (32U)
283 #define UART_TXTRIGLVL_56 (56U)
284 
294 #define UART_OPER_MODE_16X (0U)
295 #define UART_OPER_MODE_SIR (1U)
296 #define UART_OPER_MODE_16X_AUTO_BAUD (2U)
297 #define UART_OPER_MODE_13X (3U)
298 #define UART_OPER_MODE_MIR (4U)
299 #define UART_OPER_MODE_FIR (5U)
300 #define UART_OPER_MODE_CIR (6U)
301 #define UART_OPER_MODE_DISABLED (7U)
302 
313 #define UART_TX_FIFO_NOT_FULL ( \
314  UART_SSR_TX_FIFO_FULL_TX_FIFO_FULL_VALUE_0)
315 #define UART_TX_FIFO_FULL ( \
316  UART_SSR_TX_FIFO_FULL_TX_FIFO_FULL_VALUE_1)
317 
327 #define UART_INTID_MODEM_STAT (UART_IIR_IT_TYPE_IT_TYPE_VALUE_0 \
328  << \
329  UART_IIR_IT_TYPE_SHIFT)
330 #define UART_INTID_TX_THRES_REACH (UART_IIR_IT_TYPE_IT_TYPE_VALUE_1 \
331  << \
332  UART_IIR_IT_TYPE_SHIFT)
333 #define UART_INTID_RX_THRES_REACH (UART_IIR_IT_TYPE_IT_TYPE_VALUE_2 \
334  << \
335  UART_IIR_IT_TYPE_SHIFT)
336 #define UART_INTID_RX_LINE_STAT_ERROR (UART_IIR_IT_TYPE_IT_TYPE_VALUE_3 \
337  << \
338  UART_IIR_IT_TYPE_SHIFT)
339 #define UART_INTID_CHAR_TIMEOUT (UART_IIR_IT_TYPE_IT_TYPE_VALUE_6 \
340  << \
341  UART_IIR_IT_TYPE_SHIFT)
342 #define UART_INTID_XOFF_SPEC_CHAR_DETECT (UART_IIR_IT_TYPE_IT_TYPE_VALUE_8 \
343  << \
344  UART_IIR_IT_TYPE_SHIFT)
345 #define UART_INTID_MODEM_SIG_STATE_CHANGE (UART_IIR_IT_TYPE_IT_TYPE_VALUE_10 \
346  << \
347  UART_IIR_IT_TYPE_SHIFT)
348 
350 #define UART_INTR_PENDING (0U)
351 #define UART_N0_INTR_PENDING (1U)
352 
361 #define UART_INTR_CTS (UART_IER_CTS_IT_MASK)
362 #define UART_INTR_RTS (UART_IER_RTS_IT_MASK)
363 #define UART_INTR_XOFF (UART_IER_XOFF_IT_MASK)
364 #define UART_INTR_SLEEPMODE (UART_IER_SLEEP_MODE_MASK)
365 #define UART_INTR_MODEM_STAT (UART_IER_MODEM_STS_IT_MASK)
366 #define UART_INTR_LINE_STAT (UART_IER_LINE_STS_IT_MASK)
367 #define UART_INTR_THR (UART_IER_THR_IT_MASK)
368 #define UART_INTR_RHR_CTI (UART_IER_RHR_IT_MASK)
369 
370 #define UART_INTR2_RX_EMPTY (UART_IER2_EN_RXFIFO_EMPTY_MASK)
371 #define UART_INTR2_TX_EMPTY (UART_IER2_EN_TXFIFO_EMPTY_MASK)
372 
381 #define UART_FIFO_PE_FE_BI_DETECTED (UART_LSR_RX_FIFO_STS_MASK)
382 #define UART_BREAK_DETECTED_ERROR (UART_LSR_RX_BI_MASK)
383 #define UART_FRAMING_ERROR (UART_LSR_RX_FE_MASK)
384 #define UART_PARITY_ERROR (UART_LSR_RX_PE_MASK)
385 #define UART_OVERRUN_ERROR (UART_LSR_RX_OE_MASK)
386 
395 #define UART_REG_CONFIG_MODE_A ((uint32_t) 0x0080)
396 #define UART_REG_CONFIG_MODE_B ((uint32_t) 0x00BF)
397 #define UART_REG_OPERATIONAL_MODE ((uint32_t) 0x007F)
398 
399 /* ========================================================================== */
400 /* Structures and Enums */
401 /* ========================================================================== */
402 
407 typedef struct
408 {
409  void *buf;
412  uint32_t count;
416  uint32_t timeout;
418  uint32_t status;
420  void *args;
422 } UART_Transaction;
423 
431 typedef void (*UART_CallbackFxn) (UART_Handle handle,
432  UART_Transaction *transaction);
433 
444 typedef struct
445 {
446  uint32_t baudRate;
448  uint32_t dataLength;
450  uint32_t stopBits;
452  uint32_t parityType;
454  uint32_t readMode;
456  uint32_t readReturnMode;
458  uint32_t writeMode;
460  UART_CallbackFxn readCallbackFxn;
462  UART_CallbackFxn writeCallbackFxn;
464  uint32_t hwFlowControl;
466  uint32_t hwFlowControlThr;
469  /*
470  * Driver configuration
471  */
472  uint32_t intrEnable;
474  uint32_t intrNum;
476  uint8_t intrPriority;
478  uint32_t skipIntrReg;
480  uint32_t dmaEnable;
483  /*
484  * UART configuration
485  */
486  uint32_t operMode;
488  uint32_t rxTrigLvl;
490  uint32_t txTrigLvl;
492 } UART_Params;
493 
495 typedef struct
496 {
497  /*
498  * SOC configuration
499  */
500  uint32_t baseAddr;
502  uint32_t inputClkFreq;
504 } UART_Attrs;
505 
506 /* ========================================================================== */
507 /* Internal/Private Structure Declarations */
508 /* ========================================================================== */
509 
513 typedef struct
514 {
515  /*
516  * User parameters
517  */
518  UART_Handle handle;
520  UART_Params prms;
522  /*
523  * UART write variables
524  */
525  const void *writeBuf;
527  uint32_t writeCount;
529  uint32_t writeSizeRemaining;
531  /*
532  * UART receive variables
533  */
534  void *readBuf;
536  uint32_t readCount;
538  uint32_t readSizeRemaining;
540  uint32_t rxTimeoutCnt;
542  uint32_t readErrorCnt;
544  /*
545  * UART ransaction status variables
546  */
547  UART_Transaction *readTrans;
549  UART_Transaction *writeTrans;
551  /*
552  * State variables
553  */
554  uint32_t isOpen;
556  void *lock;
558  SemaphoreP_Object lockObj;
560  void *readTransferSem;
563  SemaphoreP_Object readTransferSemObj;
565  void *writeTransferSem;
568  SemaphoreP_Object writeTransferSemObj;
570  void *hwiHandle;
572  HwiP_Object hwiObj;
574 } UART_Object;
575 
582 typedef struct
583 {
584  UART_Attrs *attrs;
586  UART_Object *object;
588 } UART_Config;
589 
591 extern UART_Config gUartConfig[];
593 extern uint32_t gUartConfigNum;
594 
595 /* ========================================================================== */
596 /* Global Variables Declarations */
597 /* ========================================================================== */
598 
599 /* None */
600 
601 /* ========================================================================== */
602 /* Function Declarations */
603 /* ========================================================================== */
604 
608 void UART_init(void);
609 
613 void UART_deinit(void);
614 
631 UART_Handle UART_open(uint32_t index, const UART_Params *prms);
632 
642 void UART_close(UART_Handle handle);
643 
682 int32_t UART_write(UART_Handle handle, UART_Transaction *trans);
683 
718 int32_t UART_read(UART_Handle handle, UART_Transaction *trans);
719 
751 int32_t UART_writeCancel(UART_Handle handle, UART_Transaction *trans);
752 
784 int32_t UART_readCancel(UART_Handle handle, UART_Transaction *trans);
785 
794 UART_Handle UART_getHandle(uint32_t index);
795 
805 void UART_flushTxFifo(UART_Handle handle);
806 
812 static inline void UART_Params_init(UART_Params *prms);
813 
820 static inline void UART_Transaction_init(UART_Transaction *trans);
821 
822 /* ========================================================================== */
823 /* Static Function Definitions */
824 /* ========================================================================== */
825 
826 static inline void UART_Params_init(UART_Params *prms)
827 {
828  if(prms != NULL)
829  {
830  prms->baudRate = 115200U;
831  prms->dataLength = UART_LEN_8;
832  prms->stopBits = UART_STOPBITS_1;
833  prms->parityType = UART_PARITY_NONE;
834  prms->readMode = UART_TRANSFER_MODE_BLOCKING;
835  prms->readReturnMode = UART_READ_RETURN_MODE_FULL;
836  prms->writeMode = UART_TRANSFER_MODE_BLOCKING;
837  prms->readCallbackFxn = NULL;
838  prms->writeCallbackFxn = NULL;
839  prms->hwFlowControl = FALSE;
840  prms->hwFlowControlThr = UART_RXTRIGLVL_16;
841  prms->intrNum = 210U;
842  prms->intrEnable = TRUE;
843  prms->intrPriority = 4U;
844  prms->skipIntrReg = FALSE;
845  prms->dmaEnable = FALSE;
846  prms->operMode = UART_OPER_MODE_16X;
847  prms->rxTrigLvl = UART_RXTRIGLVL_8;
848  prms->txTrigLvl = UART_TXTRIGLVL_32;
849  }
850 }
851 
852 static inline void UART_Transaction_init(UART_Transaction *trans)
853 {
854  if(trans != NULL)
855  {
856  trans->buf = NULL;
857  trans->count = 0U;
858  trans->timeout = SystemP_WAIT_FOREVER;
859  trans->status = UART_TRANSFER_STATUS_SUCCESS;
860  trans->args = NULL;
861  }
862 }
863 
864 /* ========================================================================== */
865 /* Advanced Function Declarations */
866 /* ========================================================================== */
875 uint32_t UART_getBaseAddr(UART_Handle handle);
876 
885 void UART_enableLoopbackMode(uint32_t baseAddr);
886 
895 void UART_disableLoopbackMode(uint32_t baseAddr);
896 
914 static inline void UART_putChar(uint32_t baseAddr, uint8_t byteTx);
915 
930 static inline uint32_t UART_getChar(uint32_t baseAddr, uint8_t *pChar);
931 
960 static inline void UART_intrEnable(uint32_t baseAddr, uint32_t intrFlag);
961 
986 static inline void UART_intrDisable(uint32_t baseAddr, uint32_t intrFlag);
987 
1006 static inline void UART_intr2Enable(uint32_t baseAddr, uint32_t intrFlag);
1007 
1025 static inline void UART_intr2Disable(uint32_t baseAddr, uint32_t intrFlag);
1026 
1052 static inline uint32_t UART_getIntrIdentityStatus(uint32_t baseAddr);
1053 
1066 static inline uint32_t UART_getIntr2Status(uint32_t baseAddr);
1067 
1082 static inline uint32_t UART_checkCharsAvailInFifo(uint32_t baseAddr);
1083 
1094 static inline uint32_t UART_readLineStatus(uint32_t baseAddr);
1095 
1109 static inline uint8_t UART_getCharFifo(uint32_t baseAddr, uint8_t *readBuf);
1110 /* ========================================================================== */
1111 /* Advanced Function Definitions */
1112 /* ========================================================================== */
1113 static inline void UART_putChar(uint32_t baseAddr, uint8_t byteTx)
1114 {
1115  /* Write the byte to the Transmit Holding Register(or TX FIFO). */
1116  HW_WR_REG32(baseAddr + UART_THR, (uint32_t) byteTx);
1117 }
1118 
1119 static inline uint32_t UART_getChar(uint32_t baseAddr, uint8_t *pChar)
1120 {
1121  uint32_t lcrRegValue = 0U;
1122  uint32_t retVal = FALSE;
1123 
1124  /* Preserving the current value of LCR. */
1125  lcrRegValue = HW_RD_REG32(baseAddr + UART_LCR);
1126 
1127  /* Switching to Register Operational Mode of operation. */
1128  HW_WR_REG32(baseAddr + UART_LCR, HW_RD_REG32(baseAddr + UART_LCR)
1129  & 0x7FU);
1130 
1131  /* Checking if the RX FIFO(or RHR) has atleast one byte of data. */
1132  if ((uint32_t) UART_LSR_RX_FIFO_E_RX_FIFO_E_VALUE_0 !=
1133  (HW_RD_REG32(baseAddr + UART_LSR) &
1134  UART_LSR_RX_FIFO_E_MASK))
1135  {
1136  uint32_t tempRetVal = HW_RD_REG32(baseAddr + UART_RHR);
1137  *pChar = (uint8_t)tempRetVal;
1138  retVal = TRUE;
1139  }
1140 
1141  /* Restoring the value of LCR. */
1142  HW_WR_REG32(baseAddr + UART_LCR, lcrRegValue);
1143 
1144  return retVal;
1145 }
1146 
1147 static inline void UART_intrEnable(uint32_t baseAddr, uint32_t intrFlag)
1148 {
1149  uint32_t enhanFnBitVal = 0U;
1150  uint32_t lcrRegValue = 0U;
1151 
1152  /* Switch to mode B only when the upper 4 bits of IER needs to be changed */
1153  if ((intrFlag & 0xF0U) > 0U)
1154  {
1155  /* Preserving the current value of LCR. */
1156  lcrRegValue = HW_RD_REG32(baseAddr + UART_LCR);
1157  /* Switching to Register Configuration Mode B. */
1158  HW_WR_REG32(baseAddr + UART_LCR, UART_REG_CONFIG_MODE_B & 0xFFU);
1159 
1160  /* Collecting the current value of EFR[4] and later setting it. */
1161  enhanFnBitVal = HW_RD_FIELD32(baseAddr + UART_EFR, UART_EFR_ENHANCED_EN);
1162 
1163  HW_WR_FIELD32(baseAddr + UART_EFR, UART_EFR_ENHANCED_EN,
1164  UART_EFR_ENHANCED_EN_ENHANCED_EN_U_VALUE_1);
1165 
1166  /* Restoring the value of LCR. */
1167  HW_WR_REG32(baseAddr + UART_LCR, lcrRegValue);
1168 
1169  /* Preserving the current value of LCR. */
1170  lcrRegValue = HW_RD_REG32(baseAddr + UART_LCR);
1171 
1172  /* Switching to Register Operational Mode of operation. */
1173  HW_WR_REG32(baseAddr + UART_LCR, HW_RD_REG32(baseAddr + UART_LCR)
1174  & 0x7FU);
1175 
1176  /*
1177  ** It is suggested that the System Interrupts for UART in the
1178  ** Interrupt Controller are enabled after enabling the peripheral
1179  ** interrupts of the UART using this API. If done otherwise, there
1180  ** is a risk of LCR value not getting restored and illicit characters
1181  ** transmitted or received from/to the UART. The situation is explained
1182  ** below.
1183  ** The scene is that the system interrupt for UART is already enabled
1184  ** and the current API is invoked. On enabling the interrupts
1185  ** corresponding to IER[7:4] bits below, if any of those interrupt
1186  ** conditions already existed, there is a possibility that the control
1187  ** goes to Interrupt Service Routine (ISR) without executing the
1188  ** remaining statements in this API. Executing the remaining statements
1189  ** is critical in that the LCR value is restored in them.
1190  ** However, there seems to be no risk in this API for enabling
1191  ** interrupts corresponding to IER[3:0] because it is done at the end
1192  ** and no statements follow that.
1193  */
1194 
1195  /************* ATOMIC STATEMENTS START *************************/
1196 
1197  /* Programming the bits IER[7:4]. */
1198  HW_WR_REG32(baseAddr + UART_IER, intrFlag & 0xF0U);
1199 
1200  /* Restoring the value of LCR. */
1201  HW_WR_REG32(baseAddr + UART_LCR, lcrRegValue);
1202 
1203  /* Preserving the current value of LCR. */
1204  lcrRegValue = HW_RD_REG32(baseAddr + UART_LCR);
1205  /* Switching to Register Configuration Mode B. */
1206  HW_WR_REG32(baseAddr + UART_LCR, UART_REG_CONFIG_MODE_B & 0xFFU);
1207 
1208  /* Restoring the value of EFR[4] to its original value. */
1209  HW_WR_FIELD32(baseAddr + UART_EFR, UART_EFR_ENHANCED_EN, enhanFnBitVal);
1210 
1211  /* Restoring the value of LCR. */
1212  HW_WR_REG32(baseAddr + UART_LCR, lcrRegValue);
1213 
1214  /************** ATOMIC STATEMENTS END *************************/
1215  }
1216 
1217  /* Programming the bits IER[3:0]. */
1218  HW_WR_REG32(baseAddr + UART_IER, HW_RD_REG32(baseAddr + UART_IER) |
1219  (intrFlag & 0x0FU));
1220 }
1221 
1222 static inline void UART_intrDisable(uint32_t baseAddr, uint32_t intrFlag)
1223 {
1224  uint32_t enhanFnBitVal;
1225  uint32_t lcrRegValue;
1226 
1227  /* Switch to mode B only when the upper 4 bits of IER needs to be changed */
1228  if((intrFlag & 0xF0U) > 0U)
1229  {
1230  /* Preserving the current value of LCR. */
1231  lcrRegValue = HW_RD_REG32(baseAddr + UART_LCR);
1232  /* Switching to Register Configuration Mode B. */
1233  HW_WR_REG32(baseAddr + UART_LCR, UART_REG_CONFIG_MODE_B & 0xFFU);
1234 
1235  /* Collecting the current value of EFR[4] and later setting it. */
1236  enhanFnBitVal = HW_RD_FIELD32(baseAddr + UART_EFR, UART_EFR_ENHANCED_EN);
1237 
1238  HW_WR_FIELD32(baseAddr + UART_EFR, UART_EFR_ENHANCED_EN,
1239  UART_EFR_ENHANCED_EN_ENHANCED_EN_U_VALUE_1);
1240 
1241  /* Restoring the value of LCR. */
1242  HW_WR_REG32(baseAddr + UART_LCR, lcrRegValue);
1243  }
1244 
1245  /* Preserving the current value of LCR. */
1246  lcrRegValue = HW_RD_REG32(baseAddr + UART_LCR);
1247 
1248  /* Switching to Register Operational Mode of operation. */
1249  HW_WR_REG32(baseAddr + UART_LCR, HW_RD_REG32(baseAddr + UART_LCR)
1250  & 0x7FU);
1251 
1252  HW_WR_REG32(baseAddr + UART_IER, HW_RD_REG32(baseAddr + UART_IER) &
1253  ~(intrFlag & 0xFFU));
1254 
1255  /* Restoring the value of LCR. */
1256  HW_WR_REG32(baseAddr + UART_LCR, lcrRegValue);
1257 
1258  /* Switch to mode B only when the upper 4 bits of IER needs to be changed */
1259  if((intrFlag & 0xF0U) > 0U)
1260  {
1261  /* Preserving the current value of LCR. */
1262  lcrRegValue = HW_RD_REG32(baseAddr + UART_LCR);
1263  /* Switching to Register Configuration Mode B. */
1264  HW_WR_REG32(baseAddr + UART_LCR, UART_REG_CONFIG_MODE_B & 0xFFU);
1265 
1266  /* Restoring the value of EFR[4] to its original value. */
1267  HW_WR_FIELD32(baseAddr + UART_EFR, UART_EFR_ENHANCED_EN, enhanFnBitVal);
1268 
1269  /* Restoring the value of LCR. */
1270  HW_WR_REG32(baseAddr + UART_LCR, lcrRegValue);
1271  }
1272 }
1273 
1274 static inline void UART_intr2Enable(uint32_t baseAddr, uint32_t intrFlag)
1275 {
1276  /* Programming the bits IER2[1:0]. */
1277  HW_WR_REG32(baseAddr + UART_IER2, HW_RD_REG32(baseAddr + UART_IER2) |
1278  (intrFlag & 0x03U));
1279 }
1280 
1281 static inline void UART_intr2Disable(uint32_t baseAddr, uint32_t intrFlag)
1282 {
1283  HW_WR_REG32(baseAddr + UART_IER2, HW_RD_REG32(baseAddr + UART_IER2) &
1284  ~(intrFlag & 0x3U));
1285 }
1286 
1287 static inline uint32_t UART_getIntrIdentityStatus(uint32_t baseAddr)
1288 {
1289  uint32_t lcrRegValue = 0U;
1290  uint32_t retVal = 0U;
1291 
1292  /* Preserving the current value of LCR. */
1293  lcrRegValue = HW_RD_REG32(baseAddr + UART_LCR);
1294 
1295  /* Switching to Register Operational Mode of operation. */
1296  HW_WR_REG32(baseAddr + UART_LCR, HW_RD_REG32(baseAddr + UART_LCR)
1297  & 0x7FU);
1298 
1299  retVal = HW_RD_REG32(baseAddr + UART_IIR) & UART_IIR_IT_TYPE_MASK;
1300 
1301  /* Restoring the value of LCR. */
1302  HW_WR_REG32(baseAddr + UART_LCR, lcrRegValue);
1303 
1304  return retVal;
1305 }
1306 
1307 static inline uint32_t UART_getIntr2Status(uint32_t baseAddr)
1308 {
1309  uint32_t retVal = 0U;
1310 
1311  retVal = HW_RD_REG32(baseAddr + UART_ISR2) &
1312  (UART_IER2_EN_RXFIFO_EMPTY_MASK | UART_IER2_EN_TXFIFO_EMPTY_MASK);
1313 
1314  return retVal;
1315 }
1316 
1317 static inline uint32_t UART_checkCharsAvailInFifo(uint32_t baseAddr)
1318 {
1319  uint32_t lcrRegValue = 0;
1320  uint32_t retVal = FALSE;
1321 
1322  /* Preserving the current value of LCR. */
1323  lcrRegValue = HW_RD_REG32(baseAddr + UART_LCR);
1324 
1325  /* Switching to Register Operational Mode of operation. */
1326  HW_WR_REG32(baseAddr + UART_LCR, HW_RD_REG32(baseAddr + UART_LCR)
1327  & 0x7FU);
1328 
1329  /* Checking if the RHR(or RX FIFO) has atleast one byte to be read. */
1330  if ((uint32_t) UART_LSR_RX_FIFO_E_RX_FIFO_E_VALUE_0 !=
1331  (HW_RD_REG32(baseAddr + UART_LSR) &
1332  UART_LSR_RX_FIFO_E_MASK))
1333  {
1334  retVal = (uint32_t) TRUE;
1335  }
1336 
1337  /* Restoring the value of LCR. */
1338  HW_WR_REG32(baseAddr + UART_LCR, lcrRegValue);
1339 
1340  return retVal;
1341 }
1342 
1343 static inline uint32_t UART_readLineStatus(uint32_t baseAddr)
1344 {
1345  uint32_t lcrRegValue = 0U;
1346  uint32_t retVal = 0U;
1347 
1348  /* Preserving the current value of LCR. */
1349  lcrRegValue = HW_RD_REG32(baseAddr + UART_LCR);
1350 
1351  /* Switching to Register Operational Mode of operation. */
1352  HW_WR_REG32(baseAddr + UART_LCR, HW_RD_REG32(baseAddr + UART_LCR)
1353  & 0x7FU);
1354 
1355  retVal = HW_RD_REG32(baseAddr + UART_LSR);
1356 
1357  /* Restoring the value of LCR. */
1358  HW_WR_REG32(baseAddr + UART_LCR, lcrRegValue);
1359 
1360  return retVal;
1361 }
1362 
1363 static inline uint8_t UART_getCharFifo(uint32_t baseAddr, uint8_t *readBuf)
1364 {
1365  uint8_t readByte = 0;
1366  uint32_t waitCount = UART_ERROR_COUNT;
1367  uint32_t errorVal;
1368  uint32_t lcrRegValue = 0;
1369 
1370  /* Preserving the current value of LCR. */
1371  lcrRegValue = HW_RD_REG32(baseAddr + UART_LCR);
1372 
1373  /* Switching to Register Operational Mode of operation. */
1374  HW_WR_REG32(baseAddr + UART_LCR, HW_RD_REG32(baseAddr + UART_LCR)
1375  & 0x7FU);
1376 
1377  /* Read Rx Error Status */
1378  errorVal = HW_RD_REG32(baseAddr + UART_LSR) &
1379  (UART_LSR_RX_FIFO_STS_MASK |
1380  UART_LSR_RX_BI_MASK |
1381  UART_LSR_RX_FE_MASK |
1382  UART_LSR_RX_PE_MASK |
1383  UART_LSR_RX_OE_MASK);
1384 
1385  /* Restoring the value of LCR. */
1386  HW_WR_REG32(baseAddr + UART_LCR, lcrRegValue);
1387 
1388  /* Read and throw Erroneous bytes from RxFIFO */
1389  while ((UART_LSR_RX_FIFO_STS_MASK |
1390  UART_LSR_RX_BI_MASK |
1391  UART_LSR_RX_FE_MASK |
1392  UART_LSR_RX_PE_MASK |
1393  UART_LSR_RX_OE_MASK) == errorVal)
1394  {
1395  readByte = HW_RD_REG32(baseAddr + UART_RHR);
1396  waitCount--;
1397  if (0U == waitCount)
1398  {
1399  break;
1400  }
1401 
1402  /* Preserving the current value of LCR. */
1403  lcrRegValue = HW_RD_REG32(baseAddr + UART_LCR);
1404 
1405  /* Switching to Register Operational Mode of operation. */
1406  HW_WR_REG32(baseAddr + UART_LCR, HW_RD_REG32(baseAddr + UART_LCR)
1407  & 0x7FU);
1408 
1409  /* Read Rx Error Status */
1410  errorVal = HW_RD_REG32(baseAddr + UART_LSR) &
1411  (UART_LSR_RX_FIFO_STS_MASK |
1412  UART_LSR_RX_BI_MASK |
1413  UART_LSR_RX_FE_MASK |
1414  UART_LSR_RX_PE_MASK |
1415  UART_LSR_RX_OE_MASK);
1416 
1417  /* Restoring the value of LCR. */
1418  HW_WR_REG32(baseAddr + UART_LCR, lcrRegValue);
1419  }
1420 
1421  /* Read non-erroneous byte from RxFIFO */
1422  readByte = HW_RD_REG32(baseAddr + UART_RHR);
1423 
1424  return readByte;
1425 }
1426 
1427 #ifdef __cplusplus
1428 }
1429 #endif
1430 
1431 #endif /* #ifndef UART_V0_H_ */
1432 
UART_enableLoopbackMode
void UART_enableLoopbackMode(uint32_t baseAddr)
Function to enable loopback mode. This function is for internal use. Not recommended for customers to...
UART_deinit
void UART_deinit(void)
This function de-initializes the UART module.
UART_Object::readTransferSem
void * readTransferSem
Definition: uart/v0/uart.h:560
UART_ERROR_COUNT
#define UART_ERROR_COUNT
Count Value to check error in the recieved byte
Definition: uart/v0/uart.h:82
UART_TRANSFER_MODE_BLOCKING
#define UART_TRANSFER_MODE_BLOCKING
UART read/write APIs blocks execution. This mode can only be used when called within a Task context.
Definition: uart/v0/uart.h:138
UART_Object::lockObj
SemaphoreP_Object lockObj
Definition: uart/v0/uart.h:558
UART_Transaction_init
static void UART_Transaction_init(UART_Transaction *trans)
Function to initialize the UART_Transaction struct to its defaults.
Definition: uart/v0/uart.h:852
UART_Object::readTransferSemObj
SemaphoreP_Object readTransferSemObj
Definition: uart/v0/uart.h:563
UART_REG_CONFIG_MODE_B
#define UART_REG_CONFIG_MODE_B
Definition: uart/v0/uart.h:396
UART_STOPBITS_1
#define UART_STOPBITS_1
Definition: uart/v0/uart.h:195
UART_TRANSFER_STATUS_SUCCESS
#define UART_TRANSFER_STATUS_SUCCESS
Transaction success.
Definition: uart/v0/uart.h:96
UART_Object::handle
UART_Handle handle
Definition: uart/v0/uart.h:518
UART_intr2Enable
static void UART_intr2Enable(uint32_t baseAddr, uint32_t intrFlag)
This API enables the specified interrupts in the UART mode of operation for IER2.
Definition: uart/v0/uart.h:1274
UART_Object::hwiHandle
void * hwiHandle
Definition: uart/v0/uart.h:570
index
uint16_t index
Definition: tisci_rm_proxy.h:3
UART_Object::writeBuf
const void * writeBuf
Definition: uart/v0/uart.h:525
SystemP.h
UART_Transaction::timeout
uint32_t timeout
Definition: uart/v0/uart.h:416
UART_Handle
void * UART_Handle
A handle that is returned from a UART_open() call.
Definition: uart/v0/uart.h:85
UART_Object::writeTrans
UART_Transaction * writeTrans
Definition: uart/v0/uart.h:549
UART_getHandle
UART_Handle UART_getHandle(uint32_t index)
Function to return a open'ed UART handle given a UART instance index.
UART_writeCancel
int32_t UART_writeCancel(UART_Handle handle, UART_Transaction *trans)
Function to perform UART canceling of current write transaction.
UART_Config
UART global configuration array.
Definition: uart/v0/uart.h:583
UART_Params::writeMode
uint32_t writeMode
Definition: uart/v0/uart.h:458
UART_getIntr2Status
static uint32_t UART_getIntr2Status(uint32_t baseAddr)
This API determines the UART Interrupt Status 2.
Definition: uart/v0/uart.h:1307
UART_Object::writeSizeRemaining
uint32_t writeSizeRemaining
Definition: uart/v0/uart.h:529
UART_CallbackFxn
void(* UART_CallbackFxn)(UART_Handle handle, UART_Transaction *transaction)
The definition of a callback function used by the UART driver when used in UART_TRANSFER_MODE_CALLBAC...
Definition: uart/v0/uart.h:431
UART_Params::dataLength
uint32_t dataLength
Definition: uart/v0/uart.h:448
SystemP_WAIT_FOREVER
#define SystemP_WAIT_FOREVER
Value to use when needing a timeout of infinity or wait forver until resource is available.
Definition: SystemP.h:83
UART_Params::intrPriority
uint8_t intrPriority
Definition: uart/v0/uart.h:476
UART_write
int32_t UART_write(UART_Handle handle, UART_Transaction *trans)
Function to perform UART write operation.
UART_Params::readMode
uint32_t readMode
Definition: uart/v0/uart.h:454
UART_RXTRIGLVL_8
#define UART_RXTRIGLVL_8
Definition: uart/v0/uart.h:265
UART_Params::intrEnable
uint32_t intrEnable
Definition: uart/v0/uart.h:472
SemaphoreP.h
UART_intrDisable
static void UART_intrDisable(uint32_t baseAddr, uint32_t intrFlag)
This API disables the specified interrupts in the UART mode of operation.
Definition: uart/v0/uart.h:1222
UART_disableLoopbackMode
void UART_disableLoopbackMode(uint32_t baseAddr)
Function to disable loopback mode. This function is for internal use. Not recommended for customers t...
UART_PARITY_NONE
#define UART_PARITY_NONE
Definition: uart/v0/uart.h:207
UART_Params::rxTrigLvl
uint32_t rxTrigLvl
Definition: uart/v0/uart.h:488
UART_getChar
static uint32_t UART_getChar(uint32_t baseAddr, uint8_t *pChar)
This API reads a byte from the Receiver Buffer Register (RBR). It checks once if any character is rea...
Definition: uart/v0/uart.h:1119
UART_close
void UART_close(UART_Handle handle)
Function to close a UART peripheral specified by the UART handle.
gUartConfig
UART_Config gUartConfig[]
Externally defined driver configuration array.
UART_getIntrIdentityStatus
static uint32_t UART_getIntrIdentityStatus(uint32_t baseAddr)
This API determines the UART Interrupt Status.
Definition: uart/v0/uart.h:1287
UART_Transaction::args
void * args
Definition: uart/v0/uart.h:420
UART_READ_RETURN_MODE_FULL
#define UART_READ_RETURN_MODE_FULL
Unblock/callback when buffer is full.
Definition: uart/v0/uart.h:166
UART_Object::isOpen
uint32_t isOpen
Definition: uart/v0/uart.h:554
UART_flushTxFifo
void UART_flushTxFifo(UART_Handle handle)
Function to flush a TX FIFO of peripheral specified by the UART handle.
UART_Params::skipIntrReg
uint32_t skipIntrReg
Definition: uart/v0/uart.h:478
UART_Config::attrs
UART_Attrs * attrs
Definition: uart/v0/uart.h:584
UART_Params::dmaEnable
uint32_t dmaEnable
Definition: uart/v0/uart.h:480
UART_Object::writeTransferSemObj
SemaphoreP_Object writeTransferSemObj
Definition: uart/v0/uart.h:568
UART_Object::lock
void * lock
Definition: uart/v0/uart.h:556
UART_Object::readCount
uint32_t readCount
Definition: uart/v0/uart.h:536
UART_Params::parityType
uint32_t parityType
Definition: uart/v0/uart.h:452
UART_Object::rxTimeoutCnt
uint32_t rxTimeoutCnt
Definition: uart/v0/uart.h:540
UART_putChar
static void UART_putChar(uint32_t baseAddr, uint8_t byteTx)
This API writes a byte to the Transmitter FIFO without checking for the emptiness of the Transmitter ...
Definition: uart/v0/uart.h:1113
UART_Object::writeCount
uint32_t writeCount
Definition: uart/v0/uart.h:527
UART_Params::hwFlowControl
uint32_t hwFlowControl
Definition: uart/v0/uart.h:464
UART_Object::readSizeRemaining
uint32_t readSizeRemaining
Definition: uart/v0/uart.h:538
UART_Params::readReturnMode
uint32_t readReturnMode
Definition: uart/v0/uart.h:456
HwiP.h
UART_init
void UART_init(void)
This function initializes the UART module.
UART_Params
UART Parameters.
Definition: uart/v0/uart.h:445
UART_readCancel
int32_t UART_readCancel(UART_Handle handle, UART_Transaction *trans)
Function to perform UART canceling of current read transaction.
UART_Params::baudRate
uint32_t baudRate
Definition: uart/v0/uart.h:446
UART_Params::readCallbackFxn
UART_CallbackFxn readCallbackFxn
Definition: uart/v0/uart.h:460
UART_Object::readErrorCnt
uint32_t readErrorCnt
Definition: uart/v0/uart.h:542
UART_Object::writeTransferSem
void * writeTransferSem
Definition: uart/v0/uart.h:565
UART_Transaction::status
uint32_t status
Definition: uart/v0/uart.h:418
UART_Config::object
UART_Object * object
Definition: uart/v0/uart.h:586
UART_Transaction
Data structure used with UART_read() and UART_write()
Definition: uart/v0/uart.h:408
UART_getBaseAddr
uint32_t UART_getBaseAddr(UART_Handle handle)
Function to get base address of UART instance of a particular handle.
UART_LEN_8
#define UART_LEN_8
Definition: uart/v0/uart.h:184
UART_checkCharsAvailInFifo
static uint32_t UART_checkCharsAvailInFifo(uint32_t baseAddr)
This API checks if the RX FIFO (or RHR in non-FIFO mode) has atleast one byte of data to be read.
Definition: uart/v0/uart.h:1317
UART_Params::intrNum
uint32_t intrNum
Definition: uart/v0/uart.h:474
UART_Attrs::inputClkFreq
uint32_t inputClkFreq
Definition: uart/v0/uart.h:502
UART_open
UART_Handle UART_open(uint32_t index, const UART_Params *prms)
This function opens a given UART peripheral.
UART_Params::writeCallbackFxn
UART_CallbackFxn writeCallbackFxn
Definition: uart/v0/uart.h:462
HwiP_Object
Opaque Hwi object used with the Hwi APIs.
Definition: HwiP.h:91
UART_Object
UART driver object.
Definition: uart/v0/uart.h:514
UART_Params::hwFlowControlThr
uint32_t hwFlowControlThr
Definition: uart/v0/uart.h:466
UART_Object::readTrans
UART_Transaction * readTrans
Definition: uart/v0/uart.h:547
UART_Params::stopBits
uint32_t stopBits
Definition: uart/v0/uart.h:450
UART_intr2Disable
static void UART_intr2Disable(uint32_t baseAddr, uint32_t intrFlag)
This API disables the specified interrupts in the UART mode of operation for IER2.
Definition: uart/v0/uart.h:1281
UART_Object::readBuf
void * readBuf
Definition: uart/v0/uart.h:534
UART_Params_init
static void UART_Params_init(UART_Params *prms)
Function to initialize the UART_Params struct to its defaults.
Definition: uart/v0/uart.h:826
gUartConfigNum
uint32_t gUartConfigNum
Externally defined driver configuration array size.
SemaphoreP_Object
Opaque semaphore object used with the semaphore APIs.
Definition: SemaphoreP.h:59
UART_read
int32_t UART_read(UART_Handle handle, UART_Transaction *trans)
Function to perform UART read operation.
UART_TXTRIGLVL_32
#define UART_TXTRIGLVL_32
Definition: uart/v0/uart.h:282
UART_OPER_MODE_16X
#define UART_OPER_MODE_16X
Definition: uart/v0/uart.h:294
UART_Attrs
UART instance attributes - used during init time.
Definition: uart/v0/uart.h:496
UART_RXTRIGLVL_16
#define UART_RXTRIGLVL_16
Definition: uart/v0/uart.h:266
UART_readLineStatus
static uint32_t UART_readLineStatus(uint32_t baseAddr)
This API reads the line status register value.
Definition: uart/v0/uart.h:1343
UART_getCharFifo
static uint8_t UART_getCharFifo(uint32_t baseAddr, uint8_t *readBuf)
This API reads the data present at the top of the RX FIFO, that is, the data in the Receive Holding R...
Definition: uart/v0/uart.h:1363
UART_Attrs::baseAddr
uint32_t baseAddr
Definition: uart/v0/uart.h:500
UART_Transaction::buf
void * buf
Definition: uart/v0/uart.h:409
UART_intrEnable
static void UART_intrEnable(uint32_t baseAddr, uint32_t intrFlag)
This API enables the specified interrupts in the UART mode of operation.
Definition: uart/v0/uart.h:1147
UART_Object::hwiObj
HwiP_Object hwiObj
Definition: uart/v0/uart.h:572
UART_Object::prms
UART_Params prms
Definition: uart/v0/uart.h:520
UART_Transaction::count
uint32_t count
Definition: uart/v0/uart.h:412
UART_Params::txTrigLvl
uint32_t txTrigLvl
Definition: uart/v0/uart.h:490
UART_Params::operMode
uint32_t operMode
Definition: uart/v0/uart.h:486