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AM64x MCU+ SDK
08.01.00
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34 #ifndef CSLR_SOC_DEFINES_H_
35 #define CSLR_SOC_DEFINES_H_
51 #if defined(__aarch64__)
52 #define CSL_CACHE_L1P_LINESIZE (64U)
53 #define CSL_CACHE_L1D_LINESIZE (64U)
54 #define CSL_CACHE_L2_LINESIZE (64U)
55 #elif (__ARM_ARCH == 7) && (__ARM_ARCH_PROFILE == 'R')
56 #define CSL_CACHE_L1P_LINESIZE (32U)
57 #define CSL_CACHE_L1D_LINESIZE (32U)
58 #elif (__ARM_ARCH == 7) && (__ARM_ARCH_PROFILE == 'M')
68 #define CSL_CORE_ID_M4FSS0_0 (0U)
69 #define CSL_CORE_ID_R5FSS0_0 (1U)
70 #define CSL_CORE_ID_R5FSS0_1 (2U)
71 #define CSL_CORE_ID_R5FSS1_0 (3U)
72 #define CSL_CORE_ID_R5FSS1_1 (4U)
73 #define CSL_CORE_ID_A53SS0_0 (5U)
74 #define CSL_CORE_ID_A53SS0_1 (6U)
75 #define CSL_CORE_ID_MAX (7U)
79 #define CSL_EPWM_PER_CNT (9U)
84 #define MCAN_MSG_RAM_MAX_WORD_COUNT (4352U)