AM64x MCU+ SDK  08.01.00
Enet Layer 2 ICSSG Example

Table of Contents

Introduction

The layer 2 icssg example is dedicated to demonstrate usage of Enet with ICSSG peripheral operation.

On AM64X, we can do ethernet based communication using ICSSG HW Mechanism

This example do below:

  • Target-side application running on a Cortex R5F core.
    • Application receives the packet, copies the payload into a new packet which is then sent back.
    • The application has a menu to enable/disable features, such as getting mac address and stats. This menu along with application logs are implemented via UART.
  • Host-side functionality
    • Software applications like Colasoft Pkt Builder or packETH tool could be used to generate and send packets, Wireshark can be used to receive and verify packet contents
  • The data path enabled in this example is as follows:
    • Host side (PC) application sends a packet to MAC port.
    • Based on Switch mode or Dual-EMAC mode the data flow will differ.
    • In Switch mode:
      • If packet is non directed unicast(UC) packet, it will be only forwarded.
      • If packet is directed unicast(UC) packet, it will be sent only to target application.
      • If packet is multicast(MC) or broadcast(BC) packet, it will be forwarded as well as sent to target application.
    • In Dual-mac mode:
      • If packet is Non directed unicast(UC) packet it will be dropped.
      • If packet is directed unicast(UC) or multicast(MC) or broadcast(BC) packet, it will be sent to target application.
      • Currently to test both MAC ports simultaneously in Dual-MAC mode it requires additional enet lld(UDMA channel allocation) changes.
    • Target side application receives the packet, updates the MAC addresses in the Layer-2 header and sends the packet back.
    • Application like Wireshark (PC) receives the packet and can be seen in the capture window.

Supported Combinations

Parameter Value
CPU + OS r5fss0-0_freertos
Toolchain ti-arm-clang
Board am64x-evm
Icssg Instance ICSSG1
Example folder examples/networking/enet_layer2_icssg

Steps to Run the Example

Build the example

  • When using CCS projects to build, import the CCS project for the required combination and build it using the CCS project menu (see Using SDK with CCS Projects).
  • When using makefiles to build, note the required combination and build using make command (see Using SDK with Makefiles)
Note
Enable the ENET_TEST_MII_MODE macro in test application and change the mode to MII from RGMII in SysConfig and rebuid the application to test the ICSSG ports in MII mode.

HW Setup

Note
Make sure you have setup the EVM with cable connections as shown here, EVM Setup. In addition do below steps.

AM64X-EVM

For ICSSG based example

  • Connect two ethernet cables to the EVM from two host PC's as shown below

Ethernet cable for ICSS based ethernet

Run the example

Attention
If you need to reload and run again, a CPU power-cycle is MUST
  • Launch a CCS debug session and run the example executable, see CCS Launch, Load and Run
  • You will see logs in the UART terminal as shown in the next section.
  • We can start sending packets from Colasoft Pkt Builder or packETH tool and capture the packets in Wireshark.

Sample output for Layer2 ICSSG example

==========================
MULTIPORT TEST
==========================
Init Enet's OSAL and utils to use defaults
Init memory utils
Create clock and task for periodic tick
Create periodic tick task
Create periodic tick clock
Open Main UDMA driver
Init all peripheral clocks
----------------------------------------------
Enabling clocks!
Init all configs
----------------------------------------------
icssg1: init config
Open all peripherals
----------------------------------------------
icssg1: Open enet
icssg1: Register async IOCTL callback
icssg1: Register TX timestamp callback
Attach core id 1 on all peripherals
----------------------------------------------
icssg1: Attach core
Create RX tasks
----------------------------------------------
icssg1: Create RX task
icssg1: Open port 1
icssg1: Open port 1 link
EnetPhy_bindDriver: PHY 15: OUI:080028 Model:0f Ver:01 <-> 'dp83869' : OK
icssg1: Open port 2
icssg1: Open port 2 link
EnetPhy_bindDriver: PHY 3: OUI:080028 Model:0f Ver:01 <-> 'dp83869' : OK
icssg1: Waiting for link up...
Enet Multiport Menu:
's' - Print statistics
'r' - Reset statistics
'm' - Show allocated MAC addresses
'x' - Stop the test
Icssg_handleLinkUp: icssg1: Port 1: Link up: 1-Gbps Full-Duplex
Icssg_handleLinkUp: icssg1: Port 2: Link up: 1-Gbps Full-Duplex
icssg1: Port 1 link is up
icssg1: Set port state to 'Forward'
icssg1: Async IOCTL completed
icssg1: Async IOCTL completed
icssg1: Port 2 link is up
icssg1: Set port state to 'Forward'
icssg1: Async IOCTL completed
icssg1: Async IOCTL completed
icssg1: Open DMA
initQs() txFreePktInfoQ initialized with 8 pkts
icssg1: Set MAC addr: 70:ff:76:1d:92:c1
icssg1: MAC port addr: 70:ff:76:1d:92:c1
m
Allocated MAC addresses
----------------------------------------------
icssg1: 70:ff:76:1d:92:c1
s
Print statistics
----------------------------------------------
icssg1 - PA statistics
--------------------------------
hostRxByteCnt = 2560
hostTxByteCnt = 2480
hostRxPktCnt = 20
hostTxPktCnt = 20
icssg1 - Port 1 statistics
--------------------------------
rxGoodFrames = 10
rxBCastFrames = 10
rxMCastFrames = 10
rxClass8 = 10
rxClass9 = 10
rxBucket2SizedFrame = 10
rxTotalByte = 1280
rxTxTotalByte = 4000
txGoodFrame = 20
txBcastFrame = 10
txMcastFrame = 10
txBucket3SizedFrame = 20
txTotalByte = 2720
icssg1 - Port 2 statistics
--------------------------------
rxGoodFrames = 10
rxBCastFrames = 10
rxMCastFrames = 10
rxClass8 = 10
rxClass9 = 10
rxBucket2SizedFrame = 10
rxTotalByte = 1280
rxTxTotalByte = 4000
txGoodFrame = 20
txBcastFrame = 10
txMcastFrame = 10
txBucket3SizedFrame = 20
txTotalByte = 2720
  • On Wireshark we can see the packets received:

Wireshark log for Layer 2 ICSSG Example

See Also

Networking