AM64x MCU+ SDK  07.03.00
EtherCAT Slave

Table of Contents

Introduction

This software is designed for the TI SoCs with PRU-ICSS IP to enable customers add EtherCAT Slave protocol support to their system. It implements EtherCAT Slave Controller(ESC) Layer 2 functionality and provides EtherCAT ASIC like functionality integrated into TI SoCs.

Features Supported

  • EtherCAT Slave Controller
    • All EtherCAT Commands (NOP, APRD, APWR, APRW, FPRD, FPWR, FPRW, BRD, BWR, BRW, LRD, LWR, LRW, ARMW and FRMW)
    • 8 FMMU support
    • 8 SM support
    • 59KB of Process Data RAM
    • Distributed clocks
      • 64-bit DC
      • SYNC0 out generation single shot and cyclic mode support
      • SYNC1 out generation - SYNC1 cycle time multiple of SYNC0 cycle time
      • Latch0 and Latch1 inputs
      • System Time PDI control
    • DL Loop Control
      • Using MII_RX_LINK (fast - depending on PHY link loss detection latency) - mandatory for cable redundancy support
      • Using PRU-ICSS MDIO state machine - not recommended for cable redundancy support
    • Interrupts - AL/ECAT events
      • SYNC0, SYNC1 and PDI interrupt events on external SOC pins
    • Watchdog - PDI and SM
    • Error Counters
      • RX Invalid Frame Counter Port 0/1
      • RX ERR Counter Port 0/1
      • Forwarded Error Counter Port 0/1
      • ECAT Processing Unit Error Counter
    • LED - Run, Error and Port0/1 activity
    • EEPROM Emulation for ESI EEPROM support
    • Management Interface for PHY over EtherCAT
    • PHY address configuration and host side API for PHY programming
    • Cable redundancy support
    • Beckhoff EtherCAT Slave Stack Code (SSC) Version 5.12 based example

SysConfig Features

Note
It is strongly recommend to use SysConfig where it is available instead of using direct SW API calls. This will help simplify the SW application and also catch common mistakes early in the development cycle.

SysConfig can be used to configure things mentioned below:

  • Selecting the PRU-ICSS instance
  • Configuring PINMUX needed for MII mode
  • Configuring ETHPHY for the two PHY ports of PRU-ICSS

Features Not Supported

  • In general, peripherals or features not mentioned as part of “Features Supported” section are not supported in this release.
  • EtherCAT Slave Controller
    • ECAT side register protection when using LRD command
    • APRW/FPRW/BRW for SM mapped area
  • EtherCAT G
  • Reset Isolation
  • Online Firmware Upgrade

Known Issues

Record ID Details Workaround
MCUSDK-354 EtherCAT State Machine from EtherCAT Conformance Test fails intermittently This issue is seen with FreeRTOS library in release mode. Use debug mode library for FreeRTOS
PINDSW-47 Multiple FMMU access in a single datagram to a slave for process data using LRD/LWR commands Use LRW instead of LRD/LWR
PINDSW-72 PDI/PD watchdog counter incremented by 1 whenever PDI/PD watchdog is disabled None
PINDSW-74 LRD access on unused registers increment WKC - no register protection while using LRD None
PINDSW-141 LRW access to non-interleaved input and output process data of multiple slaves does not work. SOEM accesses slaves in LRW mode this way Use LRD/LWR for process data access or use more optimal interleaved access for process data access from Master (TwinCAT way)
PINDSW-2204 Frames with no SFD not counted as errors if received on reverse path None
PINDSW-2360 System time of next Sync0 pulse register (0x990:0x993) is not instantaneous, resulting in read of incorrect value if read immediately after sync pulse None
PINDSW-3120 Lost Link Counter register (0x310) increments with "2" on every link down instead of "1" Revert back the MDIO Link interrupt to Edge in tiesc_pruss_intc_mapping.h file. Customers need to make sure that above mentioned link stability issue is not seen in their setup before making this change.
PINDSW-4310 EtherCAT Slave in DC slave mode takes longer to recover from reference clock shifts None

For more details, please see the EtherCAT Slave Errata document.

Important Files and Directory Structure

Folder/Files Description
${SDK_INSTALL_PATH}/source/networking/ethercat_slave
icss_fwhal/firmware Firmware for the PRU cores in PRUICSS. Firmware Version : 5.4.242
icss_fwhal/lib/ Firmware (FW) HAL library for EtherCAT Slave
icss_fwhal/tiescbsp.h FWHAL interface file
icss_fwhal/etg_stack/esi ESI XML file for Beckhoff Slave Stack Code(SSC) based example
icss_fwhal/etg_stack/patch Patch file for Beckhoff Slave Stack Code(SSC) sources
icss_fwhal/etg_stack/stack_hal Stack adaptation APIs for Beckhoff Slave Stack Code(SSC)
icss_fwhal/etg_stack/stack_sources Folder where Beckhoff Slave Stack Code(SSC) sources should be copied. Stack sources are not packaged in the SDK

Block Diagram (Software Architecture)

Software Architecture

Procedure to kick-off the EtherCAT Slave Controller(ESC)

  • Initialize memories (register protection, register reset values, EEPROM cache) and PRUICSS INTC module. This is done by FWHAL.
  • Load firmware into PRUs of PRUICSS. This is done by FWHAL.
  • Enable the PRU cores. This is done by FWHAL.
  • Initialize the EtherCAT slave stack.
  • Wait for AL Event Request and SYNC (in DC synchronous mode) interrupts from PRU and run EtherCAT stack main loop for handling mailbox and ESC state machine.
  • Handle the events as needed. Note that this is handled by the stack.

FWHAL APIs

APIs implement the key interface between EtherCAT Slave Controller Emulation firmware and EtherCAT stack. Please see APIs for Ethercat Slave FWHAL for API documentation.

It is recommended to use these FWHAL APIs in the stack adaptation files. For example, see ${SDK_INSTALL_PATH}/source/networking/ethercat_slave/icss_fwhal/etg_stack/stack_hal, which contains the stack adaptation APIs for Slave Stack Code(SSC).

EtherCAT Slave Controller(ESC) Register List

TI EtherCAT Slave Controller Register List contains descriptions of the registers in TI's EtherCAT Slave Controller implementation.

EtherCAT Slave Controller(ESC) Exceptions

TI EtherCAT Slave Controller Exceptions lists the exceptions TI's EtherCAT Slave Controller implementation when compared with ET1100 ASIC. Please note that TI ESC is a 2 port EtherCAT slave and it does not support E-bus interface and all the corresponding register fields are not implemented.

Performance Benchmarking

EtherCAT Slave Example application was used for benchmarking. TwinCAT Master was used as the EtherCAT master for these tests.

Cycle Time

Lowest cycle time tested is 50 us(microseconds) with Distributed Clock(DC) Synchronization mode

Interrupt Processing Time

Following is the interrupt processing time for PDI and Sync ISRs with 50 us cycle time. The RxPDO size is 5 bytes and TxPDO size is 7 bytes in this example.

Scenario PDI ISR Processing Time (microseconds) SYNC0 ISR Processing Time (microseconds) SYNC1 ISR Processing Time (microseconds)
DC mode with SYNC0 enabled 2.7 3.2 0
DC mode with SYNC0 and SYNC1 enabled 2.7 0.8 2.6

Additional References

Please refer to below documents to understand more about EtherCAT slave on TI platforms and EtherCAT slave protocol specifications.

Document Description
EtherCAT on Sitara Processors Application note by TI on the EtherCAT slave implementation on TI's Sitara Processors.
PRU-ICSS EtherCAT Slave Troubleshooting Guide This troubleshooting guide is intend to provide guidance on how to set up and debug the EtherCAT slave implemented on TI's Sitara processors.
EtherCAT ESC Datasheet Section 1 - Technology Section 1 of Beckhoff's EtherCAT Slave Controller (ESC) documentation which decribes basic EtherCAT technology.
EtherCAT ESC Datasheet Section 2 - Register Description Section 2 of Beckhoff's EtherCAT Slave Controller (ESC) documentation which contains ESC register descriptions.
Application Note ET9300 (EtherCAT Slave Stack Code) This contains details on how to start EtherCAT Slave development with Slave Stack Code.
EtherCAT Slave Implementation Guide from EtherCAT Technology Group This contains information on how to develop a EtherCAT slave implementation.

See also