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AM62x MCU+ SDK
11.02.00
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Go to the documentation of this file.
54 #ifndef TISCI_PROTOCOL_H
55 #define TISCI_PROTOCOL_H
67 #define TISCI_MSG_FLAG_RESERVED0 TISCI_BIT(0)
75 #define TISCI_MSG_FLAG_AOP TISCI_BIT(1)
78 #define TISCI_MSG_FLAG_SEC TISCI_BIT(2)
84 #define TISCI_MSG_FLAG_ACK TISCI_BIT(1)
129 #define TISCI_MSG_VERSION (0x0002U)
130 #define TISCI_MSG_DM_VERSION (0x000FU)
131 #define TISCI_MSG_BOOT_NOTIFICATION (0x000AU)
132 #define TISCI_MSG_BOARD_CONFIG (0x000BU)
133 #define TISCI_MSG_BOARD_CONFIG_RM (0x000CU)
134 #define TISCI_MSG_BOARD_CONFIG_SECURITY (0x000DU)
135 #define TISCI_MSG_BOARD_CONFIG_PM (0x000EU)
137 #define TISCI_MSG_ENABLE_WDT (0x0000U)
138 #define TISCI_MSG_WAKE_RESET (0x0001U)
139 #define TISCI_MSG_WAKE_REASON (0x0003U)
140 #define TISCI_MSG_GOODBYE (0x0004U)
141 #define TISCI_MSG_SYS_RESET (0x0005U)
143 #define TISCI_MSG_QUERY_MSMC (0x0020U)
144 #define TISCI_MSG_GET_TRACE_CONFIG (0x0021U)
145 #define TISCI_MSG_QUERY_FW_CAPS (0x0022U)
147 #define TISCI_MSG_SET_CLOCK (0x0100U)
148 #define TISCI_MSG_GET_CLOCK (0x0101U)
149 #define TISCI_MSG_SET_CLOCK_PARENT (0x0102U)
150 #define TISCI_MSG_GET_CLOCK_PARENT (0x0103U)
151 #define TISCI_MSG_GET_NUM_CLOCK_PARENTS (0x0104U)
152 #define TISCI_MSG_SET_CLOCK_SSC (0x010aU)
153 #define TISCI_MSG_GET_CLOCK_SSC (0x010bU)
154 #define TISCI_MSG_SET_FREQ (0x010cU)
155 #define TISCI_MSG_QUERY_FREQ (0x010dU)
156 #define TISCI_MSG_GET_FREQ (0x010eU)
158 #define TISCI_MSG_SET_DEVICE (0x0200U)
159 #define TISCI_MSG_GET_DEVICE (0x0201U)
160 #define TISCI_MSG_SET_DEVICE_RESETS (0x0202U)
161 #define TISCI_MSG_DEVICE_DROP_POWERUP_REF (0x0203U)
163 #define TISCI_MSG_PREPARE_SLEEP (0x0300U)
164 #define TISCI_MSG_ENTER_SLEEP (0x0301U)
170 #define TISCI_MSG_SYNC_RESUME (0x0302U)
171 #define TISCI_MSG_CONTINUE_RESUME (0x0303U)
172 #define TISCI_MSG_CORE_RESUME (0x0304U)
173 #define TISCI_MSG_DM_ABORT_SLEEP (0x0305U)
174 #define TISCI_MSG_LPM_WAKE_REASON (0x0306U)
175 #define TISCI_MSG_SET_IO_ISOLATION (0x0307U)
176 #define TISCI_MSG_MIN_CONTEXT_RESTORE (0x0308U)
177 #define TISCI_MSG_LPM_SET_DEVICE_CONSTRAINT (0x0309U)
178 #define TISCI_MSG_LPM_SET_LATENCY_CONSTRAINT (0x030AU)
179 #define TISCI_MSG_LPM_GET_DEVICE_CONSTRAINT (0x030BU)
180 #define TISCI_MSG_LPM_GET_LATENCY_CONSTRAINT (0x030CU)
181 #define TISCI_MSG_LPM_GET_NEXT_SYS_MODE (0x030DU)
182 #define TISCI_MSG_LPM_GET_NEXT_HOST_STATE (0x030EU)
185 #define TISCI_MSG_LPM_ENCRYPT (0x030FU)
187 #define TISCI_MSG_LPM_DECRYPT (0x0310U)
188 #define TISCI_MSG_LPM_ABORT (0x0311U)
189 #define TISCI_MSG_GET_SUSPEND_INITIATOR (0x0312U)
190 #define TISCI_MSG_LPM_SAVE_ADDR (0x0313U)
192 #define TISCI_MSG_FIRMWARE_LOAD (0x8105U)
193 #define MSG_FIRMWARE_LOAD_RESULT (0x8805U)
196 #define TISCI_MSG_SET_FWL_REGION (0x9000U)
198 #define TISCI_MSG_GET_FWL_REGION (0x9001U)
200 #define TISCI_MSG_CHANGE_FWL_OWNER (0x9002U)
202 #define TISCI_MSG_CRYPTO_SET_DKEK (0x9003U)
204 #define TISCI_MSG_SA2UL_SET_DKEK TISCI_MSG_CRYPTO_SET_DKEK
206 #define TISCI_MSG_CRYPTO_RELEASE_DKEK (0x9004U)
208 #define TISCI_MSG_SA2UL_RELEASE_DKEK TISCI_MSG_CRYPTO_RELEASE_DKEK
210 #define TISCI_MSG_KEYSTORE_IMPORT_SKEY (0x9005U)
212 #define TISCI_MSG_KEYSTORE_ERASE_SKEY (0x9006U)
214 #define TISCI_MSG_SEC_RESERVED_9007 (0x9007U)
216 #define TISCI_MSG_SEC_RESERVED_9008 (0x9008U)
218 #define TISCI_MSG_SET_ISC_REGION (0x9009U)
220 #define TISCI_MSG_GET_ISC_REGION (0x900AU)
222 #define TISCI_MSG_FWL_EXCP_NOTIFICATION (0x900BU)
224 #define TISCI_MSG_OPEN_DEBUG_FWLS (0x900CU)
229 #define TISCI_MSG_KEYSTORE_WRITE (0x900DU)
234 #define TISCI_MSG_KEYSTORE_EXPORT_ALL (0x900EU)
236 #define TISCI_MSG_KEYSTORE_IMPORT_ALL (0x900FU)
238 #define TISCI_MSG_SEC_RESERVED_9010 (0x9010U)
240 #define TISCI_MSG_SEC_RESERVED_9011 (0x9011U)
242 #define TISCI_MSG_SEC_RESERVED_9012 (0x9012U)
244 #define TISCI_MSG_SEC_RESERVED_9013 (0x9013U)
246 #define TISCI_MSG_SEC_RESERVED_9014 (0x9014U)
248 #define TISCI_MSG_SEC_RESERVED_9015 (0x9015U)
251 #define TISCI_MSG_SEC_RESERVED_9016 (0x9016U)
254 #define TISCI_MSG_SA2UL_AUTH_RES_ACQUIRE (0x9017U)
257 #define TISCI_MSG_SA2UL_AUTH_RES_RELEASE (0x9018U)
260 #define TISCI_MSG_SEC_RESERVED_9020 (0x9020U)
263 #define TISCI_MSG_GET_SOC_UID (0x9021U)
269 #define TISCI_MSG_READ_OTP_MMR (0x9022U)
272 #define TISCI_MSG_WRITE_OTP_ROW (0x9023U)
275 #define TISCI_MSG_LOCK_OTP_ROW (0x9024U)
278 #define TISCI_MSG_SOFT_LOCK_OTP_WRITE_GLOBAL (0x9025U)
281 #define TISCI_MSG_GET_OTP_ROW_LOCK_STATUS (0x9026U)
284 #define TISCI_MSG_RSVD_OTP_1 (0x9027U)
287 #define TISCI_MSG_RSVD_OTP_2 (0x9028U)
290 #define TISCI_MSG_CRYPTO_GET_DKEK (0x9029U)
292 #define TISCI_MSG_SA2UL_GET_DKEK TISCI_MSG_CRYPTO_GET_DKEK
295 #define TISCI_MSG_ALLOW_FWL_CTRL_READ (0x902CU)
298 #define TISCI_MSG_FORBID_FWL_CTRL_READ (0x902DU)
303 #define TISCI_MSG_SEC_HANDOVER (0x9030U)
308 #define TISCI_MSG_KEY_WRITER (0x9031U)
311 #define TISCI_MSG_WRITE_SWREV (0x9032U)
314 #define TISCI_MSG_READ_SWREV (0x9033U)
317 #define TISCI_MSG_READ_KEYCNT_KEYREV (0x9034U)
320 #define TISCI_MSG_WRITE_KEYREV (0x9035U)
323 #define TISCI_MSG_CRYPTO_GET_DSMEK (0x9036U)
325 #define TISCI_MSG_SA2UL_GET_DSMEK TISCI_MSG_CRYPTO_GET_DSMEK
328 #define TISCI_MSG_CRYPTO_SET_DSMEK (0x9037U)
330 #define TISCI_MSG_SA2UL_SET_DSMEK TISCI_MSG_CRYPTO_SET_DSMEK
333 #define TISCI_MSG_CRYPTO_RELEASE_DSMEK (0x9038U)
335 #define TISCI_MSG_SA2UL_RELEASE_DSMEK TISCI_MSG_CRYPTO_RELEASE_DSMEK
338 #define TISCI_MSG_KEYRING_IMPORT (0X9039U)
341 #define TISCI_MSG_CRYPTO_SET_DKEK_CONST (0x902AU)
343 #define TISCI_MSG_SA2UL_SET_DKEK_CONST TISCI_MSG_CRYPTO_SET_DKEK_CONST
346 #define TISCI_MSG_CRYPTO_GET_DKEK_CONST (0x902BU)
348 #define TISCI_MSG_SA2UL_GET_DKEK_CONST TISCI_MSG_CRYPTO_GET_DKEK_CONST
351 #define TISCI_MSG_CRYPTO_AES_ENCRYPT (0x9040U)
353 #define TISCI_MSG_SA2UL_AES_ENCRYPT TISCI_MSG_CRYPTO_AES_ENCRYPT
356 #define TISCI_MSG_CRYPTO_AES_DECRYPT (0x9041U)
358 #define TISCI_MSG_SA2UL_AES_DECRYPT TISCI_MSG_CRYPTO_AES_DECRYPT
361 #define TISCI_MSG_DISABLE_JTAG_UNLOCK (0x9042U)
364 #define TISCI_MSG_DISABLE_JTAG_UNLOCK_CHECK (0x9043U)
367 #define TISCI_MSG_SET_OTP_BOOT_MODE (0x9044U)
370 #define TISCI_MSG_KEY_WRITER_LITE (0x9045U)
377 #define TISCI_MSG_PROC_REQUEST (0xC000U)
379 #define TISCI_MSG_PROC_RELEASE (0xC001U)
381 #define TISCI_MSG_PROC_HANDOVER (0xC005U)
384 #define TISCI_MSG_PROC_SET_CONFIG (0xC100U)
386 #define TISCI_MSG_PROC_SET_CONTROL (0xC101U)
389 #define TISCI_MSG_PROC_GET_STATUS (0xC400U)
392 #define TISCI_MSG_PROC_WAIT_STATUS (0xC401U)
395 #define TISCI_MSG_PROC_AUTH_BOOT (0xC120U)
398 #define TISCI_MSG_MCELF_PROC_AUTH_BOOT_INIT (0xC122U)
401 #define TISCI_MSG_MCELF_PROC_AUTH_BOOT_UPDATE (0xC123U)
407 #define TISCI_MSG_MCELF_PROC_AUTH_BOOT_FINISH (0xC124U)
410 #define TISCI_MSG_CONFIGURE_CC_REGISTER (0xC125U)
417 #define TISCI_MSG_RM_GET_RESOURCE_RANGE (0x1500U)
421 #define TISCI_MSG_RM_IRQ_SET (0x1000U)
425 #define TISCI_MSG_RM_IRQ_RELEASE (0x1001U)
427 #define TISCI_MSG_RM_RESERVED_1100 (0x1100U)
429 #define TISCI_MSG_RM_RESERVED_1101 (0x1101U)
431 #define TISCI_MSG_RM_RESERVED_1102 (0x1102U)
433 #define TISCI_MSG_RM_RESERVED_1103 (0x1103U)
437 #define TISCI_MSG_RM_RING_CFG (0x1110U)
439 #define TISCI_MSG_RM_RESERVED_1111 (0x1111U)
443 #define TISCI_MSG_RM_RING_MON_CFG (0x1120U)
445 #define TISCI_MSG_RM_RESERVED_1200 (0x1200U)
447 #define TISCI_MSG_RM_RESERVED_1201 (0x1201U)
451 #define TISCI_MSG_RM_UDMAP_TX_CH_CFG (0x1205U)
453 #define TISCI_MSG_RM_RESERVED_1206 (0x1206U)
455 #define TISCI_MSG_RM_RESERVED_1210 (0x1210U)
457 #define TISCI_MSG_RM_RESERVED_1211 (0x1211U)
461 #define TISCI_MSG_RM_UDMAP_RX_CH_CFG (0x1215U)
462 #define TISCI_MSG_RM_RESERVED_1216 (0x1216U)
464 #define TISCI_MSG_RM_RESERVED_1220 (0x1220U)
466 #define TISCI_MSG_RM_RESERVED_1221 (0x1221U)
470 #define TISCI_MSG_RM_UDMAP_FLOW_CFG (0x1230U)
475 #define TISCI_MSG_RM_UDMAP_FLOW_SIZE_THRESH_CFG (0x1231U)
477 #define TISCI_MSG_RM_RESERVED_1232 (0x1232U)
479 #define TISCI_MSG_RM_RESERVED_1233 (0x1233U)
483 #define TISCI_MSG_RM_UDMAP_FLOW_DELEGATE (0x1234U)
488 #define TISCI_MSG_RM_UDMAP_GCFG_CFG (0x1240U)
490 #define TISCI_MSG_RM_RESERVED_1241 (0x1241U)
494 #define TISCI_MSG_RM_PSIL_PAIR (0x1280U)
498 #define TISCI_MSG_RM_PSIL_UNPAIR (0x1281U)
502 #define TISCI_MSG_RM_PSIL_READ (0x1282U)
506 #define TISCI_MSG_RM_PSIL_WRITE (0x1283U)
511 #define TISCI_MSG_RM_PROXY_CFG (0x1300U)