AM62x MCU+ SDK  09.02.00
UDMA SW Trigger

Introduction

UDMA SW trigger sample application performs 3D transfer using SW trigger method as below Loop N times (icnt2)

  • SW trigger CH 0 -> Triggers MSMC to Intermediate buffer
  • Wait for CH 0 icnt0 x icnt1 to complete
  • SW trigger Channel 1 -> Triggers Intermediate buffer to MSMC
  • Wait for CH 1 icnt0 x icnt1 to complete

Each loop transfers M (icnt0 x icnt1) bytes of data. MSMC size is M x N and intermediate buffer size is just M bytes. Intermediate buffer memory set to wrap around after M bytes of transfer.

Where,

  • M is icnt0 x icnt1 (UDMA_TEST_1D_SIZE x UDMA_TEST_2D_SIZE)
  • N is icnt2 = UDMA_TEST_3D_SIZE

Once the transfer it completes, it does cache operation for data coherency and compares the source and destination buffers for any data mismatch.

Supported Combinations

Parameter Value
CPU + OS r5fss0-0 freertos
Toolchain ti-arm-clang
Board am62x-sk, am62x-sip-sk
Example folder examples/drivers/udma/udma_sw_trigger

Steps to Run the Example

Attention
As the wake-up R5 is the device manager, it needs to be started by the SBL. So it can not be loaded through CCS. It should be flashed and booted through SBL.

See Also

UDMA

Sample Output

Shown below is a sample output when the application is run,

[UDMA] SW Trigger application started ...
All tests have passed!!