AM62x MCU+ SDK  09.02.00
DDR PERF Test

Introduction

This example prints the read, write and total DDR bandwidth during memcpy operation. The memcpy operation is done on source and destination buffers allocated from DDR scratch region. The cache is disabled for this memory region. The values are calculated using the DDR performance counter registers available in DDR Subsystem. First performance counter is configured to count write operations and second one is configured to count read operations. The idle thread updates the DDR performance load stats.

Supported Combinations

Parameter Value
CPU + OS r5fss0-0 freertos
Toolchain ti-arm-clang
Board am62x-sk, am62x-sk-lp, am62x-sip-sk
Example folder examples/drivers/ddr/ddr_perf/

Steps to Run the Example

Attention
As the wake-up R5 is the device manager, it needs to be started by the SBL. So it can not be loaded through CCS. It should be flashed and booted through SBL.

See Also

DDR

Sample Output

Shown below is a sample output when the application is run,

DDR performance statistics
==========================
DDR: READ BW: AVG = 285 MiB/s
DDR: WRITE BW: AVG = 323 MiB/s
DDR: TOTAL BW: AVG = 608 MiB/s
totalTime = 2354274
totalRead = 671249664
totalWrite = 761457664