AM62x MCU+ SDK  09.02.01
soc.h
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32 
33 #ifndef SOC_AM62X_H_
34 #define SOC_AM62X_H_
35 
36 #ifdef __cplusplus
37 extern "C"
38 {
39 #endif
40 
49 #include <stdint.h>
50 #include <kernel/dpl/SystemP.h>
51 #if (__ARM_ARCH_PROFILE =='R')
52 #include <drivers/device_manager/sciclient.h>
53 #else
54 #include <drivers/sciclient.h>
55 #endif
56 
62 #define SOC_DOMAIN_ID_MAIN (0U)
63 #define SOC_DOMAIN_ID_MCU (1U)
64 #define SOC_DOMAIN_ID_WKUP (2U)
65 
72 /* PSC Instances */
73 #define SOC_PSC_DOMAIN_ID_MAIN (0U)
74 #define SOC_PSC_DOMAIN_ID_MCU (1U)
75 
82 /* PSC (Power Sleep Controller) Module states */
83 #define SOC_PSC_SYNCRESETDISABLE (0x0U)
84 #define SOC_PSC_SYNCRESET (0x1U)
85 #define SOC_PSC_DISABLE (0x2U)
86 #define SOC_PSC_ENABLE (0x3U)
87 
94 #define SOC_PSC_DOMAIN_OFF (0x0U)
95 #define SOC_PSC_DOMAIN_ON (0x1U)
96 
101 #define SOC_BOOTMODE_MMCSD (0X36C3)
102 
112 int32_t SOC_moduleClockEnable(uint32_t moduleId, uint32_t enable);
113 
124 int32_t SOC_moduleSetClockFrequency(uint32_t moduleId, uint32_t clkId, uint64_t clkRate);
125 
135 int32_t SOC_moduleGetClockFrequency(uint32_t moduleId, uint32_t clkId, uint64_t *clkRate);
136 
144 const char *SOC_getCoreName(uint16_t coreId);
145 
151 uint64_t SOC_getSelfCpuClk(void);
152 
159 void SOC_controlModuleLockMMR(uint32_t domainId, uint32_t partition);
160 
167 void SOC_controlModuleUnlockMMR(uint32_t domainId, uint32_t partition);
168 
175 void SOC_setEpwmTbClk(uint32_t epwmInstance, uint32_t enable);
176 
181 void SOC_unlockAllMMR(void);
182 
188 void SOC_setDevStat(uint32_t bootMode);
189 
190 
195 
200 
207 
212 
217 
222 
229 
238 void SOC_clearResetCauseMainMcuDomain(uint32_t resetCause);
239 
245 
261 int32_t SOC_enableResetIsolation(uint32_t main2McuIsolation,
262  uint32_t mcu2MainIsolation,
263  uint32_t mcu2dmIsolation,
264  uint32_t debugIsolationEnable);
272 
277 
289 int32_t SOC_getPSCState(uint32_t instNum, uint32_t domainNum, uint32_t moduleNum,
290  uint32_t *domainState, uint32_t *moduleState);
291 
302 int32_t SOC_setPSCState(uint32_t instNum, uint32_t domainNum, uint32_t moduleNum, uint32_t pscState);
303 
306 #ifdef __cplusplus
307 }
308 #endif
309 
310 #endif
sciclient.h
This file contains prototypes for APIs contained as a part of SCICLIENT as well as the structures of ...
SOC_enableResetIsolation
int32_t SOC_enableResetIsolation(uint32_t main2McuIsolation, uint32_t mcu2MainIsolation, uint32_t mcu2dmIsolation, uint32_t debugIsolationEnable)
Enable reset isolation of MCU domain for safety applications.
SOC_moduleSetClockFrequency
int32_t SOC_moduleSetClockFrequency(uint32_t moduleId, uint32_t clkId, uint64_t clkRate)
Set module clock to specified frequency.
SOC_controlModuleUnlockMMR
void SOC_controlModuleUnlockMMR(uint32_t domainId, uint32_t partition)
Unlock control module partition to allow writes into control MMRs.
SOC_generateSwWarmResetMainDomainFromMcuDomain
void SOC_generateSwWarmResetMainDomainFromMcuDomain(void)
Generate SW WARM Reset Main Domain from Mcu Domain.
SOC_generateSwPORResetMainDomainFromMcuDomain
void SOC_generateSwPORResetMainDomainFromMcuDomain(void)
Generate SW POR Reset Main Domain from Mcu Domain.
SystemP.h
SOC_clearResetCauseMainMcuDomain
void SOC_clearResetCauseMainMcuDomain(uint32_t resetCause)
Clears reason for Warm and Main/Mcu Domain Power On Resets. CTRLMMR_RST_SRC is just a mirror of CTRLM...
SOC_triggerMcuLpmWakeup
void SOC_triggerMcuLpmWakeup()
Generates the MCU IPC interrupt to DM R5 to wakeup the main domain from MCU only LPM mode.
SOC_unlockAllMMR
void SOC_unlockAllMMR(void)
Unlocks all the control MMRs.
SOC_setMCUResetIsolationDone
void SOC_setMCUResetIsolationDone(uint32_t value)
Set MCU reset isolation done flag.
SOC_generateSwWarmResetMcuDomain
void SOC_generateSwWarmResetMcuDomain(void)
Generate SW WARM Reset Mcu Domain.
SOC_moduleGetClockFrequency
int32_t SOC_moduleGetClockFrequency(uint32_t moduleId, uint32_t clkId, uint64_t *clkRate)
Get module clock frequency.
SOC_getWarmResetCauseMainDomain
uint32_t SOC_getWarmResetCauseMainDomain(void)
Get the reset reason source for Main Domain.
SOC_waitMainDomainReset
void SOC_waitMainDomainReset(void)
Wait for main domain reset to complete.
value
uint32_t value
Definition: tisci_otp_revision.h:2
SOC_setPSCState
int32_t SOC_setPSCState(uint32_t instNum, uint32_t domainNum, uint32_t moduleNum, uint32_t pscState)
Set PSC (Power Sleep Controller) state.
SOC_getSelfCpuClk
uint64_t SOC_getSelfCpuClk(void)
Get the clock frequency in Hz of the CPU on which the driver is running.
SOC_generateSwWarmResetMainDomain
void SOC_generateSwWarmResetMainDomain(void)
Generate SW Warm Reset Main Domain.
SOC_generateSwPORResetMainDomain
void SOC_generateSwPORResetMainDomain(void)
Generate SW POR Reset Main Domain.
SOC_controlModuleLockMMR
void SOC_controlModuleLockMMR(uint32_t domainId, uint32_t partition)
Lock control module partition to prevent writes into control MMRs.
SOC_moduleClockEnable
int32_t SOC_moduleClockEnable(uint32_t moduleId, uint32_t enable)
Enable clock to specified module.
SOC_setDevStat
void SOC_setDevStat(uint32_t bootMode)
Change boot mode by setting devstat register.
SOC_getPSCState
int32_t SOC_getPSCState(uint32_t instNum, uint32_t domainNum, uint32_t moduleNum, uint32_t *domainState, uint32_t *moduleState)
Get PSC (Power Sleep Controller) state.
SOC_getCoreName
const char * SOC_getCoreName(uint16_t coreId)
Convert a core ID to a user readable name.
SOC_setEpwmTbClk
void SOC_setEpwmTbClk(uint32_t epwmInstance, uint32_t enable)
Enable or disable ePWM time base clock from Control MMR.
SOC_getWarmResetCauseMcuDomain
uint32_t SOC_getWarmResetCauseMcuDomain(void)
Get the reset reason source for Mcu Domain.