AM62x MCU+ SDK  09.02.01
sciclient_fmwMsgParams.h
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1 /*
2  * Copyright (C) 2022-24 Texas Instruments Incorporated
3  *
4  * Redistribution and use in source and binary forms, with or without
5  * modification, are permitted provided that the following conditions
6  * are met:
7  *
8  * Redistributions of source code must retain the above copyright
9  * notice, this list of conditions and the following disclaimer.
10  *
11  * Redistributions in binary form must reproduce the above copyright
12  * notice, this list of conditions and the following disclaimer in the
13  * documentation and/or other materials provided with the
14  * distribution.
15  *
16  * Neither the name of Texas Instruments Incorporated nor the names of
17  * its contributors may be used to endorse or promote products derived
18  * from this software without specific prior written permission.
19  *
20  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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23  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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25  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
26  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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28  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
29  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
30  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31  *
32  */
33 
48 #ifndef SCICLIENT_FMWMSGPARAMS_H_
49 #define SCICLIENT_FMWMSGPARAMS_H_
50 
51 /* ========================================================================== */
52 /* Include Files */
53 /* ========================================================================== */
54 
55 #include <stdint.h>
56 
57 #ifdef __cplusplus
58 extern "C" {
59 #endif
60 
61 /* ========================================================================== */
62 /* Macros & Typedefs */
63 /* ========================================================================== */
64 
66 #define TISCI_PARAM_UNDEF (0xFFFFFFFFU)
67 
74 /* ABI Major revision - Major revision changes
75 * indicate backward compatibility breakage */
76 #define SCICLIENT_FIRMWARE_ABI_MAJOR (3U)
77 /* ABI Minor revision - Minor revision changes
78 * indicate backward compatibility is maintained,
79 * however, new messages OR extensions to existing
80 * messages might have been adde */
81 #define SCICLIENT_FIRMWARE_ABI_MINOR (5U)
82 
91 #define SCICLIENT_CONTEXT_R5_SEC_0 (0U)
92 
93 #define SCICLIENT_CONTEXT_R5_NONSEC_0 (1U)
94 
95 #define SCICLIENT_CONTEXT_R5_SEC_1 (2U)
96 
97 #define SCICLIENT_CONTEXT_R5_NONSEC_1 (3U)
98 
99 #define SCICLIENT_CONTEXT_A53_SEC_0 (4U)
100 
101 #define SCICLIENT_CONTEXT_A53_SEC_1 (5U)
102 
103 #define SCICLIENT_CONTEXT_A53_NONSEC_0 (6U)
104 
105 #define SCICLIENT_CONTEXT_A53_NONSEC_1 (7U)
106 
107 #define SCICLIENT_CONTEXT_M4_NONSEC_0 (8U)
108 
109 #define SCICLIENT_CONTEXT_GPU_NONSEC_0 (9U)
110 
111 #define SCICLIENT_CONTEXT_A53_NONSEC_2 (10U)
112 
114 #define SCICLIENT_CONTEXT_MAX_NUM (11U)
115 
125 #define SCICLIENT_PROC_ID_A53SS0_CORE_0 (0x20U)
126 
127 #define SCICLIENT_PROC_ID_A53SS0_CORE_1 (0x21U)
128 
129 #define SCICLIENT_PROC_ID_A53SS0_CORE_2 (0x22U)
130 
131 #define SCICLIENT_PROC_ID_A53SS0_CORE_3 (0x23U)
132 
133 #define SCICLIENT_PROC_ID_R5FSS0_CORE0 (0x01U)
134 /*** AM62_MAIN_SEC_MMR_MAIN_0: (Cluster 16 Processor 0) */
135 #define SCICLIENT_PROC_ID_MCU_M4FSS0_CORE0 (0x18U)
136 /*** AM62A_HSM_SEC_MMR_0: (Cluster 28 Processor 0) */
137 #define SCICLIENT_PROC_ID_HSM_M4FSS0_CORE0 (0x80U)
138 
140 #define SOC_NUM_SCICLIENT_PROCESSORS (0x07U)
141 
142 
143 
147 #define TISCI_MSG_VALUE_RM_NULL_RING_TYPE (0xFFFFu)
148 #define TISCI_MSG_VALUE_RM_NULL_RING_INDEX (0xFFFFFFFFu)
149 #define TISCI_MSG_VALUE_RM_NULL_RING_ADDR (0xFFFFFFFFu)
150 #define TISCI_MSG_VALUE_RM_NULL_RING_COUNT (0xFFFFFFFFu)
151 
156 #define TISCI_MSG_VALUE_RM_NULL_RING_MODE (0xFFu)
157 #define TISCI_MSG_VALUE_RM_NULL_RING_SIZE (0xFFu)
158 #define TISCI_MSG_VALUE_RM_NULL_ORDER_ID (0xFFu)
159 #define TISCI_MSG_VALUE_RM_UDMAP_NULL_CH_TYPE (0xFFu)
160 #define TISCI_MSG_VALUE_RM_UDMAP_NULL_CH_INDEX (0xFFFFFFFFu)
161 
188 #define TISCI_RINGACC0_OES_IRQ_SRC_IDX_START (20U)
189 #define TISCI_RINGACC0_EOES_IRQ_SRC_IDX_START (32U)
190 #define TISCI_TIMERMGR_OES_IRQ_SRC_IDX_START (0U)
191 #define TISCI_PKTDMA0_TX_EOES_IRQ_SRC_IDX_START (4096U)
192 #define TISCI_PKTDMA0_TX_FLOW_OES_IRQ_SRC_IDX_START (4608U)
193 #define TISCI_PKTDMA0_RX_EOES_IRQ_SRC_IDX_START (5120U)
194 #define TISCI_PKTDMA0_RX_FLOW_OES_IRQ_SRC_IDX_START (5632U)
195 #define TISCI_PKTDMA0_RX_FLOW_SOES_IRQ_SRC_IDX_START (6144U)
196 #define TISCI_PKTDMA0_RX_FLOW_FOES_IRQ_SRC_IDX_START (6656U)
197 #define TISCI_BCDMA0_BC_EOES_IRQ_SRC_IDX_START (8192U)
198 #define TISCI_BCDMA0_BC_DC_OES_IRQ_SRC_IDX_START (8704U)
199 #define TISCI_BCDMA0_BC_RC_OES_IRQ_SRC_IDX_START (9216U)
200 #define TISCI_BCDMA0_TX_EOES_IRQ_SRC_IDX_START (9728U)
201 #define TISCI_BCDMA0_TX_DC_OES_IRQ_SRC_IDX_START (10240U)
202 #define TISCI_BCDMA0_TX_RC_OES_IRQ_SRC_IDX_START (10752U)
203 #define TISCI_BCDMA0_RX_EOES_IRQ_SRC_IDX_START (11264U)
204 #define TISCI_BCDMA0_RX_DC_OES_IRQ_SRC_IDX_START (11776U)
205 #define TISCI_BCDMA0_RX_RC_OES_IRQ_SRC_IDX_START (12288U)
206 
215 #define SCICLIENT_DEV_MCU_R5FSS0_CORE0 (TISCI_DEV_WKUP_R5FSS0_CORE0)
216 #define SCICLIENT_DEV_MCU_R5FSS0_CORE1 (TISCI_DEV_WKUP_R5FSS0_CORE0)
217 
225 #define SCICLIENT_DEV_MCU_R5FSS0_CORE0_PROCID \
226  (SCICLIENT_PROC_ID_R5FSS0_CORE0)
227 #define SCICLIENT_DEV_MCU_R5FSS0_CORE1_PROCID \
228  (SCICLIENT_PROC_ID_R5FSS0_CORE0)
229 
232 #define SCICLIENT_ALLOWED_BOARDCFG_BASE_START 1U
233 
234 #define SCICLIENT_ALLOWED_BOARDCFG_BASE_END 0xFFFFFFFFU
235 
236 /* ========================================================================== */
237 /* Structure Declarations */
238 /* ========================================================================== */
239 
240 /* None */
241 
242 #ifdef __cplusplus
243 }
244 #endif
245 
246 #endif /* #ifndef SCICLIENT_FMWMSGPARAMS_H_ */
247 
tisci_clocks.h
tisci_devices.h