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AM62x MCU+ SDK
09.02.01
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46 #ifndef SAFETY_CHECKERS_SOC_H_
47 #define SAFETY_CHECKERS_SOC_H_
72 #define SAFETY_CHECKERS_PM_PSC_BASE_ADDRESS (0x400000UL)
73 #define SAFETY_CHECKERS_PM_PLL_CFG_BASE_ADDRESS (0x680000UL)
74 #define SAFETY_CHECKERS_PM_MCU_PLL_CFG_BASE_ADDRESS (0x4040000UL)
77 #define SAFETY_CHECKERS_PM_WKUP_PD_STAT_NUM (0x02U)
78 #define SAFETY_CHECKERS_PM_WKUP_MD_STAT_NUM (0x0AU)
79 #define SAFETY_CHECKERS_PM_PD_STAT_NUM (0x0AU)
80 #define SAFETY_CHECKERS_PM_MD_STAT_NUM (0x34U)
83 #define SAFETY_CHECKERS_PM_PLL0_LENGTH (0xA8U)
84 #define SAFETY_CHECKERS_PM_PLL1_LENGTH (0x9CU)
85 #define SAFETY_CHECKERS_PM_PLL2_LENGTH (0xA8U)
86 #define SAFETY_CHECKERS_PM_PLL8_LENGTH (0x84U)
87 #define SAFETY_CHECKERS_PM_PLL12_LENGTH (0x84U)
88 #define SAFETY_CHECKERS_PM_PLL15_LENGTH (0x88U)
89 #define SAFETY_CHECKERS_PM_PLL16_LENGTH (0x84U)
90 #define SAFETY_CHECKERS_PM_PLL17_LENGTH (0x84U)
91 #define SAFETY_CHECKERS_PM_MCU_PLL0_LENGTH (0x94U)
94 #define TIFS_CHECKER_FWL_MAX_NUM (0x10U)
99 #define SAFETY_CHECKERS_PM_PSC_REGDUMP_SIZE (SAFETY_CHECKERS_PM_WKUP_PD_STAT_NUM + \
100 SAFETY_CHECKERS_PM_WKUP_MD_STAT_NUM + \
101 SAFETY_CHECKERS_PM_PD_STAT_NUM + \
102 SAFETY_CHECKERS_PM_MD_STAT_NUM)
112 #define SAFETY_CHECKERS_PM_PLL_REGDUMP_SIZE (137U)
120 #define SAFETY_CHECKERS_RM_REGDUMP_SIZE (3360U)
123 #define SAFETY_CHECKERS_RM_BA0_IR (CSL_TIMESYNC_EVENT_ROUTER0_INTR_ROUTER_CFG_BASE)
124 #define SAFETY_CHECKERS_RM_BA1_IR (CSL_WKUP_MCU_GPIOMUX_INTROUTER0_INTR_ROUTER_CFG_BASE)
125 #define SAFETY_CHECKERS_RM_BA2_IR (CSL_MAIN_GPIOMUX_INTROUTER0_INTR_ROUTER_CFG_BASE)
126 #define SAFETY_CHECKERS_RM_BA3_IR (CSL_CMP_EVENT_INTROUTER0_INTR_ROUTER_CFG_BASE)
129 #define SAFETY_CHECKERS_RM_IR_REG0_NUM (64U)
130 #define SAFETY_CHECKERS_RM_IR_REG1_NUM (48U)
131 #define SAFETY_CHECKERS_RM_IR_REG2_NUM (48U)
132 #define SAFETY_CHECKERS_RM_IR_REG3_NUM (32U)
135 #define SAFETY_CHECKERS_RM_IR_SUBMOD0_NUM (1U)
138 #define SAFETY_CHECKERS_RM_BA0_IA_IMAP (CSL_DMASS0_INTAGGR_IMAP_BASE)
141 #define SAFETY_CHECKERS_RM_REG0_IA_IMAP (1536U)
144 #define SAFETY_CHECKERS_RM_SUBMOD0_IA_IMAP (1U)
147 #define SAFETY_CHECKERS_RM_BA0_RA (CSL_DMASS0_BCDMA_RING_BASE)
148 #define SAFETY_CHECKERS_RM_BA1_RA (CSL_DMASS0_PKTDMA_RING_BASE)
149 #define SAFETY_CHECKERS_RM_BA2_RA (CSL_DMASS0_RINGACC_CFG_BASE)
152 #define SAFETY_CHECKERS_RM_RA_REG0_NUM (82U)
153 #define SAFETY_CHECKERS_RM_RA_REG1_NUM (20U)
154 #define SAFETY_CHECKERS_RM_RA_REG2_NUM (150U)
157 #define SAFETY_CHECKERS_RM_SUBMOD0_RA (3U)
158 #define SAFETY_CHECKERS_RM_RA_SUBMOD1 (5U)
161 #define SAFETY_CHECKERS_RM_BA0_UDMA_TX (CSL_DMASS0_BCDMA_TCHAN_BASE)
162 #define SAFETY_CHECKERS_RM_BA1_UDMA_TX (CSL_DMASS0_PKTDMA_TCHAN_BASE)
165 #define SAFETY_CHECKERS_RM_REG0_UDMA_TX (22U)
166 #define SAFETY_CHECKERS_RM_REG1_UDMA_TX (29U)
169 #define SAFETY_CHECKERS_RM_SUBMOD0_UDMA_TX (5U)
172 #define SAFETY_CHECKERS_RM_BA0_UDMA_RX (CSL_DMASS0_BCDMA_RCHAN_BASE)
173 #define SAFETY_CHECKERS_RM_BA1_UDMA_RX (CSL_DMASS0_PKTDMA_RCHAN_BASE)
176 #define SAFETY_CHECKERS_RM_REG0_UDMA_RX (32U)
177 #define SAFETY_CHECKERS_RM_REG1_UDMA_RX (28U)
180 #define SAFETY_CHECKERS_RM_SUBMOD0_UDMA_RX (4U)
183 #define SAFETY_CHECKERS_RM_BA0_UDMA_FLW (CSL_DMASS0_PKTDMA_RFLOW_BASE)
186 #define SAFETY_CHECKERS_RM_REG0_UDMA_FLW (51U)
189 #define SAFETY_CHECKERS_RM_SUBMOD0_UDMA_FLW (1U)
192 #define SAFETY_CHECKERS_RM_BA0_UDMA_GCFG (CSL_DMASS0_BCDMA_GCFG_BASE)
193 #define SAFETY_CHECKERS_RM_BA1_UDMA_GCFG (CSL_DMASS0_PKTDMA_GCFG_BASE)
196 #define SAFETY_CHECKERS_RM_REG0_UDMA_GCFG (1U)
197 #define SAFETY_CHECKERS_RM_REG1_UDMA_GCFG (1U)
200 #define SAFETY_CHECKERS_RM_SUBMOD0_UDMA_GCFG (13U)
201 #define SAFETY_CHECKERS_RM_SUBMOD1_UDMA_GCFG (14U)
259 {
SAFETY_CHECKERS_RM_BA0_IR,
SAFETY_CHECKERS_RM_IR_SUBMOD0_NUM,
SAFETY_CHECKERS_RM_IR_REG0_NUM,
SAFETY_CHECKERS_RM_REG_HEX0, {0X0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U}},
260 {
SAFETY_CHECKERS_RM_BA1_IR,
SAFETY_CHECKERS_RM_IR_SUBMOD0_NUM,
SAFETY_CHECKERS_RM_IR_REG1_NUM,
SAFETY_CHECKERS_RM_REG_HEX0, {0X0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U}},
261 {
SAFETY_CHECKERS_RM_BA2_IR,
SAFETY_CHECKERS_RM_IR_SUBMOD0_NUM,
SAFETY_CHECKERS_RM_IR_REG2_NUM,
SAFETY_CHECKERS_RM_REG_HEX0, {0X0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U}},
262 {
SAFETY_CHECKERS_RM_BA3_IR,
SAFETY_CHECKERS_RM_IR_SUBMOD0_NUM,
SAFETY_CHECKERS_RM_IR_REG3_NUM,
SAFETY_CHECKERS_RM_REG_HEX0, {0X0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U}},
264 {
SAFETY_CHECKERS_RM_BA0_IA_IMAP,
SAFETY_CHECKERS_RM_SUBMOD0_IA_IMAP,
SAFETY_CHECKERS_RM_REG0_IA_IMAP,
SAFETY_CHECKERS_RM_REG_HEX0, {0X0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U}},
266 {
SAFETY_CHECKERS_RM_BA0_RA,
SAFETY_CHECKERS_RM_SUBMOD0_RA,
SAFETY_CHECKERS_RM_RA_REG0_NUM,
SAFETY_CHECKERS_RM_REG_HEX100, {0x40U, 0x44U, 0x48U,0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U}},
267 {
SAFETY_CHECKERS_RM_BA1_RA,
SAFETY_CHECKERS_RM_SUBMOD0_RA,
SAFETY_CHECKERS_RM_RA_REG1_NUM,
SAFETY_CHECKERS_RM_REG_HEX100, {0x40U, 0x44U, 0x48U,0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U}},
268 {
SAFETY_CHECKERS_RM_BA2_RA,
SAFETY_CHECKERS_RM_RA_SUBMOD1,
SAFETY_CHECKERS_RM_RA_REG2_NUM,
SAFETY_CHECKERS_RM_REG_HEX100, {0x40U, 0x44U, 0x48U, 0x4CU, 0x50U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U}},
270 {
SAFETY_CHECKERS_RM_BA0_UDMA_TX,
SAFETY_CHECKERS_RM_SUBMOD0_UDMA_TX,
SAFETY_CHECKERS_RM_REG0_UDMA_TX,
SAFETY_CHECKERS_RM_REG_HEX100, {0x0U, 0x64U, 0x68U, 0x70U, 0x80U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U}},
271 {
SAFETY_CHECKERS_RM_BA1_UDMA_TX,
SAFETY_CHECKERS_RM_SUBMOD0_UDMA_TX,
SAFETY_CHECKERS_RM_REG1_UDMA_TX,
SAFETY_CHECKERS_RM_REG_HEX100, {0x0U, 0x64U, 0x68U, 0x70U, 0x80U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U}},
273 {
SAFETY_CHECKERS_RM_BA0_UDMA_RX,
SAFETY_CHECKERS_RM_SUBMOD0_UDMA_RX,
SAFETY_CHECKERS_RM_REG0_UDMA_RX,
SAFETY_CHECKERS_RM_REG_HEX100, {0x0U, 0x64U, 0x68U, 0x80U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U}},
274 {
SAFETY_CHECKERS_RM_BA1_UDMA_RX,
SAFETY_CHECKERS_RM_SUBMOD0_UDMA_RX,
SAFETY_CHECKERS_RM_REG1_UDMA_RX,
SAFETY_CHECKERS_RM_REG_HEX100, {0x0U, 0x14U, 0x20U, 0x60U, 0x64U, 0x68U, 0x80U, 0xF0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U}},
276 {
SAFETY_CHECKERS_RM_BA0_UDMA_FLW,
SAFETY_CHECKERS_RM_SUBMOD0_UDMA_FLW,
SAFETY_CHECKERS_RM_REG0_UDMA_FLW,
SAFETY_CHECKERS_RM_REG_HEX40, {0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U}},
278 {
SAFETY_CHECKERS_RM_BA0_UDMA_GCFG,
SAFETY_CHECKERS_RM_SUBMOD0_UDMA_GCFG,
SAFETY_CHECKERS_RM_REG0_UDMA_GCFG,
SAFETY_CHECKERS_RM_REG_HEX0, {0x0U, 0x04U, 0X08U, 0x10U, 0x20U, 0x24U, 0x28U, 0x2CU, 0x30U, 0x60U, 0x64U, 0x78U, 0x7CU, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U}},
279 {
SAFETY_CHECKERS_RM_BA1_UDMA_GCFG,
SAFETY_CHECKERS_RM_SUBMOD1_UDMA_GCFG,
SAFETY_CHECKERS_RM_REG1_UDMA_GCFG,
SAFETY_CHECKERS_RM_REG_HEX0, {0x0U, 0x04U, 0X08U, 0x10U, 0x20U, 0x24U, 0x28U, 0x2CU, 0x30U, 0x60U, 0x64U, 0x78U, 0x7CU, 0x88U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U}},
#define SAFETY_CHECKERS_RM_BA0_UDMA_TX
RM UDMA TX module base addresses.
Definition: safety_checkers_soc.h:161
static SafetyCheckers_PmPllData gSafetyCheckers_PmPllData[]
Structure defines PLL register base address and the total length of registers.
Definition: safety_checkers_soc.h:227
#define SAFETY_CHECKERS_RM_IR_REG0_NUM
Formula input of IR module to read relevant registers from register group.
Definition: safety_checkers_soc.h:129
#define SAFETY_CHECKERS_RM_IR_REG3_NUM
Definition: safety_checkers_soc.h:132
#define SAFETY_CHECKERS_RM_SUBMOD0_UDMA_GCFG
Number of registers in UDMA GCFG register group.
Definition: safety_checkers_soc.h:200
#define SAFETY_CHECKERS_PM_PD_STAT_NUM
Definition: safety_checkers_soc.h:79
#define SAFETY_CHECKERS_RM_BA1_UDMA_TX
Definition: safety_checkers_soc.h:162
static uint32_t gSafetyCheckers_PmPllRegOffset3[]
Definition: safety_checkers_pm_soc.h:119
Structure to hold the base address and the number of Module Domain(MD) stat and Power Domain(PD) stat...
Definition: safety_checkers_pm.h:98
static SafetyCheckers_RmRegData gSafetyCheckers_RmRegData[]
Structure defines RM module register base address and the total length of registers.
Definition: safety_checkers_soc.h:257
#define SAFETY_CHECKERS_RM_SUBMOD0_UDMA_RX
Number of registers in UDMA RX register group.
Definition: safety_checkers_soc.h:180
#define SAFETY_CHECKERS_RM_SUBMOD0_IA_IMAP
Number of registers in IAIMAP register group.
Definition: safety_checkers_soc.h:144
#define SAFETY_CHECKERS_RM_REG0_UDMA_RX
Formula input of UDMA RX to read relevant registers from register group.
Definition: safety_checkers_soc.h:176
#define SAFETY_CHECKERS_PM_PLL_BASE_ADDRESS(i)
Each PLL base addresses.
Definition: safety_checkers_pm_soc.h:80
#define SAFETY_CHECKERS_RM_BA0_IA_IMAP
RM IAIMAP module base addresses.
Definition: safety_checkers_soc.h:138
#define SAFETY_CHECKERS_RM_REG0_UDMA_GCFG
Formula input of UDMA GCFG to read relevant registers from register group.
Definition: safety_checkers_soc.h:196
#define SAFETY_CHECKERS_PM_PLL2_LENGTH
Definition: safety_checkers_soc.h:85
#define SAFETY_CHECKERS_RM_REG1_UDMA_GCFG
Definition: safety_checkers_soc.h:197
#define SAFETY_CHECKERS_RM_SUBMOD1_UDMA_GCFG
Definition: safety_checkers_soc.h:201
#define SAFETY_CHECKERS_RM_SUBMOD0_RA
Number of registers in RA register group.
Definition: safety_checkers_soc.h:157
#define SAFETY_CHECKERS_RM_BA1_RA
Definition: safety_checkers_soc.h:148
#define SAFETY_CHECKERS_RM_IR_REG2_NUM
Definition: safety_checkers_soc.h:131
#define SAFETY_CHECKERS_PM_PLL1_LENGTH
Definition: safety_checkers_soc.h:84
#define SAFETY_CHECKERS_RM_RA_REG1_NUM
Definition: safety_checkers_soc.h:153
#define SAFETY_CHECKERS_RM_BA1_IR
Definition: safety_checkers_soc.h:124
Structure to hold the base address and the length of PLLs.
Definition: safety_checkers_pm.h:82
#define SAFETY_CHECKERS_PM_PLL17_LENGTH
Definition: safety_checkers_soc.h:90
#define SAFETY_CHECKERS_RM_SUBMOD0_UDMA_TX
Number of registers in UDMA TX register group.
Definition: safety_checkers_soc.h:169
#define SAFETY_CHECKERS_RM_IR_SUBMOD0_NUM
Number of registers in IR register group.
Definition: safety_checkers_soc.h:135
#define SAFETY_CHECKERS_PM_WKUP_MD_STAT_NUM
Definition: safety_checkers_soc.h:78
#define SAFETY_CHECKERS_PM_PLL15_LENGTH
Definition: safety_checkers_soc.h:88
#define SAFETY_CHECKERS_PM_PLL12_LENGTH
Definition: safety_checkers_soc.h:87
#define SAFETY_CHECKERS_RM_BA2_RA
Definition: safety_checkers_soc.h:149
#define SAFETY_CHECKERS_PM_WKUP_PSC_BASE_ADDRESS
WKUP PSC base address.
Definition: safety_checkers_pm_soc.h:72
#define SAFETY_CHECKERS_RM_REG0_UDMA_TX
Formula input of UDMA TX to read relevant registers from register group.
Definition: safety_checkers_soc.h:165
#define SAFETY_CHECKERS_RM_REG1_UDMA_TX
Definition: safety_checkers_soc.h:166
#define SAFETY_CHECKERS_RM_BA1_UDMA_GCFG
Definition: safety_checkers_soc.h:193
#define SAFETY_CHECKERS_RM_RA_REG2_NUM
Definition: safety_checkers_soc.h:154
#define SAFETY_CHECKERS_PM_WKUP_PD_STAT_NUM
PD STAT and MD STAT registers details for PSC.
Definition: safety_checkers_soc.h:77
#define SAFETY_CHECKERS_PM_PSC_BASE_ADDRESS
PLL and PSC base addresses.
Definition: safety_checkers_soc.h:72
#define SAFETY_CHECKERS_PM_MD_STAT_NUM
Definition: safety_checkers_soc.h:80
#define SAFETY_CHECKERS_RM_BA0_UDMA_RX
RM UDMA RX module base addresses.
Definition: safety_checkers_soc.h:172
#define SAFETY_CHECKERS_RM_BA1_UDMA_RX
Definition: safety_checkers_soc.h:173
Structure to hold the base address and the register details of RM control module registers.
Definition: safety_checkers_rm.h:99
#define SAFETY_CHECKERS_RM_BA2_IR
Definition: safety_checkers_soc.h:125
#define SAFETY_CHECKERS_PM_MCU_PLL_BASE_ADDRESS(i)
Definition: safety_checkers_pm_soc.h:81
#define SAFETY_CHECKERS_RM_REG0_UDMA_FLW
Formula input of UDMA FLOW to read relevant registers from register group.
Definition: safety_checkers_soc.h:186
#define SAFETY_CHECKERS_PM_PLL0_LENGTH
PLL register details.
Definition: safety_checkers_soc.h:83
#define SAFETY_CHECKERS_RM_BA0_RA
RM RA module base addresses.
Definition: safety_checkers_soc.h:147
#define SAFETY_CHECKERS_PM_MCU_PLL0_LENGTH
Definition: safety_checkers_soc.h:91
#define SAFETY_CHECKERS_RM_REG_HEX100
Definition: safety_checkers_rm_soc.h:74
#define SAFETY_CHECKERS_RM_REG0_IA_IMAP
Formula input of IAIMAP module to read relevant registers from register group.
Definition: safety_checkers_soc.h:141
#define SAFETY_CHECKERS_PM_PLL8_LENGTH
Definition: safety_checkers_soc.h:86
static SafetyCheckers_PmPscData gSafetyCheckers_PmPscData[]
Structure defines PSC register base address and the total length of registers.
Definition: safety_checkers_soc.h:246
#define SAFETY_CHECKERS_RM_REG_HEX40
Definition: safety_checkers_rm_soc.h:73
#define SAFETY_CHECKERS_RM_RA_SUBMOD1
Definition: safety_checkers_soc.h:158
#define SAFETY_CHECKERS_RM_SUBMOD0_UDMA_FLW
Number of registers in UDMA FLOW register group.
Definition: safety_checkers_soc.h:189
This file contains data structures for PM safety checker module.
#define SAFETY_CHECKERS_RM_RA_REG0_NUM
Formula input of RA module to read relevant registers from register group.
Definition: safety_checkers_soc.h:152
#define SAFETY_CHECKERS_RM_REG1_UDMA_RX
Definition: safety_checkers_soc.h:177
This file contains data structures for RM safety checker module.
#define SAFETY_CHECKERS_RM_BA0_UDMA_GCFG
RM UDMA GCFG module base addresses.
Definition: safety_checkers_soc.h:192
#define SAFETY_CHECKERS_RM_REG_HEX0
Offsets for RM register blobs.
Definition: safety_checkers_rm_soc.h:70
#define SAFETY_CHECKERS_PM_PLL16_LENGTH
Definition: safety_checkers_soc.h:89
#define SAFETY_CHECKERS_RM_BA0_UDMA_FLW
RM UDMA FLOW module base addresses.
Definition: safety_checkers_soc.h:183
#define SAFETY_CHECKERS_RM_BA0_IR
RM IR module base addresses.
Definition: safety_checkers_soc.h:123
#define SAFETY_CHECKERS_RM_BA3_IR
Definition: safety_checkers_soc.h:126
#define SAFETY_CHECKERS_RM_IR_REG1_NUM
Definition: safety_checkers_soc.h:130