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AM62x MCU+ SDK
09.00.00
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51 #ifndef SDL_IP_PBIST_H_
52 #define SDL_IP_PBIST_H_
61 #include <sdl/pbist/v0/soc/sdl_soc_pbist.h>
uint32_t RAMT
Definition: sdl_ip_pbist.h:162
Definition: sdlr_pbist.h:53
uint32_t I0
Definition: sdl_ip_pbist.h:146
int32_t SDL_PBIST_checkResult(const SDL_pbistRegs *pPBISTRegs, bool *pResult)
PBIST check result.
uint32_t I1
Definition: sdl_ip_pbist.h:150
uint64_t scrambleValue
Definition: sdl_ip_pbist.h:90
uint32_t I2
Definition: sdl_ip_pbist.h:154
uint32_t CMS
Definition: sdl_ip_pbist.h:138
uint64_t memoryGroupsBitMap
Definition: sdl_ip_pbist.h:86
int32_t SDL_PBIST_releaseTestMode(SDL_pbistRegs *pPBISTRegs)
PBIST Release Test mode.
uint32_t CSR
Definition: sdl_ip_pbist.h:142
This structure contains the different configuration used for PBIST.
Definition: sdl_ip_pbist.h:72
uint32_t CL3
Definition: sdl_ip_pbist.h:134
uint32_t CA2
Definition: sdl_ip_pbist.h:114
uint32_t CA1
Definition: sdl_ip_pbist.h:110
uint32_t CL0
Definition: sdl_ip_pbist.h:122
uint32_t CA0
Definition: sdl_ip_pbist.h:106
int32_t SDL_PBIST_start(SDL_pbistRegs *pPBISTRegs, const SDL_PBIST_config *pConfig)
PBIST Start.
uint32_t CL2
Definition: sdl_ip_pbist.h:130
uint32_t algorithmsBitMap
Definition: sdl_ip_pbist.h:82
int32_t SDL_PBIST_softReset(SDL_pbistRegs *pPBISTRegs)
PBIST Soft reset.
uint32_t CA3
Definition: sdl_ip_pbist.h:118
uint32_t CL1
Definition: sdl_ip_pbist.h:126
This structure contains the different configuration used for PBIST for the failure insertion test to ...
Definition: sdl_ip_pbist.h:103
uint32_t I3
Definition: sdl_ip_pbist.h:158
int32_t SDL_PBIST_startNeg(SDL_pbistRegs *pPBISTRegs, const SDL_PBIST_configNeg *pConfig)
PBIST Failure Insertion Test Start.