sdl_ecc_soc.h

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/*
 * SDL ECC
 *
 * Software Diagnostics Library module for ECC
 *
 *  Copyright (c) Texas Instruments Incorporated 2023
 *
 *  Redistribution and use in source and binary forms, with or without
 *  modification, are permitted provided that the following conditions
 *  are met:
 *
 *    Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 *
 *    Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the
 *    distribution.
 *
 *    Neither the name of Texas Instruments Incorporated nor the names of
 *    its contributors may be used to endorse or promote products derived
 *    from this software without specific prior written permission.
 *
 *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
 *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
 *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
 *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
 *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
 */
 #ifndef INCLUDE_SDL_ECC_SOC_H_
 #define INCLUDE_SDL_ECC_SOC_H_
 
 #include <stdint.h>
 #include <sdl/sdl_ecc.h>
 #include <sdl/ecc/sdl_ip_ecc.h>
 #include <sdl/include/sdl_types.h>
 #include <sdl/esm/soc/am62x/sdl_esm_core.h>
 #include <sdl/ecc/sdl_ecc_priv.h>
 #include <sdl/include/am62x/sdlr_soc_ecc_aggr.h>
 #include <sdl/include/am62x/sdlr_intr_esm0.h>
 #include <sdl/include/am62x/sdlr_soc_baseaddress.h>
 
/* define Max memEntries for each aggregator (i.e. the number of RAM ID's with * Wrapper type) */
#define SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (0U)
#define SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_RAM_IDS_TOTAL_ENTRIES (0U)
#define SDL_PSRAMECC0_PSRAM256X32E_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (1U)
#define SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (1U)
#define SDL_ICSSM0_ICSS_M_CORE_BORG_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (5U)
#define SDL_FSS0_FSS_UL_OSPI0_OSPI_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (1U)
#define SDL_GICSS0_GIC500SS_1_4_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (3U)
#define SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_RAM_IDS_TOTAL_ENTRIES (16U)
#define SDL_SA3_SS0_SA3SS_AM62_SA_UL_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (12U)
#define SDL_DMASS0_DMSS_AM62_ECCAGGR_RAM_IDS_TOTAL_ENTRIES (28U)
#define SDL_PSRAMECC_16K0_PSRAM16KX32E_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (1U)
#define SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (7U)
#define SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_RXMEM_RAM_IDS_TOTAL_ENTRIES (1U)
#define SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_TXMEM_RAM_IDS_TOTAL_ENTRIES (1U)
#define SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_RXMEM_RAM_IDS_TOTAL_ENTRIES (1U)
#define SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_TXMEM_RAM_IDS_TOTAL_ENTRIES (1U)
#define SDL_PDMA0_SAM62_PDMA_SPI_ECCAGGR_RAM_IDS_TOTAL_ENTRIES (4U)
#define SDL_MMCSD0_EMMCSD8SS_ECC_AGGR_TXMEM_RAM_IDS_TOTAL_ENTRIES (1U)
#define SDL_MMCSD0_EMMCSD8SS_ECC_AGGR_RXMEM_RAM_IDS_TOTAL_ENTRIES (1U)
#define SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (29U)
#define SDL_SMS0_SMS_HSM_ECC_RAM_IDS_TOTAL_ENTRIES (2U)
#define SDL_SMS0_SMS_TIFS_ECC_RAM_IDS_TOTAL_ENTRIES (2U)
#define SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (4U)
#define SDL_USB1_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (2U)
#define SDL_USB0_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (2U)
#define SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (0U)
#define SDL_PDMA1_SAM62_PDMA_UART_ECCAGGR_RAM_IDS_TOTAL_ENTRIES (4U)
#define SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (1U)
#define SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_RAM_IDS_TOTAL_ENTRIES (27U)
#define SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_RAM_IDS_TOTAL_ENTRIES (27U)
#define SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_RAM_IDS_TOTAL_ENTRIES (27U)
#define SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_RAM_IDS_TOTAL_ENTRIES (27U)
#define SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_RAM_IDS_TOTAL_ENTRIES (24U)
#define SDL_MCU_M4FSS0_BLAZAR_ECC_RAM_IDS_TOTAL_ENTRIES (2U)
#define SDL_MCU_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (1U)
#define SDL_MCU_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (1U)
#define SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (8U)
#define SDL_ECC_Base_Address_TOTAL_ENTRIES (37U)
 
/*Special case for CPSW0*/
#define SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR_SPECIAL_NUM_RAMS  (20U)
 
static const SDL_GrpChkConfig_t SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_groupEntries[SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_MAX_NUM_CHECKERS] =
{
    {  SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_0_WIDTH },
    {  SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_1_WIDTH },
    {  SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_2_WIDTH },
    {  SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_3_WIDTH },
    {  SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_4_WIDTH },
    {  SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_5_WIDTH },
    {  SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_6_WIDTH },
    {  SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_7_WIDTH },
    {  SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_8_WIDTH },
    {  SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_9_WIDTH },
    {  SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_10_WIDTH },
    {  SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_11_WIDTH },
    {  SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_12_WIDTH },
    {  SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_13_WIDTH },
    {  SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_14_WIDTH },
    {  SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_15_WIDTH },
    {  SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_16_WIDTH },
    {  SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_17_WIDTH },
    {  SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_18_WIDTH },
    {  SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_19_WIDTH },
    {  SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_20_WIDTH },
    {  SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_21_WIDTH },
    {  SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_22_WIDTH },
    {  SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_23_WIDTH },
    {  SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_24_WIDTH },
    {  SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_25_WIDTH },
};
 
static const SDL_GrpChkConfig_t SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_groupEntries[SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_MAX_NUM_CHECKERS] =
{
    {  SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_0_WIDTH },
    {  SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_1_WIDTH },
    {  SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_2_WIDTH },
    {  SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_3_WIDTH },
    {  SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_4_WIDTH },
    {  SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_5_WIDTH },
    {  SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_6_WIDTH },
    {  SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_7_WIDTH },
    {  SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_8_WIDTH },
    {  SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_9_WIDTH },
    {  SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_10_WIDTH },
    {  SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_11_WIDTH },
    {  SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_12_WIDTH },
    {  SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_13_WIDTH },
    {  SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_14_WIDTH },
    {  SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_15_WIDTH },
    {  SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_16_WIDTH },
    {  SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_17_WIDTH },
    {  SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_18_WIDTH },
    {  SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_19_WIDTH },
    {  SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_20_WIDTH },
    {  SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_21_WIDTH },
};
 
static const SDL_GrpChkConfig_t SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_IK3VTM_N16FFC_WKUP_0_VBUSP_P2P_BRIDGE_IK3VTM_N16FFC_WKUP_0_VBUSP_BRIDGE_BUSECC_groupEntries[SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_IK3VTM_N16FFC_WKUP_0_VBUSP_P2P_BRIDGE_IK3VTM_N16FFC_WKUP_0_VBUSP_BRIDGE_BUSECC_MAX_NUM_CHECKERS] =
{
    {  SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_IK3VTM_N16FFC_WKUP_0_VBUSP_P2P_BRIDGE_IK3VTM_N16FFC_WKUP_0_VBUSP_BRIDGE_BUSECC_GROUP_0_WIDTH },
    {  SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_IK3VTM_N16FFC_WKUP_0_VBUSP_P2P_BRIDGE_IK3VTM_N16FFC_WKUP_0_VBUSP_BRIDGE_BUSECC_GROUP_1_WIDTH },
    {  SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_IK3VTM_N16FFC_WKUP_0_VBUSP_P2P_BRIDGE_IK3VTM_N16FFC_WKUP_0_VBUSP_BRIDGE_BUSECC_GROUP_2_WIDTH },
    {  SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_IK3VTM_N16FFC_WKUP_0_VBUSP_P2P_BRIDGE_IK3VTM_N16FFC_WKUP_0_VBUSP_BRIDGE_BUSECC_GROUP_3_WIDTH },
    {  SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_IK3VTM_N16FFC_WKUP_0_VBUSP_P2P_BRIDGE_IK3VTM_N16FFC_WKUP_0_VBUSP_BRIDGE_BUSECC_GROUP_4_WIDTH },
    {  SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_IK3VTM_N16FFC_WKUP_0_VBUSP_P2P_BRIDGE_IK3VTM_N16FFC_WKUP_0_VBUSP_BRIDGE_BUSECC_GROUP_5_WIDTH },
    {  SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_IK3VTM_N16FFC_WKUP_0_VBUSP_P2P_BRIDGE_IK3VTM_N16FFC_WKUP_0_VBUSP_BRIDGE_BUSECC_GROUP_6_WIDTH },
    {  SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_IK3VTM_N16FFC_WKUP_0_VBUSP_P2P_BRIDGE_IK3VTM_N16FFC_WKUP_0_VBUSP_BRIDGE_BUSECC_GROUP_7_WIDTH },
    {  SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_IK3VTM_N16FFC_WKUP_0_VBUSP_P2P_BRIDGE_IK3VTM_N16FFC_WKUP_0_VBUSP_BRIDGE_BUSECC_GROUP_8_WIDTH },
    {  SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_IK3VTM_N16FFC_WKUP_0_VBUSP_P2P_BRIDGE_IK3VTM_N16FFC_WKUP_0_VBUSP_BRIDGE_BUSECC_GROUP_9_WIDTH },
    {  SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_IK3VTM_N16FFC_WKUP_0_VBUSP_P2P_BRIDGE_IK3VTM_N16FFC_WKUP_0_VBUSP_BRIDGE_BUSECC_GROUP_10_WIDTH },
    {  SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_IK3VTM_N16FFC_WKUP_0_VBUSP_P2P_BRIDGE_IK3VTM_N16FFC_WKUP_0_VBUSP_BRIDGE_BUSECC_GROUP_11_WIDTH },
    {  SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_IK3VTM_N16FFC_WKUP_0_VBUSP_P2P_BRIDGE_IK3VTM_N16FFC_WKUP_0_VBUSP_BRIDGE_BUSECC_GROUP_12_WIDTH },
};
 
static const SDL_GrpChkConfig_t SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_ISAM62_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM62_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_DST_BUSECC_groupEntries[SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_ISAM62_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM62_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS] =
{
    {  SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_ISAM62_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM62_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_DST_BUSECC_GROUP_0_WIDTH },
    {  SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_ISAM62_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM62_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_DST_BUSECC_GROUP_1_WIDTH },
    {  SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_ISAM62_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM62_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_DST_BUSECC_GROUP_2_WIDTH },
    {  SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_ISAM62_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM62_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_DST_BUSECC_GROUP_3_WIDTH },
    {  SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_ISAM62_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM62_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_DST_BUSECC_GROUP_4_WIDTH },
    {  SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_ISAM62_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM62_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_DST_BUSECC_GROUP_5_WIDTH },
    {  SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_ISAM62_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM62_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_DST_BUSECC_GROUP_6_WIDTH },
};
 
static const SDL_GrpChkConfig_t SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_ISAM62_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM62_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_SRC_BUSECC_groupEntries[SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_ISAM62_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM62_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS] =
{
    {  SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_ISAM62_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM62_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_SRC_BUSECC_GROUP_0_WIDTH },
    {  SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_ISAM62_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM62_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_SRC_BUSECC_GROUP_1_WIDTH },
    {  SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_ISAM62_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM62_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_SRC_BUSECC_GROUP_2_WIDTH },
    {  SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_ISAM62_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM62_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_SRC_BUSECC_GROUP_3_WIDTH },
    {  SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_ISAM62_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM62_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_SRC_BUSECC_GROUP_4_WIDTH },
    {  SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_ISAM62_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM62_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_SRC_BUSECC_GROUP_5_WIDTH },
    {  SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_ISAM62_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM62_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_SRC_BUSECC_GROUP_6_WIDTH },
    {  SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_ISAM62_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM62_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_SRC_BUSECC_GROUP_7_WIDTH },
    {  SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_ISAM62_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM62_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_SRC_BUSECC_GROUP_8_WIDTH },
    {  SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_ISAM62_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM62_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_SRC_BUSECC_GROUP_9_WIDTH },
    {  SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_ISAM62_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM62_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_SRC_BUSECC_GROUP_10_WIDTH },
    {  SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_ISAM62_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM62_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_SRC_BUSECC_GROUP_11_WIDTH },
    {  SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_ISAM62_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM62_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_SRC_BUSECC_GROUP_12_WIDTH },
    {  SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_ISAM62_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM62_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_SRC_BUSECC_GROUP_13_WIDTH },
    {  SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_ISAM62_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM62_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_SRC_BUSECC_GROUP_14_WIDTH },
    {  SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_ISAM62_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM62_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_SRC_BUSECC_GROUP_15_WIDTH },
    {  SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_ISAM62_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM62_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_SRC_BUSECC_GROUP_16_WIDTH },
};
 
static const SDL_GrpChkConfig_t SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_groupEntries[SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS] =
{
    {  SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
    {  SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
    {  SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
    {  SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
    {  SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
    {  SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_5_WIDTH },
    {  SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_6_WIDTH },
    {  SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_7_WIDTH },
    {  SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_8_WIDTH },
    {  SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_9_WIDTH },
    {  SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_10_WIDTH },
    {  SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_11_WIDTH },
    {  SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_12_WIDTH },
    {  SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_13_WIDTH },
    {  SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_14_WIDTH },
    {  SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_15_WIDTH },
    {  SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_16_WIDTH },
    {  SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_17_WIDTH },
    {  SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_18_WIDTH },
    {  SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_19_WIDTH },
    {  SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_20_WIDTH },
    {  SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_21_WIDTH },
    {  SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_22_WIDTH },
    {  SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_23_WIDTH },
    {  SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_24_WIDTH },
    {  SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_25_WIDTH },
    {  SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_26_WIDTH },
    {  SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_27_WIDTH },
    {  SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_28_WIDTH },
    {  SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_29_WIDTH },
    {  SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_30_WIDTH },
    {  SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_31_WIDTH },
    {  SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_32_WIDTH },
    {  SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_33_WIDTH },
    {  SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_34_WIDTH },
    {  SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_35_WIDTH },
    {  SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_36_WIDTH },
    {  SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_37_WIDTH },
    {  SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_38_WIDTH },
    {  SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_39_WIDTH },
    {  SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_40_WIDTH },
    {  SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_41_WIDTH },
    {  SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_42_WIDTH },
    {  SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_43_WIDTH },
    {  SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_44_WIDTH },
    {  SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_45_WIDTH },
    {  SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_46_WIDTH },
    {  SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_47_WIDTH },
    {  SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_48_WIDTH },
    {  SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_49_WIDTH },
    {  SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_50_WIDTH },
    {  SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_51_WIDTH },
    {  SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_52_WIDTH },
    {  SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_53_WIDTH },
    {  SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_54_WIDTH },
    {  SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_55_WIDTH },
    {  SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_56_WIDTH },
    {  SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_57_WIDTH },
    {  SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_58_WIDTH },
    {  SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_59_WIDTH },
    {  SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_60_WIDTH },
    {  SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_61_WIDTH },
    {  SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_62_WIDTH },
    {  SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_63_WIDTH },
    {  SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_64_WIDTH },
    {  SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_65_WIDTH },
    {  SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_66_WIDTH },
    {  SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_67_WIDTH },
    {  SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_68_WIDTH },
    {  SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_69_WIDTH },
    {  SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_70_WIDTH },
    {  SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_71_WIDTH },
    {  SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_72_WIDTH },
};
 
static const SDL_GrpChkConfig_t SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS] =
{
    {  SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
    {  SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
    {  SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
    {  SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
    {  SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
    {  SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_5_WIDTH },
    {  SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_6_WIDTH },
    {  SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_7_WIDTH },
    {  SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_8_WIDTH },
    {  SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_9_WIDTH },
    {  SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_10_WIDTH },
    {  SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_11_WIDTH },
    {  SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_12_WIDTH },
    {  SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_13_WIDTH },
    {  SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_14_WIDTH },
    {  SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_15_WIDTH },
    {  SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_16_WIDTH },
    {  SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_17_WIDTH },
    {  SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_18_WIDTH },
    {  SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_19_WIDTH },
    {  SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_20_WIDTH },
    {  SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_21_WIDTH },
    {  SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_22_WIDTH },
    {  SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_23_WIDTH },
    {  SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_24_WIDTH },
    {  SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_25_WIDTH },
    {  SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_26_WIDTH },
    {  SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_27_WIDTH },
    {  SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_28_WIDTH },
    {  SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_29_WIDTH },
    {  SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_30_WIDTH },
    {  SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_31_WIDTH },
    {  SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_32_WIDTH },
    {  SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_33_WIDTH },
    {  SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_34_WIDTH },
    {  SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_35_WIDTH },
    {  SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_36_WIDTH },
    {  SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_37_WIDTH },
    {  SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_38_WIDTH },
    {  SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_39_WIDTH },
    {  SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_40_WIDTH },
    {  SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_41_WIDTH },
    {  SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_42_WIDTH },
    {  SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_43_WIDTH },
    {  SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_44_WIDTH },
    {  SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_45_WIDTH },
    {  SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_46_WIDTH },
    {  SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_47_WIDTH },
    {  SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_48_WIDTH },
    {  SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_49_WIDTH },
    {  SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_50_WIDTH },
    {  SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_51_WIDTH },
    {  SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_52_WIDTH },
    {  SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_53_WIDTH },
    {  SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_54_WIDTH },
    {  SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_55_WIDTH },
    {  SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_56_WIDTH },
    {  SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_57_WIDTH },
    {  SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_58_WIDTH },
    {  SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_59_WIDTH },
    {  SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_60_WIDTH },
    {  SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_61_WIDTH },
    {  SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_62_WIDTH },
    {  SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_63_WIDTH },
    {  SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_64_WIDTH },
    {  SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_65_WIDTH },
};
 
static const SDL_GrpChkConfig_t SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_SAM62_DM_ECC_AGGR_EDC_CTRL_groupEntries[SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_SAM62_DM_ECC_AGGR_EDC_CTRL_MAX_NUM_CHECKERS] =
{
    {  SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_SAM62_DM_ECC_AGGR_EDC_CTRL_GROUP_0_WIDTH },
    {  SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_SAM62_DM_ECC_AGGR_EDC_CTRL_GROUP_1_WIDTH },
    {  SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_SAM62_DM_ECC_AGGR_EDC_CTRL_GROUP_2_WIDTH },
    {  SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_SAM62_DM_ECC_AGGR_EDC_CTRL_GROUP_3_WIDTH },
    {  SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_SAM62_DM_ECC_AGGR_EDC_CTRL_GROUP_4_WIDTH },
    {  SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_SAM62_DM_ECC_AGGR_EDC_CTRL_GROUP_5_WIDTH },
};
 
static const SDL_GrpChkConfig_t SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_ECCAGGR_EDC_CTRL_groupEntries[SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_ECCAGGR_EDC_CTRL_MAX_NUM_CHECKERS] =
{
    {  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_ECCAGGR_EDC_CTRL_GROUP_0_WIDTH },
    {  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_ECCAGGR_EDC_CTRL_GROUP_1_WIDTH },
    {  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_ECCAGGR_EDC_CTRL_GROUP_2_WIDTH },
    {  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_ECCAGGR_EDC_CTRL_GROUP_3_WIDTH },
    {  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_ECCAGGR_EDC_CTRL_GROUP_4_WIDTH },
    {  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_ECCAGGR_EDC_CTRL_GROUP_5_WIDTH },
};
 
static const SDL_GrpChkConfig_t SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_groupEntries[SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_MAX_NUM_CHECKERS] =
{
    {  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_0_WIDTH },
    {  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_1_WIDTH },
    {  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_2_WIDTH },
    {  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_3_WIDTH },
    {  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_4_WIDTH },
    {  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_5_WIDTH },
    {  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_6_WIDTH },
    {  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_7_WIDTH },
    {  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_8_WIDTH },
    {  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_9_WIDTH },
    {  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_10_WIDTH },
    {  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_11_WIDTH },
    {  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_12_WIDTH },
    {  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_13_WIDTH },
    {  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_14_WIDTH },
    {  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_15_WIDTH },
    {  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_16_WIDTH },
    {  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_17_WIDTH },
    {  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_18_WIDTH },
    {  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_19_WIDTH },
    {  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_20_WIDTH },
    {  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_21_WIDTH },
    {  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_22_WIDTH },
    {  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_23_WIDTH },
    {  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_24_WIDTH },
    {  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_25_WIDTH },
    {  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_26_WIDTH },
    {  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_27_WIDTH },
    {  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_28_WIDTH },
    {  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_29_WIDTH },
    {  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_30_WIDTH },
    {  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_31_WIDTH },
    {  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_32_WIDTH },
    {  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_33_WIDTH },
    {  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_34_WIDTH },
    {  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_35_WIDTH },
    {  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_36_WIDTH },
    {  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_37_WIDTH },
    {  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_38_WIDTH },
    {  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_39_WIDTH },
    {  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_40_WIDTH },
    {  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_41_WIDTH },
    {  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_42_WIDTH },
    {  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_43_WIDTH },
    {  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_44_WIDTH },
    {  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_45_WIDTH },
    {  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_46_WIDTH },
    {  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_47_WIDTH },
    {  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_48_WIDTH },
    {  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_49_WIDTH },
    {  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_50_WIDTH },
    {  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_51_WIDTH },
    {  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_52_WIDTH },
    {  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_53_WIDTH },
    {  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_54_WIDTH },
    {  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_55_WIDTH },
    {  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_56_WIDTH },
    {  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_57_WIDTH },
    {  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_58_WIDTH },
    {  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_59_WIDTH },
    {  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_60_WIDTH },
    {  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_61_WIDTH },
    {  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_62_WIDTH },
    {  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_63_WIDTH },
    {  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_64_WIDTH },
    {  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_65_WIDTH },
    {  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_66_WIDTH },
    {  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_67_WIDTH },
    {  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_68_WIDTH },
    {  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_69_WIDTH },
    {  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_70_WIDTH },
    {  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_71_WIDTH },
    {  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_72_WIDTH },
    {  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_73_WIDTH },
    {  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_74_WIDTH },
    {  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_75_WIDTH },
    {  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_76_WIDTH },
    {  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_77_WIDTH },
    {  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_78_WIDTH },
    {  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_79_WIDTH },
    {  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_80_WIDTH },
    {  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_81_WIDTH },
    {  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_82_WIDTH },
    {  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_83_WIDTH },
    {  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_84_WIDTH },
    {  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_85_WIDTH },
    {  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_86_WIDTH },
    {  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_87_WIDTH },
    {  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_88_WIDTH },
    {  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_89_WIDTH },
    {  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_90_WIDTH },
    {  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_91_WIDTH },
    {  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_92_WIDTH },
    {  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_93_WIDTH },
    {  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_94_WIDTH },
    {  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_95_WIDTH },
    {  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_96_WIDTH },
    {  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_97_WIDTH },
    {  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_98_WIDTH },
    {  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_99_WIDTH },
    {  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_100_WIDTH },
    {  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_101_WIDTH },
    {  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_102_WIDTH },
    {  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_103_WIDTH },
    {  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_104_WIDTH },
    {  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_105_WIDTH },
    {  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_106_WIDTH },
    {  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_107_WIDTH },
    {  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_108_WIDTH },
    {  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_109_WIDTH },
    {  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_110_WIDTH },
    {  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_111_WIDTH },
    {  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_112_WIDTH },
    {  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_113_WIDTH },
    {  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_114_WIDTH },
    {  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_115_WIDTH },
    {  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_116_WIDTH },
    {  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_117_WIDTH },
    {  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_118_WIDTH },
    {  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_119_WIDTH },
    {  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_120_WIDTH },
    {  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_121_WIDTH },
    {  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_122_WIDTH },
    {  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_123_WIDTH },
    {  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_124_WIDTH },
    {  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_125_WIDTH },
    {  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_126_WIDTH },
    {  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_127_WIDTH },
    {  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_128_WIDTH },
    {  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_129_WIDTH },
    {  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_130_WIDTH },
    {  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_131_WIDTH },
    {  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_132_WIDTH },
    {  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_133_WIDTH },
    {  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_134_WIDTH },
    {  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_135_WIDTH },
    {  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_136_WIDTH },
    {  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_137_WIDTH },
    {  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_138_WIDTH },
    {  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_139_WIDTH },
    {  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_140_WIDTH },
    {  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_141_WIDTH },
    {  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_142_WIDTH },
    {  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_143_WIDTH },
    {  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_144_WIDTH },
    {  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_145_WIDTH },
    {  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_146_WIDTH },
    {  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_147_WIDTH },
    {  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_148_WIDTH },
    {  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_149_WIDTH },
    {  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_150_WIDTH },
    {  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_151_WIDTH },
    {  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_152_WIDTH },
    {  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_153_WIDTH },
    {  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_154_WIDTH },
    {  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_155_WIDTH },
    {  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_156_WIDTH },
    {  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_157_WIDTH },
    {  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_158_WIDTH },
    {  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_159_WIDTH },
    {  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_160_WIDTH },
    {  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_161_WIDTH },
    {  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_162_WIDTH },
    {  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_163_WIDTH },
    {  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_164_WIDTH },
    {  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_165_WIDTH },
    {  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_166_WIDTH },
    {  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_167_WIDTH },
    {  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_168_WIDTH },
    {  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_169_WIDTH },
    {  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_170_WIDTH },
};
 
static const SDL_GrpChkConfig_t SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_VBUSP_P2P_BRIDGE_EDC_CTRL_0_groupEntries[SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_VBUSP_P2P_BRIDGE_EDC_CTRL_0_MAX_NUM_CHECKERS] =
{
    {  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_VBUSP_P2P_BRIDGE_EDC_CTRL_0_GROUP_0_WIDTH },
    {  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_VBUSP_P2P_BRIDGE_EDC_CTRL_0_GROUP_1_WIDTH },
    {  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_VBUSP_P2P_BRIDGE_EDC_CTRL_0_GROUP_2_WIDTH },
};
 
static const SDL_GrpChkConfig_t SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_groupEntries[SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_MAX_NUM_CHECKERS] =
{
    {  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_0_WIDTH },
    {  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_1_WIDTH },
    {  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_2_WIDTH },
    {  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_3_WIDTH },
    {  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_4_WIDTH },
    {  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_5_WIDTH },
    {  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_6_WIDTH },
    {  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_7_WIDTH },
    {  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_8_WIDTH },
    {  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_9_WIDTH },
    {  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_10_WIDTH },
    {  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_11_WIDTH },
    {  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_12_WIDTH },
    {  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_13_WIDTH },
    {  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_14_WIDTH },
    {  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_15_WIDTH },
    {  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_16_WIDTH },
    {  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_17_WIDTH },
    {  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_18_WIDTH },
    {  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_19_WIDTH },
    {  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_20_WIDTH },
    {  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_21_WIDTH },
    {  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_22_WIDTH },
    {  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_23_WIDTH },
    {  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_24_WIDTH },
    {  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_25_WIDTH },
    {  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_26_WIDTH },
    {  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_27_WIDTH },
    {  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_28_WIDTH },
    {  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_29_WIDTH },
    {  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_30_WIDTH },
    {  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_31_WIDTH },
    {  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_32_WIDTH },
    {  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_33_WIDTH },
    {  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_34_WIDTH },
    {  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_35_WIDTH },
    {  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_36_WIDTH },
    {  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_37_WIDTH },
    {  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_38_WIDTH },
    {  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_39_WIDTH },
    {  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_40_WIDTH },
    {  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_41_WIDTH },
    {  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_42_WIDTH },
    {  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_43_WIDTH },
    {  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_44_WIDTH },
    {  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_45_WIDTH },
    {  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_46_WIDTH },
    {  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_47_WIDTH },
    {  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_48_WIDTH },
    {  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_49_WIDTH },
};
 
static const SDL_MemConfig_t SDL_PSRAMECC0_PSRAM256X32E_ECC_AGGR_MemEntries[SDL_PSRAMECC0_PSRAM256X32E_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES] =
{
    { SDL_PSRAMECC0_PSRAM256X32E_ECC_AGGR_PSRAM256X32E_PSRAM0_ECC_RAM_ID, 0u,
      SDL_PSRAMECC0_PSRAM256X32E_ECC_AGGR_PSRAM256X32E_PSRAM0_ECC_RAM_SIZE, 4u,
      SDL_PSRAMECC0_PSRAM256X32E_ECC_AGGR_PSRAM256X32E_PSRAM0_ECC_ROW_WIDTH, ((bool)true) },
};
 
static const SDL_MemConfig_t SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_MemEntries[SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES] =
{
    { SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_IMAILBOX1_MAIN_0_RAMECC_RAM_ID, 0u,
      SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_IMAILBOX1_MAIN_0_RAMECC_RAM_SIZE, 4u,
      SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_IMAILBOX1_MAIN_0_RAMECC_ROW_WIDTH, ((bool)false) },
};
 
static const SDL_GrpChkConfig_t SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_groupEntries[SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_MAX_NUM_CHECKERS] =
{
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_0_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_1_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_2_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_3_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_4_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_5_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_6_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_7_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_8_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_9_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_10_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_11_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_12_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_13_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_14_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_15_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_16_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_17_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_18_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_19_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_20_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_21_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_22_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_23_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_24_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_25_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_26_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_27_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_28_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_29_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_30_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_31_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_32_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_33_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_34_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_35_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_36_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_37_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_38_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_39_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_40_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_41_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_42_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_43_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_44_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_45_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_46_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_47_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_48_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_49_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_50_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_51_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_52_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_53_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_54_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_55_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_56_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_57_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_58_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_59_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_60_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_61_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_62_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_63_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_64_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_65_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_66_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_67_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_68_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_69_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_70_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_71_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_72_WIDTH },
};
 
static const SDL_GrpChkConfig_t SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_IAM62_MAIN_IPCSS_CBASS_MAIN_0_AM62_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_groupEntries[SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_IAM62_MAIN_IPCSS_CBASS_MAIN_0_AM62_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_MAX_NUM_CHECKERS] =
{
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_IAM62_MAIN_IPCSS_CBASS_MAIN_0_AM62_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_0_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_IAM62_MAIN_IPCSS_CBASS_MAIN_0_AM62_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_1_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_IAM62_MAIN_IPCSS_CBASS_MAIN_0_AM62_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_2_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_IAM62_MAIN_IPCSS_CBASS_MAIN_0_AM62_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_3_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_IAM62_MAIN_IPCSS_CBASS_MAIN_0_AM62_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_4_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_IAM62_MAIN_IPCSS_CBASS_MAIN_0_AM62_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_5_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_IAM62_MAIN_IPCSS_CBASS_MAIN_0_AM62_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_6_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_IAM62_MAIN_IPCSS_CBASS_MAIN_0_AM62_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_7_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_IAM62_MAIN_IPCSS_CBASS_MAIN_0_AM62_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_8_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_IAM62_MAIN_IPCSS_CBASS_MAIN_0_AM62_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_9_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_IAM62_MAIN_IPCSS_CBASS_MAIN_0_AM62_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_10_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_IAM62_MAIN_IPCSS_CBASS_MAIN_0_AM62_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_11_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_IAM62_MAIN_IPCSS_CBASS_MAIN_0_AM62_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_12_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_IAM62_MAIN_IPCSS_CBASS_MAIN_0_AM62_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_13_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_IAM62_MAIN_IPCSS_CBASS_MAIN_0_AM62_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_14_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_IAM62_MAIN_IPCSS_CBASS_MAIN_0_AM62_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_15_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_IAM62_MAIN_IPCSS_CBASS_MAIN_0_AM62_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_16_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_IAM62_MAIN_IPCSS_CBASS_MAIN_0_AM62_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_17_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_IAM62_MAIN_IPCSS_CBASS_MAIN_0_AM62_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_18_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_IAM62_MAIN_IPCSS_CBASS_MAIN_0_AM62_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_19_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_IAM62_MAIN_IPCSS_CBASS_MAIN_0_AM62_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_20_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_IAM62_MAIN_IPCSS_CBASS_MAIN_0_AM62_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_21_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_IAM62_MAIN_IPCSS_CBASS_MAIN_0_AM62_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_22_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_IAM62_MAIN_IPCSS_CBASS_MAIN_0_AM62_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_23_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_IAM62_MAIN_IPCSS_CBASS_MAIN_0_AM62_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_24_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_IAM62_MAIN_IPCSS_CBASS_MAIN_0_AM62_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_25_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_IAM62_MAIN_IPCSS_CBASS_MAIN_0_AM62_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_26_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_IAM62_MAIN_IPCSS_CBASS_MAIN_0_AM62_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_27_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_IAM62_MAIN_IPCSS_CBASS_MAIN_0_AM62_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_28_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_IAM62_MAIN_IPCSS_CBASS_MAIN_0_AM62_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_29_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_IAM62_MAIN_IPCSS_CBASS_MAIN_0_AM62_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_30_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_IAM62_MAIN_IPCSS_CBASS_MAIN_0_AM62_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_31_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_IAM62_MAIN_IPCSS_CBASS_MAIN_0_AM62_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_32_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_IAM62_MAIN_IPCSS_CBASS_MAIN_0_AM62_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_33_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_IAM62_MAIN_IPCSS_CBASS_MAIN_0_AM62_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_34_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_IAM62_MAIN_IPCSS_CBASS_MAIN_0_AM62_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_35_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_IAM62_MAIN_IPCSS_CBASS_MAIN_0_AM62_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_36_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_IAM62_MAIN_IPCSS_CBASS_MAIN_0_AM62_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_37_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_IAM62_MAIN_IPCSS_CBASS_MAIN_0_AM62_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_38_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_IAM62_MAIN_IPCSS_CBASS_MAIN_0_AM62_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_39_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_IAM62_MAIN_IPCSS_CBASS_MAIN_0_AM62_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_40_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_IAM62_MAIN_IPCSS_CBASS_MAIN_0_AM62_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_41_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_IAM62_MAIN_IPCSS_CBASS_MAIN_0_AM62_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_42_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_IAM62_MAIN_IPCSS_CBASS_MAIN_0_AM62_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_43_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_IAM62_MAIN_IPCSS_CBASS_MAIN_0_AM62_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_44_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_IAM62_MAIN_IPCSS_CBASS_MAIN_0_AM62_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_45_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_IAM62_MAIN_IPCSS_CBASS_MAIN_0_AM62_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_46_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_IAM62_MAIN_IPCSS_CBASS_MAIN_0_AM62_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_47_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_IAM62_MAIN_IPCSS_CBASS_MAIN_0_AM62_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_48_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_IAM62_MAIN_IPCSS_CBASS_MAIN_0_AM62_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_49_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_IAM62_MAIN_IPCSS_CBASS_MAIN_0_AM62_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_50_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_IAM62_MAIN_IPCSS_CBASS_MAIN_0_AM62_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_51_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_IAM62_MAIN_IPCSS_CBASS_MAIN_0_AM62_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_52_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_IAM62_MAIN_IPCSS_CBASS_MAIN_0_AM62_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_53_WIDTH },
};
 
static const SDL_GrpChkConfig_t SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_IAM62_MAIN_FW_CBASS_MAIN_0_AM62_MAIN_FW_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_groupEntries[SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_IAM62_MAIN_FW_CBASS_MAIN_0_AM62_MAIN_FW_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_MAX_NUM_CHECKERS] =
{
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_IAM62_MAIN_FW_CBASS_MAIN_0_AM62_MAIN_FW_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_0_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_IAM62_MAIN_FW_CBASS_MAIN_0_AM62_MAIN_FW_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_1_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_IAM62_MAIN_FW_CBASS_MAIN_0_AM62_MAIN_FW_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_2_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_IAM62_MAIN_FW_CBASS_MAIN_0_AM62_MAIN_FW_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_3_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_IAM62_MAIN_FW_CBASS_MAIN_0_AM62_MAIN_FW_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_4_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_IAM62_MAIN_FW_CBASS_MAIN_0_AM62_MAIN_FW_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_5_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_IAM62_MAIN_FW_CBASS_MAIN_0_AM62_MAIN_FW_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_6_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_IAM62_MAIN_FW_CBASS_MAIN_0_AM62_MAIN_FW_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_7_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_IAM62_MAIN_FW_CBASS_MAIN_0_AM62_MAIN_FW_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_8_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_IAM62_MAIN_FW_CBASS_MAIN_0_AM62_MAIN_FW_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_9_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_IAM62_MAIN_FW_CBASS_MAIN_0_AM62_MAIN_FW_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_10_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_IAM62_MAIN_FW_CBASS_MAIN_0_AM62_MAIN_FW_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_11_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_IAM62_MAIN_FW_CBASS_MAIN_0_AM62_MAIN_FW_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_12_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_IAM62_MAIN_FW_CBASS_MAIN_0_AM62_MAIN_FW_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_13_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_IAM62_MAIN_FW_CBASS_MAIN_0_AM62_MAIN_FW_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_14_WIDTH },
};
 
static const SDL_GrpChkConfig_t SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_FW_CBASS_IAM62_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM62_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_groupEntries[SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_FW_CBASS_IAM62_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM62_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS] =
{
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_FW_CBASS_IAM62_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM62_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_GROUP_0_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_FW_CBASS_IAM62_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM62_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_GROUP_1_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_FW_CBASS_IAM62_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM62_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_GROUP_2_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_FW_CBASS_IAM62_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM62_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_GROUP_3_WIDTH },
};
 
static const SDL_GrpChkConfig_t SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_FW_CBASS_IAM62_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM62_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_groupEntries[SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_FW_CBASS_IAM62_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM62_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS] =
{
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_FW_CBASS_IAM62_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM62_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_0_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_FW_CBASS_IAM62_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM62_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_1_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_FW_CBASS_IAM62_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM62_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_2_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_FW_CBASS_IAM62_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM62_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_3_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_FW_CBASS_IAM62_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM62_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_4_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_FW_CBASS_IAM62_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM62_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_5_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_FW_CBASS_IAM62_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM62_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_6_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_FW_CBASS_IAM62_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM62_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_7_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_FW_CBASS_IAM62_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM62_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_8_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_FW_CBASS_IAM62_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM62_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_9_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_FW_CBASS_IAM62_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM62_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_10_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_FW_CBASS_IAM62_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM62_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_11_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_FW_CBASS_IAM62_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM62_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_12_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_FW_CBASS_IAM62_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM62_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_13_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_FW_CBASS_IAM62_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM62_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_14_WIDTH },
};
 
static const SDL_GrpChkConfig_t SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_DST_BUSECC_groupEntries[SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS] =
{
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_DST_BUSECC_GROUP_0_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_DST_BUSECC_GROUP_1_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_DST_BUSECC_GROUP_2_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_DST_BUSECC_GROUP_3_WIDTH },
};
 
static const SDL_GrpChkConfig_t SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_SRC_BUSECC_groupEntries[SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS] =
{
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_SRC_BUSECC_GROUP_0_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_SRC_BUSECC_GROUP_1_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_SRC_BUSECC_GROUP_2_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_SRC_BUSECC_GROUP_3_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_SRC_BUSECC_GROUP_4_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_SRC_BUSECC_GROUP_5_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_SRC_BUSECC_GROUP_6_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_SRC_BUSECC_GROUP_7_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_SRC_BUSECC_GROUP_8_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_SRC_BUSECC_GROUP_9_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_SRC_BUSECC_GROUP_10_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_SRC_BUSECC_GROUP_11_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_SRC_BUSECC_GROUP_12_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_SRC_BUSECC_GROUP_13_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_SRC_BUSECC_GROUP_14_WIDTH },
};
 
static const SDL_GrpChkConfig_t SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_HSM_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_HSM_VBUSP_S_BRIDGE_BUSECC_groupEntries[SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_HSM_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_HSM_VBUSP_S_BRIDGE_BUSECC_MAX_NUM_CHECKERS] =
{
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_HSM_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_HSM_VBUSP_S_BRIDGE_BUSECC_GROUP_0_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_HSM_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_HSM_VBUSP_S_BRIDGE_BUSECC_GROUP_1_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_HSM_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_HSM_VBUSP_S_BRIDGE_BUSECC_GROUP_2_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_HSM_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_HSM_VBUSP_S_BRIDGE_BUSECC_GROUP_3_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_HSM_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_HSM_VBUSP_S_BRIDGE_BUSECC_GROUP_4_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_HSM_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_HSM_VBUSP_S_BRIDGE_BUSECC_GROUP_5_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_HSM_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_HSM_VBUSP_S_BRIDGE_BUSECC_GROUP_6_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_HSM_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_HSM_VBUSP_S_BRIDGE_BUSECC_GROUP_7_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_HSM_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_HSM_VBUSP_S_BRIDGE_BUSECC_GROUP_8_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_HSM_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_HSM_VBUSP_S_BRIDGE_BUSECC_GROUP_9_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_HSM_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_HSM_VBUSP_S_BRIDGE_BUSECC_GROUP_10_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_HSM_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_HSM_VBUSP_S_BRIDGE_BUSECC_GROUP_11_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_HSM_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_HSM_VBUSP_S_BRIDGE_BUSECC_GROUP_12_WIDTH },
};
 
static const SDL_GrpChkConfig_t SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_TIFS_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_TIFS_VBUSP_S_BRIDGE_BUSECC_groupEntries[SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_TIFS_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_TIFS_VBUSP_S_BRIDGE_BUSECC_MAX_NUM_CHECKERS] =
{
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_TIFS_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_TIFS_VBUSP_S_BRIDGE_BUSECC_GROUP_0_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_TIFS_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_TIFS_VBUSP_S_BRIDGE_BUSECC_GROUP_1_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_TIFS_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_TIFS_VBUSP_S_BRIDGE_BUSECC_GROUP_2_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_TIFS_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_TIFS_VBUSP_S_BRIDGE_BUSECC_GROUP_3_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_TIFS_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_TIFS_VBUSP_S_BRIDGE_BUSECC_GROUP_4_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_TIFS_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_TIFS_VBUSP_S_BRIDGE_BUSECC_GROUP_5_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_TIFS_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_TIFS_VBUSP_S_BRIDGE_BUSECC_GROUP_6_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_TIFS_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_TIFS_VBUSP_S_BRIDGE_BUSECC_GROUP_7_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_TIFS_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_TIFS_VBUSP_S_BRIDGE_BUSECC_GROUP_8_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_TIFS_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_TIFS_VBUSP_S_BRIDGE_BUSECC_GROUP_9_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_TIFS_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_TIFS_VBUSP_S_BRIDGE_BUSECC_GROUP_10_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_TIFS_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_TIFS_VBUSP_S_BRIDGE_BUSECC_GROUP_11_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_TIFS_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_TIFS_VBUSP_S_BRIDGE_BUSECC_GROUP_12_WIDTH },
};
 
static const SDL_GrpChkConfig_t SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_CENTRAL_CBASS_EXPORT_AM62_MAIN_CENTRAL_CBASS_TO_AM62_MCU_CBASS_DATA_L0_P2M_BRIDGE_EXPORT_AM62_MAIN_CENTRAL_CBASS_TO_AM62_MCU_CBASS_DATA_L0_BRIDGE_DST_BUSECC_groupEntries[SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_CENTRAL_CBASS_EXPORT_AM62_MAIN_CENTRAL_CBASS_TO_AM62_MCU_CBASS_DATA_L0_P2M_BRIDGE_EXPORT_AM62_MAIN_CENTRAL_CBASS_TO_AM62_MCU_CBASS_DATA_L0_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS] =
{
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_CENTRAL_CBASS_EXPORT_AM62_MAIN_CENTRAL_CBASS_TO_AM62_MCU_CBASS_DATA_L0_P2M_BRIDGE_EXPORT_AM62_MAIN_CENTRAL_CBASS_TO_AM62_MCU_CBASS_DATA_L0_BRIDGE_DST_BUSECC_GROUP_0_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_CENTRAL_CBASS_EXPORT_AM62_MAIN_CENTRAL_CBASS_TO_AM62_MCU_CBASS_DATA_L0_P2M_BRIDGE_EXPORT_AM62_MAIN_CENTRAL_CBASS_TO_AM62_MCU_CBASS_DATA_L0_BRIDGE_DST_BUSECC_GROUP_1_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_CENTRAL_CBASS_EXPORT_AM62_MAIN_CENTRAL_CBASS_TO_AM62_MCU_CBASS_DATA_L0_P2M_BRIDGE_EXPORT_AM62_MAIN_CENTRAL_CBASS_TO_AM62_MCU_CBASS_DATA_L0_BRIDGE_DST_BUSECC_GROUP_2_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_CENTRAL_CBASS_EXPORT_AM62_MAIN_CENTRAL_CBASS_TO_AM62_MCU_CBASS_DATA_L0_P2M_BRIDGE_EXPORT_AM62_MAIN_CENTRAL_CBASS_TO_AM62_MCU_CBASS_DATA_L0_BRIDGE_DST_BUSECC_GROUP_3_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_CENTRAL_CBASS_EXPORT_AM62_MAIN_CENTRAL_CBASS_TO_AM62_MCU_CBASS_DATA_L0_P2M_BRIDGE_EXPORT_AM62_MAIN_CENTRAL_CBASS_TO_AM62_MCU_CBASS_DATA_L0_BRIDGE_DST_BUSECC_GROUP_4_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_CENTRAL_CBASS_EXPORT_AM62_MAIN_CENTRAL_CBASS_TO_AM62_MCU_CBASS_DATA_L0_P2M_BRIDGE_EXPORT_AM62_MAIN_CENTRAL_CBASS_TO_AM62_MCU_CBASS_DATA_L0_BRIDGE_DST_BUSECC_GROUP_5_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_CENTRAL_CBASS_EXPORT_AM62_MAIN_CENTRAL_CBASS_TO_AM62_MCU_CBASS_DATA_L0_P2M_BRIDGE_EXPORT_AM62_MAIN_CENTRAL_CBASS_TO_AM62_MCU_CBASS_DATA_L0_BRIDGE_DST_BUSECC_GROUP_6_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_CENTRAL_CBASS_EXPORT_AM62_MAIN_CENTRAL_CBASS_TO_AM62_MCU_CBASS_DATA_L0_P2M_BRIDGE_EXPORT_AM62_MAIN_CENTRAL_CBASS_TO_AM62_MCU_CBASS_DATA_L0_BRIDGE_DST_BUSECC_GROUP_7_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_CENTRAL_CBASS_EXPORT_AM62_MAIN_CENTRAL_CBASS_TO_AM62_MCU_CBASS_DATA_L0_P2M_BRIDGE_EXPORT_AM62_MAIN_CENTRAL_CBASS_TO_AM62_MCU_CBASS_DATA_L0_BRIDGE_DST_BUSECC_GROUP_8_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_CENTRAL_CBASS_EXPORT_AM62_MAIN_CENTRAL_CBASS_TO_AM62_MCU_CBASS_DATA_L0_P2M_BRIDGE_EXPORT_AM62_MAIN_CENTRAL_CBASS_TO_AM62_MCU_CBASS_DATA_L0_BRIDGE_DST_BUSECC_GROUP_9_WIDTH },
};
 
static const SDL_GrpChkConfig_t SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_CENTRAL_CBASS_EXPORT_AM62_MAIN_CENTRAL_CBASS_TO_AM62_MCU_CBASS_DATA_L0_P2M_BRIDGE_EXPORT_AM62_MAIN_CENTRAL_CBASS_TO_AM62_MCU_CBASS_DATA_L0_BRIDGE_SRC_BUSECC_groupEntries[SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_CENTRAL_CBASS_EXPORT_AM62_MAIN_CENTRAL_CBASS_TO_AM62_MCU_CBASS_DATA_L0_P2M_BRIDGE_EXPORT_AM62_MAIN_CENTRAL_CBASS_TO_AM62_MCU_CBASS_DATA_L0_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS] =
{
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_CENTRAL_CBASS_EXPORT_AM62_MAIN_CENTRAL_CBASS_TO_AM62_MCU_CBASS_DATA_L0_P2M_BRIDGE_EXPORT_AM62_MAIN_CENTRAL_CBASS_TO_AM62_MCU_CBASS_DATA_L0_BRIDGE_SRC_BUSECC_GROUP_0_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_CENTRAL_CBASS_EXPORT_AM62_MAIN_CENTRAL_CBASS_TO_AM62_MCU_CBASS_DATA_L0_P2M_BRIDGE_EXPORT_AM62_MAIN_CENTRAL_CBASS_TO_AM62_MCU_CBASS_DATA_L0_BRIDGE_SRC_BUSECC_GROUP_1_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_CENTRAL_CBASS_EXPORT_AM62_MAIN_CENTRAL_CBASS_TO_AM62_MCU_CBASS_DATA_L0_P2M_BRIDGE_EXPORT_AM62_MAIN_CENTRAL_CBASS_TO_AM62_MCU_CBASS_DATA_L0_BRIDGE_SRC_BUSECC_GROUP_2_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_CENTRAL_CBASS_EXPORT_AM62_MAIN_CENTRAL_CBASS_TO_AM62_MCU_CBASS_DATA_L0_P2M_BRIDGE_EXPORT_AM62_MAIN_CENTRAL_CBASS_TO_AM62_MCU_CBASS_DATA_L0_BRIDGE_SRC_BUSECC_GROUP_3_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_CENTRAL_CBASS_EXPORT_AM62_MAIN_CENTRAL_CBASS_TO_AM62_MCU_CBASS_DATA_L0_P2M_BRIDGE_EXPORT_AM62_MAIN_CENTRAL_CBASS_TO_AM62_MCU_CBASS_DATA_L0_BRIDGE_SRC_BUSECC_GROUP_4_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_CENTRAL_CBASS_EXPORT_AM62_MAIN_CENTRAL_CBASS_TO_AM62_MCU_CBASS_DATA_L0_P2M_BRIDGE_EXPORT_AM62_MAIN_CENTRAL_CBASS_TO_AM62_MCU_CBASS_DATA_L0_BRIDGE_SRC_BUSECC_GROUP_5_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_CENTRAL_CBASS_EXPORT_AM62_MAIN_CENTRAL_CBASS_TO_AM62_MCU_CBASS_DATA_L0_P2M_BRIDGE_EXPORT_AM62_MAIN_CENTRAL_CBASS_TO_AM62_MCU_CBASS_DATA_L0_BRIDGE_SRC_BUSECC_GROUP_6_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_CENTRAL_CBASS_EXPORT_AM62_MAIN_CENTRAL_CBASS_TO_AM62_MCU_CBASS_DATA_L0_P2M_BRIDGE_EXPORT_AM62_MAIN_CENTRAL_CBASS_TO_AM62_MCU_CBASS_DATA_L0_BRIDGE_SRC_BUSECC_GROUP_7_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_CENTRAL_CBASS_EXPORT_AM62_MAIN_CENTRAL_CBASS_TO_AM62_MCU_CBASS_DATA_L0_P2M_BRIDGE_EXPORT_AM62_MAIN_CENTRAL_CBASS_TO_AM62_MCU_CBASS_DATA_L0_BRIDGE_SRC_BUSECC_GROUP_8_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_CENTRAL_CBASS_EXPORT_AM62_MAIN_CENTRAL_CBASS_TO_AM62_MCU_CBASS_DATA_L0_P2M_BRIDGE_EXPORT_AM62_MAIN_CENTRAL_CBASS_TO_AM62_MCU_CBASS_DATA_L0_BRIDGE_SRC_BUSECC_GROUP_9_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_CENTRAL_CBASS_EXPORT_AM62_MAIN_CENTRAL_CBASS_TO_AM62_MCU_CBASS_DATA_L0_P2M_BRIDGE_EXPORT_AM62_MAIN_CENTRAL_CBASS_TO_AM62_MCU_CBASS_DATA_L0_BRIDGE_SRC_BUSECC_GROUP_10_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_CENTRAL_CBASS_EXPORT_AM62_MAIN_CENTRAL_CBASS_TO_AM62_MCU_CBASS_DATA_L0_P2M_BRIDGE_EXPORT_AM62_MAIN_CENTRAL_CBASS_TO_AM62_MCU_CBASS_DATA_L0_BRIDGE_SRC_BUSECC_GROUP_11_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_CENTRAL_CBASS_EXPORT_AM62_MAIN_CENTRAL_CBASS_TO_AM62_MCU_CBASS_DATA_L0_P2M_BRIDGE_EXPORT_AM62_MAIN_CENTRAL_CBASS_TO_AM62_MCU_CBASS_DATA_L0_BRIDGE_SRC_BUSECC_GROUP_12_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_CENTRAL_CBASS_EXPORT_AM62_MAIN_CENTRAL_CBASS_TO_AM62_MCU_CBASS_DATA_L0_P2M_BRIDGE_EXPORT_AM62_MAIN_CENTRAL_CBASS_TO_AM62_MCU_CBASS_DATA_L0_BRIDGE_SRC_BUSECC_GROUP_13_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_CENTRAL_CBASS_EXPORT_AM62_MAIN_CENTRAL_CBASS_TO_AM62_MCU_CBASS_DATA_L0_P2M_BRIDGE_EXPORT_AM62_MAIN_CENTRAL_CBASS_TO_AM62_MCU_CBASS_DATA_L0_BRIDGE_SRC_BUSECC_GROUP_14_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_CENTRAL_CBASS_EXPORT_AM62_MAIN_CENTRAL_CBASS_TO_AM62_MCU_CBASS_DATA_L0_P2M_BRIDGE_EXPORT_AM62_MAIN_CENTRAL_CBASS_TO_AM62_MCU_CBASS_DATA_L0_BRIDGE_SRC_BUSECC_GROUP_15_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_CENTRAL_CBASS_EXPORT_AM62_MAIN_CENTRAL_CBASS_TO_AM62_MCU_CBASS_DATA_L0_P2M_BRIDGE_EXPORT_AM62_MAIN_CENTRAL_CBASS_TO_AM62_MCU_CBASS_DATA_L0_BRIDGE_SRC_BUSECC_GROUP_16_WIDTH },
};
 
static const SDL_GrpChkConfig_t SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_IP2P_SA3_DMSS_CFG_DST_BUSECC_groupEntries[SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_IP2P_SA3_DMSS_CFG_DST_BUSECC_MAX_NUM_CHECKERS] =
{
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_IP2P_SA3_DMSS_CFG_DST_BUSECC_GROUP_0_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_IP2P_SA3_DMSS_CFG_DST_BUSECC_GROUP_1_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_IP2P_SA3_DMSS_CFG_DST_BUSECC_GROUP_2_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_IP2P_SA3_DMSS_CFG_DST_BUSECC_GROUP_3_WIDTH },
};
 
static const SDL_GrpChkConfig_t SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_IP2P_SA3_DMSS_CFG_SRC_BUSECC_groupEntries[SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_IP2P_SA3_DMSS_CFG_SRC_BUSECC_MAX_NUM_CHECKERS] =
{
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_IP2P_SA3_DMSS_CFG_SRC_BUSECC_GROUP_0_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_IP2P_SA3_DMSS_CFG_SRC_BUSECC_GROUP_1_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_IP2P_SA3_DMSS_CFG_SRC_BUSECC_GROUP_2_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_IP2P_SA3_DMSS_CFG_SRC_BUSECC_GROUP_3_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_IP2P_SA3_DMSS_CFG_SRC_BUSECC_GROUP_4_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_IP2P_SA3_DMSS_CFG_SRC_BUSECC_GROUP_5_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_IP2P_SA3_DMSS_CFG_SRC_BUSECC_GROUP_6_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_IP2P_SA3_DMSS_CFG_SRC_BUSECC_GROUP_7_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_IP2P_SA3_DMSS_CFG_SRC_BUSECC_GROUP_8_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_IP2P_SA3_DMSS_CFG_SRC_BUSECC_GROUP_9_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_IP2P_SA3_DMSS_CFG_SRC_BUSECC_GROUP_10_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_IP2P_SA3_DMSS_CFG_SRC_BUSECC_GROUP_11_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_IP2P_SA3_DMSS_CFG_SRC_BUSECC_GROUP_12_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_IP2P_SA3_DMSS_CFG_SRC_BUSECC_GROUP_13_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_IP2P_SA3_DMSS_CFG_SRC_BUSECC_GROUP_14_WIDTH },
};
 
static const SDL_GrpChkConfig_t SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_IP2P_SA3_PKTDMA_CRED_DST_BUSECC_groupEntries[SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_IP2P_SA3_PKTDMA_CRED_DST_BUSECC_MAX_NUM_CHECKERS] =
{
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_IP2P_SA3_PKTDMA_CRED_DST_BUSECC_GROUP_0_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_IP2P_SA3_PKTDMA_CRED_DST_BUSECC_GROUP_1_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_IP2P_SA3_PKTDMA_CRED_DST_BUSECC_GROUP_2_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_IP2P_SA3_PKTDMA_CRED_DST_BUSECC_GROUP_3_WIDTH },
};
 
static const SDL_GrpChkConfig_t SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_IP2P_SA3_PKTDMA_CRED_SRC_BUSECC_groupEntries[SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_IP2P_SA3_PKTDMA_CRED_SRC_BUSECC_MAX_NUM_CHECKERS] =
{
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_IP2P_SA3_PKTDMA_CRED_SRC_BUSECC_GROUP_0_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_IP2P_SA3_PKTDMA_CRED_SRC_BUSECC_GROUP_1_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_IP2P_SA3_PKTDMA_CRED_SRC_BUSECC_GROUP_2_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_IP2P_SA3_PKTDMA_CRED_SRC_BUSECC_GROUP_3_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_IP2P_SA3_PKTDMA_CRED_SRC_BUSECC_GROUP_4_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_IP2P_SA3_PKTDMA_CRED_SRC_BUSECC_GROUP_5_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_IP2P_SA3_PKTDMA_CRED_SRC_BUSECC_GROUP_6_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_IP2P_SA3_PKTDMA_CRED_SRC_BUSECC_GROUP_7_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_IP2P_SA3_PKTDMA_CRED_SRC_BUSECC_GROUP_8_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_IP2P_SA3_PKTDMA_CRED_SRC_BUSECC_GROUP_9_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_IP2P_SA3_PKTDMA_CRED_SRC_BUSECC_GROUP_10_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_IP2P_SA3_PKTDMA_CRED_SRC_BUSECC_GROUP_11_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_IP2P_SA3_PKTDMA_CRED_SRC_BUSECC_GROUP_12_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_IP2P_SA3_PKTDMA_CRED_SRC_BUSECC_GROUP_13_WIDTH },
    {  SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_IP2P_SA3_PKTDMA_CRED_SRC_BUSECC_GROUP_14_WIDTH },
};
 
static const SDL_MemConfig_t SDL_ICSSM0_ICSS_M_CORE_BORG_ECC_AGGR_MemEntries[SDL_ICSSM0_ICSS_M_CORE_BORG_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES] =
{
    { SDL_ICSSM0_ICSS_M_CORE_BORG_ECC_AGGR_ICSS_M_CORE_DRAM0_ECC_RAM_ID, 0x30040000u,
      SDL_ICSSM0_ICSS_M_CORE_BORG_ECC_AGGR_ICSS_M_CORE_DRAM0_ECC_RAM_SIZE, 4u,
      SDL_ICSSM0_ICSS_M_CORE_BORG_ECC_AGGR_ICSS_M_CORE_DRAM0_ECC_ROW_WIDTH, ((bool)true) },
    { SDL_ICSSM0_ICSS_M_CORE_BORG_ECC_AGGR_ICSS_M_CORE_DRAM1_ECC_RAM_ID, 0x30042000u,
      SDL_ICSSM0_ICSS_M_CORE_BORG_ECC_AGGR_ICSS_M_CORE_DRAM1_ECC_RAM_SIZE, 4u,
      SDL_ICSSM0_ICSS_M_CORE_BORG_ECC_AGGR_ICSS_M_CORE_DRAM1_ECC_ROW_WIDTH, ((bool)true) },
    { SDL_ICSSM0_ICSS_M_CORE_BORG_ECC_AGGR_ICSS_M_CORE_PR1_PDSP0_IRAM_ECC_RAM_ID, 0x30074000u,
      SDL_ICSSM0_ICSS_M_CORE_BORG_ECC_AGGR_ICSS_M_CORE_PR1_PDSP0_IRAM_ECC_RAM_SIZE, 4u,
      SDL_ICSSM0_ICSS_M_CORE_BORG_ECC_AGGR_ICSS_M_CORE_PR1_PDSP0_IRAM_ECC_ROW_WIDTH, ((bool)true) },
    { SDL_ICSSM0_ICSS_M_CORE_BORG_ECC_AGGR_ICSS_M_CORE_PR1_PDSP1_IRAM_ECC_RAM_ID, 0x30078000u,
      SDL_ICSSM0_ICSS_M_CORE_BORG_ECC_AGGR_ICSS_M_CORE_PR1_PDSP1_IRAM_ECC_RAM_SIZE, 4u,
      SDL_ICSSM0_ICSS_M_CORE_BORG_ECC_AGGR_ICSS_M_CORE_PR1_PDSP1_IRAM_ECC_ROW_WIDTH, ((bool)true) },
    { SDL_ICSSM0_ICSS_M_CORE_BORG_ECC_AGGR_ICSS_M_CORE_RAM_ECC_RAM_ID, 0x30050000u,
      SDL_ICSSM0_ICSS_M_CORE_BORG_ECC_AGGR_ICSS_M_CORE_RAM_ECC_RAM_SIZE, 4u,
      SDL_ICSSM0_ICSS_M_CORE_BORG_ECC_AGGR_ICSS_M_CORE_RAM_ECC_ROW_WIDTH, ((bool)true) },
};
 
static const SDL_MemConfig_t SDL_FSS0_FSS_UL_OSPI0_OSPI_WRAP_ECC_AGGR_MemEntries[SDL_FSS0_FSS_UL_OSPI0_OSPI_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES] =
{
    { SDL_FSS0_FSS_UL_OSPI0_OSPI_WRAP_ECC_AGGR_OSPI_OSPI_WRAP_SRAM_RAM_ID, 0u,
      SDL_FSS0_FSS_UL_OSPI0_OSPI_WRAP_ECC_AGGR_OSPI_OSPI_WRAP_SRAM_RAM_SIZE, 4u,
      SDL_FSS0_FSS_UL_OSPI0_OSPI_WRAP_ECC_AGGR_OSPI_OSPI_WRAP_SRAM_ROW_WIDTH, ((bool)false) },
};
 
static const SDL_MemConfig_t SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR_MemEntries[SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES] =
{
    { SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR_ALE_RAM_RAM_ID, 0u,
      SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR_ALE_RAM_RAM_SIZE, 4u,
      SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR_ALE_RAM_ROW_WIDTH, ((bool)false) },
    { SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR_P0_RX_FIFO_RAM_ID, 0u,
      SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR_P0_RX_FIFO_RAM_SIZE, 4u,
      SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR_P0_RX_FIFO_ROW_WIDTH, ((bool)false) },
    { SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR_P0_TX_FIFO_RAM_ID, 0u,
      SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR_P0_TX_FIFO_RAM_SIZE, 4u,
      SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR_P0_TX_FIFO_ROW_WIDTH, ((bool)false) },
    { SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR_P1_RX_FIFO_RAM_ID, 0u,
      SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR_P1_RX_FIFO_RAM_SIZE, 4u,
      SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR_P1_RX_FIFO_ROW_WIDTH, ((bool)false) },
    { SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR_P1_TX_FIFO_RAM_ID, 0u,
      SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR_P1_TX_FIFO_RAM_SIZE, 4u,
      SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR_P1_TX_FIFO_ROW_WIDTH, ((bool)false) },
    { SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR_P2_RX_FIFO_RAM_ID, 0u,
      SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR_P2_RX_FIFO_RAM_SIZE, 4u,
      SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR_P2_RX_FIFO_ROW_WIDTH, ((bool)false) },
    { SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR_P2_TX_FIFO_RAM_ID, 0u,
      SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR_P2_TX_FIFO_RAM_SIZE, 4u,
      SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR_P2_TX_FIFO_ROW_WIDTH, ((bool)false) },
    { SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR_EST_RAM_RAM_ID, 0u,
      SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR_EST_RAM_RAM_SIZE, 4u,
      SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR_EST_RAM_ROW_WIDTH, ((bool)false) },
};
static const SDL_MemConfig_t SDL_GICSS0_GIC500SS_1_4_ECC_AGGR_MemEntries[SDL_GICSS0_GIC500SS_1_4_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES] =
{
    { SDL_GICSS0_GIC500SS_1_4_ECC_AGGR_ICB_RAMECC_RAM_ID, 0x3F004000u,
      SDL_GICSS0_GIC500SS_1_4_ECC_AGGR_ICB_RAMECC_RAM_SIZE, 4u,
      SDL_GICSS0_GIC500SS_1_4_ECC_AGGR_ICB_RAMECC_ROW_WIDTH, ((bool)true) },
    { SDL_GICSS0_GIC500SS_1_4_ECC_AGGR_ITE_RAMECC_RAM_ID, 0u,
      SDL_GICSS0_GIC500SS_1_4_ECC_AGGR_ITE_RAMECC_RAM_SIZE, 4u,
      SDL_GICSS0_GIC500SS_1_4_ECC_AGGR_ITE_RAMECC_ROW_WIDTH, ((bool)true) },
    { SDL_GICSS0_GIC500SS_1_4_ECC_AGGR_LPI_RAMECC_RAM_ID, 0u,
      SDL_GICSS0_GIC500SS_1_4_ECC_AGGR_LPI_RAMECC_RAM_SIZE, 4u,
      SDL_GICSS0_GIC500SS_1_4_ECC_AGGR_LPI_RAMECC_ROW_WIDTH, ((bool)true) },
};
 
static const SDL_MemConfig_t SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_MemEntries[SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_RAM_IDS_TOTAL_ENTRIES] =
{
    { SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_CFG_CONFIG_RAM_ID, 0u,
      SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_CFG_CONFIG_RAM_SIZE, 4u,
      SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_CFG_CONFIG_ROW_WIDTH, ((bool)false) },
    { SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_CFG_STATE_RAM_ID, 0u,
      SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_CFG_STATE_RAM_SIZE, 4u,
      SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_CFG_STATE_ROW_WIDTH, ((bool)false) },
    { SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_TPCFIFO_F0_RAM_ID, 0u,
      SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_TPCFIFO_F0_RAM_SIZE, 4u,
      SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_TPCFIFO_F0_ROW_WIDTH, ((bool)false) },
    { SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_TPCFIFO_F1_RAM_ID, 0u,
      SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_TPCFIFO_F1_RAM_SIZE, 4u,
      SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_TPCFIFO_F1_ROW_WIDTH, ((bool)false) },
    { SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_RPCFIFO_F0_RAM_ID, 0u,
      SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_RPCFIFO_F0_RAM_SIZE, 4u,
      SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_RPCFIFO_F0_ROW_WIDTH, ((bool)false) },
    { SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_RPCFIFO_F1_RAM_ID, 0u,
      SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_RPCFIFO_F1_RAM_SIZE, 4u,
      SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_RPCFIFO_F1_ROW_WIDTH, ((bool)false) },
    { SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_RPCFIFO_WC_RAM_ID, 0u,
      SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_RPCFIFO_WC_RAM_SIZE, 4u,
      SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_RPCFIFO_WC_ROW_WIDTH, ((bool)false) },
    { SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_STATS_STST0_RAM_ID, 0u,
      SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_STATS_STST0_RAM_SIZE, 4u,
      SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_STATS_STST0_ROW_WIDTH, ((bool)false) },
    { SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_STATS_STSR0_RAM_ID, 0u,
      SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_STATS_STSR0_RAM_SIZE, 4u,
      SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_STATS_STSR0_ROW_WIDTH, ((bool)false) },
    { SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_RINGOCC_CNTR_RAM_ID, 0u,
      SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_RINGOCC_CNTR_RAM_SIZE, 4u,
      SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_RINGOCC_CNTR_ROW_WIDTH, ((bool)false) },
    { SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_STATREG_SR_SPRAM_8X128_SWW_SR_RAM_ID, 0u,
      SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_STATREG_SR_SPRAM_8X128_SWW_SR_RAM_SIZE, 4u,
      SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_STATREG_SR_SPRAM_8X128_SWW_SR_ROW_WIDTH, ((bool)false) },
    { SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_COMMON_IM_TPRAM_158X34_SWW_SR_RAM_ID, 0u,
      SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_COMMON_IM_TPRAM_158X34_SWW_SR_RAM_SIZE, 4u,
      SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_COMMON_IM_TPRAM_158X34_SWW_SR_ROW_WIDTH, ((bool)false) },
    { SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_STRAM_RAM_ID, 0u,
      SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_STRAM_RAM_SIZE, 4u,
      SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_STRAM_ROW_WIDTH, ((bool)false) },
    { SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_BUF_STRAM_RAM_ID, 0u,
      SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_BUF_STRAM_RAM_SIZE, 4u,
      SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_BUF_STRAM_ROW_WIDTH, ((bool)false) },
    { SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_BUF_BUFRAM_RAM_ID, 0u,
      SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_BUF_BUFRAM_RAM_SIZE, 4u,
      SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_BUF_BUFRAM_ROW_WIDTH, ((bool)false) },
    { SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_ECC0_RAM_ID, 0u,
      SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_ECC0_RAM_SIZE, 4u,
      SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_ECC0_ROW_WIDTH, ((bool)false) },
};
 
static const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_ECCAGGR_EDC_CTRL_groupEntries[SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_ECCAGGR_EDC_CTRL_MAX_NUM_CHECKERS] =
{
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_ECCAGGR_EDC_CTRL_GROUP_0_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_ECCAGGR_EDC_CTRL_GROUP_1_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_ECCAGGR_EDC_CTRL_GROUP_2_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_ECCAGGR_EDC_CTRL_GROUP_3_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_ECCAGGR_EDC_CTRL_GROUP_4_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_ECCAGGR_EDC_CTRL_GROUP_5_WIDTH },
};
 
static const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_groupEntries[SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_MAX_NUM_CHECKERS] =
{
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_0_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_1_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_2_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_3_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_4_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_5_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_6_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_7_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_8_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_9_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_10_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_11_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_12_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_13_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_14_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_15_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_16_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_17_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_18_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_19_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_20_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_21_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_22_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_23_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_24_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_25_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_26_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_27_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_28_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_29_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_30_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_31_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_32_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_33_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_34_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_35_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_36_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_37_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_38_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_39_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_40_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_41_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_42_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_43_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_44_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_45_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_46_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_47_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_48_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_49_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_50_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_51_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_52_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_53_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_54_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_55_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_56_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_57_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_58_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_59_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_60_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_61_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_62_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_63_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_64_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_65_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_66_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_67_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_68_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_69_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_70_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_71_WIDTH },
};
 
static const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_EDC_CTRL_0_groupEntries[SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_EDC_CTRL_0_MAX_NUM_CHECKERS] =
{
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_EDC_CTRL_0_GROUP_0_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_EDC_CTRL_0_GROUP_1_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_EDC_CTRL_0_GROUP_2_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_EDC_CTRL_0_GROUP_3_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_EDC_CTRL_0_GROUP_4_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_EDC_CTRL_0_GROUP_5_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_EDC_CTRL_0_GROUP_6_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_EDC_CTRL_0_GROUP_7_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_EDC_CTRL_0_GROUP_8_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_EDC_CTRL_0_GROUP_9_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_EDC_CTRL_0_GROUP_10_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_EDC_CTRL_0_GROUP_11_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_EDC_CTRL_0_GROUP_12_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_EDC_CTRL_0_GROUP_13_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_EDC_CTRL_0_GROUP_14_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_EDC_CTRL_0_GROUP_15_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_EDC_CTRL_0_GROUP_16_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_EDC_CTRL_0_GROUP_17_WIDTH },
};
 
static const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_groupEntries[SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_MAX_NUM_CHECKERS] =
{
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_0_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_1_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_2_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_3_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_4_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_5_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_6_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_7_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_8_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_9_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_10_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_11_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_12_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_13_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_14_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_15_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_16_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_17_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_18_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_19_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_20_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_21_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_22_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_23_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_24_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_25_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_26_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_27_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_28_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_29_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_30_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_31_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_32_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_33_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_34_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_35_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_36_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_37_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_38_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_39_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_40_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_41_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_42_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_43_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_44_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_45_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_46_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_47_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_48_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_49_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_50_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_51_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_52_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_53_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_54_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_55_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_56_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_57_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_58_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_59_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_60_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_61_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_62_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_63_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_64_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_65_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_66_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_67_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_68_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_69_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_70_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_71_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_72_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_73_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_74_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_75_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_76_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_77_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_78_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_79_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_80_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_81_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_82_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_83_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_84_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_85_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_86_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_87_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_88_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_89_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_90_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_91_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_92_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_93_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_94_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_95_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_96_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_97_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_98_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_99_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_100_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_101_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_102_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_103_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_104_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_105_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_106_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_107_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_108_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_109_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_110_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_111_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_112_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_113_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_114_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_115_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_116_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_117_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_118_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_119_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_120_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_121_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_122_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_123_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_124_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_125_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_126_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_127_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_128_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_129_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_130_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_131_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_132_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_133_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_134_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_135_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_136_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_137_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_138_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_139_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_140_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_141_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_142_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_143_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_144_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_145_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_146_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_147_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_148_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_149_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_150_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_151_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_152_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_153_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_154_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_155_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_156_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_157_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_158_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_159_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_160_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_161_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_162_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_163_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_164_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_165_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_166_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_167_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_168_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_169_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_170_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_171_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_172_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_173_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_174_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_175_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_176_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_177_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_178_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_179_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_180_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_181_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_182_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_183_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_184_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_185_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_186_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_187_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_188_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_189_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_190_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_191_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_192_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_193_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_194_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_195_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_196_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_197_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_198_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_199_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_200_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_201_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_202_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_203_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_204_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_205_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_206_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_207_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_208_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_209_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_210_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_211_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_212_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_213_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_214_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_215_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_216_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_217_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_218_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_219_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_220_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_221_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_222_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_223_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_224_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_225_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_226_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_227_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_228_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_229_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_230_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_231_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_232_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_233_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_234_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_235_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_236_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_237_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_238_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_239_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_240_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_241_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_242_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_243_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_244_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_245_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_246_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_247_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_248_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_249_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_250_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_251_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_252_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_253_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_254_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_255_WIDTH },
};
 
static const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_groupEntries[SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_MAX_NUM_CHECKERS] =
{
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_0_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_1_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_2_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_3_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_4_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_5_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_6_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_7_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_8_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_9_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_10_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_11_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_12_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_13_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_14_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_15_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_16_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_17_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_18_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_19_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_20_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_21_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_22_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_23_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_24_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_25_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_26_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_27_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_28_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_29_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_30_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_31_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_32_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_33_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_34_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_35_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_36_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_37_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_38_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_39_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_40_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_41_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_42_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_43_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_44_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_45_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_46_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_47_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_48_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_49_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_50_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_51_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_52_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_53_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_54_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_55_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_56_WIDTH },
};
 
static const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_groupEntries[SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_MAX_NUM_CHECKERS] =
{
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_0_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_1_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_2_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_3_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_4_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_5_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_6_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_7_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_8_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_9_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_10_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_11_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_12_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_13_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_14_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_15_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_16_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_17_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_18_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_19_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_20_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_21_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_22_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_23_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_24_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_25_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_26_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_27_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_28_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_29_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_30_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_31_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_32_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_33_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_34_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_35_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_36_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_37_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_38_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_39_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_40_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_41_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_42_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_43_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_44_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_45_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_46_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_47_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_48_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_49_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_50_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_51_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_52_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_53_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_54_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_55_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_56_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_57_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_58_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_59_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_60_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_61_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_62_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_63_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_64_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_65_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_66_WIDTH },
};
 
static const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries[SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS] =
{
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_0_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_1_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_2_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_3_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_4_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_5_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_6_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_7_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_8_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_9_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_10_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_11_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_12_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_13_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_14_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_15_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_16_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_17_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_18_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_19_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_20_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_21_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_22_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_23_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_24_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_25_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_26_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_27_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_28_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_29_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_30_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_31_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_32_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_33_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_34_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_35_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_36_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_37_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_38_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_39_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_40_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_41_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_42_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_43_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_44_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_45_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_46_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_47_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_48_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_49_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_50_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_51_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_52_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_53_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_54_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_55_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_56_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_57_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_58_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_59_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_60_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_61_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_62_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_63_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_64_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_65_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_66_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_67_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_68_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_69_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_70_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_71_WIDTH },
};
 
static const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_groupEntries[SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_MAX_NUM_CHECKERS] =
{
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_0_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_1_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_2_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_3_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_4_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_5_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_6_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_7_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_8_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_9_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_10_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_11_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_12_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_13_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_14_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_15_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_16_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_17_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_18_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_19_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_20_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_21_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_22_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_23_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_24_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_25_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_26_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_27_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_28_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_29_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_30_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_31_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_32_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_33_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_34_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_35_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_36_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_37_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_38_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_39_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_40_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_41_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_42_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_43_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_44_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_45_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_46_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_47_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_48_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_49_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_50_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_51_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_52_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_53_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_54_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_55_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_56_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_57_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_58_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_59_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_60_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_61_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_62_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_63_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_64_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_65_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_66_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_67_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_68_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_69_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_70_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_71_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_72_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_73_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_74_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_75_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_76_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_77_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_78_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_79_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_80_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_81_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_82_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_83_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_84_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_85_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_86_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_87_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_88_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_89_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_90_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_91_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_92_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_93_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_94_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_95_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_96_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_97_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_98_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_99_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_100_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_101_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_102_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_103_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_104_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_105_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_106_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_107_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_108_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_109_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_110_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_111_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_112_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_113_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_114_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_115_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_116_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_117_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_118_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_119_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_120_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_121_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_122_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_123_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_124_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_125_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_126_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_127_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_128_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_129_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_130_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_131_WIDTH },
};
 
static const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_VD2GCLK_EDC_CTRL_0_groupEntries[SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_VD2GCLK_EDC_CTRL_0_MAX_NUM_CHECKERS] =
{
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_0_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_1_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_2_WIDTH },
};
 
static const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_groupEntries[SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_MAX_NUM_CHECKERS] =
{
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_0_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_1_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_2_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_3_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_4_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_5_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_6_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_7_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_8_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_9_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_10_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_11_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_12_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_13_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_14_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_15_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_16_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_17_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_18_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_19_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_20_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_21_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_22_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_23_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_24_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_25_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_26_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_27_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_28_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_29_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_30_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_31_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_32_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_33_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_34_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_35_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_36_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_37_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_38_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_39_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_40_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_41_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_42_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_43_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_44_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_45_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_46_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_47_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_48_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_49_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_50_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_51_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_52_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_53_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_54_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_55_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_56_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_57_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_58_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_59_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_60_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_61_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_62_WIDTH },
};
 
static const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_groupEntries[SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_MAX_NUM_CHECKERS] =
{
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_0_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_1_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_2_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_3_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_4_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_5_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_6_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_7_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_8_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_9_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_10_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_11_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_12_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_13_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_14_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_15_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_16_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_17_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_18_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_19_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_20_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_21_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_22_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_23_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_24_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_25_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_26_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_27_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_28_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_29_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_30_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_31_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_32_WIDTH },
};
 
static const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_groupEntries[SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_MAX_NUM_CHECKERS] =
{
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_0_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_1_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_2_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_3_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_4_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_5_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_6_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_7_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_8_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_9_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_10_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_11_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_12_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_13_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_14_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_15_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_16_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_17_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_18_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_19_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_20_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_21_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_22_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_23_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_24_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_25_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_26_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_27_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_28_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_29_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_30_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_31_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_32_WIDTH },
};
 
static const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_groupEntries[SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_MAX_NUM_CHECKERS] =
{
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_0_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_1_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_2_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_3_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_4_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_5_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_6_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_7_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_8_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_9_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_10_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_11_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_12_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_13_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_14_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_15_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_16_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_17_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_18_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_19_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_20_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_21_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_22_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_23_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_24_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_25_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_26_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_27_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_28_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_29_WIDTH },
};
 
static const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_groupEntries[SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_MAX_NUM_CHECKERS] =
{
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_0_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_1_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_2_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_3_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_4_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_5_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_6_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_7_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_8_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_9_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_10_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_11_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_12_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_13_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_14_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_15_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_16_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_17_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_18_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_19_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_20_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_21_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_22_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_23_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_24_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_25_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_26_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_27_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_28_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_29_WIDTH },
};
 
static const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_groupEntries[SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_MAX_NUM_CHECKERS] =
{
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_0_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_1_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_2_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_3_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_4_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_5_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_6_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_7_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_8_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_9_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_10_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_11_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_12_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_13_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_14_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_15_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_16_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_17_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_18_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_19_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_20_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_21_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_22_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_23_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_24_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_25_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_26_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_27_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_28_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_29_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_30_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_31_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_32_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_33_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_34_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_35_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_36_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_37_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_38_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_39_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_40_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_41_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_42_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_43_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_44_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_45_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_46_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_47_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_48_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_49_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_50_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_51_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_52_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_53_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_54_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_55_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_56_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_57_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_58_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_59_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_60_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_61_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_62_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_63_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_64_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_65_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_66_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_67_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_68_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_69_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_70_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_71_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_72_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_73_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_74_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_75_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_76_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_77_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_78_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_79_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_80_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_81_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_82_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_83_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_84_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_85_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_86_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_87_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_88_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_89_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_90_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_91_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_92_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_93_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_94_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_95_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_96_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_97_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_98_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_99_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_100_WIDTH },
};
 
static const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_groupEntries[SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_MAX_NUM_CHECKERS] =
{
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_0_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_1_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_2_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_3_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_4_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_5_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_6_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_7_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_8_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_9_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_10_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_11_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_12_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_13_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_14_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_15_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_16_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_17_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_18_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_19_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_20_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_21_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_22_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_23_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_24_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_25_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_26_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_27_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_28_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_29_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_30_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_31_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_32_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_33_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_34_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_35_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_36_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_37_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_38_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_39_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_40_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_41_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_42_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_43_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_44_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_45_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_46_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_47_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_48_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_49_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_50_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_51_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_52_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_53_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_54_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_55_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_56_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_57_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_58_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_59_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_60_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_61_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_62_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_63_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_64_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_65_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_66_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_67_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_68_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_69_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_70_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_71_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_72_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_73_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_74_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_75_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_76_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_77_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_78_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_79_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_80_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_81_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_82_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_83_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_84_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_85_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_86_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_87_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_88_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_89_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_90_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_91_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_92_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_93_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_94_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_95_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_96_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_97_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_98_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_99_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_100_WIDTH },
};
 
static const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_groupEntries[SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_MAX_NUM_CHECKERS] =
{
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_0_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_1_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_2_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_3_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_4_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_5_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_6_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_7_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_8_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_9_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_10_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_11_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_12_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_13_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_14_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_15_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_16_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_17_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_18_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_19_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_20_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_21_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_22_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_23_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_24_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_25_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_26_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_27_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_28_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_29_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_30_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_31_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_32_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_33_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_34_WIDTH },
};
 
static const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_groupEntries[SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_MAX_NUM_CHECKERS] =
{
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_0_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_1_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_2_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_3_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_4_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_5_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_6_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_7_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_8_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_9_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_10_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_11_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_12_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_13_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_14_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_15_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_16_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_17_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_18_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_19_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_20_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_21_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_22_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_23_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_24_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_25_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_26_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_27_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_28_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_29_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_30_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_31_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_32_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_33_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_34_WIDTH },
};
 
static const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_groupEntries[SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_MAX_NUM_CHECKERS] =
{
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_0_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_1_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_2_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_3_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_4_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_5_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_6_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_7_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_8_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_9_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_10_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_11_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_12_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_13_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_14_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_15_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_16_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_17_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_18_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_19_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_20_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_21_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_22_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_23_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_24_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_25_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_26_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_27_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_28_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_29_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_30_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_31_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_32_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_33_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_34_WIDTH },
};
 
static const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_INTAGGR_EVT_EDC_CTRL_0_groupEntries[SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_INTAGGR_EVT_EDC_CTRL_0_MAX_NUM_CHECKERS] =
{
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_INTAGGR_EVT_EDC_CTRL_0_GROUP_0_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_INTAGGR_EVT_EDC_CTRL_0_GROUP_1_WIDTH },
};
 
static const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_INTAGGR_CEVT_EDC_CTRL_0_groupEntries[SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_INTAGGR_CEVT_EDC_CTRL_0_MAX_NUM_CHECKERS] =
{
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_INTAGGR_CEVT_EDC_CTRL_0_GROUP_0_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_INTAGGR_CEVT_EDC_CTRL_0_GROUP_1_WIDTH },
};
 
static const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_INTAGGR_MEVT_IN_EDC_CTRL_0_groupEntries[SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_INTAGGR_MEVT_IN_EDC_CTRL_0_MAX_NUM_CHECKERS] =
{
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_INTAGGR_MEVT_IN_EDC_CTRL_0_GROUP_0_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_INTAGGR_MEVT_IN_EDC_CTRL_0_GROUP_1_WIDTH },
};
 
static const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_groupEntries[SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_MAX_NUM_CHECKERS] =
{
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_0_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_1_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_2_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_3_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_4_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_5_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_6_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_7_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_8_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_9_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_10_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_11_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_12_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_13_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_14_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_15_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_16_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_17_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_18_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_19_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_20_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_21_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_22_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_23_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_24_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_25_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_26_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_27_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_28_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_29_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_30_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_31_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_32_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_33_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_34_WIDTH },
};
 
static const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CFG_EDC_CTRL_0_groupEntries[SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CFG_EDC_CTRL_0_MAX_NUM_CHECKERS] =
{
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CFG_EDC_CTRL_0_GROUP_0_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CFG_EDC_CTRL_0_GROUP_1_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CFG_EDC_CTRL_0_GROUP_2_WIDTH },
};
 
static const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_groupEntries[SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_MAX_NUM_CHECKERS] =
{
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_0_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_1_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_2_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_3_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_4_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_5_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_6_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_7_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_8_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_9_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_10_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_11_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_12_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_13_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_14_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_15_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_16_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_17_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_18_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_19_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_20_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_21_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_22_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_23_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_24_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_25_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_26_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_27_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_28_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_29_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_30_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_31_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_32_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_33_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_34_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_35_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_36_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_37_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_38_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_39_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_40_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_41_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_42_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_43_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_44_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_45_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_46_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_47_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_48_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_49_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_50_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_51_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_52_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_53_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_54_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_55_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_56_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_57_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_58_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_59_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_60_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_61_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_62_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_63_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_64_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_65_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_66_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_67_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_68_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_69_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_70_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_71_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_72_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_73_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_74_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_75_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_76_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_77_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_78_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_79_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_80_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_81_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_82_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_83_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_84_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_85_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_86_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_87_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_88_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_89_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_90_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_91_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_92_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_93_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_94_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_95_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_96_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_97_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_98_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_99_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_100_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_101_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_102_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_103_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_104_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_105_WIDTH },
};
 
static const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_groupEntries[SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_MAX_NUM_CHECKERS] =
{
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_0_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_1_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_2_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_3_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_4_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_5_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_6_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_7_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_8_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_9_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_10_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_11_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_12_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_13_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_14_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_15_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_16_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_17_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_18_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_19_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_20_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_21_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_22_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_23_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_24_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_25_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_26_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_27_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_28_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_29_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_30_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_31_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_32_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_33_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_34_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_35_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_36_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_37_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_38_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_39_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_40_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_41_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_42_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_43_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_44_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_45_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_46_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_47_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_48_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_49_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_50_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_51_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_52_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_53_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_54_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_55_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_56_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_57_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_58_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_59_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_60_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_61_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_62_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_63_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_64_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_65_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_66_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_67_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_68_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_69_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_70_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_71_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_72_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_73_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_74_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_75_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_76_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_77_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_78_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_79_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_80_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_81_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_82_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_83_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_84_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_85_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_86_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_87_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_88_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_89_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_90_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_91_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_92_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_93_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_94_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_95_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_96_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_97_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_98_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_99_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_100_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_101_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_102_WIDTH },
};
 
static const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_groupEntries[SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_MAX_NUM_CHECKERS] =
{
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_0_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_1_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_2_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_3_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_4_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_5_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_6_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_7_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_8_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_9_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_10_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_11_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_12_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_13_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_14_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_15_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_16_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_17_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_18_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_19_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_20_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_21_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_22_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_23_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_24_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_25_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_26_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_27_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_28_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_29_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_30_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_31_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_32_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_33_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_34_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_35_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_36_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_37_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_38_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_39_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_40_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_41_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_42_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_43_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_44_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_45_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_46_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_47_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_48_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_49_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_50_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_51_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_52_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_53_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_54_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_55_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_56_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_57_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_58_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_59_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_60_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_61_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_62_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_63_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_64_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_65_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_66_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_67_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_68_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_69_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_70_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_71_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_72_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_73_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_74_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_75_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_76_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_77_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_78_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_79_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_80_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_81_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_82_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_83_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_84_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_85_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_86_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_87_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_88_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_89_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_90_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_91_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_92_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_93_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_94_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_95_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_96_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_97_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_98_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_99_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_100_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_101_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_102_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_103_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_104_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_105_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_106_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_107_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_108_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_109_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_110_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_111_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_112_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_113_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_114_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_115_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_116_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_117_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_118_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_119_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_120_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_121_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_122_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_123_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_124_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_125_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_126_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_127_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_128_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_129_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_130_WIDTH },
};
 
static const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_VD2GCLK_EDC_CTRL_0_groupEntries[SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_VD2GCLK_EDC_CTRL_0_MAX_NUM_CHECKERS] =
{
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_VD2GCLK_EDC_CTRL_0_GROUP_0_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_VD2GCLK_EDC_CTRL_0_GROUP_1_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_VD2GCLK_EDC_CTRL_0_GROUP_2_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_VD2GCLK_EDC_CTRL_0_GROUP_3_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_VD2GCLK_EDC_CTRL_0_GROUP_4_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_VD2GCLK_EDC_CTRL_0_GROUP_5_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_VD2GCLK_EDC_CTRL_0_GROUP_6_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_VD2GCLK_EDC_CTRL_0_GROUP_7_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_VD2GCLK_EDC_CTRL_0_GROUP_8_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_VD2GCLK_EDC_CTRL_0_GROUP_9_WIDTH },
};
 
static const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_DMSS_CFG_P2P_BRIDGE_EDC_CTRL_0_groupEntries[SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_DMSS_CFG_P2P_BRIDGE_EDC_CTRL_0_MAX_NUM_CHECKERS] =
{
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_DMSS_CFG_P2P_BRIDGE_EDC_CTRL_0_GROUP_0_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_DMSS_CFG_P2P_BRIDGE_EDC_CTRL_0_GROUP_1_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_DMSS_CFG_P2P_BRIDGE_EDC_CTRL_0_GROUP_2_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_DMSS_CFG_P2P_BRIDGE_EDC_CTRL_0_GROUP_3_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_DMSS_CFG_P2P_BRIDGE_EDC_CTRL_0_GROUP_4_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_DMSS_CFG_P2P_BRIDGE_EDC_CTRL_0_GROUP_5_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_DMSS_CFG_P2P_BRIDGE_EDC_CTRL_0_GROUP_6_WIDTH },
};
 
static const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_groupEntries[SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_MAX_NUM_CHECKERS] =
{
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_0_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_1_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_2_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_3_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_4_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_5_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_6_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_7_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_8_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_9_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_10_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_11_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_12_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_13_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_14_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_15_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_16_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_17_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_18_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_19_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_20_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_21_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_22_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_23_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_24_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_25_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_26_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_27_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_28_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_29_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_30_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_31_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_32_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_33_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_34_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_35_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_36_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_37_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_38_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_39_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_40_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_41_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_42_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_43_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_44_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_45_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_46_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_47_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_48_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_49_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_50_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_51_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_52_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_53_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_54_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_55_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_56_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_57_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_58_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_59_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_60_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_61_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_62_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_63_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_64_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_65_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_66_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_67_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_68_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_69_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_70_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_71_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_72_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_73_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_74_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_75_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_76_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_77_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_78_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_79_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_80_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_81_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_82_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_83_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_84_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_85_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_86_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_87_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_88_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_89_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_90_WIDTH },
};
 
static const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_groupEntries[SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_MAX_NUM_CHECKERS] =
{
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_0_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_1_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_2_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_3_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_4_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_5_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_6_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_7_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_8_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_9_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_10_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_11_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_12_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_13_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_14_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_15_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_16_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_17_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_18_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_19_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_20_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_21_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_22_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_23_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_24_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_25_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_26_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_27_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_28_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_29_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_30_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_31_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_32_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_33_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_34_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_35_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_36_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_37_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_38_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_39_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_40_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_41_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_42_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_43_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_44_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_45_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_46_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_47_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_48_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_49_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_50_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_51_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_52_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_53_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_54_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_55_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_56_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_57_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_58_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_59_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_60_WIDTH },
    {  SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_61_WIDTH },
};
 
static const SDL_MemConfig_t SDL_SA3_SS0_SA3SS_AM62_SA_UL_ECC_AGGR_MemEntries[SDL_SA3_SS0_SA3SS_AM62_SA_UL_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES] =
{
    { SDL_SA3_SS0_SA3SS_AM62_SA_UL_ECC_AGGR_SA3_UL_PKTRAM0_ECC_RAM_ID, 0u,
      SDL_SA3_SS0_SA3SS_AM62_SA_UL_ECC_AGGR_SA3_UL_PKTRAM0_ECC_RAM_SIZE, 4u,
      SDL_SA3_SS0_SA3SS_AM62_SA_UL_ECC_AGGR_SA3_UL_PKTRAM0_ECC_ROW_WIDTH, ((bool)false) },
    { SDL_SA3_SS0_SA3SS_AM62_SA_UL_ECC_AGGR_SA3_UL_PKTRAM1_ECC_RAM_ID, 0u,
      SDL_SA3_SS0_SA3SS_AM62_SA_UL_ECC_AGGR_SA3_UL_PKTRAM1_ECC_RAM_SIZE, 4u,
      SDL_SA3_SS0_SA3SS_AM62_SA_UL_ECC_AGGR_SA3_UL_PKTRAM1_ECC_ROW_WIDTH, ((bool)false) },
    { SDL_SA3_SS0_SA3SS_AM62_SA_UL_ECC_AGGR_SA3_UL_PKA_PROG_RAM_ECC_RAM_ID, 0u,
      SDL_SA3_SS0_SA3SS_AM62_SA_UL_ECC_AGGR_SA3_UL_PKA_PROG_RAM_ECC_RAM_SIZE, 4u,
      SDL_SA3_SS0_SA3SS_AM62_SA_UL_ECC_AGGR_SA3_UL_PKA_PROG_RAM_ECC_ROW_WIDTH, ((bool)false) },
    { SDL_SA3_SS0_SA3SS_AM62_SA_UL_ECC_AGGR_SA3_UL_ENCR_CTXRAM_BANK01_ECC_RAM_ID, 0u,
      SDL_SA3_SS0_SA3SS_AM62_SA_UL_ECC_AGGR_SA3_UL_ENCR_CTXRAM_BANK01_ECC_RAM_SIZE, 4u,
      SDL_SA3_SS0_SA3SS_AM62_SA_UL_ECC_AGGR_SA3_UL_ENCR_CTXRAM_BANK01_ECC_ROW_WIDTH, ((bool)false) },
    { SDL_SA3_SS0_SA3SS_AM62_SA_UL_ECC_AGGR_SA3_UL_ENCR_CTXRAM_BANK23_ECC_RAM_ID, 0u,
      SDL_SA3_SS0_SA3SS_AM62_SA_UL_ECC_AGGR_SA3_UL_ENCR_CTXRAM_BANK23_ECC_RAM_SIZE, 4u,
      SDL_SA3_SS0_SA3SS_AM62_SA_UL_ECC_AGGR_SA3_UL_ENCR_CTXRAM_BANK23_ECC_ROW_WIDTH, ((bool)false) },
    { SDL_SA3_SS0_SA3SS_AM62_SA_UL_ECC_AGGR_SA3_UL_ENCR_CTXRAM_BANK4_ECC_RAM_ID, 0u,
      SDL_SA3_SS0_SA3SS_AM62_SA_UL_ECC_AGGR_SA3_UL_ENCR_CTXRAM_BANK4_ECC_RAM_SIZE, 4u,
      SDL_SA3_SS0_SA3SS_AM62_SA_UL_ECC_AGGR_SA3_UL_ENCR_CTXRAM_BANK4_ECC_ROW_WIDTH, ((bool)false) },
    { SDL_SA3_SS0_SA3SS_AM62_SA_UL_ECC_AGGR_SA3_UL_AUTH_CTXRAM_BANK01_ECC_RAM_ID, 0u,
      SDL_SA3_SS0_SA3SS_AM62_SA_UL_ECC_AGGR_SA3_UL_AUTH_CTXRAM_BANK01_ECC_RAM_SIZE, 4u,
      SDL_SA3_SS0_SA3SS_AM62_SA_UL_ECC_AGGR_SA3_UL_AUTH_CTXRAM_BANK01_ECC_ROW_WIDTH, ((bool)false) },
    { SDL_SA3_SS0_SA3SS_AM62_SA_UL_ECC_AGGR_SA3_UL_AUTH_CTXRAM_BANK23_ECC_RAM_ID, 0u,
      SDL_SA3_SS0_SA3SS_AM62_SA_UL_ECC_AGGR_SA3_UL_AUTH_CTXRAM_BANK23_ECC_RAM_SIZE, 4u,
      SDL_SA3_SS0_SA3SS_AM62_SA_UL_ECC_AGGR_SA3_UL_AUTH_CTXRAM_BANK23_ECC_ROW_WIDTH, ((bool)false) },
    { SDL_SA3_SS0_SA3SS_AM62_SA_UL_ECC_AGGR_SA3_UL_AUTH_CTXRAM_BANK45_ECC_RAM_ID, 0u,
      SDL_SA3_SS0_SA3SS_AM62_SA_UL_ECC_AGGR_SA3_UL_AUTH_CTXRAM_BANK45_ECC_RAM_SIZE, 4u,
      SDL_SA3_SS0_SA3SS_AM62_SA_UL_ECC_AGGR_SA3_UL_AUTH_CTXRAM_BANK45_ECC_ROW_WIDTH, ((bool)false) },
    { SDL_SA3_SS0_SA3SS_AM62_SA_UL_ECC_AGGR_SA3_UL_AUTH_CTXRAM_BANK67_ECC_RAM_ID, 0u,
      SDL_SA3_SS0_SA3SS_AM62_SA_UL_ECC_AGGR_SA3_UL_AUTH_CTXRAM_BANK67_ECC_RAM_SIZE, 4u,
      SDL_SA3_SS0_SA3SS_AM62_SA_UL_ECC_AGGR_SA3_UL_AUTH_CTXRAM_BANK67_ECC_ROW_WIDTH, ((bool)false) },
    { SDL_SA3_SS0_SA3SS_AM62_SA_UL_ECC_AGGR_SA3_UL_AUTH_CTXRAM_BANK89_ECC_RAM_ID, 0u,
      SDL_SA3_SS0_SA3SS_AM62_SA_UL_ECC_AGGR_SA3_UL_AUTH_CTXRAM_BANK89_ECC_RAM_SIZE, 4u,
      SDL_SA3_SS0_SA3SS_AM62_SA_UL_ECC_AGGR_SA3_UL_AUTH_CTXRAM_BANK89_ECC_ROW_WIDTH, ((bool)false) },
    { SDL_SA3_SS0_SA3SS_AM62_SA_UL_ECC_AGGR_SA3_UL_AUTH_CTXRAM_BANK10_ECC_RAM_ID, 0u,
      SDL_SA3_SS0_SA3SS_AM62_SA_UL_ECC_AGGR_SA3_UL_AUTH_CTXRAM_BANK10_ECC_RAM_SIZE, 4u,
      SDL_SA3_SS0_SA3SS_AM62_SA_UL_ECC_AGGR_SA3_UL_AUTH_CTXRAM_BANK10_ECC_ROW_WIDTH, ((bool)false) },
};
 
static const SDL_MemConfig_t SDL_DMASS0_DMSS_AM62_ECCAGGR_MemEntries[SDL_DMASS0_DMSS_AM62_ECCAGGR_RAM_IDS_TOTAL_ENTRIES] =
{
    { SDL_DMASS0_DMSS_AM62_ECCAGGR_DMSS_AM62_PKTDMA_CFG_CONFIG_RAM_ID, 0u,
      SDL_DMASS0_DMSS_AM62_ECCAGGR_DMSS_AM62_PKTDMA_CFG_CONFIG_RAM_SIZE, 4u,
      SDL_DMASS0_DMSS_AM62_ECCAGGR_DMSS_AM62_PKTDMA_CFG_CONFIG_ROW_WIDTH, ((bool)false) },
    { SDL_DMASS0_DMSS_AM62_ECCAGGR_DMSS_AM62_PKTDMA_CFG_STATE_RAM_ID, 0u,
      SDL_DMASS0_DMSS_AM62_ECCAGGR_DMSS_AM62_PKTDMA_CFG_STATE_RAM_SIZE, 4u,
      SDL_DMASS0_DMSS_AM62_ECCAGGR_DMSS_AM62_PKTDMA_CFG_STATE_ROW_WIDTH, ((bool)false) },
    { SDL_DMASS0_DMSS_AM62_ECCAGGR_DMSS_AM62_PKTDMA_TPCFIFO_F0_RAM_ID, 0u,
      SDL_DMASS0_DMSS_AM62_ECCAGGR_DMSS_AM62_PKTDMA_TPCFIFO_F0_RAM_SIZE, 4u,
      SDL_DMASS0_DMSS_AM62_ECCAGGR_DMSS_AM62_PKTDMA_TPCFIFO_F0_ROW_WIDTH, ((bool)false) },
    { SDL_DMASS0_DMSS_AM62_ECCAGGR_DMSS_AM62_PKTDMA_TPCFIFO_F1_RAM_ID, 0u,
      SDL_DMASS0_DMSS_AM62_ECCAGGR_DMSS_AM62_PKTDMA_TPCFIFO_F1_RAM_SIZE, 4u,
      SDL_DMASS0_DMSS_AM62_ECCAGGR_DMSS_AM62_PKTDMA_TPCFIFO_F1_ROW_WIDTH, ((bool)false) },
    { SDL_DMASS0_DMSS_AM62_ECCAGGR_DMSS_AM62_PKTDMA_RPCFIFO_F0_RAM_ID, 0u,
      SDL_DMASS0_DMSS_AM62_ECCAGGR_DMSS_AM62_PKTDMA_RPCFIFO_F0_RAM_SIZE, 4u,
      SDL_DMASS0_DMSS_AM62_ECCAGGR_DMSS_AM62_PKTDMA_RPCFIFO_F0_ROW_WIDTH, ((bool)false) },
    { SDL_DMASS0_DMSS_AM62_ECCAGGR_DMSS_AM62_PKTDMA_RPCFIFO_F1_RAM_ID, 0u,
      SDL_DMASS0_DMSS_AM62_ECCAGGR_DMSS_AM62_PKTDMA_RPCFIFO_F1_RAM_SIZE, 4u,
      SDL_DMASS0_DMSS_AM62_ECCAGGR_DMSS_AM62_PKTDMA_RPCFIFO_F1_ROW_WIDTH, ((bool)false) },
    { SDL_DMASS0_DMSS_AM62_ECCAGGR_DMSS_AM62_PKTDMA_RPCFIFO_WC_RAM_ID, 0u,
      SDL_DMASS0_DMSS_AM62_ECCAGGR_DMSS_AM62_PKTDMA_RPCFIFO_WC_RAM_SIZE, 4u,
      SDL_DMASS0_DMSS_AM62_ECCAGGR_DMSS_AM62_PKTDMA_RPCFIFO_WC_ROW_WIDTH, ((bool)false) },
    { SDL_DMASS0_DMSS_AM62_ECCAGGR_DMSS_AM62_PKTDMA_STATS_STST0_RAM_ID, 0u,
      SDL_DMASS0_DMSS_AM62_ECCAGGR_DMSS_AM62_PKTDMA_STATS_STST0_RAM_SIZE, 4u,
      SDL_DMASS0_DMSS_AM62_ECCAGGR_DMSS_AM62_PKTDMA_STATS_STST0_ROW_WIDTH, ((bool)false) },
    { SDL_DMASS0_DMSS_AM62_ECCAGGR_DMSS_AM62_PKTDMA_STATS_STSR0_RAM_ID, 0u,
      SDL_DMASS0_DMSS_AM62_ECCAGGR_DMSS_AM62_PKTDMA_STATS_STSR0_RAM_SIZE, 4u,
      SDL_DMASS0_DMSS_AM62_ECCAGGR_DMSS_AM62_PKTDMA_STATS_STSR0_ROW_WIDTH, ((bool)false) },
    { SDL_DMASS0_DMSS_AM62_ECCAGGR_DMSS_AM62_PKTDMA_RINGOCC_CNTR_RAM_ID, 0u,
      SDL_DMASS0_DMSS_AM62_ECCAGGR_DMSS_AM62_PKTDMA_RINGOCC_CNTR_RAM_SIZE, 4u,
      SDL_DMASS0_DMSS_AM62_ECCAGGR_DMSS_AM62_PKTDMA_RINGOCC_CNTR_ROW_WIDTH, ((bool)false) },
    { SDL_DMASS0_DMSS_AM62_ECCAGGR_DMSS_AM62_BCDMA_CFG_CONFIG_RAM_ID, 0u,
      SDL_DMASS0_DMSS_AM62_ECCAGGR_DMSS_AM62_BCDMA_CFG_CONFIG_RAM_SIZE, 4u,
      SDL_DMASS0_DMSS_AM62_ECCAGGR_DMSS_AM62_BCDMA_CFG_CONFIG_ROW_WIDTH, ((bool)false) },
    { SDL_DMASS0_DMSS_AM62_ECCAGGR_DMSS_AM62_BCDMA_CFG_STATE_RAM_ID, 0u,
      SDL_DMASS0_DMSS_AM62_ECCAGGR_DMSS_AM62_BCDMA_CFG_STATE_RAM_SIZE, 4u,
      SDL_DMASS0_DMSS_AM62_ECCAGGR_DMSS_AM62_BCDMA_CFG_STATE_ROW_WIDTH, ((bool)false) },
    { SDL_DMASS0_DMSS_AM62_ECCAGGR_DMSS_AM62_BCDMA_PCFIFO_DFIFO_F0_RAM_ID, 0u,
      SDL_DMASS0_DMSS_AM62_ECCAGGR_DMSS_AM62_BCDMA_PCFIFO_DFIFO_F0_RAM_SIZE, 4u,
      SDL_DMASS0_DMSS_AM62_ECCAGGR_DMSS_AM62_BCDMA_PCFIFO_DFIFO_F0_ROW_WIDTH, ((bool)false) },
    { SDL_DMASS0_DMSS_AM62_ECCAGGR_DMSS_AM62_BCDMA_PCFIFO_DFIFO_F1_RAM_ID, 0u,
      SDL_DMASS0_DMSS_AM62_ECCAGGR_DMSS_AM62_BCDMA_PCFIFO_DFIFO_F1_RAM_SIZE, 4u,
      SDL_DMASS0_DMSS_AM62_ECCAGGR_DMSS_AM62_BCDMA_PCFIFO_DFIFO_F1_ROW_WIDTH, ((bool)false) },
    { SDL_DMASS0_DMSS_AM62_ECCAGGR_DMSS_AM62_BCDMA_TPCFIFO_F0_RAM_ID, 0u,
      SDL_DMASS0_DMSS_AM62_ECCAGGR_DMSS_AM62_BCDMA_TPCFIFO_F0_RAM_SIZE, 4u,
      SDL_DMASS0_DMSS_AM62_ECCAGGR_DMSS_AM62_BCDMA_TPCFIFO_F0_ROW_WIDTH, ((bool)false) },
    { SDL_DMASS0_DMSS_AM62_ECCAGGR_DMSS_AM62_BCDMA_TPCFIFO_F1_RAM_ID, 0u,
      SDL_DMASS0_DMSS_AM62_ECCAGGR_DMSS_AM62_BCDMA_TPCFIFO_F1_RAM_SIZE, 4u,
      SDL_DMASS0_DMSS_AM62_ECCAGGR_DMSS_AM62_BCDMA_TPCFIFO_F1_ROW_WIDTH, ((bool)false) },
    { SDL_DMASS0_DMSS_AM62_ECCAGGR_DMSS_AM62_BCDMA_RPCFIFO_F0_RAM_ID, 0u,
      SDL_DMASS0_DMSS_AM62_ECCAGGR_DMSS_AM62_BCDMA_RPCFIFO_F0_RAM_SIZE, 4u,
      SDL_DMASS0_DMSS_AM62_ECCAGGR_DMSS_AM62_BCDMA_RPCFIFO_F0_ROW_WIDTH, ((bool)false) },
    { SDL_DMASS0_DMSS_AM62_ECCAGGR_DMSS_AM62_BCDMA_RPCFIFO_F1_RAM_ID, 0u,
      SDL_DMASS0_DMSS_AM62_ECCAGGR_DMSS_AM62_BCDMA_RPCFIFO_F1_RAM_SIZE, 4u,
      SDL_DMASS0_DMSS_AM62_ECCAGGR_DMSS_AM62_BCDMA_RPCFIFO_F1_ROW_WIDTH, ((bool)false) },
    { SDL_DMASS0_DMSS_AM62_ECCAGGR_DMSS_AM62_BCDMA_RPCFIFO_WC_RAM_ID, 0u,
      SDL_DMASS0_DMSS_AM62_ECCAGGR_DMSS_AM62_BCDMA_RPCFIFO_WC_RAM_SIZE, 4u,
      SDL_DMASS0_DMSS_AM62_ECCAGGR_DMSS_AM62_BCDMA_RPCFIFO_WC_ROW_WIDTH, ((bool)false) },
    { SDL_DMASS0_DMSS_AM62_ECCAGGR_DMSS_AM62_BCDMA_STATS_STST0_RAM_ID, 0u,
      SDL_DMASS0_DMSS_AM62_ECCAGGR_DMSS_AM62_BCDMA_STATS_STST0_RAM_SIZE, 4u,
      SDL_DMASS0_DMSS_AM62_ECCAGGR_DMSS_AM62_BCDMA_STATS_STST0_ROW_WIDTH, ((bool)false) },
    { SDL_DMASS0_DMSS_AM62_ECCAGGR_DMSS_AM62_BCDMA_STATS_STSR0_RAM_ID, 0u,
      SDL_DMASS0_DMSS_AM62_ECCAGGR_DMSS_AM62_BCDMA_STATS_STSR0_RAM_SIZE, 4u,
      SDL_DMASS0_DMSS_AM62_ECCAGGR_DMSS_AM62_BCDMA_STATS_STSR0_ROW_WIDTH, ((bool)false) },
    { SDL_DMASS0_DMSS_AM62_ECCAGGR_DMSS_AM62_BCDMA_RINGOCC_CNTR_RAM_ID, 0u,
      SDL_DMASS0_DMSS_AM62_ECCAGGR_DMSS_AM62_BCDMA_RINGOCC_CNTR_RAM_SIZE, 4u,
      SDL_DMASS0_DMSS_AM62_ECCAGGR_DMSS_AM62_BCDMA_RINGOCC_CNTR_ROW_WIDTH, ((bool)false) },
    { SDL_DMASS0_DMSS_AM62_ECCAGGR_DMSS_AM62_INTAGGR_STATREG_SR_SPRAM_184X128_SWW_SR_RAM_ID, 0u,
      SDL_DMASS0_DMSS_AM62_ECCAGGR_DMSS_AM62_INTAGGR_STATREG_SR_SPRAM_184X128_SWW_SR_RAM_SIZE, 4u,
      SDL_DMASS0_DMSS_AM62_ECCAGGR_DMSS_AM62_INTAGGR_STATREG_SR_SPRAM_184X128_SWW_SR_ROW_WIDTH, ((bool)false) },
    { SDL_DMASS0_DMSS_AM62_ECCAGGR_DMSS_AM62_INTAGGR_COMMON_IM_TPRAM_1531X34_SWW_SR_RAM_ID, 0u,
      SDL_DMASS0_DMSS_AM62_ECCAGGR_DMSS_AM62_INTAGGR_COMMON_IM_TPRAM_1531X34_SWW_SR_RAM_SIZE, 4u,
      SDL_DMASS0_DMSS_AM62_ECCAGGR_DMSS_AM62_INTAGGR_COMMON_IM_TPRAM_1531X34_SWW_SR_ROW_WIDTH, ((bool)false) },
    { SDL_DMASS0_DMSS_AM62_ECCAGGR_DMSS_AM62_IPCSS_RINGACC_STRAM_RAM_ID, 0u,
      SDL_DMASS0_DMSS_AM62_ECCAGGR_DMSS_AM62_IPCSS_RINGACC_STRAM_RAM_SIZE, 4u,
      SDL_DMASS0_DMSS_AM62_ECCAGGR_DMSS_AM62_IPCSS_RINGACC_STRAM_ROW_WIDTH, ((bool)false) },
    { SDL_DMASS0_DMSS_AM62_ECCAGGR_DMSS_AM62_IPCSS_SEC_PROXY_BUF_STRAM_RAM_ID, 0u,
      SDL_DMASS0_DMSS_AM62_ECCAGGR_DMSS_AM62_IPCSS_SEC_PROXY_BUF_STRAM_RAM_SIZE, 4u,
      SDL_DMASS0_DMSS_AM62_ECCAGGR_DMSS_AM62_IPCSS_SEC_PROXY_BUF_STRAM_ROW_WIDTH, ((bool)false) },
    { SDL_DMASS0_DMSS_AM62_ECCAGGR_DMSS_AM62_IPCSS_SEC_PROXY_BUF_BUFRAM_RAM_ID, 0u,
      SDL_DMASS0_DMSS_AM62_ECCAGGR_DMSS_AM62_IPCSS_SEC_PROXY_BUF_BUFRAM_RAM_SIZE, 4u,
      SDL_DMASS0_DMSS_AM62_ECCAGGR_DMSS_AM62_IPCSS_SEC_PROXY_BUF_BUFRAM_ROW_WIDTH, ((bool)false) },
    { SDL_DMASS0_DMSS_AM62_ECCAGGR_DMSS_AM62_IPCSS_MSRAM_ECC0_RAM_ID, 0u,
      SDL_DMASS0_DMSS_AM62_ECCAGGR_DMSS_AM62_IPCSS_MSRAM_ECC0_RAM_SIZE, 4u,
      SDL_DMASS0_DMSS_AM62_ECCAGGR_DMSS_AM62_IPCSS_MSRAM_ECC0_ROW_WIDTH, ((bool)false) },
};
 
static const SDL_MemConfig_t SDL_PSRAMECC_16K0_PSRAM16KX32E_ECC_AGGR_MemEntries[SDL_PSRAMECC_16K0_PSRAM16KX32E_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES] =
{
    { SDL_PSRAMECC_16K0_PSRAM16KX32E_ECC_AGGR_PSRAM16KX32E_PSRAM0_ECC_RAM_ID, 0x70000000u,
      SDL_PSRAMECC_16K0_PSRAM16KX32E_ECC_AGGR_PSRAM16KX32E_PSRAM0_ECC_RAM_SIZE, 4u,
      SDL_PSRAMECC_16K0_PSRAM16KX32E_ECC_AGGR_PSRAM16KX32E_PSRAM0_ECC_ROW_WIDTH, ((bool)true) },
};
 
static const SDL_MemConfig_t SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_MemEntries[SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES] =
{
    { SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_RX_SHIM_DMA_PSIL_FIFO_RAM_ID, 0u,
      SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_RX_SHIM_DMA_PSIL_FIFO_RAM_SIZE, 4u,
      SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_RX_SHIM_DMA_PSIL_FIFO_ROW_WIDTH, ((bool)false) },
    { SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_RAM_WRAPPER0_FIFO_RAM_ID, 0u,
      SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_RAM_WRAPPER0_FIFO_RAM_SIZE, 4u,
      SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_RAM_WRAPPER0_FIFO_ROW_WIDTH, ((bool)false) },
    { SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_RAM_WRAPPER1_FIFO_RAM_ID, 0u,
      SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_RAM_WRAPPER1_FIFO_RAM_SIZE, 4u,
      SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_RAM_WRAPPER1_FIFO_ROW_WIDTH, ((bool)false) },
    { SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_RAM_WRAPPER2_FIFO_RAM_ID, 0u,
      SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_RAM_WRAPPER2_FIFO_RAM_SIZE, 4u,
      SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_RAM_WRAPPER2_FIFO_ROW_WIDTH, ((bool)false) },
    { SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_RAM_WRAPPER3_FIFO_RAM_ID, 0u,
      SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_RAM_WRAPPER3_FIFO_RAM_SIZE, 4u,
      SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_RAM_WRAPPER3_FIFO_ROW_WIDTH, ((bool)false) },
    { SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_VP0_VP_FIFO_RAM_ID, 0u,
      SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_VP0_VP_FIFO_RAM_SIZE, 4u,
      SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_VP0_VP_FIFO_ROW_WIDTH, ((bool)false) },
    { SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_VP1_VP_FIFO_RAM_ID, 0u,
      SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_VP1_VP_FIFO_RAM_SIZE, 4u,
      SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_VP1_VP_FIFO_ROW_WIDTH, ((bool)false) },
};
 
static const SDL_GrpChkConfig_t SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_EDC_CTRL_0_groupEntries[SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_EDC_CTRL_0_MAX_NUM_CHECKERS] =
{
    {  SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_EDC_CTRL_0_GROUP_0_WIDTH },
    {  SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_EDC_CTRL_0_GROUP_1_WIDTH },
};
 
static const SDL_MemConfig_t SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_RXMEM_MemEntries[SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_RXMEM_RAM_IDS_TOTAL_ENTRIES] =
{
    { SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_RXMEM_EMMCSD4SS_SDHC_WRAP_RXMEM_RAM_ID, 0u,
      SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_RXMEM_EMMCSD4SS_SDHC_WRAP_RXMEM_RAM_SIZE, 4u,
      SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_RXMEM_EMMCSD4SS_SDHC_WRAP_RXMEM_ROW_WIDTH, ((bool)false) },
};
 
static const SDL_MemConfig_t SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_TXMEM_MemEntries[SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_TXMEM_RAM_IDS_TOTAL_ENTRIES] =
{
    { SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_TXMEM_EMMCSD4SS_SDHC_WRAP_TXMEM_RAM_ID, 0u,
      SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_TXMEM_EMMCSD4SS_SDHC_WRAP_TXMEM_RAM_SIZE, 4u,
      SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_TXMEM_EMMCSD4SS_SDHC_WRAP_TXMEM_ROW_WIDTH, ((bool)false) },
};
 
static const SDL_MemConfig_t SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_RXMEM_MemEntries[SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_RXMEM_RAM_IDS_TOTAL_ENTRIES] =
{
    { SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_RXMEM_EMMCSD4SS_SDHC_WRAP_RXMEM_RAM_ID, 0u,
      SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_RXMEM_EMMCSD4SS_SDHC_WRAP_RXMEM_RAM_SIZE, 4u,
      SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_RXMEM_EMMCSD4SS_SDHC_WRAP_RXMEM_ROW_WIDTH, ((bool)false) },
};
 
static const SDL_MemConfig_t SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_TXMEM_MemEntries[SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_TXMEM_RAM_IDS_TOTAL_ENTRIES] =
{
    { SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_TXMEM_EMMCSD4SS_SDHC_WRAP_TXMEM_RAM_ID, 0u,
      SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_TXMEM_EMMCSD4SS_SDHC_WRAP_TXMEM_RAM_SIZE, 4u,
      SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_TXMEM_EMMCSD4SS_SDHC_WRAP_TXMEM_ROW_WIDTH, ((bool)false) },
};
 
static const SDL_MemConfig_t SDL_PDMA0_SAM62_PDMA_SPI_ECCAGGR_MemEntries[SDL_PDMA0_SAM62_PDMA_SPI_ECCAGGR_RAM_IDS_TOTAL_ENTRIES] =
{
    { SDL_PDMA0_SAM62_PDMA_SPI_ECCAGGR_SAM62_PDMA_SPI_PDMA_CORE_TF0_F0_TPRAM_60X128_SBW_SR_RAM_ID, 0u,
      SDL_PDMA0_SAM62_PDMA_SPI_ECCAGGR_SAM62_PDMA_SPI_PDMA_CORE_TF0_F0_TPRAM_60X128_SBW_SR_RAM_SIZE, 4u,
      SDL_PDMA0_SAM62_PDMA_SPI_ECCAGGR_SAM62_PDMA_SPI_PDMA_CORE_TF0_F0_TPRAM_60X128_SBW_SR_ROW_WIDTH, ((bool)false) },
    { SDL_PDMA0_SAM62_PDMA_SPI_ECCAGGR_SAM62_PDMA_SPI_PDMA_CORE_TF0_F1_TPRAM_60X128_SBW_SR_RAM_ID, 0u,
      SDL_PDMA0_SAM62_PDMA_SPI_ECCAGGR_SAM62_PDMA_SPI_PDMA_CORE_TF0_F1_TPRAM_60X128_SBW_SR_RAM_SIZE, 4u,
      SDL_PDMA0_SAM62_PDMA_SPI_ECCAGGR_SAM62_PDMA_SPI_PDMA_CORE_TF0_F1_TPRAM_60X128_SBW_SR_ROW_WIDTH, ((bool)false) },
    { SDL_PDMA0_SAM62_PDMA_SPI_ECCAGGR_SAM62_PDMA_SPI_PDMA_CORE_RF0_F0_TPRAM_60X144_SBW_SR_RAM_ID, 0u,
      SDL_PDMA0_SAM62_PDMA_SPI_ECCAGGR_SAM62_PDMA_SPI_PDMA_CORE_RF0_F0_TPRAM_60X144_SBW_SR_RAM_SIZE, 4u,
      SDL_PDMA0_SAM62_PDMA_SPI_ECCAGGR_SAM62_PDMA_SPI_PDMA_CORE_RF0_F0_TPRAM_60X144_SBW_SR_ROW_WIDTH, ((bool)false) },
    { SDL_PDMA0_SAM62_PDMA_SPI_ECCAGGR_SAM62_PDMA_SPI_PDMA_CORE_RF0_F1_TPRAM_60X144_SBW_SR_RAM_ID, 0u,
      SDL_PDMA0_SAM62_PDMA_SPI_ECCAGGR_SAM62_PDMA_SPI_PDMA_CORE_RF0_F1_TPRAM_60X144_SBW_SR_RAM_SIZE, 4u,
      SDL_PDMA0_SAM62_PDMA_SPI_ECCAGGR_SAM62_PDMA_SPI_PDMA_CORE_RF0_F1_TPRAM_60X144_SBW_SR_ROW_WIDTH, ((bool)false) },
};
 
static const SDL_MemConfig_t SDL_MMCSD0_EMMCSD8SS_ECC_AGGR_TXMEM_MemEntries[SDL_MMCSD0_EMMCSD8SS_ECC_AGGR_TXMEM_RAM_IDS_TOTAL_ENTRIES] =
{
    { SDL_MMCSD0_EMMCSD8SS_ECC_AGGR_TXMEM_EMMCSD8SS_SDHC_WRAP_TXMEM_RAM_ID, 0u,
      SDL_MMCSD0_EMMCSD8SS_ECC_AGGR_TXMEM_EMMCSD8SS_SDHC_WRAP_TXMEM_RAM_SIZE, 4u,
      SDL_MMCSD0_EMMCSD8SS_ECC_AGGR_TXMEM_EMMCSD8SS_SDHC_WRAP_TXMEM_ROW_WIDTH, ((bool)false) },
};
 
static const SDL_MemConfig_t SDL_MMCSD0_EMMCSD8SS_ECC_AGGR_RXMEM_MemEntries[SDL_MMCSD0_EMMCSD8SS_ECC_AGGR_RXMEM_RAM_IDS_TOTAL_ENTRIES] =
{
    { SDL_MMCSD0_EMMCSD8SS_ECC_AGGR_RXMEM_EMMCSD8SS_SDHC_WRAP_RXMEM_RAM_ID, 0u,
      SDL_MMCSD0_EMMCSD8SS_ECC_AGGR_RXMEM_EMMCSD8SS_SDHC_WRAP_RXMEM_RAM_SIZE, 4u,
      SDL_MMCSD0_EMMCSD8SS_ECC_AGGR_RXMEM_EMMCSD8SS_SDHC_WRAP_RXMEM_ROW_WIDTH, ((bool)false) },
};
 
static const SDL_MemConfig_t SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_MemEntries[SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES] =
{
    { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_ITAG_RAM0_RAM_ID, 0u,
      SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_ITAG_RAM0_RAM_SIZE, 4u,
      SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_ITAG_RAM0_ROW_WIDTH, ((bool)false) },
    { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_ITAG_RAM1_RAM_ID, 0u,
      SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_ITAG_RAM1_RAM_SIZE, 4u,
      SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_ITAG_RAM1_ROW_WIDTH, ((bool)false) },
    { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_ITAG_RAM2_RAM_ID, 0u,
      SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_ITAG_RAM2_RAM_SIZE, 4u,
      SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_ITAG_RAM2_ROW_WIDTH, ((bool)false) },
    { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_ITAG_RAM3_RAM_ID, 0u,
      SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_ITAG_RAM3_RAM_SIZE, 4u,
      SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_ITAG_RAM3_ROW_WIDTH, ((bool)false) },
    { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_IDATA_BANK0_RAM_ID, 0u,
      SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_IDATA_BANK0_RAM_SIZE, 4u,
      SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_IDATA_BANK0_ROW_WIDTH, ((bool)true) },
    { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_IDATA_BANK1_RAM_ID, 0u,
      SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_IDATA_BANK1_RAM_SIZE, 4u,
      SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_IDATA_BANK1_ROW_WIDTH, ((bool)true) },
    { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_IDATA_BANK2_RAM_ID, 0u,
      SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_IDATA_BANK2_RAM_SIZE, 4u,
      SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_IDATA_BANK2_ROW_WIDTH, ((bool)true) },
    { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_IDATA_BANK3_RAM_ID, 0u,
      SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_IDATA_BANK3_RAM_SIZE, 4u,
      SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_IDATA_BANK3_ROW_WIDTH, ((bool)true) },
    { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DTAG_RAM0_RAM_ID, 0u,
      SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DTAG_RAM0_RAM_SIZE, 4u,
      SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DTAG_RAM0_ROW_WIDTH, ((bool)false) },
    { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DTAG_RAM1_RAM_ID, 0u,
      SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DTAG_RAM1_RAM_SIZE, 4u,
      SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DTAG_RAM1_ROW_WIDTH, ((bool)false) },
    { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DTAG_RAM2_RAM_ID, 0u,
      SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DTAG_RAM2_RAM_SIZE, 4u,
      SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DTAG_RAM2_ROW_WIDTH, ((bool)false) },
    { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DTAG_RAM3_RAM_ID, 0u,
      SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DTAG_RAM3_RAM_SIZE, 4u,
      SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DTAG_RAM3_ROW_WIDTH, ((bool)false) },
    { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDIRTY_RAM_RAM_ID, 0u,
      SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDIRTY_RAM_RAM_SIZE, 4u,
      SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDIRTY_RAM_ROW_WIDTH, ((bool)false) },
    { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM0_RAM_ID, 0u,
      SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM0_RAM_SIZE, 4u,
      SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM0_ROW_WIDTH, ((bool)true) },
    { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM1_RAM_ID, 0u,
      SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM1_RAM_SIZE, 4u,
      SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM1_ROW_WIDTH, ((bool)true) },
    { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM2_RAM_ID, 0u,
      SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM2_RAM_SIZE, 4u,
      SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM2_ROW_WIDTH, ((bool)true) },
    { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM3_RAM_ID, 0u,
      SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM3_RAM_SIZE, 4u,
      SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM3_ROW_WIDTH, ((bool)true) },
    { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM4_RAM_ID, 0u,
      SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM4_RAM_SIZE, 4u,
      SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM4_ROW_WIDTH, ((bool)true) },
    { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM5_RAM_ID, 0u,
      SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM5_RAM_SIZE, 4u,
      SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM5_ROW_WIDTH, ((bool)true) },
    { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM6_RAM_ID, 0u,
      SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM6_RAM_SIZE, 4u,
      SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM6_ROW_WIDTH, ((bool)true) },
    { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM7_RAM_ID, 0u,
      SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM7_RAM_SIZE, 4u,
      SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM7_ROW_WIDTH, ((bool)true) },
    { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_ATCM0_BANK0_RAM_ID, 0x78000000u,
      SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_ATCM0_BANK0_RAM_SIZE, 4u,
      SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_ATCM0_BANK0_ROW_WIDTH, ((bool)true) },
    { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_ATCM0_BANK1_RAM_ID, 0x78000000u,
      SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_ATCM0_BANK1_RAM_SIZE, 4u,
      SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_ATCM0_BANK1_ROW_WIDTH, ((bool)true) },
    { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_B0TCM0_BANK0_RAM_ID, 0x78100000u,
      SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_B0TCM0_BANK0_RAM_SIZE, 4u,
      SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_B0TCM0_BANK0_ROW_WIDTH, ((bool)true) },
    { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_B0TCM0_BANK1_RAM_ID, 0x78100000u,
      SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_B0TCM0_BANK1_RAM_SIZE, 4u,
      SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_B0TCM0_BANK1_ROW_WIDTH, ((bool)true) },
    { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_B1TCM0_BANK0_RAM_ID, 0x78100000u,
      SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_B1TCM0_BANK0_RAM_SIZE, 4u,
      SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_B1TCM0_BANK0_ROW_WIDTH, ((bool)true) },
    { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_B1TCM0_BANK1_RAM_ID, 0x78100000u,
      SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_B1TCM0_BANK1_RAM_SIZE, 4u,
      SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_B1TCM0_BANK1_ROW_WIDTH, ((bool)true) },
    { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_PULSAR_KS_VIM_COMMON_CORE0_RAM_RAM_ID, 0u,
      SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_PULSAR_KS_VIM_COMMON_CORE0_RAM_RAM_SIZE, 4u,
      SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_PULSAR_KS_VIM_COMMON_CORE0_RAM_ROW_WIDTH, ((bool)false) },
    { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_MEM_MST0_KSBUS_AXI2VBUSM_R_RDATA_BUFFER_RAM_ID, 0u,
      SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_MEM_MST0_KSBUS_AXI2VBUSM_R_RDATA_BUFFER_RAM_SIZE, 4u,
      SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_MEM_MST0_KSBUS_AXI2VBUSM_R_RDATA_BUFFER_ROW_WIDTH, ((bool)false) },
};
 
static const SDL_MemConfig_t SDL_SMS0_SMS_HSM_ECC_MemEntries[SDL_SMS0_SMS_HSM_ECC_RAM_IDS_TOTAL_ENTRIES] =
{
    { SDL_SMS0_SMS_HSM_ECC_ISRAM0_RAMECC_RAM_ID, 0u,
      SDL_SMS0_SMS_HSM_ECC_ISRAM0_RAMECC_RAM_SIZE, 4u,
      SDL_SMS0_SMS_HSM_ECC_ISRAM0_RAMECC_ROW_WIDTH, ((bool)false) },
    { SDL_SMS0_SMS_HSM_ECC_ISRAM1_RAMECC_RAM_ID, 0u,
      SDL_SMS0_SMS_HSM_ECC_ISRAM1_RAMECC_RAM_SIZE, 4u,
      SDL_SMS0_SMS_HSM_ECC_ISRAM1_RAMECC_ROW_WIDTH, ((bool)false) },
};
 
static const SDL_GrpChkConfig_t SDL_SMS0_SMS_HSM_ECC_ISRAM0_BUSECC_groupEntries[SDL_SMS0_SMS_HSM_ECC_ISRAM0_BUSECC_MAX_NUM_CHECKERS] =
{
    {  SDL_SMS0_SMS_HSM_ECC_ISRAM0_BUSECC_GROUP_0_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_ISRAM0_BUSECC_GROUP_1_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_ISRAM0_BUSECC_GROUP_2_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_ISRAM0_BUSECC_GROUP_3_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_ISRAM0_BUSECC_GROUP_4_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_ISRAM0_BUSECC_GROUP_5_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_ISRAM0_BUSECC_GROUP_6_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_ISRAM0_BUSECC_GROUP_7_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_ISRAM0_BUSECC_GROUP_8_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_ISRAM0_BUSECC_GROUP_9_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_ISRAM0_BUSECC_GROUP_10_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_ISRAM0_BUSECC_GROUP_11_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_ISRAM0_BUSECC_GROUP_12_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_ISRAM0_BUSECC_GROUP_13_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_ISRAM0_BUSECC_GROUP_14_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_ISRAM0_BUSECC_GROUP_15_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_ISRAM0_BUSECC_GROUP_16_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_ISRAM0_BUSECC_GROUP_17_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_ISRAM0_BUSECC_GROUP_18_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_ISRAM0_BUSECC_GROUP_19_WIDTH },
};
 
static const SDL_GrpChkConfig_t SDL_SMS0_SMS_HSM_ECC_ISRAM1_BUSECC_groupEntries[SDL_SMS0_SMS_HSM_ECC_ISRAM1_BUSECC_MAX_NUM_CHECKERS] =
{
    {  SDL_SMS0_SMS_HSM_ECC_ISRAM1_BUSECC_GROUP_0_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_ISRAM1_BUSECC_GROUP_1_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_ISRAM1_BUSECC_GROUP_2_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_ISRAM1_BUSECC_GROUP_3_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_ISRAM1_BUSECC_GROUP_4_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_ISRAM1_BUSECC_GROUP_5_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_ISRAM1_BUSECC_GROUP_6_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_ISRAM1_BUSECC_GROUP_7_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_ISRAM1_BUSECC_GROUP_8_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_ISRAM1_BUSECC_GROUP_9_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_ISRAM1_BUSECC_GROUP_10_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_ISRAM1_BUSECC_GROUP_11_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_ISRAM1_BUSECC_GROUP_12_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_ISRAM1_BUSECC_GROUP_13_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_ISRAM1_BUSECC_GROUP_14_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_ISRAM1_BUSECC_GROUP_15_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_ISRAM1_BUSECC_GROUP_16_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_ISRAM1_BUSECC_GROUP_17_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_ISRAM1_BUSECC_GROUP_18_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_ISRAM1_BUSECC_GROUP_19_WIDTH },
};
 
static const SDL_GrpChkConfig_t SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_groupEntries[SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_MAX_NUM_CHECKERS] =
{
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_0_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_1_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_2_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_3_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_4_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_5_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_6_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_7_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_8_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_9_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_10_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_11_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_12_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_13_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_14_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_15_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_16_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_17_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_18_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_19_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_20_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_21_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_22_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_23_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_24_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_25_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_26_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_27_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_28_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_29_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_30_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_31_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_32_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_33_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_34_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_35_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_36_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_37_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_38_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_39_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_40_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_41_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_42_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_43_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_44_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_45_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_46_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_47_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_48_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_49_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_50_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_51_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_52_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_53_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_54_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_55_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_56_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_57_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_58_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_59_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_60_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_61_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_62_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_63_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_64_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_65_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_66_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_67_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_68_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_69_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_70_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_71_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_72_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_73_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_74_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_75_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_76_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_77_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_78_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_79_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_80_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_81_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_82_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_83_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_84_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_85_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_86_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_87_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_88_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_89_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_90_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_91_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_92_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_93_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_94_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_95_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_96_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_97_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_98_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_99_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_100_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_101_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_102_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_103_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_104_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_105_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_106_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_107_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_108_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_109_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_110_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_111_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_112_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_113_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_114_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_115_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_116_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_117_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_118_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_119_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_120_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_121_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_122_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_123_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_124_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_125_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_126_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_127_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_128_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_129_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_130_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_131_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_132_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_133_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_134_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_135_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_136_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_137_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_138_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_139_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_140_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_141_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_142_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_143_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_144_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_145_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_146_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_147_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_148_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_149_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_150_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_151_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_152_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_153_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_154_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_155_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_156_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_157_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_158_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_159_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_160_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_161_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_162_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_163_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_164_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_165_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_166_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_167_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_168_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_169_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_170_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_171_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_172_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_173_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_174_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_175_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_176_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_177_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_178_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_179_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_180_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_181_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_182_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_183_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_184_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_185_WIDTH },
};
 
static const SDL_GrpChkConfig_t SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_groupEntries[SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_MAX_NUM_CHECKERS] =
{
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_GROUP_0_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_GROUP_1_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_GROUP_2_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_GROUP_3_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_GROUP_4_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_GROUP_5_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_GROUP_6_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_GROUP_7_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_GROUP_8_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_GROUP_9_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_GROUP_10_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_GROUP_11_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_GROUP_12_WIDTH },
};
 
static const SDL_GrpChkConfig_t SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_groupEntries[SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS] =
{
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_5_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_6_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_7_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_8_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_9_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_10_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_11_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_12_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_13_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_14_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_15_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_16_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_17_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_18_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_19_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_20_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_21_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_22_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_23_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_24_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_25_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_26_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_27_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_28_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_29_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_30_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_31_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_32_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_33_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_34_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_35_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_36_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_37_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_38_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_39_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_40_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_41_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_42_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_43_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_44_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_45_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_46_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_47_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_48_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_49_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_50_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_51_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_52_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_53_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_54_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_55_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_56_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_57_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_58_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_59_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_60_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_61_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_62_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_63_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_64_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_65_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_66_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_67_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_68_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_69_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_70_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_71_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_72_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_73_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_74_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_75_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_76_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_77_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_78_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_79_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_80_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_81_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_82_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_83_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_84_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_85_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_86_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_87_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_88_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_89_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_90_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_91_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_92_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_93_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_94_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_95_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_96_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_97_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_98_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_99_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_100_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_101_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_102_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_103_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_104_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_105_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_106_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_107_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_108_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_109_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_110_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_111_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_112_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_113_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_114_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_115_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_116_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_117_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_118_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_119_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_120_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_121_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_122_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_123_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_124_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_125_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_126_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_127_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_128_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_129_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_130_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_131_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_132_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_133_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_134_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_135_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_136_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_137_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_138_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_139_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_140_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_141_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_142_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_143_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_144_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_145_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_146_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_147_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_148_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_149_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_150_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_151_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_152_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_153_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_154_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_155_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_156_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_157_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_158_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_159_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_160_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_161_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_162_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_163_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_164_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_165_WIDTH },
};
 
static const SDL_GrpChkConfig_t SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_groupEntries[SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS] =
{
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_5_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_6_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_7_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_8_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_9_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_10_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_11_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_12_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_13_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_14_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_15_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_16_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_17_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_18_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_19_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_20_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_21_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_22_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_23_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_24_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_25_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_26_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_27_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_28_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_29_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_30_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_31_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_32_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_33_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_34_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_35_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_36_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_37_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_38_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_39_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_40_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_41_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_42_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_43_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_44_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_45_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_46_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_47_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_48_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_49_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_50_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_51_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_52_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_53_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_54_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_55_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_56_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_57_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_58_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_59_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_60_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_61_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_62_WIDTH },
};
 
static const SDL_GrpChkConfig_t SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_DEFAULT_MMRS_SMS_HSM_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_groupEntries[SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_DEFAULT_MMRS_SMS_HSM_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS] =
{
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_DEFAULT_MMRS_SMS_HSM_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_DEFAULT_MMRS_SMS_HSM_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_DEFAULT_MMRS_SMS_HSM_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_DEFAULT_MMRS_SMS_HSM_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_DEFAULT_MMRS_SMS_HSM_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_DEFAULT_MMRS_SMS_HSM_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_5_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_DEFAULT_MMRS_SMS_HSM_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_6_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_DEFAULT_MMRS_SMS_HSM_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_7_WIDTH },
};
 
static const SDL_GrpChkConfig_t SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_groupEntries[SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS] =
{
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_5_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_6_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_7_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_8_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_9_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_10_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_11_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_12_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_13_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_14_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_15_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_16_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_17_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_18_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_19_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_20_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_21_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_22_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_23_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_24_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_25_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_26_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_27_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_28_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_29_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_30_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_31_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_32_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_33_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_34_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_35_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_36_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_37_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_38_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_39_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_40_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_41_WIDTH },
};
 
static const SDL_GrpChkConfig_t SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_groupEntries[SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_MAX_NUM_CHECKERS] =
{
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_0_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_1_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_2_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_3_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_4_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_5_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_6_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_7_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_8_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_9_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_10_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_11_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_12_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_13_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_14_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_15_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_16_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_17_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_18_WIDTH },
};
 
static const SDL_GrpChkConfig_t SDL_SMS0_SMS_HSM_ECC_SMS_HSM_WWRTI_CM_EDC_CTRL_BUSECC_groupEntries[SDL_SMS0_SMS_HSM_ECC_SMS_HSM_WWRTI_CM_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS] =
{
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_WWRTI_CM_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_WWRTI_CM_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_WWRTI_CM_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_WWRTI_CM_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_WWRTI_CM_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_WWRTI_CM_EDC_CTRL_BUSECC_GROUP_5_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_WWRTI_CM_EDC_CTRL_BUSECC_GROUP_6_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_WWRTI_CM_EDC_CTRL_BUSECC_GROUP_7_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_WWRTI_CM_EDC_CTRL_BUSECC_GROUP_8_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_WWRTI_CM_EDC_CTRL_BUSECC_GROUP_9_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_WWRTI_CM_EDC_CTRL_BUSECC_GROUP_10_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_WWRTI_CM_EDC_CTRL_BUSECC_GROUP_11_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_WWRTI_CM_EDC_CTRL_BUSECC_GROUP_12_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_WWRTI_CM_EDC_CTRL_BUSECC_GROUP_13_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_WWRTI_CM_EDC_CTRL_BUSECC_GROUP_14_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_WWRTI_CM_EDC_CTRL_BUSECC_GROUP_15_WIDTH },
};
 
static const SDL_GrpChkConfig_t SDL_SMS0_SMS_HSM_ECC_SMS_HSM_ECC_EDC_CTRL_groupEntries[SDL_SMS0_SMS_HSM_ECC_SMS_HSM_ECC_EDC_CTRL_MAX_NUM_CHECKERS] =
{
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_ECC_EDC_CTRL_GROUP_0_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_ECC_EDC_CTRL_GROUP_1_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_ECC_EDC_CTRL_GROUP_2_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_ECC_EDC_CTRL_GROUP_3_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_ECC_EDC_CTRL_GROUP_4_WIDTH },
    {  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_ECC_EDC_CTRL_GROUP_5_WIDTH },
};
 
static const SDL_MemConfig_t SDL_SMS0_SMS_TIFS_ECC_MemEntries[SDL_SMS0_SMS_TIFS_ECC_RAM_IDS_TOTAL_ENTRIES] =
{
    { SDL_SMS0_SMS_TIFS_ECC_ISRAM0_RAMECC_RAM_ID, 0u,
      SDL_SMS0_SMS_TIFS_ECC_ISRAM0_RAMECC_RAM_SIZE, 4u,
      SDL_SMS0_SMS_TIFS_ECC_ISRAM0_RAMECC_ROW_WIDTH, ((bool)false) },
    { SDL_SMS0_SMS_TIFS_ECC_ISRAM1_RAMECC_RAM_ID, 0u,
      SDL_SMS0_SMS_TIFS_ECC_ISRAM1_RAMECC_RAM_SIZE, 4u,
      SDL_SMS0_SMS_TIFS_ECC_ISRAM1_RAMECC_ROW_WIDTH, ((bool)false) },
};
 
static const SDL_GrpChkConfig_t SDL_SMS0_SMS_TIFS_ECC_ISRAM0_BUSECC_groupEntries[SDL_SMS0_SMS_TIFS_ECC_ISRAM0_BUSECC_MAX_NUM_CHECKERS] =
{
    {  SDL_SMS0_SMS_TIFS_ECC_ISRAM0_BUSECC_GROUP_0_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_ISRAM0_BUSECC_GROUP_1_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_ISRAM0_BUSECC_GROUP_2_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_ISRAM0_BUSECC_GROUP_3_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_ISRAM0_BUSECC_GROUP_4_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_ISRAM0_BUSECC_GROUP_5_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_ISRAM0_BUSECC_GROUP_6_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_ISRAM0_BUSECC_GROUP_7_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_ISRAM0_BUSECC_GROUP_8_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_ISRAM0_BUSECC_GROUP_9_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_ISRAM0_BUSECC_GROUP_10_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_ISRAM0_BUSECC_GROUP_11_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_ISRAM0_BUSECC_GROUP_12_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_ISRAM0_BUSECC_GROUP_13_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_ISRAM0_BUSECC_GROUP_14_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_ISRAM0_BUSECC_GROUP_15_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_ISRAM0_BUSECC_GROUP_16_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_ISRAM0_BUSECC_GROUP_17_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_ISRAM0_BUSECC_GROUP_18_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_ISRAM0_BUSECC_GROUP_19_WIDTH },
};
 
static const SDL_GrpChkConfig_t SDL_SMS0_SMS_TIFS_ECC_ISRAM1_BUSECC_groupEntries[SDL_SMS0_SMS_TIFS_ECC_ISRAM1_BUSECC_MAX_NUM_CHECKERS] =
{
    {  SDL_SMS0_SMS_TIFS_ECC_ISRAM1_BUSECC_GROUP_0_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_ISRAM1_BUSECC_GROUP_1_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_ISRAM1_BUSECC_GROUP_2_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_ISRAM1_BUSECC_GROUP_3_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_ISRAM1_BUSECC_GROUP_4_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_ISRAM1_BUSECC_GROUP_5_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_ISRAM1_BUSECC_GROUP_6_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_ISRAM1_BUSECC_GROUP_7_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_ISRAM1_BUSECC_GROUP_8_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_ISRAM1_BUSECC_GROUP_9_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_ISRAM1_BUSECC_GROUP_10_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_ISRAM1_BUSECC_GROUP_11_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_ISRAM1_BUSECC_GROUP_12_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_ISRAM1_BUSECC_GROUP_13_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_ISRAM1_BUSECC_GROUP_14_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_ISRAM1_BUSECC_GROUP_15_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_ISRAM1_BUSECC_GROUP_16_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_ISRAM1_BUSECC_GROUP_17_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_ISRAM1_BUSECC_GROUP_18_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_ISRAM1_BUSECC_GROUP_19_WIDTH },
};
 
static const SDL_GrpChkConfig_t SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_groupEntries[SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_MAX_NUM_CHECKERS] =
{
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_0_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_1_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_2_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_3_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_4_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_5_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_6_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_7_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_8_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_9_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_10_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_11_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_12_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_13_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_14_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_15_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_16_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_17_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_18_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_19_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_20_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_21_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_22_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_23_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_24_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_25_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_26_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_27_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_28_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_29_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_30_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_31_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_32_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_33_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_34_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_35_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_36_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_37_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_38_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_39_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_40_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_41_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_42_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_43_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_44_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_45_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_46_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_47_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_48_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_49_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_50_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_51_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_52_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_53_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_54_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_55_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_56_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_57_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_58_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_59_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_60_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_61_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_62_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_63_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_64_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_65_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_66_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_67_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_68_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_69_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_70_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_71_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_72_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_73_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_74_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_75_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_76_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_77_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_78_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_79_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_80_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_81_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_82_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_83_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_84_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_85_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_86_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_87_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_88_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_89_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_90_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_91_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_92_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_93_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_94_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_95_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_96_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_97_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_98_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_99_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_100_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_101_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_102_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_103_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_104_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_105_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_106_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_107_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_108_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_109_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_110_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_111_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_112_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_113_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_114_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_115_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_116_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_117_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_118_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_119_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_120_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_121_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_122_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_123_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_124_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_125_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_126_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_127_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_128_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_129_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_130_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_131_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_132_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_133_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_134_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_135_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_136_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_137_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_138_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_139_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_140_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_141_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_142_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_143_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_144_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_145_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_146_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_147_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_148_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_149_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_150_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_151_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_152_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_153_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_154_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_155_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_156_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_157_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_158_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_159_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_160_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_161_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_162_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_163_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_164_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_165_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_166_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_167_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_168_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_169_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_170_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_171_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_172_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_173_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_174_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_175_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_176_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_177_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_178_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_179_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_180_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_181_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_182_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_183_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_184_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_185_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_186_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_187_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_188_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_189_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_190_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_191_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_192_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_193_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_194_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_195_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_196_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_197_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_198_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_199_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_200_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_201_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_202_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_203_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_204_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_205_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_206_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_207_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_208_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_209_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_210_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_211_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_212_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_213_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_214_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_215_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_216_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_217_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_218_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_219_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_220_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_221_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_222_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_223_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_224_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_225_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_226_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_227_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_228_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_229_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_230_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_231_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_232_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_233_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_234_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_235_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_236_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_237_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_238_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_239_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_240_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_241_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_242_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_243_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_244_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_245_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_246_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_247_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_248_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_249_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_250_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_251_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_252_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_253_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_254_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_255_WIDTH },
};
 
static const SDL_GrpChkConfig_t SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_groupEntries[SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_MAX_NUM_CHECKERS] =
{
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_0_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_1_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_2_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_3_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_4_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_5_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_6_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_7_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_8_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_9_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_10_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_11_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_12_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_13_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_14_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_15_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_16_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_17_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_18_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_19_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_20_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_21_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_22_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_23_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_24_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_25_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_26_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_27_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_28_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_29_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_30_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_31_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_32_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_33_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_34_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_35_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_36_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_37_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_38_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_39_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_40_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_41_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_42_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_43_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_44_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_45_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_46_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_47_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_48_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_49_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_50_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_51_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_52_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_53_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_54_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_55_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_56_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_57_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_58_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_59_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_60_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_61_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_62_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_63_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_64_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_65_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_66_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_67_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_68_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_69_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_70_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_71_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_72_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_73_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_74_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_75_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_76_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_77_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_78_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_79_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_80_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_81_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_82_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_83_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_84_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_85_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_86_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_87_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_88_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_89_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_90_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_91_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_92_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_93_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_94_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_95_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_96_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_97_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_98_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_99_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_100_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_101_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_102_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_103_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_104_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_105_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_106_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_107_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_108_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_109_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_110_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_111_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_112_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_113_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_114_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_115_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_116_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_117_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_118_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_119_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_120_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_121_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_122_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_123_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_124_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_125_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_126_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_127_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_128_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_129_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_130_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_131_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_132_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_133_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_134_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_135_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_136_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_137_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_138_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_139_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_140_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_141_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_142_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_143_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_144_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_145_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_146_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_147_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_148_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_149_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_150_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_151_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_152_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_153_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_154_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_155_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_156_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_157_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_158_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_159_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_160_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_161_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_162_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_163_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_164_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_165_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_166_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_167_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_168_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_169_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_170_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_171_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_172_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_173_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_174_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_175_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_176_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_177_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_178_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_179_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_180_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_181_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_182_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_183_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_184_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_185_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_186_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_187_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_188_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_189_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_190_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_191_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_192_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_193_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_194_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_195_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_196_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_197_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_198_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_199_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_200_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_201_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_202_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_203_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_204_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_205_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_206_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_207_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_208_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_209_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_210_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_211_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_212_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_213_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_214_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_215_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_216_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_217_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_218_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_219_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_220_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_221_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_222_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_223_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_224_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_225_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_226_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_227_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_228_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_229_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_230_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_231_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_232_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_233_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_234_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_235_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_236_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_237_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_238_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_239_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_240_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_241_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_242_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_243_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_244_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_245_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_246_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_247_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_248_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_249_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_250_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_251_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_252_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_253_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_254_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_255_WIDTH },
};
 
static const SDL_GrpChkConfig_t SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_2_groupEntries[SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_2_MAX_NUM_CHECKERS] =
{
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_2_GROUP_0_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_2_GROUP_1_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_2_GROUP_2_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_2_GROUP_3_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_2_GROUP_4_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_2_GROUP_5_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_2_GROUP_6_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_2_GROUP_7_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_2_GROUP_8_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_2_GROUP_9_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_2_GROUP_10_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_2_GROUP_11_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_2_GROUP_12_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_2_GROUP_13_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_2_GROUP_14_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_2_GROUP_15_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_2_GROUP_16_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_2_GROUP_17_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_2_GROUP_18_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_2_GROUP_19_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_2_GROUP_20_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_2_GROUP_21_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_2_GROUP_22_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_2_GROUP_23_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_2_GROUP_24_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_2_GROUP_25_WIDTH },
};
 
static const SDL_GrpChkConfig_t SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_groupEntries[SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_MAX_NUM_CHECKERS] =
{
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_GROUP_0_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_GROUP_1_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_GROUP_2_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_GROUP_3_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_GROUP_4_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_GROUP_5_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_GROUP_6_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_GROUP_7_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_GROUP_8_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_GROUP_9_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_GROUP_10_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_GROUP_11_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_GROUP_12_WIDTH },
};
 
static const SDL_GrpChkConfig_t SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IFWMGR_M_P2P_BRIDGE_IFWMGR_M_BRIDGE_BUSECC_groupEntries[SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IFWMGR_M_P2P_BRIDGE_IFWMGR_M_BRIDGE_BUSECC_MAX_NUM_CHECKERS] =
{
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IFWMGR_M_P2P_BRIDGE_IFWMGR_M_BRIDGE_BUSECC_GROUP_0_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IFWMGR_M_P2P_BRIDGE_IFWMGR_M_BRIDGE_BUSECC_GROUP_1_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IFWMGR_M_P2P_BRIDGE_IFWMGR_M_BRIDGE_BUSECC_GROUP_2_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IFWMGR_M_P2P_BRIDGE_IFWMGR_M_BRIDGE_BUSECC_GROUP_3_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IFWMGR_M_P2P_BRIDGE_IFWMGR_M_BRIDGE_BUSECC_GROUP_4_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IFWMGR_M_P2P_BRIDGE_IFWMGR_M_BRIDGE_BUSECC_GROUP_5_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IFWMGR_M_P2P_BRIDGE_IFWMGR_M_BRIDGE_BUSECC_GROUP_6_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IFWMGR_M_P2P_BRIDGE_IFWMGR_M_BRIDGE_BUSECC_GROUP_7_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IFWMGR_M_P2P_BRIDGE_IFWMGR_M_BRIDGE_BUSECC_GROUP_8_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IFWMGR_M_P2P_BRIDGE_IFWMGR_M_BRIDGE_BUSECC_GROUP_9_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IFWMGR_M_P2P_BRIDGE_IFWMGR_M_BRIDGE_BUSECC_GROUP_10_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IFWMGR_M_P2P_BRIDGE_IFWMGR_M_BRIDGE_BUSECC_GROUP_11_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IFWMGR_M_P2P_BRIDGE_IFWMGR_M_BRIDGE_BUSECC_GROUP_12_WIDTH },
};
 
static const SDL_GrpChkConfig_t SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_groupEntries[SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_MAX_NUM_CHECKERS] =
{
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_0_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_1_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_2_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_3_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_4_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_5_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_6_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_7_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_8_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_9_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_10_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_11_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_12_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_13_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_14_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_15_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_16_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_17_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_18_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_19_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_20_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_21_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_22_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_23_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_24_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_25_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_26_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_27_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_28_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_29_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_30_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_31_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_32_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_33_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_34_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_35_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_36_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_37_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_38_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_39_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_40_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_41_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_42_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_43_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_44_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_45_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_46_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_47_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_48_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_49_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_50_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_51_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_52_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_53_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_54_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_55_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_56_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_57_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_58_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_59_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_60_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_61_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_62_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_63_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_64_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_65_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_66_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_67_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_68_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_69_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_70_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_71_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_72_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_73_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_74_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_75_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_76_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_77_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_78_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_79_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_80_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_81_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_82_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_83_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_84_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_85_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_86_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_87_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_88_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_89_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_90_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_91_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_92_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_93_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_94_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_95_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_96_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_97_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_98_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_99_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_100_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_101_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_102_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_103_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_104_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_105_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_106_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_107_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_108_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_109_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_110_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_111_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_112_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_113_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_114_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_115_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_116_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_117_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_118_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_119_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_120_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_121_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_122_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_123_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_124_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_125_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_126_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_127_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_128_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_129_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_130_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_131_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_132_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_133_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_134_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_135_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_136_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_137_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_138_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_139_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_140_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_141_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_142_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_143_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_144_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_145_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_146_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_147_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_148_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_149_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_150_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_151_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_152_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_153_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_154_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_155_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_156_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_157_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_158_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_159_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_160_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_161_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_162_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_163_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_164_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_165_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_166_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_167_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_168_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_169_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_170_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_171_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_172_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_173_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_174_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_175_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_176_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_177_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_178_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_179_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_180_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_181_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_182_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_183_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_184_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_185_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_186_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_187_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_188_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_189_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_190_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_191_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_192_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_193_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_194_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_195_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_196_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_197_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_198_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_199_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_200_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_201_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_202_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_203_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_204_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_205_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_206_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_207_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_208_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_209_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_210_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_211_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_212_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_213_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_214_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_215_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_216_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_217_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_218_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_219_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_220_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_221_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_222_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_223_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_224_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_225_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_226_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_227_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_228_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_229_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_230_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_231_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_232_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_233_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_234_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_235_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_236_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_237_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_238_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_239_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_240_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_241_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_242_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_243_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_244_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_245_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_246_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_247_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_248_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_249_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_250_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_251_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_252_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_253_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_254_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_255_WIDTH },
};
 
static const SDL_GrpChkConfig_t SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_groupEntries[SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_MAX_NUM_CHECKERS] =
{
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_0_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_1_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_2_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_3_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_4_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_5_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_6_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_7_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_8_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_9_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_10_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_11_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_12_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_13_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_14_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_15_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_16_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_17_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_18_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_19_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_20_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_21_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_22_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_23_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_24_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_25_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_26_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_27_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_28_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_29_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_30_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_31_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_32_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_33_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_34_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_35_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_36_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_37_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_38_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_39_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_40_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_41_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_42_WIDTH },
};
 
static const SDL_GrpChkConfig_t SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_groupEntries[SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS] =
{
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_5_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_6_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_7_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_8_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_9_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_10_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_11_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_12_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_13_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_14_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_15_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_16_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_17_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_18_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_19_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_20_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_21_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_22_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_23_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_24_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_25_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_26_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_27_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_28_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_29_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_30_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_31_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_32_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_33_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_34_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_35_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_36_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_37_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_38_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_39_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_40_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_41_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_42_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_43_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_44_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_45_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_46_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_47_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_48_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_49_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_50_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_51_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_52_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_53_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_54_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_55_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_56_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_57_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_58_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_59_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_60_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_61_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_62_WIDTH },
};
 
static const SDL_GrpChkConfig_t SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_DEFAULT_MMRS_SMS_TIFS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_groupEntries[SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_DEFAULT_MMRS_SMS_TIFS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS] =
{
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_DEFAULT_MMRS_SMS_TIFS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_DEFAULT_MMRS_SMS_TIFS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_DEFAULT_MMRS_SMS_TIFS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_DEFAULT_MMRS_SMS_TIFS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_DEFAULT_MMRS_SMS_TIFS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_DEFAULT_MMRS_SMS_TIFS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_5_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_DEFAULT_MMRS_SMS_TIFS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_6_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_DEFAULT_MMRS_SMS_TIFS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_7_WIDTH },
};
 
static const SDL_GrpChkConfig_t SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_groupEntries[SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS] =
{
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_5_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_6_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_7_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_8_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_9_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_10_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_11_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_12_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_13_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_14_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_15_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_16_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_17_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_18_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_19_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_20_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_21_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_22_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_23_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_24_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_25_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_26_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_27_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_28_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_29_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_30_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_31_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_32_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_33_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_34_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_35_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_36_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_37_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_38_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_39_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_40_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_41_WIDTH },
};
 
static const SDL_GrpChkConfig_t SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_groupEntries[SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_MAX_NUM_CHECKERS] =
{
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_0_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_1_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_2_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_3_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_4_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_5_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_6_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_7_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_8_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_9_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_10_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_11_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_12_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_13_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_14_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_15_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_16_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_17_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_18_WIDTH },
};
 
static const SDL_GrpChkConfig_t SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_groupEntries[SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS] =
{
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_5_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_6_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_7_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_8_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_9_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_10_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_11_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_12_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_13_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_14_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_15_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_16_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_17_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_18_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_19_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_20_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_21_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_22_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_23_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_24_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_25_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_26_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_27_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_28_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_29_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_30_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_31_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_32_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_33_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_34_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_35_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_36_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_37_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_38_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_39_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_40_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_41_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_42_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_43_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_44_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_45_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_46_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_47_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_48_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_49_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_50_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_51_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_52_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_53_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_54_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_55_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_56_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_57_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_58_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_59_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_60_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_61_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_62_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_63_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_64_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_65_WIDTH },
};
 
static const SDL_GrpChkConfig_t SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_DMSS_HSM_P2P_BRIDGE_SMS_DMSS_HSM_BRIDGE_BUSECC_groupEntries[SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_DMSS_HSM_P2P_BRIDGE_SMS_DMSS_HSM_BRIDGE_BUSECC_MAX_NUM_CHECKERS] =
{
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_DMSS_HSM_P2P_BRIDGE_SMS_DMSS_HSM_BRIDGE_BUSECC_GROUP_0_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_DMSS_HSM_P2P_BRIDGE_SMS_DMSS_HSM_BRIDGE_BUSECC_GROUP_1_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_DMSS_HSM_P2P_BRIDGE_SMS_DMSS_HSM_BRIDGE_BUSECC_GROUP_2_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_DMSS_HSM_P2P_BRIDGE_SMS_DMSS_HSM_BRIDGE_BUSECC_GROUP_3_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_DMSS_HSM_P2P_BRIDGE_SMS_DMSS_HSM_BRIDGE_BUSECC_GROUP_4_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_DMSS_HSM_P2P_BRIDGE_SMS_DMSS_HSM_BRIDGE_BUSECC_GROUP_5_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_DMSS_HSM_P2P_BRIDGE_SMS_DMSS_HSM_BRIDGE_BUSECC_GROUP_6_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_DMSS_HSM_P2P_BRIDGE_SMS_DMSS_HSM_BRIDGE_BUSECC_GROUP_7_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_DMSS_HSM_P2P_BRIDGE_SMS_DMSS_HSM_BRIDGE_BUSECC_GROUP_8_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_DMSS_HSM_P2P_BRIDGE_SMS_DMSS_HSM_BRIDGE_BUSECC_GROUP_9_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_DMSS_HSM_P2P_BRIDGE_SMS_DMSS_HSM_BRIDGE_BUSECC_GROUP_10_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_DMSS_HSM_P2P_BRIDGE_SMS_DMSS_HSM_BRIDGE_BUSECC_GROUP_11_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_DMSS_HSM_P2P_BRIDGE_SMS_DMSS_HSM_BRIDGE_BUSECC_GROUP_12_WIDTH },
};
 
static const SDL_GrpChkConfig_t SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_WWRTI_CM_EDC_CTRL_BUSECC_groupEntries[SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_WWRTI_CM_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS] =
{
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_WWRTI_CM_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_WWRTI_CM_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_WWRTI_CM_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_WWRTI_CM_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_WWRTI_CM_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_WWRTI_CM_EDC_CTRL_BUSECC_GROUP_5_WIDTH },
};
 
static const SDL_GrpChkConfig_t SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CM_EDC_CTRL_BUSECC_groupEntries[SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CM_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS] =
{
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CM_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CM_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CM_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CM_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CM_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CM_EDC_CTRL_BUSECC_GROUP_5_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CM_EDC_CTRL_BUSECC_GROUP_6_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CM_EDC_CTRL_BUSECC_GROUP_7_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CM_EDC_CTRL_BUSECC_GROUP_8_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CM_EDC_CTRL_BUSECC_GROUP_9_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CM_EDC_CTRL_BUSECC_GROUP_10_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CM_EDC_CTRL_BUSECC_GROUP_11_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CM_EDC_CTRL_BUSECC_GROUP_12_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CM_EDC_CTRL_BUSECC_GROUP_13_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CM_EDC_CTRL_BUSECC_GROUP_14_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CM_EDC_CTRL_BUSECC_GROUP_15_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CM_EDC_CTRL_BUSECC_GROUP_16_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CM_EDC_CTRL_BUSECC_GROUP_17_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CM_EDC_CTRL_BUSECC_GROUP_18_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CM_EDC_CTRL_BUSECC_GROUP_19_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CM_EDC_CTRL_BUSECC_GROUP_20_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CM_EDC_CTRL_BUSECC_GROUP_21_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CM_EDC_CTRL_BUSECC_GROUP_22_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CM_EDC_CTRL_BUSECC_GROUP_23_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CM_EDC_CTRL_BUSECC_GROUP_24_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CM_EDC_CTRL_BUSECC_GROUP_25_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CM_EDC_CTRL_BUSECC_GROUP_26_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CM_EDC_CTRL_BUSECC_GROUP_27_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CM_EDC_CTRL_BUSECC_GROUP_28_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CM_EDC_CTRL_BUSECC_GROUP_29_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CM_EDC_CTRL_BUSECC_GROUP_30_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CM_EDC_CTRL_BUSECC_GROUP_31_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CM_EDC_CTRL_BUSECC_GROUP_32_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CM_EDC_CTRL_BUSECC_GROUP_33_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CM_EDC_CTRL_BUSECC_GROUP_34_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CM_EDC_CTRL_BUSECC_GROUP_35_WIDTH },
};
 
static const SDL_GrpChkConfig_t SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_SEC_CM_EDC_CTRL_BUSECC_groupEntries[SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_SEC_CM_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS] =
{
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_SEC_CM_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_SEC_CM_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_SEC_CM_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_SEC_CM_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_SEC_CM_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_SEC_CM_EDC_CTRL_BUSECC_GROUP_5_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_SEC_CM_EDC_CTRL_BUSECC_GROUP_6_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_SEC_CM_EDC_CTRL_BUSECC_GROUP_7_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_SEC_CM_EDC_CTRL_BUSECC_GROUP_8_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_SEC_CM_EDC_CTRL_BUSECC_GROUP_9_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_SEC_CM_EDC_CTRL_BUSECC_GROUP_10_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_SEC_CM_EDC_CTRL_BUSECC_GROUP_11_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_SEC_CM_EDC_CTRL_BUSECC_GROUP_12_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_SEC_CM_EDC_CTRL_BUSECC_GROUP_13_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_SEC_CM_EDC_CTRL_BUSECC_GROUP_14_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_SEC_CM_EDC_CTRL_BUSECC_GROUP_15_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_SEC_CM_EDC_CTRL_BUSECC_GROUP_16_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_SEC_CM_EDC_CTRL_BUSECC_GROUP_17_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_SEC_CM_EDC_CTRL_BUSECC_GROUP_18_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_SEC_CM_EDC_CTRL_BUSECC_GROUP_19_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_SEC_CM_EDC_CTRL_BUSECC_GROUP_20_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_SEC_CM_EDC_CTRL_BUSECC_GROUP_21_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_SEC_CM_EDC_CTRL_BUSECC_GROUP_22_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_SEC_CM_EDC_CTRL_BUSECC_GROUP_23_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_SEC_CM_EDC_CTRL_BUSECC_GROUP_24_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_SEC_CM_EDC_CTRL_BUSECC_GROUP_25_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_SEC_CM_EDC_CTRL_BUSECC_GROUP_26_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_SEC_CM_EDC_CTRL_BUSECC_GROUP_27_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_SEC_CM_EDC_CTRL_BUSECC_GROUP_28_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_SEC_CM_EDC_CTRL_BUSECC_GROUP_29_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_SEC_CM_EDC_CTRL_BUSECC_GROUP_30_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_SEC_CM_EDC_CTRL_BUSECC_GROUP_31_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_SEC_CM_EDC_CTRL_BUSECC_GROUP_32_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_SEC_CM_EDC_CTRL_BUSECC_GROUP_33_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_SEC_CM_EDC_CTRL_BUSECC_GROUP_34_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_SEC_CM_EDC_CTRL_BUSECC_GROUP_35_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_SEC_CM_EDC_CTRL_BUSECC_GROUP_36_WIDTH },
};
 
static const SDL_GrpChkConfig_t SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_ECC_EDC_CTRL_groupEntries[SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_ECC_EDC_CTRL_MAX_NUM_CHECKERS] =
{
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_ECC_EDC_CTRL_GROUP_0_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_ECC_EDC_CTRL_GROUP_1_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_ECC_EDC_CTRL_GROUP_2_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_ECC_EDC_CTRL_GROUP_3_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_ECC_EDC_CTRL_GROUP_4_WIDTH },
    {  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_ECC_EDC_CTRL_GROUP_5_WIDTH },
};
 
static const SDL_MemConfig_t SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_MemEntries[SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES] =
{
    { SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_ISAM62_MCU2CENTRAL_VBUSM_GASKET_MCU_0_RD_RAMECC_RAM_ID, 0u,
      SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_ISAM62_MCU2CENTRAL_VBUSM_GASKET_MCU_0_RD_RAMECC_RAM_SIZE, 4u,
      SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_ISAM62_MCU2CENTRAL_VBUSM_GASKET_MCU_0_RD_RAMECC_ROW_WIDTH, ((bool)false) },
    { SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_ISAM62_MCU2CENTRAL_VBUSM_GASKET_MCU_0_WR_RAMECC_RAM_ID, 0u,
      SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_ISAM62_MCU2CENTRAL_VBUSM_GASKET_MCU_0_WR_RAMECC_RAM_SIZE, 4u,
      SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_ISAM62_MCU2CENTRAL_VBUSM_GASKET_MCU_0_WR_RAMECC_ROW_WIDTH, ((bool)false) },
    { SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_ISAM62_MCU2DM_VBUSM_GASKET_MCU_1_RD_RAMECC_RAM_ID, 0u,
      SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_ISAM62_MCU2DM_VBUSM_GASKET_MCU_1_RD_RAMECC_RAM_SIZE, 4u,
      SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_ISAM62_MCU2DM_VBUSM_GASKET_MCU_1_RD_RAMECC_ROW_WIDTH, ((bool)false) },
    { SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_ISAM62_MCU2DM_VBUSM_GASKET_MCU_1_WR_RAMECC_RAM_ID, 0u,
      SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_ISAM62_MCU2DM_VBUSM_GASKET_MCU_1_WR_RAMECC_RAM_SIZE, 4u,
      SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_ISAM62_MCU2DM_VBUSM_GASKET_MCU_1_WR_RAMECC_ROW_WIDTH, ((bool)false) },
};
 
static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_BLAZAR_VBUSP_M_P2P_DST_BUSECC_groupEntries[SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_BLAZAR_VBUSP_M_P2P_DST_BUSECC_MAX_NUM_CHECKERS] =
{
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_BLAZAR_VBUSP_M_P2P_DST_BUSECC_GROUP_0_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_BLAZAR_VBUSP_M_P2P_DST_BUSECC_GROUP_1_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_BLAZAR_VBUSP_M_P2P_DST_BUSECC_GROUP_2_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_BLAZAR_VBUSP_M_P2P_DST_BUSECC_GROUP_3_WIDTH },
};
 
static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_BLAZAR_VBUSP_M_P2P_SRC_BUSECC_groupEntries[SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_BLAZAR_VBUSP_M_P2P_SRC_BUSECC_MAX_NUM_CHECKERS] =
{
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_BLAZAR_VBUSP_M_P2P_SRC_BUSECC_GROUP_0_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_BLAZAR_VBUSP_M_P2P_SRC_BUSECC_GROUP_1_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_BLAZAR_VBUSP_M_P2P_SRC_BUSECC_GROUP_2_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_BLAZAR_VBUSP_M_P2P_SRC_BUSECC_GROUP_3_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_BLAZAR_VBUSP_M_P2P_SRC_BUSECC_GROUP_4_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_BLAZAR_VBUSP_M_P2P_SRC_BUSECC_GROUP_5_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_BLAZAR_VBUSP_M_P2P_SRC_BUSECC_GROUP_6_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_BLAZAR_VBUSP_M_P2P_SRC_BUSECC_GROUP_7_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_BLAZAR_VBUSP_M_P2P_SRC_BUSECC_GROUP_8_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_BLAZAR_VBUSP_M_P2P_SRC_BUSECC_GROUP_9_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_BLAZAR_VBUSP_M_P2P_SRC_BUSECC_GROUP_10_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_BLAZAR_VBUSP_M_P2P_SRC_BUSECC_GROUP_11_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_BLAZAR_VBUSP_M_P2P_SRC_BUSECC_GROUP_12_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_BLAZAR_VBUSP_M_P2P_SRC_BUSECC_GROUP_13_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_BLAZAR_VBUSP_M_P2P_SRC_BUSECC_GROUP_14_WIDTH },
};
 
static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_BLAZAR_VBUSP_S_P2P_DST_BUSECC_groupEntries[SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_BLAZAR_VBUSP_S_P2P_DST_BUSECC_MAX_NUM_CHECKERS] =
{
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_BLAZAR_VBUSP_S_P2P_DST_BUSECC_GROUP_0_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_BLAZAR_VBUSP_S_P2P_DST_BUSECC_GROUP_1_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_BLAZAR_VBUSP_S_P2P_DST_BUSECC_GROUP_2_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_BLAZAR_VBUSP_S_P2P_DST_BUSECC_GROUP_3_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_BLAZAR_VBUSP_S_P2P_DST_BUSECC_GROUP_4_WIDTH },
};
 
static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_BLAZAR_VBUSP_S_P2P_SRC_BUSECC_groupEntries[SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_BLAZAR_VBUSP_S_P2P_SRC_BUSECC_MAX_NUM_CHECKERS] =
{
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_BLAZAR_VBUSP_S_P2P_SRC_BUSECC_GROUP_0_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_BLAZAR_VBUSP_S_P2P_SRC_BUSECC_GROUP_1_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_BLAZAR_VBUSP_S_P2P_SRC_BUSECC_GROUP_2_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_BLAZAR_VBUSP_S_P2P_SRC_BUSECC_GROUP_3_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_BLAZAR_VBUSP_S_P2P_SRC_BUSECC_GROUP_4_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_BLAZAR_VBUSP_S_P2P_SRC_BUSECC_GROUP_5_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_BLAZAR_VBUSP_S_P2P_SRC_BUSECC_GROUP_6_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_BLAZAR_VBUSP_S_P2P_SRC_BUSECC_GROUP_7_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_BLAZAR_VBUSP_S_P2P_SRC_BUSECC_GROUP_8_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_BLAZAR_VBUSP_S_P2P_SRC_BUSECC_GROUP_9_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_BLAZAR_VBUSP_S_P2P_SRC_BUSECC_GROUP_10_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_BLAZAR_VBUSP_S_P2P_SRC_BUSECC_GROUP_11_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_BLAZAR_VBUSP_S_P2P_SRC_BUSECC_GROUP_12_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_BLAZAR_VBUSP_S_P2P_SRC_BUSECC_GROUP_13_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_BLAZAR_VBUSP_S_P2P_SRC_BUSECC_GROUP_14_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_BLAZAR_VBUSP_S_P2P_SRC_BUSECC_GROUP_15_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_BLAZAR_VBUSP_S_P2P_SRC_BUSECC_GROUP_16_WIDTH },
};
 
static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_IAM62_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM62_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_BUSECC_groupEntries[SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_IAM62_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM62_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_BUSECC_MAX_NUM_CHECKERS] =
{
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_IAM62_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM62_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_BUSECC_GROUP_0_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_IAM62_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM62_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_BUSECC_GROUP_1_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_IAM62_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM62_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_BUSECC_GROUP_2_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_IAM62_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM62_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_BUSECC_GROUP_3_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_IAM62_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM62_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_BUSECC_GROUP_4_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_IAM62_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM62_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_BUSECC_GROUP_5_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_IAM62_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM62_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_BUSECC_GROUP_6_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_IAM62_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM62_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_BUSECC_GROUP_7_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_IAM62_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM62_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_BUSECC_GROUP_8_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_IAM62_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM62_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_BUSECC_GROUP_9_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_IAM62_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM62_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_BUSECC_GROUP_10_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_IAM62_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM62_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_BUSECC_GROUP_11_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_IAM62_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM62_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_BUSECC_GROUP_12_WIDTH },
};
 
static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_IBLAZAR_MCU_0_VBUSP_S_P2P_BRIDGE_IBLAZAR_MCU_0_VBUSP_S_BRIDGE_BUSECC_groupEntries[SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_IBLAZAR_MCU_0_VBUSP_S_P2P_BRIDGE_IBLAZAR_MCU_0_VBUSP_S_BRIDGE_BUSECC_MAX_NUM_CHECKERS] =
{
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_IBLAZAR_MCU_0_VBUSP_S_P2P_BRIDGE_IBLAZAR_MCU_0_VBUSP_S_BRIDGE_BUSECC_GROUP_0_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_IBLAZAR_MCU_0_VBUSP_S_P2P_BRIDGE_IBLAZAR_MCU_0_VBUSP_S_BRIDGE_BUSECC_GROUP_1_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_IBLAZAR_MCU_0_VBUSP_S_P2P_BRIDGE_IBLAZAR_MCU_0_VBUSP_S_BRIDGE_BUSECC_GROUP_2_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_IBLAZAR_MCU_0_VBUSP_S_P2P_BRIDGE_IBLAZAR_MCU_0_VBUSP_S_BRIDGE_BUSECC_GROUP_3_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_IBLAZAR_MCU_0_VBUSP_S_P2P_BRIDGE_IBLAZAR_MCU_0_VBUSP_S_BRIDGE_BUSECC_GROUP_4_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_IBLAZAR_MCU_0_VBUSP_S_P2P_BRIDGE_IBLAZAR_MCU_0_VBUSP_S_BRIDGE_BUSECC_GROUP_5_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_IBLAZAR_MCU_0_VBUSP_S_P2P_BRIDGE_IBLAZAR_MCU_0_VBUSP_S_BRIDGE_BUSECC_GROUP_6_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_IBLAZAR_MCU_0_VBUSP_S_P2P_BRIDGE_IBLAZAR_MCU_0_VBUSP_S_BRIDGE_BUSECC_GROUP_7_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_IBLAZAR_MCU_0_VBUSP_S_P2P_BRIDGE_IBLAZAR_MCU_0_VBUSP_S_BRIDGE_BUSECC_GROUP_8_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_IBLAZAR_MCU_0_VBUSP_S_P2P_BRIDGE_IBLAZAR_MCU_0_VBUSP_S_BRIDGE_BUSECC_GROUP_9_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_IBLAZAR_MCU_0_VBUSP_S_P2P_BRIDGE_IBLAZAR_MCU_0_VBUSP_S_BRIDGE_BUSECC_GROUP_10_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_IBLAZAR_MCU_0_VBUSP_S_P2P_BRIDGE_IBLAZAR_MCU_0_VBUSP_S_BRIDGE_BUSECC_GROUP_11_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_IBLAZAR_MCU_0_VBUSP_S_P2P_BRIDGE_IBLAZAR_MCU_0_VBUSP_S_BRIDGE_BUSECC_GROUP_12_WIDTH },
};
 
static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_ISAM62_CENTRAL2MCU_VBUSM_GASKET_MCU_0_EDC_CTRL_groupEntries[SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_ISAM62_CENTRAL2MCU_VBUSM_GASKET_MCU_0_EDC_CTRL_MAX_NUM_CHECKERS] =
{
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_ISAM62_CENTRAL2MCU_VBUSM_GASKET_MCU_0_EDC_CTRL_GROUP_0_WIDTH },
};
 
static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_ISAM62_MCU2CENTRAL_VBUSM_GASKET_MCU_0_CFG_P2P_BRIDGE_ISAM62_MCU2CENTRAL_VBUSM_GASKET_MCU_0_CFG_BRIDGE_BUSECC_groupEntries[SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_ISAM62_MCU2CENTRAL_VBUSM_GASKET_MCU_0_CFG_P2P_BRIDGE_ISAM62_MCU2CENTRAL_VBUSM_GASKET_MCU_0_CFG_BRIDGE_BUSECC_MAX_NUM_CHECKERS] =
{
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_ISAM62_MCU2CENTRAL_VBUSM_GASKET_MCU_0_CFG_P2P_BRIDGE_ISAM62_MCU2CENTRAL_VBUSM_GASKET_MCU_0_CFG_BRIDGE_BUSECC_GROUP_0_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_ISAM62_MCU2CENTRAL_VBUSM_GASKET_MCU_0_CFG_P2P_BRIDGE_ISAM62_MCU2CENTRAL_VBUSM_GASKET_MCU_0_CFG_BRIDGE_BUSECC_GROUP_1_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_ISAM62_MCU2CENTRAL_VBUSM_GASKET_MCU_0_CFG_P2P_BRIDGE_ISAM62_MCU2CENTRAL_VBUSM_GASKET_MCU_0_CFG_BRIDGE_BUSECC_GROUP_2_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_ISAM62_MCU2CENTRAL_VBUSM_GASKET_MCU_0_CFG_P2P_BRIDGE_ISAM62_MCU2CENTRAL_VBUSM_GASKET_MCU_0_CFG_BRIDGE_BUSECC_GROUP_3_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_ISAM62_MCU2CENTRAL_VBUSM_GASKET_MCU_0_CFG_P2P_BRIDGE_ISAM62_MCU2CENTRAL_VBUSM_GASKET_MCU_0_CFG_BRIDGE_BUSECC_GROUP_4_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_ISAM62_MCU2CENTRAL_VBUSM_GASKET_MCU_0_CFG_P2P_BRIDGE_ISAM62_MCU2CENTRAL_VBUSM_GASKET_MCU_0_CFG_BRIDGE_BUSECC_GROUP_5_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_ISAM62_MCU2CENTRAL_VBUSM_GASKET_MCU_0_CFG_P2P_BRIDGE_ISAM62_MCU2CENTRAL_VBUSM_GASKET_MCU_0_CFG_BRIDGE_BUSECC_GROUP_6_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_ISAM62_MCU2CENTRAL_VBUSM_GASKET_MCU_0_CFG_P2P_BRIDGE_ISAM62_MCU2CENTRAL_VBUSM_GASKET_MCU_0_CFG_BRIDGE_BUSECC_GROUP_7_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_ISAM62_MCU2CENTRAL_VBUSM_GASKET_MCU_0_CFG_P2P_BRIDGE_ISAM62_MCU2CENTRAL_VBUSM_GASKET_MCU_0_CFG_BRIDGE_BUSECC_GROUP_8_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_ISAM62_MCU2CENTRAL_VBUSM_GASKET_MCU_0_CFG_P2P_BRIDGE_ISAM62_MCU2CENTRAL_VBUSM_GASKET_MCU_0_CFG_BRIDGE_BUSECC_GROUP_9_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_ISAM62_MCU2CENTRAL_VBUSM_GASKET_MCU_0_CFG_P2P_BRIDGE_ISAM62_MCU2CENTRAL_VBUSM_GASKET_MCU_0_CFG_BRIDGE_BUSECC_GROUP_10_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_ISAM62_MCU2CENTRAL_VBUSM_GASKET_MCU_0_CFG_P2P_BRIDGE_ISAM62_MCU2CENTRAL_VBUSM_GASKET_MCU_0_CFG_BRIDGE_BUSECC_GROUP_11_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_ISAM62_MCU2CENTRAL_VBUSM_GASKET_MCU_0_CFG_P2P_BRIDGE_ISAM62_MCU2CENTRAL_VBUSM_GASKET_MCU_0_CFG_BRIDGE_BUSECC_GROUP_12_WIDTH },
};
 
static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_ISAM62_MCU2CENTRAL_VBUSM_GASKET_MCU_0_EDC_CTRL_groupEntries[SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_ISAM62_MCU2CENTRAL_VBUSM_GASKET_MCU_0_EDC_CTRL_MAX_NUM_CHECKERS] =
{
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_ISAM62_MCU2CENTRAL_VBUSM_GASKET_MCU_0_EDC_CTRL_GROUP_0_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_ISAM62_MCU2CENTRAL_VBUSM_GASKET_MCU_0_EDC_CTRL_GROUP_1_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_ISAM62_MCU2CENTRAL_VBUSM_GASKET_MCU_0_EDC_CTRL_GROUP_2_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_ISAM62_MCU2CENTRAL_VBUSM_GASKET_MCU_0_EDC_CTRL_GROUP_3_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_ISAM62_MCU2CENTRAL_VBUSM_GASKET_MCU_0_EDC_CTRL_GROUP_4_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_ISAM62_MCU2CENTRAL_VBUSM_GASKET_MCU_0_EDC_CTRL_GROUP_5_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_ISAM62_MCU2CENTRAL_VBUSM_GASKET_MCU_0_EDC_CTRL_GROUP_6_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_ISAM62_MCU2CENTRAL_VBUSM_GASKET_MCU_0_EDC_CTRL_GROUP_7_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_ISAM62_MCU2CENTRAL_VBUSM_GASKET_MCU_0_EDC_CTRL_GROUP_8_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_ISAM62_MCU2CENTRAL_VBUSM_GASKET_MCU_0_EDC_CTRL_GROUP_9_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_ISAM62_MCU2CENTRAL_VBUSM_GASKET_MCU_0_EDC_CTRL_GROUP_10_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_ISAM62_MCU2CENTRAL_VBUSM_GASKET_MCU_0_EDC_CTRL_GROUP_11_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_ISAM62_MCU2CENTRAL_VBUSM_GASKET_MCU_0_EDC_CTRL_GROUP_12_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_ISAM62_MCU2CENTRAL_VBUSM_GASKET_MCU_0_EDC_CTRL_GROUP_13_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_ISAM62_MCU2CENTRAL_VBUSM_GASKET_MCU_0_EDC_CTRL_GROUP_14_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_ISAM62_MCU2CENTRAL_VBUSM_GASKET_MCU_0_EDC_CTRL_GROUP_15_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_ISAM62_MCU2CENTRAL_VBUSM_GASKET_MCU_0_EDC_CTRL_GROUP_16_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_ISAM62_MCU2CENTRAL_VBUSM_GASKET_MCU_0_EDC_CTRL_GROUP_17_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_ISAM62_MCU2CENTRAL_VBUSM_GASKET_MCU_0_EDC_CTRL_GROUP_18_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_ISAM62_MCU2CENTRAL_VBUSM_GASKET_MCU_0_EDC_CTRL_GROUP_19_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_ISAM62_MCU2CENTRAL_VBUSM_GASKET_MCU_0_EDC_CTRL_GROUP_20_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_ISAM62_MCU2CENTRAL_VBUSM_GASKET_MCU_0_EDC_CTRL_GROUP_21_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_ISAM62_MCU2CENTRAL_VBUSM_GASKET_MCU_0_EDC_CTRL_GROUP_22_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_ISAM62_MCU2CENTRAL_VBUSM_GASKET_MCU_0_EDC_CTRL_GROUP_23_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_ISAM62_MCU2CENTRAL_VBUSM_GASKET_MCU_0_EDC_CTRL_GROUP_24_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_ISAM62_MCU2CENTRAL_VBUSM_GASKET_MCU_0_EDC_CTRL_GROUP_25_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_ISAM62_MCU2CENTRAL_VBUSM_GASKET_MCU_0_EDC_CTRL_GROUP_26_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_ISAM62_MCU2CENTRAL_VBUSM_GASKET_MCU_0_EDC_CTRL_GROUP_27_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_ISAM62_MCU2CENTRAL_VBUSM_GASKET_MCU_0_EDC_CTRL_GROUP_28_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_ISAM62_MCU2CENTRAL_VBUSM_GASKET_MCU_0_EDC_CTRL_GROUP_29_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_ISAM62_MCU2CENTRAL_VBUSM_GASKET_MCU_0_EDC_CTRL_GROUP_30_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_ISAM62_MCU2CENTRAL_VBUSM_GASKET_MCU_0_EDC_CTRL_GROUP_31_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_ISAM62_MCU2CENTRAL_VBUSM_GASKET_MCU_0_EDC_CTRL_GROUP_32_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_ISAM62_MCU2CENTRAL_VBUSM_GASKET_MCU_0_EDC_CTRL_GROUP_33_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_ISAM62_MCU2CENTRAL_VBUSM_GASKET_MCU_0_EDC_CTRL_GROUP_34_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_ISAM62_MCU2CENTRAL_VBUSM_GASKET_MCU_0_EDC_CTRL_GROUP_35_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_ISAM62_MCU2CENTRAL_VBUSM_GASKET_MCU_0_EDC_CTRL_GROUP_36_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_ISAM62_MCU2CENTRAL_VBUSM_GASKET_MCU_0_EDC_CTRL_GROUP_37_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_ISAM62_MCU2CENTRAL_VBUSM_GASKET_MCU_0_EDC_CTRL_GROUP_38_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_ISAM62_MCU2CENTRAL_VBUSM_GASKET_MCU_0_EDC_CTRL_GROUP_39_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_ISAM62_MCU2CENTRAL_VBUSM_GASKET_MCU_0_EDC_CTRL_GROUP_40_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_ISAM62_MCU2CENTRAL_VBUSM_GASKET_MCU_0_EDC_CTRL_GROUP_41_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_ISAM62_MCU2CENTRAL_VBUSM_GASKET_MCU_0_EDC_CTRL_GROUP_42_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_ISAM62_MCU2CENTRAL_VBUSM_GASKET_MCU_0_EDC_CTRL_GROUP_43_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_ISAM62_MCU2CENTRAL_VBUSM_GASKET_MCU_0_EDC_CTRL_GROUP_44_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_ISAM62_MCU2CENTRAL_VBUSM_GASKET_MCU_0_EDC_CTRL_GROUP_45_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_ISAM62_MCU2CENTRAL_VBUSM_GASKET_MCU_0_EDC_CTRL_GROUP_46_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_ISAM62_MCU2CENTRAL_VBUSM_GASKET_MCU_0_EDC_CTRL_GROUP_47_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_ISAM62_MCU2CENTRAL_VBUSM_GASKET_MCU_0_EDC_CTRL_GROUP_48_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_ISAM62_MCU2CENTRAL_VBUSM_GASKET_MCU_0_EDC_CTRL_GROUP_49_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_ISAM62_MCU2CENTRAL_VBUSM_GASKET_MCU_0_EDC_CTRL_GROUP_50_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_ISAM62_MCU2CENTRAL_VBUSM_GASKET_MCU_0_EDC_CTRL_GROUP_51_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_ISAM62_MCU2CENTRAL_VBUSM_GASKET_MCU_0_EDC_CTRL_GROUP_52_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_ISAM62_MCU2CENTRAL_VBUSM_GASKET_MCU_0_EDC_CTRL_GROUP_53_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_ISAM62_MCU2CENTRAL_VBUSM_GASKET_MCU_0_EDC_CTRL_GROUP_54_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_ISAM62_MCU2CENTRAL_VBUSM_GASKET_MCU_0_EDC_CTRL_GROUP_55_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_ISAM62_MCU2CENTRAL_VBUSM_GASKET_MCU_0_EDC_CTRL_GROUP_56_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_ISAM62_MCU2CENTRAL_VBUSM_GASKET_MCU_0_EDC_CTRL_GROUP_57_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_ISAM62_MCU2CENTRAL_VBUSM_GASKET_MCU_0_EDC_CTRL_GROUP_58_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_ISAM62_MCU2CENTRAL_VBUSM_GASKET_MCU_0_EDC_CTRL_GROUP_59_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_ISAM62_MCU2CENTRAL_VBUSM_GASKET_MCU_0_EDC_CTRL_GROUP_60_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_ISAM62_MCU2CENTRAL_VBUSM_GASKET_MCU_0_EDC_CTRL_GROUP_61_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_ISAM62_MCU2CENTRAL_VBUSM_GASKET_MCU_0_EDC_CTRL_GROUP_62_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_ISAM62_MCU2CENTRAL_VBUSM_GASKET_MCU_0_EDC_CTRL_GROUP_63_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_ISAM62_MCU2CENTRAL_VBUSM_GASKET_MCU_0_EDC_CTRL_GROUP_64_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_ISAM62_MCU2CENTRAL_VBUSM_GASKET_MCU_0_EDC_CTRL_GROUP_65_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_ISAM62_MCU2CENTRAL_VBUSM_GASKET_MCU_0_EDC_CTRL_GROUP_66_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_ISAM62_MCU2CENTRAL_VBUSM_GASKET_MCU_0_EDC_CTRL_GROUP_67_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_ISAM62_MCU2CENTRAL_VBUSM_GASKET_MCU_0_EDC_CTRL_GROUP_68_WIDTH },
};
 
static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_ISAM62_MCU2DM_VBUSM_GASKET_MCU_1_CFG_P2P_BRIDGE_ISAM62_MCU2DM_VBUSM_GASKET_MCU_1_CFG_BRIDGE_BUSECC_groupEntries[SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_ISAM62_MCU2DM_VBUSM_GASKET_MCU_1_CFG_P2P_BRIDGE_ISAM62_MCU2DM_VBUSM_GASKET_MCU_1_CFG_BRIDGE_BUSECC_MAX_NUM_CHECKERS] =
{
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_ISAM62_MCU2DM_VBUSM_GASKET_MCU_1_CFG_P2P_BRIDGE_ISAM62_MCU2DM_VBUSM_GASKET_MCU_1_CFG_BRIDGE_BUSECC_GROUP_0_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_ISAM62_MCU2DM_VBUSM_GASKET_MCU_1_CFG_P2P_BRIDGE_ISAM62_MCU2DM_VBUSM_GASKET_MCU_1_CFG_BRIDGE_BUSECC_GROUP_1_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_ISAM62_MCU2DM_VBUSM_GASKET_MCU_1_CFG_P2P_BRIDGE_ISAM62_MCU2DM_VBUSM_GASKET_MCU_1_CFG_BRIDGE_BUSECC_GROUP_2_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_ISAM62_MCU2DM_VBUSM_GASKET_MCU_1_CFG_P2P_BRIDGE_ISAM62_MCU2DM_VBUSM_GASKET_MCU_1_CFG_BRIDGE_BUSECC_GROUP_3_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_ISAM62_MCU2DM_VBUSM_GASKET_MCU_1_CFG_P2P_BRIDGE_ISAM62_MCU2DM_VBUSM_GASKET_MCU_1_CFG_BRIDGE_BUSECC_GROUP_4_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_ISAM62_MCU2DM_VBUSM_GASKET_MCU_1_CFG_P2P_BRIDGE_ISAM62_MCU2DM_VBUSM_GASKET_MCU_1_CFG_BRIDGE_BUSECC_GROUP_5_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_ISAM62_MCU2DM_VBUSM_GASKET_MCU_1_CFG_P2P_BRIDGE_ISAM62_MCU2DM_VBUSM_GASKET_MCU_1_CFG_BRIDGE_BUSECC_GROUP_6_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_ISAM62_MCU2DM_VBUSM_GASKET_MCU_1_CFG_P2P_BRIDGE_ISAM62_MCU2DM_VBUSM_GASKET_MCU_1_CFG_BRIDGE_BUSECC_GROUP_7_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_ISAM62_MCU2DM_VBUSM_GASKET_MCU_1_CFG_P2P_BRIDGE_ISAM62_MCU2DM_VBUSM_GASKET_MCU_1_CFG_BRIDGE_BUSECC_GROUP_8_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_ISAM62_MCU2DM_VBUSM_GASKET_MCU_1_CFG_P2P_BRIDGE_ISAM62_MCU2DM_VBUSM_GASKET_MCU_1_CFG_BRIDGE_BUSECC_GROUP_9_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_ISAM62_MCU2DM_VBUSM_GASKET_MCU_1_CFG_P2P_BRIDGE_ISAM62_MCU2DM_VBUSM_GASKET_MCU_1_CFG_BRIDGE_BUSECC_GROUP_10_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_ISAM62_MCU2DM_VBUSM_GASKET_MCU_1_CFG_P2P_BRIDGE_ISAM62_MCU2DM_VBUSM_GASKET_MCU_1_CFG_BRIDGE_BUSECC_GROUP_11_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_ISAM62_MCU2DM_VBUSM_GASKET_MCU_1_CFG_P2P_BRIDGE_ISAM62_MCU2DM_VBUSM_GASKET_MCU_1_CFG_BRIDGE_BUSECC_GROUP_12_WIDTH },
};
 
static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_ISAM62_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_groupEntries[SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_ISAM62_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_MAX_NUM_CHECKERS] =
{
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_ISAM62_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_0_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_ISAM62_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_1_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_ISAM62_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_2_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_ISAM62_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_3_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_ISAM62_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_4_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_ISAM62_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_5_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_ISAM62_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_6_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_ISAM62_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_7_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_ISAM62_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_8_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_ISAM62_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_9_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_ISAM62_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_10_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_ISAM62_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_11_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_ISAM62_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_12_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_ISAM62_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_13_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_ISAM62_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_14_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_ISAM62_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_15_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_ISAM62_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_16_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_ISAM62_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_17_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_ISAM62_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_18_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_ISAM62_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_19_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_ISAM62_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_20_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_ISAM62_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_21_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_ISAM62_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_22_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_ISAM62_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_23_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_ISAM62_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_24_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_ISAM62_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_25_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_ISAM62_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_26_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_ISAM62_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_27_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_ISAM62_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_28_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_ISAM62_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_29_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_ISAM62_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_30_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_ISAM62_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_31_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_ISAM62_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_32_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_ISAM62_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_33_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_ISAM62_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_34_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_ISAM62_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_35_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_ISAM62_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_36_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_ISAM62_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_37_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_ISAM62_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_38_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_ISAM62_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_39_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_ISAM62_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_40_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_ISAM62_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_41_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_ISAM62_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_42_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_ISAM62_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_43_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_ISAM62_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_44_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_ISAM62_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_45_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_ISAM62_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_46_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_ISAM62_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_47_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_ISAM62_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_48_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_ISAM62_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_49_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_ISAM62_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_50_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_ISAM62_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_51_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_ISAM62_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_52_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_ISAM62_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_53_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_ISAM62_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_54_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_ISAM62_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_55_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_ISAM62_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_56_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_ISAM62_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_57_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_ISAM62_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_58_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_ISAM62_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_59_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_ISAM62_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_60_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_ISAM62_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_61_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_ISAM62_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_62_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_ISAM62_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_63_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_ISAM62_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_64_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_ISAM62_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_65_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_ISAM62_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_66_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_ISAM62_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_67_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_ISAM62_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_68_WIDTH },
};
 
static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_ISAM62_MCU_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM62_MCU_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_groupEntries[SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_ISAM62_MCU_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM62_MCU_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_MAX_NUM_CHECKERS] =
{
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_ISAM62_MCU_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM62_MCU_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_GROUP_0_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_ISAM62_MCU_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM62_MCU_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_GROUP_1_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_ISAM62_MCU_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM62_MCU_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_GROUP_2_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_ISAM62_MCU_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM62_MCU_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_GROUP_3_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_ISAM62_MCU_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM62_MCU_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_GROUP_4_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_ISAM62_MCU_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM62_MCU_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_GROUP_5_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_ISAM62_MCU_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM62_MCU_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_GROUP_6_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_ISAM62_MCU_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM62_MCU_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_GROUP_7_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_ISAM62_MCU_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM62_MCU_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_GROUP_8_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_ISAM62_MCU_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM62_MCU_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_GROUP_9_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_ISAM62_MCU_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM62_MCU_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_GROUP_10_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_ISAM62_MCU_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM62_MCU_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_GROUP_11_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_ISAM62_MCU_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM62_MCU_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_GROUP_12_WIDTH },
};
 
static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_groupEntries[SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_MAX_NUM_CHECKERS] =
{
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_0_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_1_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_2_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_3_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_4_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_5_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_6_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_7_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_8_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_9_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_10_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_11_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_12_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_13_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_14_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_15_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_16_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_17_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_18_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_19_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_20_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_21_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_22_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_23_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_24_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_25_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_26_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_27_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_28_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_29_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_30_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_31_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_32_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_33_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_34_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_35_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_36_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_37_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_38_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_39_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_40_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_41_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_42_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_43_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_44_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_45_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_46_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_47_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_48_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_49_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_50_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_51_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_52_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_53_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_54_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_55_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_56_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_57_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_58_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_59_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_60_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_61_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_62_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_63_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_64_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_65_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_66_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_67_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_68_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_69_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_70_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_71_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_72_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_73_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_74_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_75_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_76_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_77_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_78_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_79_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_80_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_81_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_82_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_83_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_84_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_85_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_86_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_87_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_88_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_89_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_90_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_91_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_92_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_93_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_94_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_95_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_96_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_97_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_98_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_99_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_100_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_101_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_102_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_103_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_104_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_105_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_106_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_107_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_108_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_109_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_110_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_111_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_112_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_113_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_114_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_115_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_116_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_117_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_118_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_119_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_120_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_121_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_122_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_123_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_124_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_125_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_126_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_127_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_128_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_129_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_130_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_131_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_132_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_133_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_134_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_135_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_136_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_137_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_138_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_139_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_140_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_141_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_142_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_143_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_144_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_145_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_146_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_147_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_148_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_149_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_150_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_151_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_152_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_153_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_154_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_155_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_156_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_157_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_158_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_159_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_160_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_161_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_162_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_163_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_164_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_165_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_166_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_167_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_168_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_169_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_170_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_171_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_172_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_173_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_174_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_175_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_176_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_177_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_178_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_179_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_180_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_181_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_182_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_183_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_184_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_185_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_186_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_187_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_188_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_189_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_190_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_191_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_192_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_193_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_194_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_195_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_196_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_197_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_198_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_199_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_200_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_201_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_202_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_203_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_204_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_205_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_206_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_207_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_208_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_209_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_210_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_211_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_212_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_213_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_214_WIDTH },
};
 
static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_groupEntries[SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_MAX_NUM_CHECKERS] =
{
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_0_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_1_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_2_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_3_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_4_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_5_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_6_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_7_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_8_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_9_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_10_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_11_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_12_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_13_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_14_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_15_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_16_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_17_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_18_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_19_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_20_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_21_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_22_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_23_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_24_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_25_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_26_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_27_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_28_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_29_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_30_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_31_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_32_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_33_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_34_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_35_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_36_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_37_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_38_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_39_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_40_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_41_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_42_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_43_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_44_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_45_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_46_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_47_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_48_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_49_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_50_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_51_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_52_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_53_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_54_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_55_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_56_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_57_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_58_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_59_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_60_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_61_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_62_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_63_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_64_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_65_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_66_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_67_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_68_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_69_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_70_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_71_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_72_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_73_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_74_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_75_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_76_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_77_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_78_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_79_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_80_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_81_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_82_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_83_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_84_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_85_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_86_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_87_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_88_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_89_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_90_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_91_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_92_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_93_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_94_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_95_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_96_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_97_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_98_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_99_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_100_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_101_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_102_WIDTH },
};
 
static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_groupEntries[SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_MAX_NUM_CHECKERS] =
{
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_0_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_1_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_2_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_3_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_4_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_5_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_6_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_7_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_8_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_9_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_10_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_11_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_12_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_13_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_14_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_15_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_16_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_17_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_18_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_19_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_20_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_21_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_22_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_23_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_24_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_25_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_26_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_27_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_28_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_29_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_30_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_31_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_32_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_33_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_34_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_35_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_36_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_37_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_38_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_39_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_40_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_41_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_42_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_43_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_44_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_45_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_46_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_47_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_48_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_49_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_50_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_51_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_52_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_53_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_54_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_55_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_56_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_57_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_58_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_59_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_60_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_61_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_62_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_63_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_64_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_65_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_66_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_67_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_68_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_69_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_70_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_71_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_72_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_73_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_74_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_75_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_76_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_77_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_78_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_79_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_80_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_81_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_82_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_83_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_84_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_85_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_86_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_87_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_88_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_89_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_90_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_91_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_92_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_93_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_94_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_95_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_96_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_97_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_98_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_99_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_100_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_101_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_102_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_103_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_104_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_105_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_106_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_107_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_108_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_109_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_110_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_111_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_112_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_113_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_114_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_115_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_116_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_117_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_118_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_119_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_120_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_121_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_122_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_123_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_124_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_125_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_126_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_127_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_128_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_129_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_130_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_131_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_132_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_133_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_134_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_135_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_136_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_137_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_138_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_139_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_140_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_141_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_142_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_143_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_144_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_145_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_146_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_147_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_148_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_149_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_150_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_151_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_152_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_153_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_154_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_155_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_156_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_157_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_158_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_159_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_160_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_161_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_162_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_163_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_164_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_165_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_166_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_167_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_168_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_169_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_170_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_171_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_172_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_173_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_174_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_175_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_176_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_177_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_178_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_179_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_180_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_181_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_182_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_183_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_184_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_185_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_186_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_187_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_188_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_189_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_190_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_191_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_192_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_193_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_194_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_195_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_196_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_197_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_198_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_199_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_200_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_201_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_202_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_203_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_204_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_205_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_206_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_207_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_208_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_209_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_210_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_211_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_212_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_213_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_214_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_215_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_216_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_217_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_218_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_219_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_220_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_221_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_222_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_223_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_224_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_225_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_226_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_227_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_228_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_229_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_230_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_231_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_232_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_233_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_234_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_235_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_236_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_237_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_238_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_239_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_240_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_241_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_242_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_243_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_244_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_245_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_246_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_247_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_248_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_249_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_250_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_251_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_252_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_253_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_254_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_255_WIDTH },
};
 
static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_groupEntries[SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_MAX_NUM_CHECKERS] =
{
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_0_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_1_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_2_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_3_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_4_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_5_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_6_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_7_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_8_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_9_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_10_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_11_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_12_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_13_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_14_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_15_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_16_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_17_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_18_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_19_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_20_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_21_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_22_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_23_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_24_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_25_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_26_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_27_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_28_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_29_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_30_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_31_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_32_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_33_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_34_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_35_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_36_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_37_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_38_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_39_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_40_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_41_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_42_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_43_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_44_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_45_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_46_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_47_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_48_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_49_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_50_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_51_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_52_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_53_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_54_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_55_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_56_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_57_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_58_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_59_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_60_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_61_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_62_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_63_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_64_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_65_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_66_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_67_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_68_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_69_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_70_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_71_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_72_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_73_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_74_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_75_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_76_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_77_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_78_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_79_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_80_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_81_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_82_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_83_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_84_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_85_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_86_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_87_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_88_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_89_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_90_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_91_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_92_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_93_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_94_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_95_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_96_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_97_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_98_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_99_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_100_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_101_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_102_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_103_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_104_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_105_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_106_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_107_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_108_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_109_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_110_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_111_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_112_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_113_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_114_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_115_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_116_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_117_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_118_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_119_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_120_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_121_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_122_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_123_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_124_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_125_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_126_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_127_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_128_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_129_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_130_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_131_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_132_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_133_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_134_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_135_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_136_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_137_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_138_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_139_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_140_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_141_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_142_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_143_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_144_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_145_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_146_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_147_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_148_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_149_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_150_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_151_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_152_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_153_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_154_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_155_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_156_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_157_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_158_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_159_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_160_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_161_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_162_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_163_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_164_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_165_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_166_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_167_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_168_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_169_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_170_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_171_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_172_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_173_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_174_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_175_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_176_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_177_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_178_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_179_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_180_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_181_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_182_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_183_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_184_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_185_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_186_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_187_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_188_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_189_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_190_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_191_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_192_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_193_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_194_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_195_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_196_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_197_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_198_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_199_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_200_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_201_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_202_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_203_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_204_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_205_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_206_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_207_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_208_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_209_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_210_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_211_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_212_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_213_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_214_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_215_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_216_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_217_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_218_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_219_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_220_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_221_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_222_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_223_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_224_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_225_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_226_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_227_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_228_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_229_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_230_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_231_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_232_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_233_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_234_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_235_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_236_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_237_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_238_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_239_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_240_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_241_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_242_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_243_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_244_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_245_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_246_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_247_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_248_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_249_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_250_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_251_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_252_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_253_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_254_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_255_WIDTH },
};
 
static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_2_groupEntries[SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_2_MAX_NUM_CHECKERS] =
{
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_2_GROUP_0_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_2_GROUP_1_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_2_GROUP_2_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_2_GROUP_3_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_2_GROUP_4_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_2_GROUP_5_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_2_GROUP_6_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_2_GROUP_7_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_2_GROUP_8_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_2_GROUP_9_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_2_GROUP_10_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_2_GROUP_11_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_2_GROUP_12_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_2_GROUP_13_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_2_GROUP_14_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_2_GROUP_15_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_2_GROUP_16_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_2_GROUP_17_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_2_GROUP_18_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_2_GROUP_19_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_2_GROUP_20_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_2_GROUP_21_WIDTH },
};
 
static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_groupEntries[SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_MAX_NUM_CHECKERS] =
{
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_0_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_1_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_2_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_3_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_4_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_5_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_6_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_7_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_8_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_9_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_10_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_11_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_12_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_13_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_14_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_15_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_16_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_17_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_18_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_19_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_20_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_21_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_22_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_23_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_24_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_25_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_26_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_27_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_28_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_29_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_30_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_31_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_32_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_33_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_34_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_35_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_36_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_37_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_38_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_39_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_40_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_41_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_42_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_43_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_44_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_45_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_46_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_47_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_48_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_49_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_50_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_51_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_52_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_53_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_54_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_55_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_56_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_57_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_58_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_59_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_60_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_61_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_62_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_63_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_64_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_65_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_66_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_67_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_68_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_69_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_70_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_71_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_72_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_73_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_74_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_75_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_76_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_77_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_78_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_79_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_80_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_81_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_82_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_83_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_84_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_85_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_86_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_87_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_88_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_89_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_90_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_91_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_92_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_93_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_94_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_95_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_96_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_97_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_98_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_99_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_100_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_101_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_102_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_103_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_104_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_105_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_106_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_107_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_108_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_109_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_110_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_111_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_112_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_113_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_114_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_115_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_116_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_117_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_118_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_119_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_120_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_121_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_122_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_123_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_124_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_125_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_126_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_127_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_128_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_129_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_130_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_131_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_132_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_133_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_134_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_135_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_136_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_137_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_138_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_139_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_140_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_141_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_142_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_143_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_144_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_145_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_146_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_147_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_148_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_149_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_150_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_151_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_152_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_153_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_154_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_155_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_156_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_157_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_158_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_159_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_160_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_161_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_162_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_163_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_164_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_165_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_166_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_167_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_168_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_169_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_170_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_171_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_172_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_173_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_174_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_175_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_176_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_177_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_178_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_179_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_180_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_181_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_182_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_183_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_184_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_185_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_186_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_187_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_188_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_189_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_190_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_191_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_192_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_193_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_194_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_195_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_196_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_197_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_198_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_199_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_200_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_201_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_202_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_203_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_204_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_205_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_206_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_207_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_208_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_209_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_210_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_211_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_212_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_213_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_214_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_215_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_216_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_217_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_218_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_219_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_220_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_221_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_222_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_223_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_224_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_225_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_226_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_227_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_228_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_229_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_230_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_231_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_232_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_233_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_234_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_235_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_236_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_237_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_238_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_239_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_240_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_241_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_242_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_243_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_244_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_245_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_246_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_247_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_248_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_249_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_250_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_251_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_252_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_253_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_254_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_255_WIDTH },
};
 
static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_groupEntries[SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_MAX_NUM_CHECKERS] =
{
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_0_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_1_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_2_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_3_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_4_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_5_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_6_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_7_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_8_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_9_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_10_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_11_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_12_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_13_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_14_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_15_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_16_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_17_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_18_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_19_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_20_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_21_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_22_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_23_WIDTH },
};
 
static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_P2P_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_BRIDGE_DST_BUSECC_groupEntries[SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_P2P_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS] =
{
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_P2P_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_BRIDGE_DST_BUSECC_GROUP_0_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_P2P_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_BRIDGE_DST_BUSECC_GROUP_1_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_P2P_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_BRIDGE_DST_BUSECC_GROUP_2_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_P2P_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_BRIDGE_DST_BUSECC_GROUP_3_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_P2P_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_BRIDGE_DST_BUSECC_GROUP_4_WIDTH },
};
 
static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_P2P_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_BRIDGE_SRC_BUSECC_groupEntries[SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_P2P_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS] =
{
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_P2P_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_BRIDGE_SRC_BUSECC_GROUP_0_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_P2P_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_BRIDGE_SRC_BUSECC_GROUP_1_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_P2P_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_BRIDGE_SRC_BUSECC_GROUP_2_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_P2P_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_BRIDGE_SRC_BUSECC_GROUP_3_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_P2P_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_BRIDGE_SRC_BUSECC_GROUP_4_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_P2P_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_BRIDGE_SRC_BUSECC_GROUP_5_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_P2P_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_BRIDGE_SRC_BUSECC_GROUP_6_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_P2P_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_BRIDGE_SRC_BUSECC_GROUP_7_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_P2P_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_BRIDGE_SRC_BUSECC_GROUP_8_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_P2P_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_BRIDGE_SRC_BUSECC_GROUP_9_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_P2P_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_BRIDGE_SRC_BUSECC_GROUP_10_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_P2P_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_BRIDGE_SRC_BUSECC_GROUP_11_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_P2P_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_BRIDGE_SRC_BUSECC_GROUP_12_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_P2P_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_BRIDGE_SRC_BUSECC_GROUP_13_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_P2P_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_BRIDGE_SRC_BUSECC_GROUP_14_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_P2P_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_BRIDGE_SRC_BUSECC_GROUP_15_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_P2P_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_BRIDGE_SRC_BUSECC_GROUP_16_WIDTH },
};
 
static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_CBASS_DEFAULT_ERR_AM62_MCU_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_groupEntries[SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_CBASS_DEFAULT_ERR_AM62_MCU_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS] =
{
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_CBASS_DEFAULT_ERR_AM62_MCU_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_CBASS_DEFAULT_ERR_AM62_MCU_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_CBASS_DEFAULT_ERR_AM62_MCU_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_CBASS_DEFAULT_ERR_AM62_MCU_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_CBASS_DEFAULT_ERR_AM62_MCU_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
};
 
static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_CBASS_DEFAULT_MMRS_AM62_MCU_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_groupEntries[SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_CBASS_DEFAULT_MMRS_AM62_MCU_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS] =
{
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_CBASS_DEFAULT_MMRS_AM62_MCU_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_CBASS_DEFAULT_MMRS_AM62_MCU_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_CBASS_DEFAULT_MMRS_AM62_MCU_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_CBASS_DEFAULT_MMRS_AM62_MCU_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_CBASS_DEFAULT_MMRS_AM62_MCU_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_CBASS_DEFAULT_MMRS_AM62_MCU_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_5_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_CBASS_DEFAULT_MMRS_AM62_MCU_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_6_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_CBASS_DEFAULT_MMRS_AM62_MCU_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_7_WIDTH },
};
 
static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_CBASS_INT_DMSC_SCR_AM62_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_groupEntries[SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_CBASS_INT_DMSC_SCR_AM62_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS] =
{
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_CBASS_INT_DMSC_SCR_AM62_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_CBASS_INT_DMSC_SCR_AM62_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_CBASS_INT_DMSC_SCR_AM62_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_CBASS_INT_DMSC_SCR_AM62_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_CBASS_INT_DMSC_SCR_AM62_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_CBASS_INT_DMSC_SCR_AM62_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_5_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_CBASS_INT_DMSC_SCR_AM62_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_6_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_CBASS_INT_DMSC_SCR_AM62_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_7_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_CBASS_INT_DMSC_SCR_AM62_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_8_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_CBASS_INT_DMSC_SCR_AM62_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_9_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_CBASS_INT_DMSC_SCR_AM62_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_10_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_CBASS_INT_DMSC_SCR_AM62_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_11_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_CBASS_INT_DMSC_SCR_AM62_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_12_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_CBASS_INT_DMSC_SCR_AM62_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_13_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_CBASS_INT_DMSC_SCR_AM62_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_14_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_CBASS_INT_DMSC_SCR_AM62_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_15_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_CBASS_INT_DMSC_SCR_AM62_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_16_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_CBASS_INT_DMSC_SCR_AM62_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_17_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_CBASS_INT_DMSC_SCR_AM62_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_18_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_CBASS_INT_DMSC_SCR_AM62_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_19_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_CBASS_INT_DMSC_SCR_AM62_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_20_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_CBASS_INT_DMSC_SCR_AM62_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_21_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_CBASS_INT_DMSC_SCR_AM62_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_22_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_CBASS_INT_DMSC_SCR_AM62_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_23_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_CBASS_INT_DMSC_SCR_AM62_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_24_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_CBASS_INT_DMSC_SCR_AM62_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_25_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_CBASS_INT_DMSC_SCR_AM62_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_26_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_CBASS_INT_DMSC_SCR_AM62_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_27_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_CBASS_INT_DMSC_SCR_AM62_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_28_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_CBASS_INT_DMSC_SCR_AM62_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_29_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_CBASS_INT_DMSC_SCR_AM62_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_30_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_CBASS_INT_DMSC_SCR_AM62_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_31_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_CBASS_INT_DMSC_SCR_AM62_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_32_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_CBASS_INT_DMSC_SCR_AM62_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_33_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_CBASS_INT_DMSC_SCR_AM62_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_34_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_CBASS_INT_DMSC_SCR_AM62_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_35_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_CBASS_INT_DMSC_SCR_AM62_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_36_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_CBASS_INT_DMSC_SCR_AM62_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_37_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_CBASS_INT_DMSC_SCR_AM62_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_38_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_CBASS_INT_DMSC_SCR_AM62_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_39_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_CBASS_INT_DMSC_SCR_AM62_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_40_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_CBASS_INT_DMSC_SCR_AM62_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_41_WIDTH },
};
 
static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_groupEntries[SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_MAX_NUM_CHECKERS] =
{
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_0_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_1_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_2_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_3_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_4_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_5_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_6_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_7_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_8_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_9_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_10_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_11_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_12_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_13_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_14_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_15_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_16_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_17_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_18_WIDTH },
};
 
static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_ERR_SCR_AM62_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_groupEntries[SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_ERR_SCR_AM62_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS] =
{
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_ERR_SCR_AM62_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_ERR_SCR_AM62_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_ERR_SCR_AM62_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_ERR_SCR_AM62_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_ERR_SCR_AM62_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_ERR_SCR_AM62_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_5_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_ERR_SCR_AM62_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_6_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_ERR_SCR_AM62_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_7_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_ERR_SCR_AM62_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_8_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_ERR_SCR_AM62_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_9_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_ERR_SCR_AM62_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_10_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_ERR_SCR_AM62_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_11_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_ERR_SCR_AM62_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_12_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_ERR_SCR_AM62_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_13_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_ERR_SCR_AM62_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_14_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_ERR_SCR_AM62_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_15_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_ERR_SCR_AM62_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_16_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_ERR_SCR_AM62_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_17_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_ERR_SCR_AM62_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_18_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_ERR_SCR_AM62_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_19_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_ERR_SCR_AM62_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_20_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_ERR_SCR_AM62_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_21_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_ERR_SCR_AM62_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_22_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_ERR_SCR_AM62_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_23_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_ERR_SCR_AM62_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_24_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_ERR_SCR_AM62_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_25_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_ERR_SCR_AM62_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_26_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_ERR_SCR_AM62_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_27_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_ERR_SCR_AM62_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_28_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_ERR_SCR_AM62_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_29_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_ERR_SCR_AM62_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_30_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_ERR_SCR_AM62_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_31_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_ERR_SCR_AM62_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_32_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_ERR_SCR_AM62_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_33_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_ERR_SCR_AM62_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_34_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_ERR_SCR_AM62_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_35_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_ERR_SCR_AM62_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_36_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_ERR_SCR_AM62_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_37_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_ERR_SCR_AM62_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_38_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_ERR_SCR_AM62_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_39_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_ERR_SCR_AM62_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_40_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_ERR_SCR_AM62_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_41_WIDTH },
};
 
static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_groupEntries[SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_MAX_NUM_CHECKERS] =
{
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_0_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_1_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_2_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_3_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_4_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_5_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_6_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_7_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_8_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_9_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_10_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_11_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_12_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_13_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_14_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_15_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_16_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_17_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_18_WIDTH },
};
 
static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_EXPORT_AM62_MAIN_CENTRAL_CBASS_TO_AM62_MCU_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62_MAIN_CENTRAL_CBASS_TO_AM62_MCU_CBASS_DATA_L0_BRIDGE_BUSECC_groupEntries[SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_EXPORT_AM62_MAIN_CENTRAL_CBASS_TO_AM62_MCU_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62_MAIN_CENTRAL_CBASS_TO_AM62_MCU_CBASS_DATA_L0_BRIDGE_BUSECC_MAX_NUM_CHECKERS] =
{
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_EXPORT_AM62_MAIN_CENTRAL_CBASS_TO_AM62_MCU_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62_MAIN_CENTRAL_CBASS_TO_AM62_MCU_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_0_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_EXPORT_AM62_MAIN_CENTRAL_CBASS_TO_AM62_MCU_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62_MAIN_CENTRAL_CBASS_TO_AM62_MCU_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_1_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_EXPORT_AM62_MAIN_CENTRAL_CBASS_TO_AM62_MCU_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62_MAIN_CENTRAL_CBASS_TO_AM62_MCU_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_2_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_EXPORT_AM62_MAIN_CENTRAL_CBASS_TO_AM62_MCU_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62_MAIN_CENTRAL_CBASS_TO_AM62_MCU_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_3_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_EXPORT_AM62_MAIN_CENTRAL_CBASS_TO_AM62_MCU_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62_MAIN_CENTRAL_CBASS_TO_AM62_MCU_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_4_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_EXPORT_AM62_MAIN_CENTRAL_CBASS_TO_AM62_MCU_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62_MAIN_CENTRAL_CBASS_TO_AM62_MCU_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_5_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_EXPORT_AM62_MAIN_CENTRAL_CBASS_TO_AM62_MCU_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62_MAIN_CENTRAL_CBASS_TO_AM62_MCU_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_6_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_EXPORT_AM62_MAIN_CENTRAL_CBASS_TO_AM62_MCU_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62_MAIN_CENTRAL_CBASS_TO_AM62_MCU_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_7_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_EXPORT_AM62_MAIN_CENTRAL_CBASS_TO_AM62_MCU_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62_MAIN_CENTRAL_CBASS_TO_AM62_MCU_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_8_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_EXPORT_AM62_MAIN_CENTRAL_CBASS_TO_AM62_MCU_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62_MAIN_CENTRAL_CBASS_TO_AM62_MCU_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_9_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_EXPORT_AM62_MAIN_CENTRAL_CBASS_TO_AM62_MCU_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62_MAIN_CENTRAL_CBASS_TO_AM62_MCU_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_10_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_EXPORT_AM62_MAIN_CENTRAL_CBASS_TO_AM62_MCU_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62_MAIN_CENTRAL_CBASS_TO_AM62_MCU_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_11_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_EXPORT_AM62_MAIN_CENTRAL_CBASS_TO_AM62_MCU_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62_MAIN_CENTRAL_CBASS_TO_AM62_MCU_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_12_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_EXPORT_AM62_MAIN_CENTRAL_CBASS_TO_AM62_MCU_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62_MAIN_CENTRAL_CBASS_TO_AM62_MCU_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_13_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_EXPORT_AM62_MAIN_CENTRAL_CBASS_TO_AM62_MCU_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62_MAIN_CENTRAL_CBASS_TO_AM62_MCU_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_14_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_EXPORT_AM62_MAIN_CENTRAL_CBASS_TO_AM62_MCU_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62_MAIN_CENTRAL_CBASS_TO_AM62_MCU_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_15_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_EXPORT_AM62_MAIN_CENTRAL_CBASS_TO_AM62_MCU_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62_MAIN_CENTRAL_CBASS_TO_AM62_MCU_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_16_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_EXPORT_AM62_MAIN_CENTRAL_CBASS_TO_AM62_MCU_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62_MAIN_CENTRAL_CBASS_TO_AM62_MCU_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_17_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_EXPORT_AM62_MAIN_CENTRAL_CBASS_TO_AM62_MCU_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62_MAIN_CENTRAL_CBASS_TO_AM62_MCU_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_18_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_EXPORT_AM62_MAIN_CENTRAL_CBASS_TO_AM62_MCU_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62_MAIN_CENTRAL_CBASS_TO_AM62_MCU_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_19_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_EXPORT_AM62_MAIN_CENTRAL_CBASS_TO_AM62_MCU_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62_MAIN_CENTRAL_CBASS_TO_AM62_MCU_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_20_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_EXPORT_AM62_MAIN_CENTRAL_CBASS_TO_AM62_MCU_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62_MAIN_CENTRAL_CBASS_TO_AM62_MCU_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_21_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_EXPORT_AM62_MAIN_CENTRAL_CBASS_TO_AM62_MCU_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62_MAIN_CENTRAL_CBASS_TO_AM62_MCU_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_22_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_EXPORT_AM62_MAIN_CENTRAL_CBASS_TO_AM62_MCU_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62_MAIN_CENTRAL_CBASS_TO_AM62_MCU_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_23_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_EXPORT_AM62_MAIN_CENTRAL_CBASS_TO_AM62_MCU_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62_MAIN_CENTRAL_CBASS_TO_AM62_MCU_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_24_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_EXPORT_AM62_MAIN_CENTRAL_CBASS_TO_AM62_MCU_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62_MAIN_CENTRAL_CBASS_TO_AM62_MCU_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_25_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_EXPORT_AM62_MAIN_CENTRAL_CBASS_TO_AM62_MCU_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62_MAIN_CENTRAL_CBASS_TO_AM62_MCU_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_26_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_EXPORT_AM62_MAIN_CENTRAL_CBASS_TO_AM62_MCU_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62_MAIN_CENTRAL_CBASS_TO_AM62_MCU_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_27_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_EXPORT_AM62_MAIN_CENTRAL_CBASS_TO_AM62_MCU_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62_MAIN_CENTRAL_CBASS_TO_AM62_MCU_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_28_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_EXPORT_AM62_MAIN_CENTRAL_CBASS_TO_AM62_MCU_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62_MAIN_CENTRAL_CBASS_TO_AM62_MCU_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_29_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_EXPORT_AM62_MAIN_CENTRAL_CBASS_TO_AM62_MCU_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62_MAIN_CENTRAL_CBASS_TO_AM62_MCU_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_30_WIDTH },
};
 
static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_EXPORT_AM62_MCU_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_P2P_BRIDGE_EXPORT_AM62_MCU_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_DST_BUSECC_groupEntries[SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_EXPORT_AM62_MCU_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_P2P_BRIDGE_EXPORT_AM62_MCU_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS] =
{
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_EXPORT_AM62_MCU_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_P2P_BRIDGE_EXPORT_AM62_MCU_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_DST_BUSECC_GROUP_0_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_EXPORT_AM62_MCU_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_P2P_BRIDGE_EXPORT_AM62_MCU_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_DST_BUSECC_GROUP_1_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_EXPORT_AM62_MCU_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_P2P_BRIDGE_EXPORT_AM62_MCU_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_DST_BUSECC_GROUP_2_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_EXPORT_AM62_MCU_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_P2P_BRIDGE_EXPORT_AM62_MCU_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_DST_BUSECC_GROUP_3_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_EXPORT_AM62_MCU_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_P2P_BRIDGE_EXPORT_AM62_MCU_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_DST_BUSECC_GROUP_4_WIDTH },
};
 
static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_EXPORT_AM62_MCU_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_P2P_BRIDGE_EXPORT_AM62_MCU_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_SRC_BUSECC_groupEntries[SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_EXPORT_AM62_MCU_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_P2P_BRIDGE_EXPORT_AM62_MCU_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS] =
{
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_EXPORT_AM62_MCU_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_P2P_BRIDGE_EXPORT_AM62_MCU_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_SRC_BUSECC_GROUP_0_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_EXPORT_AM62_MCU_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_P2P_BRIDGE_EXPORT_AM62_MCU_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_SRC_BUSECC_GROUP_1_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_EXPORT_AM62_MCU_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_P2P_BRIDGE_EXPORT_AM62_MCU_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_SRC_BUSECC_GROUP_2_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_EXPORT_AM62_MCU_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_P2P_BRIDGE_EXPORT_AM62_MCU_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_SRC_BUSECC_GROUP_3_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_EXPORT_AM62_MCU_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_P2P_BRIDGE_EXPORT_AM62_MCU_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_SRC_BUSECC_GROUP_4_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_EXPORT_AM62_MCU_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_P2P_BRIDGE_EXPORT_AM62_MCU_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_SRC_BUSECC_GROUP_5_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_EXPORT_AM62_MCU_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_P2P_BRIDGE_EXPORT_AM62_MCU_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_SRC_BUSECC_GROUP_6_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_EXPORT_AM62_MCU_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_P2P_BRIDGE_EXPORT_AM62_MCU_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_SRC_BUSECC_GROUP_7_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_EXPORT_AM62_MCU_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_P2P_BRIDGE_EXPORT_AM62_MCU_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_SRC_BUSECC_GROUP_8_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_EXPORT_AM62_MCU_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_P2P_BRIDGE_EXPORT_AM62_MCU_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_SRC_BUSECC_GROUP_9_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_EXPORT_AM62_MCU_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_P2P_BRIDGE_EXPORT_AM62_MCU_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_SRC_BUSECC_GROUP_10_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_EXPORT_AM62_MCU_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_P2P_BRIDGE_EXPORT_AM62_MCU_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_SRC_BUSECC_GROUP_11_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_EXPORT_AM62_MCU_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_P2P_BRIDGE_EXPORT_AM62_MCU_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_SRC_BUSECC_GROUP_12_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_EXPORT_AM62_MCU_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_P2P_BRIDGE_EXPORT_AM62_MCU_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_SRC_BUSECC_GROUP_13_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_EXPORT_AM62_MCU_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_P2P_BRIDGE_EXPORT_AM62_MCU_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_SRC_BUSECC_GROUP_14_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_EXPORT_AM62_MCU_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_P2P_BRIDGE_EXPORT_AM62_MCU_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_SRC_BUSECC_GROUP_15_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_EXPORT_AM62_MCU_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_P2P_BRIDGE_EXPORT_AM62_MCU_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_SRC_BUSECC_GROUP_16_WIDTH },
};
 
static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_SAM62_MCU_ECC_AGGR_EDC_CTRL_groupEntries[SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_SAM62_MCU_ECC_AGGR_EDC_CTRL_MAX_NUM_CHECKERS] =
{
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_SAM62_MCU_ECC_AGGR_EDC_CTRL_GROUP_0_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_SAM62_MCU_ECC_AGGR_EDC_CTRL_GROUP_1_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_SAM62_MCU_ECC_AGGR_EDC_CTRL_GROUP_2_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_SAM62_MCU_ECC_AGGR_EDC_CTRL_GROUP_3_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_SAM62_MCU_ECC_AGGR_EDC_CTRL_GROUP_4_WIDTH },
    {  SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_SAM62_MCU_ECC_AGGR_EDC_CTRL_GROUP_5_WIDTH },
};
 
static const SDL_MemConfig_t SDL_USB1_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_MemEntries[SDL_USB1_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES] =
{
    { SDL_USB1_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_USB2SS_16FFC_USB2SS_CORE_AXI2VBUSM_MST_KSBUS_AXI2VBUSM_R_RDATA_BUFFER_RAM_ID, 0u,
      SDL_USB1_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_USB2SS_16FFC_USB2SS_CORE_AXI2VBUSM_MST_KSBUS_AXI2VBUSM_R_RDATA_BUFFER_RAM_SIZE, 4u,
      SDL_USB1_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_USB2SS_16FFC_USB2SS_CORE_AXI2VBUSM_MST_KSBUS_AXI2VBUSM_R_RDATA_BUFFER_ROW_WIDTH, ((bool)false) },
    { SDL_USB1_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_USB2SS_16FFC_USB2SS_CORE_RAMS_MEM_CTRL_RAM0_RAM_ID, 0u,
      SDL_USB1_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_USB2SS_16FFC_USB2SS_CORE_RAMS_MEM_CTRL_RAM0_RAM_SIZE, 4u,
      SDL_USB1_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_USB2SS_16FFC_USB2SS_CORE_RAMS_MEM_CTRL_RAM0_ROW_WIDTH, ((bool)false) },
};
 
static const SDL_MemConfig_t SDL_USB0_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_MemEntries[SDL_USB0_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES] =
{
    { SDL_USB0_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_USB2SS_16FFC_USB2SS_CORE_AXI2VBUSM_MST_KSBUS_AXI2VBUSM_R_RDATA_BUFFER_RAM_ID, 0u,
      SDL_USB0_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_USB2SS_16FFC_USB2SS_CORE_AXI2VBUSM_MST_KSBUS_AXI2VBUSM_R_RDATA_BUFFER_RAM_SIZE, 4u,
      SDL_USB0_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_USB2SS_16FFC_USB2SS_CORE_AXI2VBUSM_MST_KSBUS_AXI2VBUSM_R_RDATA_BUFFER_ROW_WIDTH, ((bool)false) },
    { SDL_USB0_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_USB2SS_16FFC_USB2SS_CORE_RAMS_MEM_CTRL_RAM0_RAM_ID, 0u,
      SDL_USB0_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_USB2SS_16FFC_USB2SS_CORE_RAMS_MEM_CTRL_RAM0_RAM_SIZE, 4u,
      SDL_USB0_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_USB2SS_16FFC_USB2SS_CORE_RAMS_MEM_CTRL_RAM0_ROW_WIDTH, ((bool)false) },
};
 
static const SDL_GrpChkConfig_t SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_groupEntries[SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_MAX_NUM_CHECKERS] =
{
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_0_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_1_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_2_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_3_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_4_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_5_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_6_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_7_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_8_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_9_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_10_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_11_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_12_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_13_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_14_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_15_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_16_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_17_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_18_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_19_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_20_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_21_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_22_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_23_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_24_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_25_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_26_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_27_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_28_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_29_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_30_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_31_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_32_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_33_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_34_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_35_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_36_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_37_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_38_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_39_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_40_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_41_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_42_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_43_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_44_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_45_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_46_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_47_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_48_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_49_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_50_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_51_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_52_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_53_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_54_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_55_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_56_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_57_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_58_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_59_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_60_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_61_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_62_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_63_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_64_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_65_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_66_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_67_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_68_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_69_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_70_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_71_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_72_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_73_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_74_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_75_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_76_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_77_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_78_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_79_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_80_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_81_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_82_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_83_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_84_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_85_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_86_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_87_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_88_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_89_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_90_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_91_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_92_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_93_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_94_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_95_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_96_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_97_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_98_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_99_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_100_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_101_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_102_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_103_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_104_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_105_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_106_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_107_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_108_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_109_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_110_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_111_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_112_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_113_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_114_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_115_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_116_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_117_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_118_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_119_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_120_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_121_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_122_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_123_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_124_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_125_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_126_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_127_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_128_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_129_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_130_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_131_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_132_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_133_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_134_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_135_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_136_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_137_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_138_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_139_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_140_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_141_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_142_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_143_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_144_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_145_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_146_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_147_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_148_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_149_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_150_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_151_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_152_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_153_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_154_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_155_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_156_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_157_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_158_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_159_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_160_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_161_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_162_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_163_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_164_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_165_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_166_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_167_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_168_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_169_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_170_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_171_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_172_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_173_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_174_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_175_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_176_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_177_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_178_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_179_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_180_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_181_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_182_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_183_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_184_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_185_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_186_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_187_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_188_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_189_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_190_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_191_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_192_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_193_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_194_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_195_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_196_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_197_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_198_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_199_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_200_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_201_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_202_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_203_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_204_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_205_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_206_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_207_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_208_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_209_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_210_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_211_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_212_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_213_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_214_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_215_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_216_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_217_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_218_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_219_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_220_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_221_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_222_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_223_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_224_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_225_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_226_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_227_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_228_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_229_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_230_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_231_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_232_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_233_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_234_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_235_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_236_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_237_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_238_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_239_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_240_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_241_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_242_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_243_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_244_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_245_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_246_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_247_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_248_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_249_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_250_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_251_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_252_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_253_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_254_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_255_WIDTH },
};
 
static const SDL_GrpChkConfig_t SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_groupEntries[SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_MAX_NUM_CHECKERS] =
{
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_0_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_1_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_2_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_3_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_4_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_5_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_6_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_7_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_8_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_9_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_10_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_11_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_12_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_13_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_14_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_15_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_16_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_17_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_18_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_19_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_20_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_21_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_22_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_23_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_24_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_25_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_26_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_27_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_28_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_29_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_30_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_31_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_32_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_33_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_34_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_35_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_36_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_37_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_38_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_39_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_40_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_41_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_42_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_43_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_44_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_45_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_46_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_47_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_48_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_49_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_50_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_51_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_52_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_53_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_54_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_55_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_56_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_57_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_58_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_59_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_60_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_61_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_62_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_63_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_64_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_65_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_66_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_67_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_68_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_69_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_70_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_71_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_72_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_73_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_74_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_75_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_76_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_77_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_78_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_79_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_80_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_81_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_82_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_83_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_84_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_85_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_86_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_87_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_88_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_89_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_90_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_91_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_92_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_93_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_94_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_95_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_96_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_97_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_98_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_99_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_100_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_101_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_102_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_103_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_104_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_105_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_106_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_107_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_108_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_109_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_110_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_111_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_112_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_113_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_114_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_115_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_116_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_117_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_118_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_119_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_120_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_121_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_122_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_123_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_124_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_125_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_126_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_127_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_128_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_129_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_130_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_131_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_132_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_133_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_134_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_135_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_136_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_137_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_138_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_139_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_140_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_141_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_142_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_143_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_144_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_145_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_146_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_147_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_148_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_149_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_150_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_151_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_152_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_153_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_154_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_155_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_156_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_157_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_158_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_159_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_160_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_161_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_162_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_163_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_164_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_165_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_166_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_167_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_168_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_169_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_170_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_171_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_172_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_173_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_174_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_175_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_176_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_177_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_178_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_179_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_180_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_181_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_182_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_183_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_184_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_185_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_186_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_187_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_188_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_189_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_190_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_191_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_192_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_193_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_194_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_195_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_196_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_197_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_198_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_199_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_200_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_201_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_202_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_203_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_204_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_205_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_206_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_207_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_208_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_209_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_210_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_211_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_212_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_213_WIDTH },
};
 
static const SDL_GrpChkConfig_t SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_PLL_MMR_EDC_CTRL_BUSECC_groupEntries[SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_PLL_MMR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS] =
{
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_5_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_6_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_7_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_8_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_9_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_10_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_11_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_12_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_13_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_14_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_15_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_16_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_17_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_18_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_19_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_20_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_21_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_22_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_23_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_24_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_25_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_26_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_27_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_28_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_29_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_30_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_31_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_32_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_33_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_34_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_35_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_36_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_37_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_38_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_39_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_40_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_41_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_42_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_43_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_44_WIDTH },
};
 
static const SDL_GrpChkConfig_t SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_groupEntries[SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_MAX_NUM_CHECKERS] =
{
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_0_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_1_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_2_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_3_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_4_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_5_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_6_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_7_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_8_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_9_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_10_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_11_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_12_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_13_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_14_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_15_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_16_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_17_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_18_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_19_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_20_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_21_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_22_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_23_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_24_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_25_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_26_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_27_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_28_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_29_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_30_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_31_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_32_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_33_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_34_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_35_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_36_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_37_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_38_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_39_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_40_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_41_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_42_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_43_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_44_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_45_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_46_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_47_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_48_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_49_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_50_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_51_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_52_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_53_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_54_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_55_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_56_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_57_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_58_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_59_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_60_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_61_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_62_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_63_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_64_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_65_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_66_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_67_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_68_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_69_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_70_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_71_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_72_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_73_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_74_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_75_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_76_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_77_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_78_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_79_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_80_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_81_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_82_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_83_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_84_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_85_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_86_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_87_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_88_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_89_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_90_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_91_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_92_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_93_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_94_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_95_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_96_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_97_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_98_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_99_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_100_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_101_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_102_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_103_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_104_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_105_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_106_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_107_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_108_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_109_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_110_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_111_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_112_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_113_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_114_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_115_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_116_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_117_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_118_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_119_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_120_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_121_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_122_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_123_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_124_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_125_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_126_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_127_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_128_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_129_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_130_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_131_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_132_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_133_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_134_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_135_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_136_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_137_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_138_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_139_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_140_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_141_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_142_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_143_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_144_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_145_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_146_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_147_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_148_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_149_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_150_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_151_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_152_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_153_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_154_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_155_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_156_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_157_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_158_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_159_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_160_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_161_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_162_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_163_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_164_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_165_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_166_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_167_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_168_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_169_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_170_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_171_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_172_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_173_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_174_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_175_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_176_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_177_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_178_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_179_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_180_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_181_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_182_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_183_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_184_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_185_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_186_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_187_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_188_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_189_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_190_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_191_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_192_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_193_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_194_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_195_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_196_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_197_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_198_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_199_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_200_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_201_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_202_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_203_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_204_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_205_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_206_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_207_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_208_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_209_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_210_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_211_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_212_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_213_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_214_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_215_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_216_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_217_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_218_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_219_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_220_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_221_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_222_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_223_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_224_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_225_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_226_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_227_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_228_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_229_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_230_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_231_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_232_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_233_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_234_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_235_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_236_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_237_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_238_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_239_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_240_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_241_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_242_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_243_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_244_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_245_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_246_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_247_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_248_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_249_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_250_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_251_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_252_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_253_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_254_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_255_WIDTH },
};
 
static const SDL_GrpChkConfig_t SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_groupEntries[SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_MAX_NUM_CHECKERS] =
{
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_0_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_1_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_2_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_3_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_4_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_5_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_6_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_7_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_8_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_9_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_10_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_11_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_12_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_13_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_14_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_15_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_16_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_17_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_18_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_19_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_20_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_21_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_22_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_23_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_24_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_25_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_26_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_27_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_28_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_29_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_30_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_31_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_32_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_33_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_34_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_35_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_36_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_37_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_38_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_39_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_40_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_41_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_42_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_43_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_44_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_45_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_46_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_47_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_48_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_49_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_50_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_51_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_52_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_53_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_54_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_55_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_56_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_57_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_58_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_59_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_60_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_61_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_62_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_63_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_64_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_65_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_66_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_67_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_68_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_69_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_70_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_71_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_72_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_73_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_74_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_75_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_76_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_77_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_78_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_79_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_80_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_81_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_82_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_83_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_84_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_85_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_86_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_87_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_88_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_89_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_90_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_91_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_92_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_93_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_94_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_95_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_96_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_97_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_98_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_99_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_100_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_101_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_102_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_103_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_104_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_105_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_106_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_107_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_108_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_109_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_110_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_111_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_112_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_113_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_114_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_115_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_116_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_117_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_118_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_119_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_120_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_121_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_122_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_123_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_124_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_125_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_126_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_127_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_128_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_129_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_130_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_131_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_132_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_133_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_134_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_135_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_136_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_137_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_138_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_139_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_140_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_141_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_142_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_143_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_144_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_145_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_146_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_147_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_148_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_149_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_150_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_151_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_152_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_153_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_154_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_155_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_156_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_157_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_158_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_159_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_160_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_161_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_162_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_163_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_164_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_165_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_166_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_167_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_168_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_169_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_170_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_171_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_172_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_173_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_174_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_175_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_176_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_177_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_178_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_179_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_180_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_181_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_182_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_183_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_184_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_185_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_186_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_187_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_188_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_189_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_190_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_191_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_192_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_193_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_194_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_195_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_196_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_197_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_198_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_199_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_200_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_201_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_202_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_203_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_204_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_205_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_206_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_207_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_208_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_209_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_210_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_211_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_212_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_213_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_214_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_215_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_216_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_217_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_218_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_219_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_220_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_221_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_222_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_223_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_224_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_225_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_226_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_227_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_228_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_229_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_230_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_231_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_232_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_233_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_234_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_235_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_236_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_237_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_238_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_239_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_240_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_241_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_242_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_243_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_244_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_245_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_246_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_247_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_248_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_249_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_250_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_251_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_252_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_253_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_254_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_255_WIDTH },
};
 
static const SDL_GrpChkConfig_t SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_groupEntries[SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_MAX_NUM_CHECKERS] =
{
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_0_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_1_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_2_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_3_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_4_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_5_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_6_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_7_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_8_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_9_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_10_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_11_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_12_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_13_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_14_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_15_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_16_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_17_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_18_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_19_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_20_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_21_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_22_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_23_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_24_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_25_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_26_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_27_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_28_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_29_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_30_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_31_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_32_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_33_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_34_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_35_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_36_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_37_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_38_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_39_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_40_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_41_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_42_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_43_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_44_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_45_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_46_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_47_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_48_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_49_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_50_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_51_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_52_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_53_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_54_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_55_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_56_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_57_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_58_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_59_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_60_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_61_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_62_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_63_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_64_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_65_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_66_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_67_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_68_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_69_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_70_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_71_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_72_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_73_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_74_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_75_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_76_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_77_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_78_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_79_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_80_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_81_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_82_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_83_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_84_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_85_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_86_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_87_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_88_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_89_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_90_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_91_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_92_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_93_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_94_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_95_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_96_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_97_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_98_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_99_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_100_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_101_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_102_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_103_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_104_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_105_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_106_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_107_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_108_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_109_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_110_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_111_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_112_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_113_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_114_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_115_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_116_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_117_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_118_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_119_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_120_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_121_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_122_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_123_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_124_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_125_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_126_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_127_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_128_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_129_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_130_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_131_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_132_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_133_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_134_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_135_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_136_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_137_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_138_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_139_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_140_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_141_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_142_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_143_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_144_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_145_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_146_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_147_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_148_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_149_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_150_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_151_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_152_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_153_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_154_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_155_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_156_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_157_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_158_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_159_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_160_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_161_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_162_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_163_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_164_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_165_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_166_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_167_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_168_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_169_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_170_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_171_WIDTH },
};
 
static const SDL_GrpChkConfig_t SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_IAM62_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM62_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_BRIDGE_BUSECC_groupEntries[SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_IAM62_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM62_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_BRIDGE_BUSECC_MAX_NUM_CHECKERS] =
{
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_IAM62_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM62_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_BRIDGE_BUSECC_GROUP_0_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_IAM62_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM62_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_BRIDGE_BUSECC_GROUP_1_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_IAM62_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM62_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_BRIDGE_BUSECC_GROUP_2_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_IAM62_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM62_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_BRIDGE_BUSECC_GROUP_3_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_IAM62_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM62_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_BRIDGE_BUSECC_GROUP_4_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_IAM62_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM62_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_BRIDGE_BUSECC_GROUP_5_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_IAM62_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM62_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_BRIDGE_BUSECC_GROUP_6_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_IAM62_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM62_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_BRIDGE_BUSECC_GROUP_7_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_IAM62_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM62_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_BRIDGE_BUSECC_GROUP_8_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_IAM62_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM62_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_BRIDGE_BUSECC_GROUP_9_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_IAM62_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM62_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_BRIDGE_BUSECC_GROUP_10_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_IAM62_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM62_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_BRIDGE_BUSECC_GROUP_11_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_IAM62_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM62_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_BRIDGE_BUSECC_GROUP_12_WIDTH },
};
 
static const SDL_GrpChkConfig_t SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_ISAM62_DM2WS_VBUSM_GASKET_MCU_0_EDC_CTRL_groupEntries[SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_ISAM62_DM2WS_VBUSM_GASKET_MCU_0_EDC_CTRL_MAX_NUM_CHECKERS] =
{
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_ISAM62_DM2WS_VBUSM_GASKET_MCU_0_EDC_CTRL_GROUP_0_WIDTH },
};
 
static const SDL_GrpChkConfig_t SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_ISAM62_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM62_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_BRIDGE_BUSECC_groupEntries[SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_ISAM62_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM62_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_BRIDGE_BUSECC_MAX_NUM_CHECKERS] =
{
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_ISAM62_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM62_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_BRIDGE_BUSECC_GROUP_0_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_ISAM62_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM62_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_BRIDGE_BUSECC_GROUP_1_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_ISAM62_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM62_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_BRIDGE_BUSECC_GROUP_2_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_ISAM62_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM62_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_BRIDGE_BUSECC_GROUP_3_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_ISAM62_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM62_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_BRIDGE_BUSECC_GROUP_4_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_ISAM62_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM62_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_BRIDGE_BUSECC_GROUP_5_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_ISAM62_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM62_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_BRIDGE_BUSECC_GROUP_6_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_ISAM62_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM62_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_BRIDGE_BUSECC_GROUP_7_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_ISAM62_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM62_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_BRIDGE_BUSECC_GROUP_8_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_ISAM62_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM62_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_BRIDGE_BUSECC_GROUP_9_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_ISAM62_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM62_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_BRIDGE_BUSECC_GROUP_10_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_ISAM62_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM62_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_BRIDGE_BUSECC_GROUP_11_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_ISAM62_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM62_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_BRIDGE_BUSECC_GROUP_12_WIDTH },
};
 
static const SDL_GrpChkConfig_t SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_groupEntries[SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_MAX_NUM_CHECKERS] =
{
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_0_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_1_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_2_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_3_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_4_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_5_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_6_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_7_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_8_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_9_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_10_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_11_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_12_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_13_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_14_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_15_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_16_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_17_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_18_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_19_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_20_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_21_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_22_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_23_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_24_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_25_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_26_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_27_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_28_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_29_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_30_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_31_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_32_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_33_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_34_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_35_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_36_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_37_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_38_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_39_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_40_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_41_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_42_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_43_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_44_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_45_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_46_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_47_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_48_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_49_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_50_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_51_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_52_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_53_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_54_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_55_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_56_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_57_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_58_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_59_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_60_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_61_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_62_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_63_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_64_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_65_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_66_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_67_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_68_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_69_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_70_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_71_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_72_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_73_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_74_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_75_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_76_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_77_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_78_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_79_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_80_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_81_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_82_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_83_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_84_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_85_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_86_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_87_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_88_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_89_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_90_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_91_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_92_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_93_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_94_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_95_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_96_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_97_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_98_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_99_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_100_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_101_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_102_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_103_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_104_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_105_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_106_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_107_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_108_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_109_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_110_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_111_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_112_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_113_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_114_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_115_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_116_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_117_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_118_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_119_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_120_WIDTH },
};
 
static const SDL_GrpChkConfig_t SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_0_groupEntries[SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_0_MAX_NUM_CHECKERS] =
{
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_0_GROUP_0_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_0_GROUP_1_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_0_GROUP_2_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_0_GROUP_3_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_0_GROUP_4_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_0_GROUP_5_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_0_GROUP_6_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_0_GROUP_7_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_0_GROUP_8_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_0_GROUP_9_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_0_GROUP_10_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_0_GROUP_11_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_0_GROUP_12_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_0_GROUP_13_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_0_GROUP_14_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_0_GROUP_15_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_0_GROUP_16_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_0_GROUP_17_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_0_GROUP_18_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_0_GROUP_19_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_0_GROUP_20_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_0_GROUP_21_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_0_GROUP_22_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_0_GROUP_23_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_0_GROUP_24_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_0_GROUP_25_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_0_GROUP_26_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_0_GROUP_27_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_0_GROUP_28_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_0_GROUP_29_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_0_GROUP_30_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_0_GROUP_31_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_0_GROUP_32_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_0_GROUP_33_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_0_GROUP_34_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_0_GROUP_35_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_0_GROUP_36_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_0_GROUP_37_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_0_GROUP_38_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_0_GROUP_39_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_0_GROUP_40_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_0_GROUP_41_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_0_GROUP_42_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_0_GROUP_43_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_0_GROUP_44_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_0_GROUP_45_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_0_GROUP_46_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_0_GROUP_47_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_0_GROUP_48_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_0_GROUP_49_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_0_GROUP_50_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_0_GROUP_51_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_0_GROUP_52_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_0_GROUP_53_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_0_GROUP_54_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_0_GROUP_55_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_0_GROUP_56_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_0_GROUP_57_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_0_GROUP_58_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_0_GROUP_59_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_0_GROUP_60_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_0_GROUP_61_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_0_GROUP_62_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_0_GROUP_63_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_0_GROUP_64_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_0_GROUP_65_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_0_GROUP_66_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_0_GROUP_67_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_0_GROUP_68_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_0_GROUP_69_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_0_GROUP_70_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_0_GROUP_71_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_0_GROUP_72_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_0_GROUP_73_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_0_GROUP_74_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_0_GROUP_75_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_0_GROUP_76_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_0_GROUP_77_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_0_GROUP_78_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_0_GROUP_79_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_0_GROUP_80_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_0_GROUP_81_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_0_GROUP_82_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_0_GROUP_83_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_0_GROUP_84_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_0_GROUP_85_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_0_GROUP_86_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_0_GROUP_87_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_0_GROUP_88_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_0_GROUP_89_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_0_GROUP_90_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_0_GROUP_91_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_0_GROUP_92_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_0_GROUP_93_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_0_GROUP_94_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_0_GROUP_95_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_0_GROUP_96_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_0_GROUP_97_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_0_GROUP_98_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_0_GROUP_99_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_0_GROUP_100_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_0_GROUP_101_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_0_GROUP_102_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_0_GROUP_103_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_0_GROUP_104_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_0_GROUP_105_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_0_GROUP_106_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_0_GROUP_107_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_0_GROUP_108_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_0_GROUP_109_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_0_GROUP_110_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_0_GROUP_111_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_0_GROUP_112_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_0_GROUP_113_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_0_GROUP_114_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_0_GROUP_115_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_0_GROUP_116_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_0_GROUP_117_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_0_GROUP_118_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_0_GROUP_119_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_0_GROUP_120_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_0_GROUP_121_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_0_GROUP_122_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_0_GROUP_123_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_0_GROUP_124_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_0_GROUP_125_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_0_GROUP_126_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_0_GROUP_127_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_0_GROUP_128_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_0_GROUP_129_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_0_GROUP_130_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_0_GROUP_131_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_0_GROUP_132_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_0_GROUP_133_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_0_GROUP_134_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_0_GROUP_135_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_0_GROUP_136_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_0_GROUP_137_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_0_GROUP_138_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_0_GROUP_139_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_0_GROUP_140_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_0_GROUP_141_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_0_GROUP_142_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_0_GROUP_143_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_0_GROUP_144_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_0_GROUP_145_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_0_GROUP_146_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_0_GROUP_147_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_0_GROUP_148_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_0_GROUP_149_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_0_GROUP_150_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_0_GROUP_151_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_0_GROUP_152_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_0_GROUP_153_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_0_GROUP_154_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_0_GROUP_155_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_0_GROUP_156_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_0_GROUP_157_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_0_GROUP_158_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_0_GROUP_159_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_0_GROUP_160_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_0_GROUP_161_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_0_GROUP_162_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_0_GROUP_163_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_0_GROUP_164_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_0_GROUP_165_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_0_GROUP_166_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_0_GROUP_167_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_0_GROUP_168_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_0_GROUP_169_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_0_GROUP_170_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_0_GROUP_171_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_0_GROUP_172_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_0_GROUP_173_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_0_GROUP_174_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_0_GROUP_175_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_0_GROUP_176_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_0_GROUP_177_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_0_GROUP_178_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_0_GROUP_179_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_0_GROUP_180_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_0_GROUP_181_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_0_GROUP_182_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_0_GROUP_183_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_0_GROUP_184_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_0_GROUP_185_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_0_GROUP_186_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_0_GROUP_187_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_0_GROUP_188_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_0_GROUP_189_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_0_GROUP_190_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_0_GROUP_191_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_0_GROUP_192_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_0_GROUP_193_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_0_GROUP_194_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_0_GROUP_195_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_0_GROUP_196_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_0_GROUP_197_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_0_GROUP_198_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_0_GROUP_199_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_0_GROUP_200_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_0_GROUP_201_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_0_GROUP_202_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_0_GROUP_203_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_0_GROUP_204_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_0_GROUP_205_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_0_GROUP_206_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_0_GROUP_207_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_0_GROUP_208_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_0_GROUP_209_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_0_GROUP_210_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_0_GROUP_211_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_0_GROUP_212_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_0_GROUP_213_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_0_GROUP_214_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_0_GROUP_215_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_0_GROUP_216_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_0_GROUP_217_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_0_GROUP_218_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_0_GROUP_219_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_0_GROUP_220_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_0_GROUP_221_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_0_GROUP_222_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_0_GROUP_223_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_0_GROUP_224_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_0_GROUP_225_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_0_GROUP_226_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_0_GROUP_227_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_0_GROUP_228_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_0_GROUP_229_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_0_GROUP_230_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_0_GROUP_231_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_0_GROUP_232_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_0_GROUP_233_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_0_GROUP_234_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_0_GROUP_235_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_0_GROUP_236_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_0_GROUP_237_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_0_GROUP_238_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_0_GROUP_239_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_0_GROUP_240_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_0_GROUP_241_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_0_GROUP_242_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_0_GROUP_243_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_0_GROUP_244_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_0_GROUP_245_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_0_GROUP_246_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_0_GROUP_247_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_0_GROUP_248_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_0_GROUP_249_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_0_GROUP_250_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_0_GROUP_251_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_0_GROUP_252_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_0_GROUP_253_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_0_GROUP_254_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_0_GROUP_255_WIDTH },
};
 
static const SDL_GrpChkConfig_t SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_1_groupEntries[SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_1_MAX_NUM_CHECKERS] =
{
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_1_GROUP_0_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_1_GROUP_1_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_1_GROUP_2_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_1_GROUP_3_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_1_GROUP_4_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_1_GROUP_5_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_1_GROUP_6_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_1_GROUP_7_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_1_GROUP_8_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_1_GROUP_9_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_1_GROUP_10_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_1_GROUP_11_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_1_GROUP_12_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_1_GROUP_13_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_1_GROUP_14_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_1_GROUP_15_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_1_GROUP_16_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_1_GROUP_17_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_1_GROUP_18_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_1_GROUP_19_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_1_GROUP_20_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_1_GROUP_21_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_1_GROUP_22_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_1_GROUP_23_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_1_GROUP_24_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_1_GROUP_25_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_1_GROUP_26_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_1_GROUP_27_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_1_GROUP_28_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_1_GROUP_29_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_1_GROUP_30_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_1_GROUP_31_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_1_GROUP_32_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_1_GROUP_33_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_1_GROUP_34_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_1_GROUP_35_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_1_GROUP_36_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_1_GROUP_37_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_1_GROUP_38_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_1_GROUP_39_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_1_GROUP_40_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_1_GROUP_41_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_1_GROUP_42_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_1_GROUP_43_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_1_GROUP_44_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_1_GROUP_45_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_1_GROUP_46_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_1_GROUP_47_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_1_GROUP_48_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_1_GROUP_49_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_1_GROUP_50_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_1_GROUP_51_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_1_GROUP_52_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_1_GROUP_53_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_1_GROUP_54_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_1_GROUP_55_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_1_GROUP_56_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_1_GROUP_57_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_1_GROUP_58_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_1_GROUP_59_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_1_GROUP_60_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_1_GROUP_61_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_1_GROUP_62_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_1_GROUP_63_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_1_GROUP_64_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_1_GROUP_65_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_1_GROUP_66_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_1_GROUP_67_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_1_GROUP_68_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_1_GROUP_69_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_1_GROUP_70_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_1_GROUP_71_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_1_GROUP_72_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_1_GROUP_73_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_1_GROUP_74_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_1_GROUP_75_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_1_GROUP_76_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_1_GROUP_77_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_1_GROUP_78_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_1_GROUP_79_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_1_GROUP_80_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_1_GROUP_81_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_1_GROUP_82_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_1_GROUP_83_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_1_GROUP_84_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_1_GROUP_85_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_1_GROUP_86_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_1_GROUP_87_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_1_GROUP_88_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_1_GROUP_89_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_1_GROUP_90_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_1_GROUP_91_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_1_GROUP_92_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_1_GROUP_93_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_1_GROUP_94_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_1_GROUP_95_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_1_GROUP_96_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_1_GROUP_97_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_1_GROUP_98_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_1_GROUP_99_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_1_GROUP_100_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_1_GROUP_101_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_1_GROUP_102_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_1_GROUP_103_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_1_GROUP_104_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_1_GROUP_105_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_1_GROUP_106_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_1_GROUP_107_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_1_GROUP_108_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_1_GROUP_109_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_1_GROUP_110_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_1_GROUP_111_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_1_GROUP_112_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_1_GROUP_113_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_1_GROUP_114_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_1_GROUP_115_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_1_GROUP_116_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_1_GROUP_117_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_1_GROUP_118_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_1_GROUP_119_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_1_GROUP_120_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_1_GROUP_121_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_1_GROUP_122_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_1_GROUP_123_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_1_GROUP_124_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_1_GROUP_125_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_1_GROUP_126_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_1_GROUP_127_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_1_GROUP_128_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_1_GROUP_129_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_1_GROUP_130_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_1_GROUP_131_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_1_GROUP_132_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_1_GROUP_133_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_1_GROUP_134_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_1_GROUP_135_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_1_GROUP_136_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_1_GROUP_137_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_1_GROUP_138_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_1_GROUP_139_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_1_GROUP_140_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_1_GROUP_141_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_1_GROUP_142_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_1_GROUP_143_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_1_GROUP_144_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_1_GROUP_145_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_1_GROUP_146_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_1_GROUP_147_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_1_GROUP_148_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_1_GROUP_149_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_1_GROUP_150_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_1_GROUP_151_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_1_GROUP_152_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_1_GROUP_153_WIDTH },
};
 
static const SDL_GrpChkConfig_t SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_CBASS_DEFAULT_ERR_AM62_WKUP_SAFE_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_groupEntries[SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_CBASS_DEFAULT_ERR_AM62_WKUP_SAFE_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS] =
{
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_CBASS_DEFAULT_ERR_AM62_WKUP_SAFE_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_CBASS_DEFAULT_ERR_AM62_WKUP_SAFE_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_CBASS_DEFAULT_ERR_AM62_WKUP_SAFE_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_CBASS_DEFAULT_ERR_AM62_WKUP_SAFE_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_CBASS_DEFAULT_ERR_AM62_WKUP_SAFE_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
};
 
static const SDL_GrpChkConfig_t SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_ERR_SCR_AM62_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_groupEntries[SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_ERR_SCR_AM62_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS] =
{
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_ERR_SCR_AM62_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_ERR_SCR_AM62_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_ERR_SCR_AM62_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_ERR_SCR_AM62_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_ERR_SCR_AM62_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_ERR_SCR_AM62_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_5_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_ERR_SCR_AM62_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_6_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_ERR_SCR_AM62_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_7_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_ERR_SCR_AM62_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_8_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_ERR_SCR_AM62_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_9_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_ERR_SCR_AM62_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_10_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_ERR_SCR_AM62_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_11_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_ERR_SCR_AM62_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_12_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_ERR_SCR_AM62_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_13_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_ERR_SCR_AM62_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_14_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_ERR_SCR_AM62_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_15_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_ERR_SCR_AM62_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_16_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_ERR_SCR_AM62_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_17_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_ERR_SCR_AM62_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_18_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_ERR_SCR_AM62_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_19_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_ERR_SCR_AM62_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_20_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_ERR_SCR_AM62_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_21_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_ERR_SCR_AM62_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_22_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_ERR_SCR_AM62_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_23_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_ERR_SCR_AM62_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_24_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_ERR_SCR_AM62_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_25_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_ERR_SCR_AM62_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_26_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_ERR_SCR_AM62_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_27_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_ERR_SCR_AM62_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_28_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_ERR_SCR_AM62_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_29_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_ERR_SCR_AM62_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_30_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_ERR_SCR_AM62_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_31_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_ERR_SCR_AM62_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_32_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_ERR_SCR_AM62_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_33_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_ERR_SCR_AM62_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_34_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_ERR_SCR_AM62_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_35_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_ERR_SCR_AM62_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_36_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_ERR_SCR_AM62_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_37_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_ERR_SCR_AM62_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_38_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_ERR_SCR_AM62_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_39_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_ERR_SCR_AM62_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_40_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_ERR_SCR_AM62_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_41_WIDTH },
};
 
static const SDL_GrpChkConfig_t SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_groupEntries[SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_MAX_NUM_CHECKERS] =
{
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_0_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_1_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_2_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_3_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_4_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_5_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_6_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_7_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_8_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_9_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_10_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_11_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_12_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_13_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_14_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_15_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_16_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_17_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_18_WIDTH },
};
 
static const SDL_GrpChkConfig_t SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_groupEntries[SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_MAX_NUM_CHECKERS] =
{
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_0_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_1_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_2_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_3_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_4_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_5_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_6_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_7_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_8_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_9_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_10_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_11_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_12_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_13_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_14_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_15_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_16_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_17_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_18_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_19_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_20_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_21_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_22_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_23_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_24_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_25_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_26_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_27_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_28_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_29_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_30_WIDTH },
};
 
static const SDL_GrpChkConfig_t SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_SAM62_WKUP_SAFE_ECC_AGGR_EDC_CTRL_groupEntries[SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_SAM62_WKUP_SAFE_ECC_AGGR_EDC_CTRL_MAX_NUM_CHECKERS] =
{
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_SAM62_WKUP_SAFE_ECC_AGGR_EDC_CTRL_GROUP_0_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_SAM62_WKUP_SAFE_ECC_AGGR_EDC_CTRL_GROUP_1_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_SAM62_WKUP_SAFE_ECC_AGGR_EDC_CTRL_GROUP_2_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_SAM62_WKUP_SAFE_ECC_AGGR_EDC_CTRL_GROUP_3_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_SAM62_WKUP_SAFE_ECC_AGGR_EDC_CTRL_GROUP_4_WIDTH },
    {  SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_SAM62_WKUP_SAFE_ECC_AGGR_EDC_CTRL_GROUP_5_WIDTH },
};
 
static const SDL_MemConfig_t SDL_PDMA1_SAM62_PDMA_UART_ECCAGGR_MemEntries[SDL_PDMA1_SAM62_PDMA_UART_ECCAGGR_RAM_IDS_TOTAL_ENTRIES] =
{
    { SDL_PDMA1_SAM62_PDMA_UART_ECCAGGR_SAM62_PDMA_UART_PDMA_CORE_TF0_F0_TPRAM_28X128_SBW_SR_RAM_ID, 0u,
      SDL_PDMA1_SAM62_PDMA_UART_ECCAGGR_SAM62_PDMA_UART_PDMA_CORE_TF0_F0_TPRAM_28X128_SBW_SR_RAM_SIZE, 4u,
      SDL_PDMA1_SAM62_PDMA_UART_ECCAGGR_SAM62_PDMA_UART_PDMA_CORE_TF0_F0_TPRAM_28X128_SBW_SR_ROW_WIDTH, ((bool)false) },
    { SDL_PDMA1_SAM62_PDMA_UART_ECCAGGR_SAM62_PDMA_UART_PDMA_CORE_TF0_F1_TPRAM_28X128_SBW_SR_RAM_ID, 0u,
      SDL_PDMA1_SAM62_PDMA_UART_ECCAGGR_SAM62_PDMA_UART_PDMA_CORE_TF0_F1_TPRAM_28X128_SBW_SR_RAM_SIZE, 4u,
      SDL_PDMA1_SAM62_PDMA_UART_ECCAGGR_SAM62_PDMA_UART_PDMA_CORE_TF0_F1_TPRAM_28X128_SBW_SR_ROW_WIDTH, ((bool)false) },
    { SDL_PDMA1_SAM62_PDMA_UART_ECCAGGR_SAM62_PDMA_UART_PDMA_CORE_RF0_F0_TPRAM_28X144_SBW_SR_RAM_ID, 0u,
      SDL_PDMA1_SAM62_PDMA_UART_ECCAGGR_SAM62_PDMA_UART_PDMA_CORE_RF0_F0_TPRAM_28X144_SBW_SR_RAM_SIZE, 4u,
      SDL_PDMA1_SAM62_PDMA_UART_ECCAGGR_SAM62_PDMA_UART_PDMA_CORE_RF0_F0_TPRAM_28X144_SBW_SR_ROW_WIDTH, ((bool)false) },
    { SDL_PDMA1_SAM62_PDMA_UART_ECCAGGR_SAM62_PDMA_UART_PDMA_CORE_RF0_F1_TPRAM_28X144_SBW_SR_RAM_ID, 0u,
      SDL_PDMA1_SAM62_PDMA_UART_ECCAGGR_SAM62_PDMA_UART_PDMA_CORE_RF0_F1_TPRAM_28X144_SBW_SR_RAM_SIZE, 4u,
      SDL_PDMA1_SAM62_PDMA_UART_ECCAGGR_SAM62_PDMA_UART_PDMA_CORE_RF0_F1_TPRAM_28X144_SBW_SR_ROW_WIDTH, ((bool)false) },
};
 
static const SDL_MemConfig_t SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_MemEntries[SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES] =
{
    { SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_ID, 0x20708000u,
      SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_SIZE, 4u,
      SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_ROW_WIDTH, ((bool)true) },
};
 
static const SDL_GrpChkConfig_t SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_groupEntries[SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_MAX_NUM_CHECKERS] =
{
    {  SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_GROUP_0_WIDTH },
};
 
static const SDL_MemConfig_t SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_MemEntries[SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_RAM_IDS_TOTAL_ENTRIES] =
{
    { SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_IDATA_SPRAM_BANK0_LO_ECC_SVBUS_RAM_ID, 0u,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_IDATA_SPRAM_BANK0_LO_ECC_SVBUS_RAM_SIZE, 4u,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_IDATA_SPRAM_BANK0_LO_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
    { SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_IDATA_SPRAM_BANK0_HI_ECC_SVBUS_RAM_ID, 0u,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_IDATA_SPRAM_BANK0_HI_ECC_SVBUS_RAM_SIZE, 4u,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_IDATA_SPRAM_BANK0_HI_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
    { SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_IDATA_SPRAM_BANK1_LO_ECC_SVBUS_RAM_ID, 0u,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_IDATA_SPRAM_BANK1_LO_ECC_SVBUS_RAM_SIZE, 4u,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_IDATA_SPRAM_BANK1_LO_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
    { SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_IDATA_SPRAM_BANK1_HI_ECC_SVBUS_RAM_ID, 0u,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_IDATA_SPRAM_BANK1_HI_ECC_SVBUS_RAM_SIZE, 4u,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_IDATA_SPRAM_BANK1_HI_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
    { SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_ITAG_SPRAM_RAM0_ECC_SVBUS_RAM_ID, 0u,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_ITAG_SPRAM_RAM0_ECC_SVBUS_RAM_SIZE, 4u,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_ITAG_SPRAM_RAM0_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
    { SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_ITAG_SPRAM_RAM1_ECC_SVBUS_RAM_ID, 0u,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_ITAG_SPRAM_RAM1_ECC_SVBUS_RAM_SIZE, 4u,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_ITAG_SPRAM_RAM1_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
    { SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DDATA_SPRAM_BANK0_ECC_SVBUS_RAM_ID, 0u,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DDATA_SPRAM_BANK0_ECC_SVBUS_RAM_SIZE, 4u,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DDATA_SPRAM_BANK0_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
    { SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DDATA_SPRAM_BANK1_ECC_SVBUS_RAM_ID, 0u,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DDATA_SPRAM_BANK1_ECC_SVBUS_RAM_SIZE, 4u,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DDATA_SPRAM_BANK1_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
    { SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DDATA_SPRAM_BANK2_ECC_SVBUS_RAM_ID, 0u,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DDATA_SPRAM_BANK2_ECC_SVBUS_RAM_SIZE, 4u,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DDATA_SPRAM_BANK2_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
    { SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DDATA_SPRAM_BANK3_ECC_SVBUS_RAM_ID, 0u,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DDATA_SPRAM_BANK3_ECC_SVBUS_RAM_SIZE, 4u,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DDATA_SPRAM_BANK3_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
    { SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DDATA_SPRAM_BANK4_ECC_SVBUS_RAM_ID, 0u,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DDATA_SPRAM_BANK4_ECC_SVBUS_RAM_SIZE, 4u,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DDATA_SPRAM_BANK4_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
    { SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DDATA_SPRAM_BANK5_ECC_SVBUS_RAM_ID, 0u,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DDATA_SPRAM_BANK5_ECC_SVBUS_RAM_SIZE, 4u,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DDATA_SPRAM_BANK5_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
    { SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DDATA_SPRAM_BANK6_ECC_SVBUS_RAM_ID, 0u,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DDATA_SPRAM_BANK6_ECC_SVBUS_RAM_SIZE, 4u,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DDATA_SPRAM_BANK6_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
    { SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DDATA_SPRAM_BANK7_ECC_SVBUS_RAM_ID, 0u,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DDATA_SPRAM_BANK7_ECC_SVBUS_RAM_SIZE, 4u,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DDATA_SPRAM_BANK7_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
    { SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DTAG_SPRAM_BANK0_ECC_SVBUS_RAM_ID, 0u,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DTAG_SPRAM_BANK0_ECC_SVBUS_RAM_SIZE, 4u,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DTAG_SPRAM_BANK0_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
    { SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DTAG_SPRAM_BANK1_ECC_SVBUS_RAM_ID, 0u,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DTAG_SPRAM_BANK1_ECC_SVBUS_RAM_SIZE, 4u,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DTAG_SPRAM_BANK1_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
    { SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DTAG_SPRAM_BANK2_ECC_SVBUS_RAM_ID, 0u,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DTAG_SPRAM_BANK2_ECC_SVBUS_RAM_SIZE, 4u,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DTAG_SPRAM_BANK2_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
    { SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DTAG_SPRAM_BANK3_ECC_SVBUS_RAM_ID, 0u,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DTAG_SPRAM_BANK3_ECC_SVBUS_RAM_SIZE, 4u,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DTAG_SPRAM_BANK3_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
    { SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DDIRTY_SPRAM_ECC_SVBUS_RAM_ID, 0u,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DDIRTY_SPRAM_ECC_SVBUS_RAM_SIZE, 4u,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DDIRTY_SPRAM_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
    { SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_TLB_SPRAM_BANK0_ECC_SVBUS_RAM_ID, 0u,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_TLB_SPRAM_BANK0_ECC_SVBUS_RAM_SIZE, 4u,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_TLB_SPRAM_BANK0_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
    { SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_TLB_SPRAM_BANK1_ECC_SVBUS_RAM_ID, 0u,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_TLB_SPRAM_BANK1_ECC_SVBUS_RAM_SIZE, 4u,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_TLB_SPRAM_BANK1_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
    { SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_TLB_SPRAM_BANK2_ECC_SVBUS_RAM_ID, 0u,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_TLB_SPRAM_BANK2_ECC_SVBUS_RAM_SIZE, 4u,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_TLB_SPRAM_BANK2_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
    { SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_TLB_SPRAM_BANK3_ECC_SVBUS_RAM_ID, 0u,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_TLB_SPRAM_BANK3_ECC_SVBUS_RAM_SIZE, 4u,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_TLB_SPRAM_BANK3_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
    { SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY0_ECC_SVBUS_RAM_ID, 0u,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY0_ECC_SVBUS_RAM_SIZE, 4u,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY0_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
    { SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY1_ECC_SVBUS_RAM_ID, 0u,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY1_ECC_SVBUS_RAM_SIZE, 4u,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY1_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
    { SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY2_ECC_SVBUS_RAM_ID, 0u,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY2_ECC_SVBUS_RAM_SIZE, 4u,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY2_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
    { SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY3_ECC_SVBUS_RAM_ID, 0u,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY3_ECC_SVBUS_RAM_SIZE, 4u,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY3_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
};
 
static const SDL_MemConfig_t SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_MemEntries[SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_RAM_IDS_TOTAL_ENTRIES] =
{
    { SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_IDATA_SPRAM_BANK0_LO_ECC_SVBUS_RAM_ID, 0u,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_IDATA_SPRAM_BANK0_LO_ECC_SVBUS_RAM_SIZE, 4u,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_IDATA_SPRAM_BANK0_LO_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
    { SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_IDATA_SPRAM_BANK0_HI_ECC_SVBUS_RAM_ID, 0u,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_IDATA_SPRAM_BANK0_HI_ECC_SVBUS_RAM_SIZE, 4u,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_IDATA_SPRAM_BANK0_HI_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
    { SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_IDATA_SPRAM_BANK1_LO_ECC_SVBUS_RAM_ID, 0u,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_IDATA_SPRAM_BANK1_LO_ECC_SVBUS_RAM_SIZE, 4u,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_IDATA_SPRAM_BANK1_LO_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
    { SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_IDATA_SPRAM_BANK1_HI_ECC_SVBUS_RAM_ID, 0u,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_IDATA_SPRAM_BANK1_HI_ECC_SVBUS_RAM_SIZE, 4u,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_IDATA_SPRAM_BANK1_HI_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
    { SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_ITAG_SPRAM_RAM0_ECC_SVBUS_RAM_ID, 0u,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_ITAG_SPRAM_RAM0_ECC_SVBUS_RAM_SIZE, 4u,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_ITAG_SPRAM_RAM0_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
    { SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_ITAG_SPRAM_RAM1_ECC_SVBUS_RAM_ID, 0u,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_ITAG_SPRAM_RAM1_ECC_SVBUS_RAM_SIZE, 4u,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_ITAG_SPRAM_RAM1_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
    { SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DDATA_SPRAM_BANK0_ECC_SVBUS_RAM_ID, 0u,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DDATA_SPRAM_BANK0_ECC_SVBUS_RAM_SIZE, 4u,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DDATA_SPRAM_BANK0_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
    { SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DDATA_SPRAM_BANK1_ECC_SVBUS_RAM_ID, 0u,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DDATA_SPRAM_BANK1_ECC_SVBUS_RAM_SIZE, 4u,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DDATA_SPRAM_BANK1_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
    { SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DDATA_SPRAM_BANK2_ECC_SVBUS_RAM_ID, 0u,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DDATA_SPRAM_BANK2_ECC_SVBUS_RAM_SIZE, 4u,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DDATA_SPRAM_BANK2_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
    { SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DDATA_SPRAM_BANK3_ECC_SVBUS_RAM_ID, 0u,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DDATA_SPRAM_BANK3_ECC_SVBUS_RAM_SIZE, 4u,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DDATA_SPRAM_BANK3_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
    { SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DDATA_SPRAM_BANK4_ECC_SVBUS_RAM_ID, 0u,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DDATA_SPRAM_BANK4_ECC_SVBUS_RAM_SIZE, 4u,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DDATA_SPRAM_BANK4_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
    { SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DDATA_SPRAM_BANK5_ECC_SVBUS_RAM_ID, 0u,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DDATA_SPRAM_BANK5_ECC_SVBUS_RAM_SIZE, 4u,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DDATA_SPRAM_BANK5_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
    { SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DDATA_SPRAM_BANK6_ECC_SVBUS_RAM_ID, 0u,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DDATA_SPRAM_BANK6_ECC_SVBUS_RAM_SIZE, 4u,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DDATA_SPRAM_BANK6_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
    { SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DDATA_SPRAM_BANK7_ECC_SVBUS_RAM_ID, 0u,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DDATA_SPRAM_BANK7_ECC_SVBUS_RAM_SIZE, 4u,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DDATA_SPRAM_BANK7_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
    { SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DTAG_SPRAM_BANK0_ECC_SVBUS_RAM_ID, 0u,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DTAG_SPRAM_BANK0_ECC_SVBUS_RAM_SIZE, 4u,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DTAG_SPRAM_BANK0_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
    { SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DTAG_SPRAM_BANK1_ECC_SVBUS_RAM_ID, 0u,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DTAG_SPRAM_BANK1_ECC_SVBUS_RAM_SIZE, 4u,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DTAG_SPRAM_BANK1_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
    { SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DTAG_SPRAM_BANK2_ECC_SVBUS_RAM_ID, 0u,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DTAG_SPRAM_BANK2_ECC_SVBUS_RAM_SIZE, 4u,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DTAG_SPRAM_BANK2_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
    { SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DTAG_SPRAM_BANK3_ECC_SVBUS_RAM_ID, 0u,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DTAG_SPRAM_BANK3_ECC_SVBUS_RAM_SIZE, 4u,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DTAG_SPRAM_BANK3_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
    { SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DDIRTY_SPRAM_ECC_SVBUS_RAM_ID, 0u,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DDIRTY_SPRAM_ECC_SVBUS_RAM_SIZE, 4u,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DDIRTY_SPRAM_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
    { SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_TLB_SPRAM_BANK0_ECC_SVBUS_RAM_ID, 0u,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_TLB_SPRAM_BANK0_ECC_SVBUS_RAM_SIZE, 4u,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_TLB_SPRAM_BANK0_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
    { SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_TLB_SPRAM_BANK1_ECC_SVBUS_RAM_ID, 0u,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_TLB_SPRAM_BANK1_ECC_SVBUS_RAM_SIZE, 4u,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_TLB_SPRAM_BANK1_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
    { SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_TLB_SPRAM_BANK2_ECC_SVBUS_RAM_ID, 0u,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_TLB_SPRAM_BANK2_ECC_SVBUS_RAM_SIZE, 4u,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_TLB_SPRAM_BANK2_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
    { SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_TLB_SPRAM_BANK3_ECC_SVBUS_RAM_ID, 0u,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_TLB_SPRAM_BANK3_ECC_SVBUS_RAM_SIZE, 4u,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_TLB_SPRAM_BANK3_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
    { SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY0_ECC_SVBUS_RAM_ID, 0u,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY0_ECC_SVBUS_RAM_SIZE, 4u,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY0_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
    { SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY1_ECC_SVBUS_RAM_ID, 0u,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY1_ECC_SVBUS_RAM_SIZE, 4u,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY1_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
    { SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY2_ECC_SVBUS_RAM_ID, 0u,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY2_ECC_SVBUS_RAM_SIZE, 4u,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY2_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
    { SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY3_ECC_SVBUS_RAM_ID, 0u,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY3_ECC_SVBUS_RAM_SIZE, 4u,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY3_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
};
 
static const SDL_MemConfig_t SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_MemEntries[SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_RAM_IDS_TOTAL_ENTRIES] =
{
    { SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_IDATA_SPRAM_BANK0_LO_ECC_SVBUS_RAM_ID, 0u,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_IDATA_SPRAM_BANK0_LO_ECC_SVBUS_RAM_SIZE, 4u,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_IDATA_SPRAM_BANK0_LO_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
    { SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_IDATA_SPRAM_BANK0_HI_ECC_SVBUS_RAM_ID, 0u,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_IDATA_SPRAM_BANK0_HI_ECC_SVBUS_RAM_SIZE, 4u,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_IDATA_SPRAM_BANK0_HI_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
    { SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_IDATA_SPRAM_BANK1_LO_ECC_SVBUS_RAM_ID, 0u,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_IDATA_SPRAM_BANK1_LO_ECC_SVBUS_RAM_SIZE, 4u,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_IDATA_SPRAM_BANK1_LO_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
    { SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_IDATA_SPRAM_BANK1_HI_ECC_SVBUS_RAM_ID, 0u,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_IDATA_SPRAM_BANK1_HI_ECC_SVBUS_RAM_SIZE, 4u,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_IDATA_SPRAM_BANK1_HI_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
    { SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_ITAG_SPRAM_RAM0_ECC_SVBUS_RAM_ID, 0u,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_ITAG_SPRAM_RAM0_ECC_SVBUS_RAM_SIZE, 4u,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_ITAG_SPRAM_RAM0_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
    { SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_ITAG_SPRAM_RAM1_ECC_SVBUS_RAM_ID, 0u,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_ITAG_SPRAM_RAM1_ECC_SVBUS_RAM_SIZE, 4u,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_ITAG_SPRAM_RAM1_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
    { SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DDATA_SPRAM_BANK0_ECC_SVBUS_RAM_ID, 0u,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DDATA_SPRAM_BANK0_ECC_SVBUS_RAM_SIZE, 4u,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DDATA_SPRAM_BANK0_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
    { SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DDATA_SPRAM_BANK1_ECC_SVBUS_RAM_ID, 0u,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DDATA_SPRAM_BANK1_ECC_SVBUS_RAM_SIZE, 4u,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DDATA_SPRAM_BANK1_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
    { SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DDATA_SPRAM_BANK2_ECC_SVBUS_RAM_ID, 0u,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DDATA_SPRAM_BANK2_ECC_SVBUS_RAM_SIZE, 4u,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DDATA_SPRAM_BANK2_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
    { SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DDATA_SPRAM_BANK3_ECC_SVBUS_RAM_ID, 0u,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DDATA_SPRAM_BANK3_ECC_SVBUS_RAM_SIZE, 4u,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DDATA_SPRAM_BANK3_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
    { SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DDATA_SPRAM_BANK4_ECC_SVBUS_RAM_ID, 0u,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DDATA_SPRAM_BANK4_ECC_SVBUS_RAM_SIZE, 4u,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DDATA_SPRAM_BANK4_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
    { SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DDATA_SPRAM_BANK5_ECC_SVBUS_RAM_ID, 0u,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DDATA_SPRAM_BANK5_ECC_SVBUS_RAM_SIZE, 4u,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DDATA_SPRAM_BANK5_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
    { SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DDATA_SPRAM_BANK6_ECC_SVBUS_RAM_ID, 0u,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DDATA_SPRAM_BANK6_ECC_SVBUS_RAM_SIZE, 4u,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DDATA_SPRAM_BANK6_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
    { SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DDATA_SPRAM_BANK7_ECC_SVBUS_RAM_ID, 0u,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DDATA_SPRAM_BANK7_ECC_SVBUS_RAM_SIZE, 4u,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DDATA_SPRAM_BANK7_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
    { SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DTAG_SPRAM_BANK0_ECC_SVBUS_RAM_ID, 0u,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DTAG_SPRAM_BANK0_ECC_SVBUS_RAM_SIZE, 4u,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DTAG_SPRAM_BANK0_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
    { SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DTAG_SPRAM_BANK1_ECC_SVBUS_RAM_ID, 0u,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DTAG_SPRAM_BANK1_ECC_SVBUS_RAM_SIZE, 4u,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DTAG_SPRAM_BANK1_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
    { SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DTAG_SPRAM_BANK2_ECC_SVBUS_RAM_ID, 0u,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DTAG_SPRAM_BANK2_ECC_SVBUS_RAM_SIZE, 4u,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DTAG_SPRAM_BANK2_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
    { SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DTAG_SPRAM_BANK3_ECC_SVBUS_RAM_ID, 0u,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DTAG_SPRAM_BANK3_ECC_SVBUS_RAM_SIZE, 4u,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DTAG_SPRAM_BANK3_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
    { SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DDIRTY_SPRAM_ECC_SVBUS_RAM_ID, 0u,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DDIRTY_SPRAM_ECC_SVBUS_RAM_SIZE, 4u,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DDIRTY_SPRAM_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
    { SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_TLB_SPRAM_BANK0_ECC_SVBUS_RAM_ID, 0u,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_TLB_SPRAM_BANK0_ECC_SVBUS_RAM_SIZE, 4u,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_TLB_SPRAM_BANK0_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
    { SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_TLB_SPRAM_BANK1_ECC_SVBUS_RAM_ID, 0u,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_TLB_SPRAM_BANK1_ECC_SVBUS_RAM_SIZE, 4u,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_TLB_SPRAM_BANK1_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
    { SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_TLB_SPRAM_BANK2_ECC_SVBUS_RAM_ID, 0u,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_TLB_SPRAM_BANK2_ECC_SVBUS_RAM_SIZE, 4u,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_TLB_SPRAM_BANK2_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
    { SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_TLB_SPRAM_BANK3_ECC_SVBUS_RAM_ID, 0u,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_TLB_SPRAM_BANK3_ECC_SVBUS_RAM_SIZE, 4u,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_TLB_SPRAM_BANK3_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
    { SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY0_ECC_SVBUS_RAM_ID, 0u,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY0_ECC_SVBUS_RAM_SIZE, 4u,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY0_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
    { SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY1_ECC_SVBUS_RAM_ID, 0u,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY1_ECC_SVBUS_RAM_SIZE, 4u,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY1_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
    { SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY2_ECC_SVBUS_RAM_ID, 0u,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY2_ECC_SVBUS_RAM_SIZE, 4u,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY2_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
    { SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY3_ECC_SVBUS_RAM_ID, 0u,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY3_ECC_SVBUS_RAM_SIZE, 4u,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY3_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
};
 
static const SDL_MemConfig_t SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_MemEntries[SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_RAM_IDS_TOTAL_ENTRIES] =
{
    { SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_IDATA_SPRAM_BANK0_LO_ECC_SVBUS_RAM_ID, 0u,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_IDATA_SPRAM_BANK0_LO_ECC_SVBUS_RAM_SIZE, 4u,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_IDATA_SPRAM_BANK0_LO_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
    { SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_IDATA_SPRAM_BANK0_HI_ECC_SVBUS_RAM_ID, 0u,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_IDATA_SPRAM_BANK0_HI_ECC_SVBUS_RAM_SIZE, 4u,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_IDATA_SPRAM_BANK0_HI_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
    { SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_IDATA_SPRAM_BANK1_LO_ECC_SVBUS_RAM_ID, 0u,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_IDATA_SPRAM_BANK1_LO_ECC_SVBUS_RAM_SIZE, 4u,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_IDATA_SPRAM_BANK1_LO_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
    { SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_IDATA_SPRAM_BANK1_HI_ECC_SVBUS_RAM_ID, 0u,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_IDATA_SPRAM_BANK1_HI_ECC_SVBUS_RAM_SIZE, 4u,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_IDATA_SPRAM_BANK1_HI_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
    { SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_ITAG_SPRAM_RAM0_ECC_SVBUS_RAM_ID, 0u,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_ITAG_SPRAM_RAM0_ECC_SVBUS_RAM_SIZE, 4u,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_ITAG_SPRAM_RAM0_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
    { SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_ITAG_SPRAM_RAM1_ECC_SVBUS_RAM_ID, 0u,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_ITAG_SPRAM_RAM1_ECC_SVBUS_RAM_SIZE, 4u,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_ITAG_SPRAM_RAM1_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
    { SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DDATA_SPRAM_BANK0_ECC_SVBUS_RAM_ID, 0u,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DDATA_SPRAM_BANK0_ECC_SVBUS_RAM_SIZE, 4u,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DDATA_SPRAM_BANK0_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
    { SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DDATA_SPRAM_BANK1_ECC_SVBUS_RAM_ID, 0u,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DDATA_SPRAM_BANK1_ECC_SVBUS_RAM_SIZE, 4u,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DDATA_SPRAM_BANK1_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
    { SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DDATA_SPRAM_BANK2_ECC_SVBUS_RAM_ID, 0u,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DDATA_SPRAM_BANK2_ECC_SVBUS_RAM_SIZE, 4u,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DDATA_SPRAM_BANK2_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
    { SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DDATA_SPRAM_BANK3_ECC_SVBUS_RAM_ID, 0u,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DDATA_SPRAM_BANK3_ECC_SVBUS_RAM_SIZE, 4u,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DDATA_SPRAM_BANK3_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
    { SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DDATA_SPRAM_BANK4_ECC_SVBUS_RAM_ID, 0u,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DDATA_SPRAM_BANK4_ECC_SVBUS_RAM_SIZE, 4u,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DDATA_SPRAM_BANK4_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
    { SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DDATA_SPRAM_BANK5_ECC_SVBUS_RAM_ID, 0u,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DDATA_SPRAM_BANK5_ECC_SVBUS_RAM_SIZE, 4u,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DDATA_SPRAM_BANK5_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
    { SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DDATA_SPRAM_BANK6_ECC_SVBUS_RAM_ID, 0u,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DDATA_SPRAM_BANK6_ECC_SVBUS_RAM_SIZE, 4u,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DDATA_SPRAM_BANK6_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
    { SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DDATA_SPRAM_BANK7_ECC_SVBUS_RAM_ID, 0u,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DDATA_SPRAM_BANK7_ECC_SVBUS_RAM_SIZE, 4u,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DDATA_SPRAM_BANK7_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
    { SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DTAG_SPRAM_BANK0_ECC_SVBUS_RAM_ID, 0u,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DTAG_SPRAM_BANK0_ECC_SVBUS_RAM_SIZE, 4u,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DTAG_SPRAM_BANK0_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
    { SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DTAG_SPRAM_BANK1_ECC_SVBUS_RAM_ID, 0u,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DTAG_SPRAM_BANK1_ECC_SVBUS_RAM_SIZE, 4u,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DTAG_SPRAM_BANK1_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
    { SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DTAG_SPRAM_BANK2_ECC_SVBUS_RAM_ID, 0u,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DTAG_SPRAM_BANK2_ECC_SVBUS_RAM_SIZE, 4u,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DTAG_SPRAM_BANK2_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
    { SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DTAG_SPRAM_BANK3_ECC_SVBUS_RAM_ID, 0u,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DTAG_SPRAM_BANK3_ECC_SVBUS_RAM_SIZE, 4u,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DTAG_SPRAM_BANK3_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
    { SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DDIRTY_SPRAM_ECC_SVBUS_RAM_ID, 0u,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DDIRTY_SPRAM_ECC_SVBUS_RAM_SIZE, 4u,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DDIRTY_SPRAM_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
    { SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_TLB_SPRAM_BANK0_ECC_SVBUS_RAM_ID, 0u,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_TLB_SPRAM_BANK0_ECC_SVBUS_RAM_SIZE, 4u,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_TLB_SPRAM_BANK0_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
    { SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_TLB_SPRAM_BANK1_ECC_SVBUS_RAM_ID, 0u,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_TLB_SPRAM_BANK1_ECC_SVBUS_RAM_SIZE, 4u,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_TLB_SPRAM_BANK1_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
    { SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_TLB_SPRAM_BANK2_ECC_SVBUS_RAM_ID, 0u,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_TLB_SPRAM_BANK2_ECC_SVBUS_RAM_SIZE, 4u,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_TLB_SPRAM_BANK2_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
    { SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_TLB_SPRAM_BANK3_ECC_SVBUS_RAM_ID, 0u,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_TLB_SPRAM_BANK3_ECC_SVBUS_RAM_SIZE, 4u,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_TLB_SPRAM_BANK3_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
    { SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY0_ECC_SVBUS_RAM_ID, 0u,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY0_ECC_SVBUS_RAM_SIZE, 4u,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY0_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
    { SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY1_ECC_SVBUS_RAM_ID, 0u,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY1_ECC_SVBUS_RAM_SIZE, 4u,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY1_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
    { SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY2_ECC_SVBUS_RAM_ID, 0u,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY2_ECC_SVBUS_RAM_SIZE, 4u,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY2_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
    { SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY3_ECC_SVBUS_RAM_ID, 0u,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY3_ECC_SVBUS_RAM_SIZE, 4u,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY3_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
};
 
static const SDL_MemConfig_t SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_MemEntries[SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_RAM_IDS_TOTAL_ENTRIES] =
{
    { SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY0_ECC_SVBUS_RAM_ID, 0u,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY0_ECC_SVBUS_RAM_SIZE, 4u,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY0_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
    { SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY1_ECC_SVBUS_RAM_ID, 0u,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY1_ECC_SVBUS_RAM_SIZE, 4u,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY1_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
    { SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY2_ECC_SVBUS_RAM_ID, 0u,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY2_ECC_SVBUS_RAM_SIZE, 4u,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY2_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
    { SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY3_ECC_SVBUS_RAM_ID, 0u,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY3_ECC_SVBUS_RAM_SIZE, 4u,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY3_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
    { SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY4_ECC_SVBUS_RAM_ID, 0u,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY4_ECC_SVBUS_RAM_SIZE, 4u,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY4_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
    { SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY5_ECC_SVBUS_RAM_ID, 0u,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY5_ECC_SVBUS_RAM_SIZE, 4u,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY5_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
    { SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY6_ECC_SVBUS_RAM_ID, 0u,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY6_ECC_SVBUS_RAM_SIZE, 4u,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY6_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
    { SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY7_ECC_SVBUS_RAM_ID, 0u,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY7_ECC_SVBUS_RAM_SIZE, 4u,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY7_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
    { SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY8_ECC_SVBUS_RAM_ID, 0u,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY8_ECC_SVBUS_RAM_SIZE, 4u,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY8_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
    { SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY9_ECC_SVBUS_RAM_ID, 0u,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY9_ECC_SVBUS_RAM_SIZE, 4u,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY9_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
    { SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY10_ECC_SVBUS_RAM_ID, 0u,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY10_ECC_SVBUS_RAM_SIZE, 4u,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY10_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
    { SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY11_ECC_SVBUS_RAM_ID, 0u,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY11_ECC_SVBUS_RAM_SIZE, 4u,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY11_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
    { SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY12_ECC_SVBUS_RAM_ID, 0u,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY12_ECC_SVBUS_RAM_SIZE, 4u,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY12_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
    { SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY13_ECC_SVBUS_RAM_ID, 0u,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY13_ECC_SVBUS_RAM_SIZE, 4u,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY13_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
    { SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY14_ECC_SVBUS_RAM_ID, 0u,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY14_ECC_SVBUS_RAM_SIZE, 4u,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY14_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
    { SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY15_ECC_SVBUS_RAM_ID, 0u,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY15_ECC_SVBUS_RAM_SIZE, 4u,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY15_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
    { SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_DATARAM_SPRAM_0_ECC_SVBUS_RAM_ID, 0u,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_DATARAM_SPRAM_0_ECC_SVBUS_RAM_SIZE, 4u,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_DATARAM_SPRAM_0_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
    { SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_DATARAM_SPRAM_1_ECC_SVBUS_RAM_ID, 0u,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_DATARAM_SPRAM_1_ECC_SVBUS_RAM_SIZE, 4u,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_DATARAM_SPRAM_1_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
    { SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_DATARAM_SPRAM_2_ECC_SVBUS_RAM_ID, 0u,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_DATARAM_SPRAM_2_ECC_SVBUS_RAM_SIZE, 4u,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_DATARAM_SPRAM_2_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
    { SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_DATARAM_SPRAM_3_ECC_SVBUS_RAM_ID, 0u,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_DATARAM_SPRAM_3_ECC_SVBUS_RAM_SIZE, 4u,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_DATARAM_SPRAM_3_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
    { SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_DATARAM_SPRAM_4_ECC_SVBUS_RAM_ID, 0u,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_DATARAM_SPRAM_4_ECC_SVBUS_RAM_SIZE, 4u,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_DATARAM_SPRAM_4_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
    { SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_DATARAM_SPRAM_5_ECC_SVBUS_RAM_ID, 0u,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_DATARAM_SPRAM_5_ECC_SVBUS_RAM_SIZE, 4u,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_DATARAM_SPRAM_5_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
    { SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_DATARAM_SPRAM_6_ECC_SVBUS_RAM_ID, 0u,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_DATARAM_SPRAM_6_ECC_SVBUS_RAM_SIZE, 4u,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_DATARAM_SPRAM_6_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
    { SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_DATARAM_SPRAM_7_ECC_SVBUS_RAM_ID, 0u,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_DATARAM_SPRAM_7_ECC_SVBUS_RAM_SIZE, 4u,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_DATARAM_SPRAM_7_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
};
 
#if defined (M4F_CORE)
static const SDL_MemConfig_t SDL_MCU_M4FSS0_BLAZAR_ECC_MemEntries[SDL_MCU_M4FSS0_BLAZAR_ECC_RAM_IDS_TOTAL_ENTRIES] =
{
    { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IIRAM_ECC_RAM_ID, 0u,
      SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IIRAM_ECC_RAM_SIZE, 4u,
      SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IIRAM_ECC_ROW_WIDTH, ((bool)true) },
    { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IDRAM_ECC_RAM_ID, 0x00030000u,
      SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IDRAM_ECC_RAM_SIZE, 4u,
      SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IDRAM_ECC_ROW_WIDTH, ((bool)true) },
};
#endif
#if defined (R5F_CORE)
static const SDL_MemConfig_t SDL_MCU_M4FSS0_BLAZAR_ECC_MemEntries[SDL_MCU_M4FSS0_BLAZAR_ECC_RAM_IDS_TOTAL_ENTRIES] =
{
    { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IIRAM_ECC_RAM_ID, 0u,
      SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IIRAM_ECC_RAM_SIZE, 4u,
      SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IIRAM_ECC_ROW_WIDTH, ((bool)true) },
    { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IDRAM_ECC_RAM_ID, 0x05040000U,
      SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IDRAM_ECC_RAM_SIZE, 4u,
      SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IDRAM_ECC_ROW_WIDTH, ((bool)true) },
};
#endif
 
static const SDL_GrpChkConfig_t SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IIRAM_EDC_CTRL_0_groupEntries[SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IIRAM_EDC_CTRL_0_MAX_NUM_CHECKERS] =
{
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IIRAM_EDC_CTRL_0_GROUP_0_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IIRAM_EDC_CTRL_0_GROUP_1_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IIRAM_EDC_CTRL_0_GROUP_2_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IIRAM_EDC_CTRL_0_GROUP_3_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IIRAM_EDC_CTRL_0_GROUP_4_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IIRAM_EDC_CTRL_0_GROUP_5_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IIRAM_EDC_CTRL_0_GROUP_6_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IIRAM_EDC_CTRL_0_GROUP_7_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IIRAM_EDC_CTRL_0_GROUP_8_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IIRAM_EDC_CTRL_0_GROUP_9_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IIRAM_EDC_CTRL_0_GROUP_10_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IIRAM_EDC_CTRL_0_GROUP_11_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IIRAM_EDC_CTRL_0_GROUP_12_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IIRAM_EDC_CTRL_0_GROUP_13_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IIRAM_EDC_CTRL_0_GROUP_14_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IIRAM_EDC_CTRL_0_GROUP_15_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IIRAM_EDC_CTRL_0_GROUP_16_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IIRAM_EDC_CTRL_0_GROUP_17_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IIRAM_EDC_CTRL_0_GROUP_18_WIDTH },
};
 
static const SDL_GrpChkConfig_t SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IDRAM_EDC_CTRL_0_groupEntries[SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IDRAM_EDC_CTRL_0_MAX_NUM_CHECKERS] =
{
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IDRAM_EDC_CTRL_0_GROUP_0_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IDRAM_EDC_CTRL_0_GROUP_1_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IDRAM_EDC_CTRL_0_GROUP_2_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IDRAM_EDC_CTRL_0_GROUP_3_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IDRAM_EDC_CTRL_0_GROUP_4_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IDRAM_EDC_CTRL_0_GROUP_5_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IDRAM_EDC_CTRL_0_GROUP_6_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IDRAM_EDC_CTRL_0_GROUP_7_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IDRAM_EDC_CTRL_0_GROUP_8_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IDRAM_EDC_CTRL_0_GROUP_9_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IDRAM_EDC_CTRL_0_GROUP_10_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IDRAM_EDC_CTRL_0_GROUP_11_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IDRAM_EDC_CTRL_0_GROUP_12_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IDRAM_EDC_CTRL_0_GROUP_13_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IDRAM_EDC_CTRL_0_GROUP_14_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IDRAM_EDC_CTRL_0_GROUP_15_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IDRAM_EDC_CTRL_0_GROUP_16_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IDRAM_EDC_CTRL_0_GROUP_17_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IDRAM_EDC_CTRL_0_GROUP_18_WIDTH },
};
 
static const SDL_GrpChkConfig_t SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_RAT_EDC_CTRL_0_groupEntries[SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_RAT_EDC_CTRL_0_MAX_NUM_CHECKERS] =
{
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_RAT_EDC_CTRL_0_GROUP_0_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_RAT_EDC_CTRL_0_GROUP_1_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_RAT_EDC_CTRL_0_GROUP_2_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_RAT_EDC_CTRL_0_GROUP_3_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_RAT_EDC_CTRL_0_GROUP_4_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_RAT_EDC_CTRL_0_GROUP_5_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_RAT_EDC_CTRL_0_GROUP_6_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_RAT_EDC_CTRL_0_GROUP_7_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_RAT_EDC_CTRL_0_GROUP_8_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_RAT_EDC_CTRL_0_GROUP_9_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_RAT_EDC_CTRL_0_GROUP_10_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_RAT_EDC_CTRL_0_GROUP_11_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_RAT_EDC_CTRL_0_GROUP_12_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_RAT_EDC_CTRL_0_GROUP_13_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_RAT_EDC_CTRL_0_GROUP_14_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_RAT_EDC_CTRL_0_GROUP_15_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_RAT_EDC_CTRL_0_GROUP_16_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_RAT_EDC_CTRL_0_GROUP_17_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_RAT_EDC_CTRL_0_GROUP_18_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_RAT_EDC_CTRL_0_GROUP_19_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_RAT_EDC_CTRL_0_GROUP_20_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_RAT_EDC_CTRL_0_GROUP_21_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_RAT_EDC_CTRL_0_GROUP_22_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_RAT_EDC_CTRL_0_GROUP_23_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_RAT_EDC_CTRL_0_GROUP_24_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_RAT_EDC_CTRL_0_GROUP_25_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_RAT_EDC_CTRL_0_GROUP_26_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_RAT_EDC_CTRL_0_GROUP_27_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_RAT_EDC_CTRL_0_GROUP_28_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_RAT_EDC_CTRL_0_GROUP_29_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_RAT_EDC_CTRL_0_GROUP_30_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_RAT_EDC_CTRL_0_GROUP_31_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_RAT_EDC_CTRL_0_GROUP_32_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_RAT_EDC_CTRL_0_GROUP_33_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_RAT_EDC_CTRL_0_GROUP_34_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_RAT_EDC_CTRL_0_GROUP_35_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_RAT_EDC_CTRL_0_GROUP_36_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_RAT_EDC_CTRL_0_GROUP_37_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_RAT_EDC_CTRL_0_GROUP_38_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_RAT_EDC_CTRL_0_GROUP_39_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_RAT_EDC_CTRL_0_GROUP_40_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_RAT_EDC_CTRL_0_GROUP_41_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_RAT_EDC_CTRL_0_GROUP_42_WIDTH },
};
 
static const SDL_GrpChkConfig_t SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_VBUSP_S_P2P_BRIDGE_VBUSP_S_BRIDGE_BUSECC_groupEntries[SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_VBUSP_S_P2P_BRIDGE_VBUSP_S_BRIDGE_BUSECC_MAX_NUM_CHECKERS] =
{
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_VBUSP_S_P2P_BRIDGE_VBUSP_S_BRIDGE_BUSECC_GROUP_0_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_VBUSP_S_P2P_BRIDGE_VBUSP_S_BRIDGE_BUSECC_GROUP_1_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_VBUSP_S_P2P_BRIDGE_VBUSP_S_BRIDGE_BUSECC_GROUP_2_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_VBUSP_S_P2P_BRIDGE_VBUSP_S_BRIDGE_BUSECC_GROUP_3_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_VBUSP_S_P2P_BRIDGE_VBUSP_S_BRIDGE_BUSECC_GROUP_4_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_VBUSP_S_P2P_BRIDGE_VBUSP_S_BRIDGE_BUSECC_GROUP_5_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_VBUSP_S_P2P_BRIDGE_VBUSP_S_BRIDGE_BUSECC_GROUP_6_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_VBUSP_S_P2P_BRIDGE_VBUSP_S_BRIDGE_BUSECC_GROUP_7_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_VBUSP_S_P2P_BRIDGE_VBUSP_S_BRIDGE_BUSECC_GROUP_8_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_VBUSP_S_P2P_BRIDGE_VBUSP_S_BRIDGE_BUSECC_GROUP_9_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_VBUSP_S_P2P_BRIDGE_VBUSP_S_BRIDGE_BUSECC_GROUP_10_WIDTH },
};
 
static const SDL_GrpChkConfig_t SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_groupEntries[SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_MAX_NUM_CHECKERS] =
{
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_GROUP_0_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_GROUP_1_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_GROUP_2_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_GROUP_3_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_GROUP_4_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_GROUP_5_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_GROUP_6_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_GROUP_7_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_GROUP_8_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_GROUP_9_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_GROUP_10_WIDTH },
};
 
static const SDL_GrpChkConfig_t SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_groupEntries[SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS] =
{
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_5_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_6_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_7_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_8_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_9_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_10_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_11_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_12_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_13_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_14_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_15_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_16_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_17_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_18_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_19_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_20_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_21_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_22_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_23_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_24_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_25_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_26_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_27_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_28_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_29_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_30_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_31_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_32_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_33_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_34_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_35_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_36_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_37_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_38_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_39_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_40_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_41_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_42_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_43_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_44_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_45_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_46_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_47_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_48_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_49_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_50_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_51_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_52_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_53_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_54_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_55_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_56_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_57_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_58_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_59_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_60_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_61_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_62_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_63_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_64_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_65_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_66_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_67_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_68_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_69_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_70_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_71_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_72_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_73_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_74_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_75_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_76_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_77_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_78_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_79_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_80_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_81_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_82_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_83_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_84_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_85_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_86_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_87_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_88_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_89_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_90_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_91_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_92_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_93_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_94_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_95_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_96_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_97_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_98_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_99_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_100_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_101_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_102_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_103_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_104_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_105_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_106_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_107_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_108_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_109_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_110_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_111_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_112_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_113_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_114_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_115_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_116_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_117_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_118_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_119_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_120_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_121_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_122_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_123_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_124_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_125_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_126_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_127_WIDTH },
};
 
static const SDL_GrpChkConfig_t SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_groupEntries[SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_MAX_NUM_CHECKERS] =
{
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_0_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_1_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_2_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_3_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_4_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_5_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_6_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_7_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_8_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_9_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_10_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_11_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_12_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_13_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_14_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_15_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_16_WIDTH },
};
 
static const SDL_GrpChkConfig_t SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_SYS_SCR_VBUS_CLK_EDC_CTRL_0_groupEntries[SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_SYS_SCR_VBUS_CLK_EDC_CTRL_0_MAX_NUM_CHECKERS] =
{
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_SYS_SCR_VBUS_CLK_EDC_CTRL_0_GROUP_0_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_SYS_SCR_VBUS_CLK_EDC_CTRL_0_GROUP_1_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_SYS_SCR_VBUS_CLK_EDC_CTRL_0_GROUP_2_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_SYS_SCR_VBUS_CLK_EDC_CTRL_0_GROUP_3_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_SYS_SCR_VBUS_CLK_EDC_CTRL_0_GROUP_4_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_SYS_SCR_VBUS_CLK_EDC_CTRL_0_GROUP_5_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_SYS_SCR_VBUS_CLK_EDC_CTRL_0_GROUP_6_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_SYS_SCR_VBUS_CLK_EDC_CTRL_0_GROUP_7_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_SYS_SCR_VBUS_CLK_EDC_CTRL_0_GROUP_8_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_SYS_SCR_VBUS_CLK_EDC_CTRL_0_GROUP_9_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_SYS_SCR_VBUS_CLK_EDC_CTRL_0_GROUP_10_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_SYS_SCR_VBUS_CLK_EDC_CTRL_0_GROUP_11_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_SYS_SCR_VBUS_CLK_EDC_CTRL_0_GROUP_12_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_SYS_SCR_VBUS_CLK_EDC_CTRL_0_GROUP_13_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_SYS_SCR_VBUS_CLK_EDC_CTRL_0_GROUP_14_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_SYS_SCR_VBUS_CLK_EDC_CTRL_0_GROUP_15_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_SYS_SCR_VBUS_CLK_EDC_CTRL_0_GROUP_16_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_SYS_SCR_VBUS_CLK_EDC_CTRL_0_GROUP_17_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_SYS_SCR_VBUS_CLK_EDC_CTRL_0_GROUP_18_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_SYS_SCR_VBUS_CLK_EDC_CTRL_0_GROUP_19_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_SYS_SCR_VBUS_CLK_EDC_CTRL_0_GROUP_20_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_SYS_SCR_VBUS_CLK_EDC_CTRL_0_GROUP_21_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_SYS_SCR_VBUS_CLK_EDC_CTRL_0_GROUP_22_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_SYS_SCR_VBUS_CLK_EDC_CTRL_0_GROUP_23_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_SYS_SCR_VBUS_CLK_EDC_CTRL_0_GROUP_24_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_SYS_SCR_VBUS_CLK_EDC_CTRL_0_GROUP_25_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_SYS_SCR_VBUS_CLK_EDC_CTRL_0_GROUP_26_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_SYS_SCR_VBUS_CLK_EDC_CTRL_0_GROUP_27_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_SYS_SCR_VBUS_CLK_EDC_CTRL_0_GROUP_28_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_SYS_SCR_VBUS_CLK_EDC_CTRL_0_GROUP_29_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_SYS_SCR_VBUS_CLK_EDC_CTRL_0_GROUP_30_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_SYS_SCR_VBUS_CLK_EDC_CTRL_0_GROUP_31_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_SYS_SCR_VBUS_CLK_EDC_CTRL_0_GROUP_32_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_SYS_SCR_VBUS_CLK_EDC_CTRL_0_GROUP_33_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_SYS_SCR_VBUS_CLK_EDC_CTRL_0_GROUP_34_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_SYS_SCR_VBUS_CLK_EDC_CTRL_0_GROUP_35_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_SYS_SCR_VBUS_CLK_EDC_CTRL_0_GROUP_36_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_SYS_SCR_VBUS_CLK_EDC_CTRL_0_GROUP_37_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_SYS_SCR_VBUS_CLK_EDC_CTRL_0_GROUP_38_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_SYS_SCR_VBUS_CLK_EDC_CTRL_0_GROUP_39_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_SYS_SCR_VBUS_CLK_EDC_CTRL_0_GROUP_40_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_SYS_SCR_VBUS_CLK_EDC_CTRL_0_GROUP_41_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_SYS_SCR_VBUS_CLK_EDC_CTRL_0_GROUP_42_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_SYS_SCR_VBUS_CLK_EDC_CTRL_0_GROUP_43_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_SYS_SCR_VBUS_CLK_EDC_CTRL_0_GROUP_44_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_SYS_SCR_VBUS_CLK_EDC_CTRL_0_GROUP_45_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_SYS_SCR_VBUS_CLK_EDC_CTRL_0_GROUP_46_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_SYS_SCR_VBUS_CLK_EDC_CTRL_0_GROUP_47_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_SYS_SCR_VBUS_CLK_EDC_CTRL_0_GROUP_48_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_SYS_SCR_VBUS_CLK_EDC_CTRL_0_GROUP_49_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_SYS_SCR_VBUS_CLK_EDC_CTRL_0_GROUP_50_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_SYS_SCR_VBUS_CLK_EDC_CTRL_0_GROUP_51_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_SYS_SCR_VBUS_CLK_EDC_CTRL_0_GROUP_52_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_SYS_SCR_VBUS_CLK_EDC_CTRL_0_GROUP_53_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_SYS_SCR_VBUS_CLK_EDC_CTRL_0_GROUP_54_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_SYS_SCR_VBUS_CLK_EDC_CTRL_0_GROUP_55_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_SYS_SCR_VBUS_CLK_EDC_CTRL_0_GROUP_56_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_SYS_SCR_VBUS_CLK_EDC_CTRL_0_GROUP_57_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_SYS_SCR_VBUS_CLK_EDC_CTRL_0_GROUP_58_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_SYS_SCR_VBUS_CLK_EDC_CTRL_0_GROUP_59_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_SYS_SCR_VBUS_CLK_EDC_CTRL_0_GROUP_60_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_SYS_SCR_VBUS_CLK_EDC_CTRL_0_GROUP_61_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_SYS_SCR_VBUS_CLK_EDC_CTRL_0_GROUP_62_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_SYS_SCR_VBUS_CLK_EDC_CTRL_0_GROUP_63_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_SYS_SCR_VBUS_CLK_EDC_CTRL_0_GROUP_64_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_SYS_SCR_VBUS_CLK_EDC_CTRL_0_GROUP_65_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_SYS_SCR_VBUS_CLK_EDC_CTRL_0_GROUP_66_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_SYS_SCR_VBUS_CLK_EDC_CTRL_0_GROUP_67_WIDTH },
};
 
static const SDL_GrpChkConfig_t SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IA2V_I_EDC_CTRL_0_groupEntries[SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IA2V_I_EDC_CTRL_0_MAX_NUM_CHECKERS] =
{
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IA2V_I_EDC_CTRL_0_GROUP_0_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IA2V_I_EDC_CTRL_0_GROUP_1_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IA2V_I_EDC_CTRL_0_GROUP_2_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IA2V_I_EDC_CTRL_0_GROUP_3_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IA2V_I_EDC_CTRL_0_GROUP_4_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IA2V_I_EDC_CTRL_0_GROUP_5_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IA2V_I_EDC_CTRL_0_GROUP_6_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IA2V_I_EDC_CTRL_0_GROUP_7_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IA2V_I_EDC_CTRL_0_GROUP_8_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IA2V_I_EDC_CTRL_0_GROUP_9_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IA2V_I_EDC_CTRL_0_GROUP_10_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IA2V_I_EDC_CTRL_0_GROUP_11_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IA2V_I_EDC_CTRL_0_GROUP_12_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IA2V_I_EDC_CTRL_0_GROUP_13_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IA2V_I_EDC_CTRL_0_GROUP_14_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IA2V_I_EDC_CTRL_0_GROUP_15_WIDTH },
};
 
static const SDL_GrpChkConfig_t SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IA2V_D_EDC_CTRL_0_groupEntries[SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IA2V_D_EDC_CTRL_0_MAX_NUM_CHECKERS] =
{
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IA2V_D_EDC_CTRL_0_GROUP_0_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IA2V_D_EDC_CTRL_0_GROUP_1_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IA2V_D_EDC_CTRL_0_GROUP_2_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IA2V_D_EDC_CTRL_0_GROUP_3_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IA2V_D_EDC_CTRL_0_GROUP_4_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IA2V_D_EDC_CTRL_0_GROUP_5_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IA2V_D_EDC_CTRL_0_GROUP_6_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IA2V_D_EDC_CTRL_0_GROUP_7_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IA2V_D_EDC_CTRL_0_GROUP_8_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IA2V_D_EDC_CTRL_0_GROUP_9_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IA2V_D_EDC_CTRL_0_GROUP_10_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IA2V_D_EDC_CTRL_0_GROUP_11_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IA2V_D_EDC_CTRL_0_GROUP_12_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IA2V_D_EDC_CTRL_0_GROUP_13_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IA2V_D_EDC_CTRL_0_GROUP_14_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IA2V_D_EDC_CTRL_0_GROUP_15_WIDTH },
};
 
static const SDL_GrpChkConfig_t SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_SYS_GASKET_EDC_CTRL_0_groupEntries[SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_SYS_GASKET_EDC_CTRL_0_MAX_NUM_CHECKERS] =
{
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_SYS_GASKET_EDC_CTRL_0_GROUP_0_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_SYS_GASKET_EDC_CTRL_0_GROUP_1_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_SYS_GASKET_EDC_CTRL_0_GROUP_2_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_SYS_GASKET_EDC_CTRL_0_GROUP_3_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_SYS_GASKET_EDC_CTRL_0_GROUP_4_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_SYS_GASKET_EDC_CTRL_0_GROUP_5_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_SYS_GASKET_EDC_CTRL_0_GROUP_6_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_SYS_GASKET_EDC_CTRL_0_GROUP_7_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_SYS_GASKET_EDC_CTRL_0_GROUP_8_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_SYS_GASKET_EDC_CTRL_0_GROUP_9_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_SYS_GASKET_EDC_CTRL_0_GROUP_10_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_SYS_GASKET_EDC_CTRL_0_GROUP_11_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_SYS_GASKET_EDC_CTRL_0_GROUP_12_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_SYS_GASKET_EDC_CTRL_0_GROUP_13_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_SYS_GASKET_EDC_CTRL_0_GROUP_14_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_SYS_GASKET_EDC_CTRL_0_GROUP_15_WIDTH },
};
 
static const SDL_GrpChkConfig_t SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_ECC_EDC_CTRL_groupEntries[SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_ECC_EDC_CTRL_MAX_NUM_CHECKERS] =
{
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_ECC_EDC_CTRL_GROUP_0_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_ECC_EDC_CTRL_GROUP_1_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_ECC_EDC_CTRL_GROUP_2_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_ECC_EDC_CTRL_GROUP_3_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_ECC_EDC_CTRL_GROUP_4_WIDTH },
    {  SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_ECC_EDC_CTRL_GROUP_5_WIDTH },
};
 
static const SDL_MemConfig_t SDL_MCU_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_MemEntries[SDL_MCU_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES] =
{
    { SDL_MCU_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_ID, 0x04E00000u,
      SDL_MCU_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_SIZE, 4u,
      SDL_MCU_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_ROW_WIDTH, ((bool)true) },
};
 
static const SDL_GrpChkConfig_t SDL_MCU_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_groupEntries[SDL_MCU_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_MAX_NUM_CHECKERS] =
{
    {  SDL_MCU_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_GROUP_0_WIDTH },
};
 
static const SDL_MemConfig_t SDL_MCU_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_MemEntries[SDL_MCU_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES] =
{
    { SDL_MCU_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_ID, 0x04E10000u,
      SDL_MCU_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_SIZE, 4u,
      SDL_MCU_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_ROW_WIDTH, ((bool)true) },
};
 
static const SDL_GrpChkConfig_t SDL_MCU_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_groupEntries[SDL_MCU_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_MAX_NUM_CHECKERS] =
{
    {  SDL_MCU_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_GROUP_0_WIDTH },
};
static const SDL_RAMIdEntry_t SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_RamIdTable[SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_NUM_RAMS] =
{
    { SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_RAM_ID,
      SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_INJECT_TYPE,
      SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_ECC_TYPE,
      SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_MAX_NUM_CHECKERS,
      SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_groupEntries },
    { SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_RAM_ID,
      SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_INJECT_TYPE,
      SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_ECC_TYPE,
      SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_MAX_NUM_CHECKERS,
      SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_groupEntries },
    { SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_IK3VTM_N16FFC_WKUP_0_VBUSP_P2P_BRIDGE_IK3VTM_N16FFC_WKUP_0_VBUSP_BRIDGE_BUSECC_RAM_ID,
      SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_IK3VTM_N16FFC_WKUP_0_VBUSP_P2P_BRIDGE_IK3VTM_N16FFC_WKUP_0_VBUSP_BRIDGE_BUSECC_INJECT_TYPE,
      SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_IK3VTM_N16FFC_WKUP_0_VBUSP_P2P_BRIDGE_IK3VTM_N16FFC_WKUP_0_VBUSP_BRIDGE_BUSECC_ECC_TYPE,
      SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_IK3VTM_N16FFC_WKUP_0_VBUSP_P2P_BRIDGE_IK3VTM_N16FFC_WKUP_0_VBUSP_BRIDGE_BUSECC_MAX_NUM_CHECKERS,
      SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_IK3VTM_N16FFC_WKUP_0_VBUSP_P2P_BRIDGE_IK3VTM_N16FFC_WKUP_0_VBUSP_BRIDGE_BUSECC_groupEntries },
    { SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_ISAM62_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM62_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_DST_BUSECC_RAM_ID,
      SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_ISAM62_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM62_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_DST_BUSECC_INJECT_TYPE,
      SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_ISAM62_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM62_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_DST_BUSECC_ECC_TYPE,
      SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_ISAM62_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM62_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS,
      SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_ISAM62_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM62_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_DST_BUSECC_groupEntries },
    { SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_ISAM62_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM62_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_SRC_BUSECC_RAM_ID,
      SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_ISAM62_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM62_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_SRC_BUSECC_INJECT_TYPE,
      SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_ISAM62_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM62_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_SRC_BUSECC_ECC_TYPE,
      SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_ISAM62_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM62_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS,
      SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_ISAM62_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM62_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_SRC_BUSECC_groupEntries },
    { SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_RAM_ID,
      SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_INJECT_TYPE,
      SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_ECC_TYPE,
      SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
      SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_groupEntries },
    { SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_RAM_ID,
      SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_INJECT_TYPE,
      SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ECC_TYPE,
      SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
      SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62_WKUP_DM_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries },
    { SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_SAM62_DM_ECC_AGGR_EDC_CTRL_RAM_ID,
      SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_SAM62_DM_ECC_AGGR_EDC_CTRL_INJECT_TYPE,
      SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_SAM62_DM_ECC_AGGR_EDC_CTRL_ECC_TYPE,
      SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_SAM62_DM_ECC_AGGR_EDC_CTRL_MAX_NUM_CHECKERS,
      SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_SAM62_DM_ECC_AGGR_EDC_CTRL_groupEntries },
};
 
static const SDL_RAMIdEntry_t SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_RamIdTable[SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_NUM_RAMS] =
{
    { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_ECCAGGR_EDC_CTRL_RAM_ID,
      SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_ECCAGGR_EDC_CTRL_INJECT_TYPE,
      SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_ECCAGGR_EDC_CTRL_ECC_TYPE,
      SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_ECCAGGR_EDC_CTRL_MAX_NUM_CHECKERS,
      SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_ECCAGGR_EDC_CTRL_groupEntries },
    { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_RAM_ID,
      SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_INJECT_TYPE,
      SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_ECC_TYPE,
      SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_MAX_NUM_CHECKERS,
      SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_groupEntries },
    { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_VBUSP_P2P_BRIDGE_EDC_CTRL_0_RAM_ID,
      SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_VBUSP_P2P_BRIDGE_EDC_CTRL_0_INJECT_TYPE,
      SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_VBUSP_P2P_BRIDGE_EDC_CTRL_0_ECC_TYPE,
      SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_VBUSP_P2P_BRIDGE_EDC_CTRL_0_MAX_NUM_CHECKERS,
      SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_VBUSP_P2P_BRIDGE_EDC_CTRL_0_groupEntries },
    { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_RAM_ID,
      SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_INJECT_TYPE,
      SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_ECC_TYPE,
      SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_MAX_NUM_CHECKERS,
      SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_groupEntries },
};
 
static const SDL_RAMIdEntry_t SDL_PSRAMECC0_PSRAM256X32E_ECC_AGGR_RamIdTable[SDL_PSRAMECC0_PSRAM256X32E_ECC_AGGR_NUM_RAMS] =
{
    { SDL_PSRAMECC0_PSRAM256X32E_ECC_AGGR_PSRAM256X32E_PSRAM0_ECC_RAM_ID,
      SDL_PSRAMECC0_PSRAM256X32E_ECC_AGGR_PSRAM256X32E_PSRAM0_ECC_INJECT_TYPE,
      SDL_PSRAMECC0_PSRAM256X32E_ECC_AGGR_PSRAM256X32E_PSRAM0_ECC_ECC_TYPE,
      0u,
      NULL },
};
 
static const SDL_RAMIdEntry_t SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_RamIdTable[SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_NUM_RAMS] =
{
    { SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_IMAILBOX1_MAIN_0_RAMECC_RAM_ID,
      SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_IMAILBOX1_MAIN_0_RAMECC_INJECT_TYPE,
      SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_IMAILBOX1_MAIN_0_RAMECC_ECC_TYPE,
      0u,
      NULL },
    { SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_RAM_ID,
      SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_INJECT_TYPE,
      SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_ECC_TYPE,
      SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_MAX_NUM_CHECKERS,
      SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_groupEntries },
    { SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_IAM62_MAIN_IPCSS_CBASS_MAIN_0_AM62_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_RAM_ID,
      SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_IAM62_MAIN_IPCSS_CBASS_MAIN_0_AM62_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_INJECT_TYPE,
      SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_IAM62_MAIN_IPCSS_CBASS_MAIN_0_AM62_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_ECC_TYPE,
      SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_IAM62_MAIN_IPCSS_CBASS_MAIN_0_AM62_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_MAX_NUM_CHECKERS,
      SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_IAM62_MAIN_IPCSS_CBASS_MAIN_0_AM62_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_groupEntries },
    { SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_IAM62_MAIN_FW_CBASS_MAIN_0_AM62_MAIN_FW_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_RAM_ID,
      SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_IAM62_MAIN_FW_CBASS_MAIN_0_AM62_MAIN_FW_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_INJECT_TYPE,
      SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_IAM62_MAIN_FW_CBASS_MAIN_0_AM62_MAIN_FW_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_ECC_TYPE,
      SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_IAM62_MAIN_FW_CBASS_MAIN_0_AM62_MAIN_FW_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_MAX_NUM_CHECKERS,
      SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_IAM62_MAIN_FW_CBASS_MAIN_0_AM62_MAIN_FW_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_groupEntries },
    { SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_FW_CBASS_IAM62_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM62_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_RAM_ID,
      SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_FW_CBASS_IAM62_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM62_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_INJECT_TYPE,
      SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_FW_CBASS_IAM62_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM62_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_ECC_TYPE,
      SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_FW_CBASS_IAM62_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM62_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS,
      SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_FW_CBASS_IAM62_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM62_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_groupEntries },
    { SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_FW_CBASS_IAM62_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM62_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_RAM_ID,
      SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_FW_CBASS_IAM62_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM62_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_INJECT_TYPE,
      SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_FW_CBASS_IAM62_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM62_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_ECC_TYPE,
      SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_FW_CBASS_IAM62_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM62_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS,
      SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_FW_CBASS_IAM62_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM62_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_groupEntries },
    { SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_DST_BUSECC_RAM_ID,
      SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_DST_BUSECC_INJECT_TYPE,
      SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_DST_BUSECC_ECC_TYPE,
      SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS,
      SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_DST_BUSECC_groupEntries },
    { SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_SRC_BUSECC_RAM_ID,
      SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_SRC_BUSECC_INJECT_TYPE,
      SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_SRC_BUSECC_ECC_TYPE,
      SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS,
      SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_SRC_BUSECC_groupEntries },
    { SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_HSM_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_HSM_VBUSP_S_BRIDGE_BUSECC_RAM_ID,
      SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_HSM_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_HSM_VBUSP_S_BRIDGE_BUSECC_INJECT_TYPE,
      SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_HSM_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_HSM_VBUSP_S_BRIDGE_BUSECC_ECC_TYPE,
      SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_HSM_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_HSM_VBUSP_S_BRIDGE_BUSECC_MAX_NUM_CHECKERS,
      SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_HSM_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_HSM_VBUSP_S_BRIDGE_BUSECC_groupEntries },
    { SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_TIFS_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_TIFS_VBUSP_S_BRIDGE_BUSECC_RAM_ID,
      SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_TIFS_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_TIFS_VBUSP_S_BRIDGE_BUSECC_INJECT_TYPE,
      SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_TIFS_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_TIFS_VBUSP_S_BRIDGE_BUSECC_ECC_TYPE,
      SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_TIFS_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_TIFS_VBUSP_S_BRIDGE_BUSECC_MAX_NUM_CHECKERS,
      SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_TIFS_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_TIFS_VBUSP_S_BRIDGE_BUSECC_groupEntries },
    { SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_CENTRAL_CBASS_EXPORT_AM62_MAIN_CENTRAL_CBASS_TO_AM62_MCU_CBASS_DATA_L0_P2M_BRIDGE_EXPORT_AM62_MAIN_CENTRAL_CBASS_TO_AM62_MCU_CBASS_DATA_L0_BRIDGE_DST_BUSECC_RAM_ID,
      SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_CENTRAL_CBASS_EXPORT_AM62_MAIN_CENTRAL_CBASS_TO_AM62_MCU_CBASS_DATA_L0_P2M_BRIDGE_EXPORT_AM62_MAIN_CENTRAL_CBASS_TO_AM62_MCU_CBASS_DATA_L0_BRIDGE_DST_BUSECC_INJECT_TYPE,
      SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_CENTRAL_CBASS_EXPORT_AM62_MAIN_CENTRAL_CBASS_TO_AM62_MCU_CBASS_DATA_L0_P2M_BRIDGE_EXPORT_AM62_MAIN_CENTRAL_CBASS_TO_AM62_MCU_CBASS_DATA_L0_BRIDGE_DST_BUSECC_ECC_TYPE,
      SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_CENTRAL_CBASS_EXPORT_AM62_MAIN_CENTRAL_CBASS_TO_AM62_MCU_CBASS_DATA_L0_P2M_BRIDGE_EXPORT_AM62_MAIN_CENTRAL_CBASS_TO_AM62_MCU_CBASS_DATA_L0_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS,
      SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_CENTRAL_CBASS_EXPORT_AM62_MAIN_CENTRAL_CBASS_TO_AM62_MCU_CBASS_DATA_L0_P2M_BRIDGE_EXPORT_AM62_MAIN_CENTRAL_CBASS_TO_AM62_MCU_CBASS_DATA_L0_BRIDGE_DST_BUSECC_groupEntries },
    { SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_CENTRAL_CBASS_EXPORT_AM62_MAIN_CENTRAL_CBASS_TO_AM62_MCU_CBASS_DATA_L0_P2M_BRIDGE_EXPORT_AM62_MAIN_CENTRAL_CBASS_TO_AM62_MCU_CBASS_DATA_L0_BRIDGE_SRC_BUSECC_RAM_ID,
      SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_CENTRAL_CBASS_EXPORT_AM62_MAIN_CENTRAL_CBASS_TO_AM62_MCU_CBASS_DATA_L0_P2M_BRIDGE_EXPORT_AM62_MAIN_CENTRAL_CBASS_TO_AM62_MCU_CBASS_DATA_L0_BRIDGE_SRC_BUSECC_INJECT_TYPE,
      SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_CENTRAL_CBASS_EXPORT_AM62_MAIN_CENTRAL_CBASS_TO_AM62_MCU_CBASS_DATA_L0_P2M_BRIDGE_EXPORT_AM62_MAIN_CENTRAL_CBASS_TO_AM62_MCU_CBASS_DATA_L0_BRIDGE_SRC_BUSECC_ECC_TYPE,
      SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_CENTRAL_CBASS_EXPORT_AM62_MAIN_CENTRAL_CBASS_TO_AM62_MCU_CBASS_DATA_L0_P2M_BRIDGE_EXPORT_AM62_MAIN_CENTRAL_CBASS_TO_AM62_MCU_CBASS_DATA_L0_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS,
      SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_AM62_MAIN_CENTRAL_CBASS_EXPORT_AM62_MAIN_CENTRAL_CBASS_TO_AM62_MCU_CBASS_DATA_L0_P2M_BRIDGE_EXPORT_AM62_MAIN_CENTRAL_CBASS_TO_AM62_MCU_CBASS_DATA_L0_BRIDGE_SRC_BUSECC_groupEntries },
    { SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_IP2P_SA3_DMSS_CFG_DST_BUSECC_RAM_ID,
      SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_IP2P_SA3_DMSS_CFG_DST_BUSECC_INJECT_TYPE,
      SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_IP2P_SA3_DMSS_CFG_DST_BUSECC_ECC_TYPE,
      SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_IP2P_SA3_DMSS_CFG_DST_BUSECC_MAX_NUM_CHECKERS,
      SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_IP2P_SA3_DMSS_CFG_DST_BUSECC_groupEntries },
    { SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_IP2P_SA3_DMSS_CFG_SRC_BUSECC_RAM_ID,
      SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_IP2P_SA3_DMSS_CFG_SRC_BUSECC_INJECT_TYPE,
      SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_IP2P_SA3_DMSS_CFG_SRC_BUSECC_ECC_TYPE,
      SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_IP2P_SA3_DMSS_CFG_SRC_BUSECC_MAX_NUM_CHECKERS,
      SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_IP2P_SA3_DMSS_CFG_SRC_BUSECC_groupEntries },
    { SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_IP2P_SA3_PKTDMA_CRED_DST_BUSECC_RAM_ID,
      SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_IP2P_SA3_PKTDMA_CRED_DST_BUSECC_INJECT_TYPE,
      SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_IP2P_SA3_PKTDMA_CRED_DST_BUSECC_ECC_TYPE,
      SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_IP2P_SA3_PKTDMA_CRED_DST_BUSECC_MAX_NUM_CHECKERS,
      SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_IP2P_SA3_PKTDMA_CRED_DST_BUSECC_groupEntries },
    { SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_IP2P_SA3_PKTDMA_CRED_SRC_BUSECC_RAM_ID,
      SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_IP2P_SA3_PKTDMA_CRED_SRC_BUSECC_INJECT_TYPE,
      SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_IP2P_SA3_PKTDMA_CRED_SRC_BUSECC_ECC_TYPE,
      SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_IP2P_SA3_PKTDMA_CRED_SRC_BUSECC_MAX_NUM_CHECKERS,
      SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_IP2P_SA3_PKTDMA_CRED_SRC_BUSECC_groupEntries },
};
 
static const SDL_RAMIdEntry_t SDL_ICSSM0_ICSS_M_CORE_BORG_ECC_AGGR_RamIdTable[SDL_ICSSM0_ICSS_M_CORE_BORG_ECC_AGGR_NUM_RAMS] =
{
    { SDL_ICSSM0_ICSS_M_CORE_BORG_ECC_AGGR_ICSS_M_CORE_DRAM0_ECC_RAM_ID,
      SDL_ICSSM0_ICSS_M_CORE_BORG_ECC_AGGR_ICSS_M_CORE_DRAM0_ECC_INJECT_TYPE,
      SDL_ICSSM0_ICSS_M_CORE_BORG_ECC_AGGR_ICSS_M_CORE_DRAM0_ECC_ECC_TYPE,
      0u,
      NULL },
    { SDL_ICSSM0_ICSS_M_CORE_BORG_ECC_AGGR_ICSS_M_CORE_DRAM1_ECC_RAM_ID,
      SDL_ICSSM0_ICSS_M_CORE_BORG_ECC_AGGR_ICSS_M_CORE_DRAM1_ECC_INJECT_TYPE,
      SDL_ICSSM0_ICSS_M_CORE_BORG_ECC_AGGR_ICSS_M_CORE_DRAM1_ECC_ECC_TYPE,
      0u,
      NULL },
    { SDL_ICSSM0_ICSS_M_CORE_BORG_ECC_AGGR_ICSS_M_CORE_PR1_PDSP0_IRAM_ECC_RAM_ID,
      SDL_ICSSM0_ICSS_M_CORE_BORG_ECC_AGGR_ICSS_M_CORE_PR1_PDSP0_IRAM_ECC_INJECT_TYPE,
      SDL_ICSSM0_ICSS_M_CORE_BORG_ECC_AGGR_ICSS_M_CORE_PR1_PDSP0_IRAM_ECC_ECC_TYPE,
      0u,
      NULL },
    { SDL_ICSSM0_ICSS_M_CORE_BORG_ECC_AGGR_ICSS_M_CORE_PR1_PDSP1_IRAM_ECC_RAM_ID,
      SDL_ICSSM0_ICSS_M_CORE_BORG_ECC_AGGR_ICSS_M_CORE_PR1_PDSP1_IRAM_ECC_INJECT_TYPE,
      SDL_ICSSM0_ICSS_M_CORE_BORG_ECC_AGGR_ICSS_M_CORE_PR1_PDSP1_IRAM_ECC_ECC_TYPE,
      0u,
      NULL },
    { SDL_ICSSM0_ICSS_M_CORE_BORG_ECC_AGGR_ICSS_M_CORE_RAM_ECC_RAM_ID,
      SDL_ICSSM0_ICSS_M_CORE_BORG_ECC_AGGR_ICSS_M_CORE_RAM_ECC_INJECT_TYPE,
      SDL_ICSSM0_ICSS_M_CORE_BORG_ECC_AGGR_ICSS_M_CORE_RAM_ECC_ECC_TYPE,
      0u,
      NULL },
};
 
static const SDL_RAMIdEntry_t SDL_FSS0_FSS_UL_OSPI0_OSPI_WRAP_ECC_AGGR_RamIdTable[SDL_FSS0_FSS_UL_OSPI0_OSPI_WRAP_ECC_AGGR_NUM_RAMS] =
{
    { SDL_FSS0_FSS_UL_OSPI0_OSPI_WRAP_ECC_AGGR_OSPI_OSPI_WRAP_SRAM_RAM_ID,
      SDL_FSS0_FSS_UL_OSPI0_OSPI_WRAP_ECC_AGGR_OSPI_OSPI_WRAP_SRAM_INJECT_TYPE,
      SDL_FSS0_FSS_UL_OSPI0_OSPI_WRAP_ECC_AGGR_OSPI_OSPI_WRAP_SRAM_ECC_TYPE,
      0u,
      NULL },
};
 
static const SDL_RAMIdEntry_t SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR_RamIdTable[SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR_SPECIAL_NUM_RAMS] =
{
    { SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR_ALE_RAM_RAM_ID,
      SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR_ALE_RAM_INJECT_TYPE,
      SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR_ALE_RAM_ECC_TYPE,
      0u,
      NULL },
    { SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR_P0_RX_FIFO_RAM_ID,
      SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR_P0_RX_FIFO_INJECT_TYPE,
      SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR_P0_RX_FIFO_ECC_TYPE,
      0u,
      NULL },
    { SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR_P0_TX_FIFO_RAM_ID,
      SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR_P0_TX_FIFO_INJECT_TYPE,
      SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR_P0_TX_FIFO_ECC_TYPE,
      0u,
      NULL },
    { SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR_P1_RX_FIFO_RAM_ID,
      SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR_P1_RX_FIFO_INJECT_TYPE,
      SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR_P1_RX_FIFO_ECC_TYPE,
      0u,
      NULL },
    { SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR_P1_TX_FIFO_RAM_ID,
      SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR_P1_TX_FIFO_INJECT_TYPE,
      SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR_P1_TX_FIFO_ECC_TYPE,
      0u,
      NULL },
    { SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR_P2_RX_FIFO_RAM_ID,
      SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR_P2_RX_FIFO_INJECT_TYPE,
      SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR_P2_RX_FIFO_ECC_TYPE,
      0u,
      NULL },
    { SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR_P2_TX_FIFO_RAM_ID,
      SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR_P2_TX_FIFO_INJECT_TYPE,
      SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR_P2_TX_FIFO_ECC_TYPE,
      0u,
      NULL },
    { SDL_ECC_RAMID_INVALID,
      0u,
      0u,
      0u,
      NULL },
    { SDL_ECC_RAMID_INVALID,
      0u,
      0u,
      0u,
      NULL },
    { SDL_ECC_RAMID_INVALID,
      0u,
      0u,
      0u,
      NULL },
    { SDL_ECC_RAMID_INVALID,
      0u,
      0u,
      0u,
      NULL },
    { SDL_ECC_RAMID_INVALID,
      0u,
      0u,
      0u,
      NULL },
    { SDL_ECC_RAMID_INVALID,
      0u,
      0u,
      0u,
      NULL },
    { SDL_ECC_RAMID_INVALID,
      0u,
      0u,
      0u,
      NULL },
    { SDL_ECC_RAMID_INVALID,
      0u,
      0u,
      0u,
      NULL },
    { SDL_ECC_RAMID_INVALID,
      0u,
      0u,
      0u,
      NULL },
    { SDL_ECC_RAMID_INVALID,
      0u,
      0u,
      0u,
      NULL },
    { SDL_ECC_RAMID_INVALID,
      0u,
      0u,
      0u,
      NULL },
    { SDL_ECC_RAMID_INVALID,
      0u,
      0u,
      0u,
      NULL },
    { SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR_EST_RAM_RAM_ID,
      SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR_EST_RAM_INJECT_TYPE,
      SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR_EST_RAM_ECC_TYPE,
      0u,
      NULL },
};
static const SDL_RAMIdEntry_t SDL_GICSS0_GIC500SS_1_4_ECC_AGGR_RamIdTable[SDL_GICSS0_GIC500SS_1_4_ECC_AGGR_NUM_RAMS] =
{
    { SDL_GICSS0_GIC500SS_1_4_ECC_AGGR_ICB_RAMECC_RAM_ID,
      SDL_GICSS0_GIC500SS_1_4_ECC_AGGR_ICB_RAMECC_INJECT_TYPE,
      SDL_GICSS0_GIC500SS_1_4_ECC_AGGR_ICB_RAMECC_ECC_TYPE,
      0u,
      NULL },
    { SDL_GICSS0_GIC500SS_1_4_ECC_AGGR_ITE_RAMECC_RAM_ID,
      SDL_GICSS0_GIC500SS_1_4_ECC_AGGR_ITE_RAMECC_INJECT_TYPE,
      SDL_GICSS0_GIC500SS_1_4_ECC_AGGR_ITE_RAMECC_ECC_TYPE,
      0u,
      NULL },
    { SDL_GICSS0_GIC500SS_1_4_ECC_AGGR_LPI_RAMECC_RAM_ID,
      SDL_GICSS0_GIC500SS_1_4_ECC_AGGR_LPI_RAMECC_INJECT_TYPE,
      SDL_GICSS0_GIC500SS_1_4_ECC_AGGR_LPI_RAMECC_ECC_TYPE,
      0u,
      NULL },
};
 
static const SDL_RAMIdEntry_t SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_RamIdTable[SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_NUM_RAMS] =
{
    { SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_ECCAGGR_EDC_CTRL_RAM_ID,
      SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_ECCAGGR_EDC_CTRL_INJECT_TYPE,
      SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_ECCAGGR_EDC_CTRL_ECC_TYPE,
      SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_ECCAGGR_EDC_CTRL_MAX_NUM_CHECKERS,
      SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_ECCAGGR_EDC_CTRL_groupEntries },
    { SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_CFG_CONFIG_RAM_ID,
      SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_CFG_CONFIG_INJECT_TYPE,
      SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_CFG_CONFIG_ECC_TYPE,
      0u,
      NULL },
    { SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_CFG_STATE_RAM_ID,
      SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_CFG_STATE_INJECT_TYPE,
      SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_CFG_STATE_ECC_TYPE,
      0u,
      NULL },
    { SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_TPCFIFO_F0_RAM_ID,
      SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_TPCFIFO_F0_INJECT_TYPE,
      SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_TPCFIFO_F0_ECC_TYPE,
      0u,
      NULL },
    { SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_TPCFIFO_F1_RAM_ID,
      SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_TPCFIFO_F1_INJECT_TYPE,
      SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_TPCFIFO_F1_ECC_TYPE,
      0u,
      NULL },
    { SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_RPCFIFO_F0_RAM_ID,
      SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_RPCFIFO_F0_INJECT_TYPE,
      SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_RPCFIFO_F0_ECC_TYPE,
      0u,
      NULL },
    { SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_RPCFIFO_F1_RAM_ID,
      SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_RPCFIFO_F1_INJECT_TYPE,
      SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_RPCFIFO_F1_ECC_TYPE,
      0u,
      NULL },
    { SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_RPCFIFO_WC_RAM_ID,
      SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_RPCFIFO_WC_INJECT_TYPE,
      SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_RPCFIFO_WC_ECC_TYPE,
      0u,
      NULL },
    { SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_STATS_STST0_RAM_ID,
      SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_STATS_STST0_INJECT_TYPE,
      SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_STATS_STST0_ECC_TYPE,
      0u,
      NULL },
    { SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_STATS_STSR0_RAM_ID,
      SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_STATS_STSR0_INJECT_TYPE,
      SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_STATS_STSR0_ECC_TYPE,
      0u,
      NULL },
    { SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_RINGOCC_CNTR_RAM_ID,
      SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_RINGOCC_CNTR_INJECT_TYPE,
      SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_RINGOCC_CNTR_ECC_TYPE,
      0u,
      NULL },
    { SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_RAM_ID,
      SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_INJECT_TYPE,
      SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_ECC_TYPE,
      SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_MAX_NUM_CHECKERS,
      SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_groupEntries },
    { SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_EDC_CTRL_0_RAM_ID,
      SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_EDC_CTRL_0_INJECT_TYPE,
      SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_EDC_CTRL_0_ECC_TYPE,
      SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_EDC_CTRL_0_MAX_NUM_CHECKERS,
      SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_EDC_CTRL_0_groupEntries },
    { SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_STATREG_SR_SPRAM_8X128_SWW_SR_RAM_ID,
      SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_STATREG_SR_SPRAM_8X128_SWW_SR_INJECT_TYPE,
      SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_STATREG_SR_SPRAM_8X128_SWW_SR_ECC_TYPE,
      0u,
      NULL },
    { SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_COMMON_IM_TPRAM_158X34_SWW_SR_RAM_ID,
      SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_COMMON_IM_TPRAM_158X34_SWW_SR_INJECT_TYPE,
      SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_COMMON_IM_TPRAM_158X34_SWW_SR_ECC_TYPE,
      0u,
      NULL },
    { SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_RAM_ID,
      SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_INJECT_TYPE,
      SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_ECC_TYPE,
      SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_MAX_NUM_CHECKERS,
      SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_groupEntries },
    { SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_RAM_ID,
      SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_INJECT_TYPE,
      SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_ECC_TYPE,
      SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_MAX_NUM_CHECKERS,
      SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_groupEntries },
    { SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_STRAM_RAM_ID,
      SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_STRAM_INJECT_TYPE,
      SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_STRAM_ECC_TYPE,
      0u,
      NULL },
    { SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_BUF_STRAM_RAM_ID,
      SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_BUF_STRAM_INJECT_TYPE,
      SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_BUF_STRAM_ECC_TYPE,
      0u,
      NULL },
    { SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_BUF_BUFRAM_RAM_ID,
      SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_BUF_BUFRAM_INJECT_TYPE,
      SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_BUF_BUFRAM_ECC_TYPE,
      0u,
      NULL },
    { SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_RAM_ID,
      SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_INJECT_TYPE,
      SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_ECC_TYPE,
      SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_MAX_NUM_CHECKERS,
      SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_groupEntries },
    { SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_RAM_ID,
      SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_INJECT_TYPE,
      SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_ECC_TYPE,
      SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS,
      SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries },
    { SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_RAM_ID,
      SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_INJECT_TYPE,
      SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_ECC_TYPE,
      SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_MAX_NUM_CHECKERS,
      SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_groupEntries },
    { SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_VD2GCLK_EDC_CTRL_0_RAM_ID,
      SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_VD2GCLK_EDC_CTRL_0_INJECT_TYPE,
      SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_VD2GCLK_EDC_CTRL_0_ECC_TYPE,
      SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_VD2GCLK_EDC_CTRL_0_MAX_NUM_CHECKERS,
      SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_VD2GCLK_EDC_CTRL_0_groupEntries },
    { SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_ECC0_RAM_ID,
      SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_ECC0_INJECT_TYPE,
      SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_ECC0_ECC_TYPE,
      0u,
      NULL },
    { SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_RAM_ID,
      SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_INJECT_TYPE,
      SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_ECC_TYPE,
      SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_MAX_NUM_CHECKERS,
      SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_groupEntries },
    { SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_RAM_ID,
      SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_INJECT_TYPE,
      SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_ECC_TYPE,
      SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_MAX_NUM_CHECKERS,
      SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_groupEntries },
    { SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_RAM_ID,
      SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_INJECT_TYPE,
      SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_ECC_TYPE,
      SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_MAX_NUM_CHECKERS,
      SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_groupEntries },
    { SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_RAM_ID,
      SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_INJECT_TYPE,
      SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_ECC_TYPE,
      SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_MAX_NUM_CHECKERS,
      SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_groupEntries },
    { SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_RAM_ID,
      SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_INJECT_TYPE,
      SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_ECC_TYPE,
      SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_MAX_NUM_CHECKERS,
      SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_groupEntries },
    { SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_RAM_ID,
      SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_INJECT_TYPE,
      SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_ECC_TYPE,
      SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_MAX_NUM_CHECKERS,
      SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_groupEntries },
    { SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_RAM_ID,
      SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_INJECT_TYPE,
      SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_ECC_TYPE,
      SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_MAX_NUM_CHECKERS,
      SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_groupEntries },
    { SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_RAM_ID,
      SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_INJECT_TYPE,
      SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_ECC_TYPE,
      SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_MAX_NUM_CHECKERS,
      SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_groupEntries },
    { SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_RAM_ID,
      SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_INJECT_TYPE,
      SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_ECC_TYPE,
      SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_MAX_NUM_CHECKERS,
      SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_groupEntries },
    { SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_RAM_ID,
      SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_INJECT_TYPE,
      SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_ECC_TYPE,
      SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_MAX_NUM_CHECKERS,
      SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_groupEntries },
    { SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_INTAGGR_EVT_EDC_CTRL_0_RAM_ID,
      SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_INTAGGR_EVT_EDC_CTRL_0_INJECT_TYPE,
      SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_INTAGGR_EVT_EDC_CTRL_0_ECC_TYPE,
      SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_INTAGGR_EVT_EDC_CTRL_0_MAX_NUM_CHECKERS,
      SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_INTAGGR_EVT_EDC_CTRL_0_groupEntries },
    { SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_INTAGGR_CEVT_EDC_CTRL_0_RAM_ID,
      SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_INTAGGR_CEVT_EDC_CTRL_0_INJECT_TYPE,
      SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_INTAGGR_CEVT_EDC_CTRL_0_ECC_TYPE,
      SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_INTAGGR_CEVT_EDC_CTRL_0_MAX_NUM_CHECKERS,
      SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_INTAGGR_CEVT_EDC_CTRL_0_groupEntries },
    { SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_INTAGGR_MEVT_IN_EDC_CTRL_0_RAM_ID,
      SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_INTAGGR_MEVT_IN_EDC_CTRL_0_INJECT_TYPE,
      SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_INTAGGR_MEVT_IN_EDC_CTRL_0_ECC_TYPE,
      SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_INTAGGR_MEVT_IN_EDC_CTRL_0_MAX_NUM_CHECKERS,
      SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_INTAGGR_MEVT_IN_EDC_CTRL_0_groupEntries },
    { SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_RAM_ID,
      SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_INJECT_TYPE,
      SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_ECC_TYPE,
      SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_MAX_NUM_CHECKERS,
      SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_groupEntries },
    { SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CFG_EDC_CTRL_0_RAM_ID,
      SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CFG_EDC_CTRL_0_INJECT_TYPE,
      SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CFG_EDC_CTRL_0_ECC_TYPE,
      SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CFG_EDC_CTRL_0_MAX_NUM_CHECKERS,
      SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CFG_EDC_CTRL_0_groupEntries },
    { SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_RAM_ID,
      SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_INJECT_TYPE,
      SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_ECC_TYPE,
      SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_MAX_NUM_CHECKERS,
      SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_groupEntries },
    { SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_RAM_ID,
      SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_INJECT_TYPE,
      SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_ECC_TYPE,
      SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_MAX_NUM_CHECKERS,
      SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_groupEntries },
    { SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_RAM_ID,
      SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_INJECT_TYPE,
      SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_ECC_TYPE,
      SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_MAX_NUM_CHECKERS,
      SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_groupEntries },
    { SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_VD2GCLK_EDC_CTRL_0_RAM_ID,
      SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_VD2GCLK_EDC_CTRL_0_INJECT_TYPE,
      SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_VD2GCLK_EDC_CTRL_0_ECC_TYPE,
      SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_VD2GCLK_EDC_CTRL_0_MAX_NUM_CHECKERS,
      SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_VD2GCLK_EDC_CTRL_0_groupEntries },
    { SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_DMSS_CFG_P2P_BRIDGE_EDC_CTRL_0_RAM_ID,
      SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_DMSS_CFG_P2P_BRIDGE_EDC_CTRL_0_INJECT_TYPE,
      SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_DMSS_CFG_P2P_BRIDGE_EDC_CTRL_0_ECC_TYPE,
      SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_DMSS_CFG_P2P_BRIDGE_EDC_CTRL_0_MAX_NUM_CHECKERS,
      SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_DMSS_CFG_P2P_BRIDGE_EDC_CTRL_0_groupEntries },
    { SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_RAM_ID,
      SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_INJECT_TYPE,
      SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_ECC_TYPE,
      SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_MAX_NUM_CHECKERS,
      SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_groupEntries },
    { SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_RAM_ID,
      SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_INJECT_TYPE,
      SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_ECC_TYPE,
      SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_MAX_NUM_CHECKERS,
      SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_groupEntries },
};
 
static const SDL_RAMIdEntry_t SDL_SA3_SS0_SA3SS_AM62_SA_UL_ECC_AGGR_RamIdTable[SDL_SA3_SS0_SA3SS_AM62_SA_UL_ECC_AGGR_NUM_RAMS] =
{
    { SDL_SA3_SS0_SA3SS_AM62_SA_UL_ECC_AGGR_SA3_UL_PKTRAM0_ECC_RAM_ID,
      SDL_SA3_SS0_SA3SS_AM62_SA_UL_ECC_AGGR_SA3_UL_PKTRAM0_ECC_INJECT_TYPE,
      SDL_SA3_SS0_SA3SS_AM62_SA_UL_ECC_AGGR_SA3_UL_PKTRAM0_ECC_ECC_TYPE,
      0u,
      NULL },
    { SDL_SA3_SS0_SA3SS_AM62_SA_UL_ECC_AGGR_SA3_UL_PKTRAM1_ECC_RAM_ID,
      SDL_SA3_SS0_SA3SS_AM62_SA_UL_ECC_AGGR_SA3_UL_PKTRAM1_ECC_INJECT_TYPE,
      SDL_SA3_SS0_SA3SS_AM62_SA_UL_ECC_AGGR_SA3_UL_PKTRAM1_ECC_ECC_TYPE,
      0u,
      NULL },
    { SDL_SA3_SS0_SA3SS_AM62_SA_UL_ECC_AGGR_SA3_UL_PKA_PROG_RAM_ECC_RAM_ID,
      SDL_SA3_SS0_SA3SS_AM62_SA_UL_ECC_AGGR_SA3_UL_PKA_PROG_RAM_ECC_INJECT_TYPE,
      SDL_SA3_SS0_SA3SS_AM62_SA_UL_ECC_AGGR_SA3_UL_PKA_PROG_RAM_ECC_ECC_TYPE,
      0u,
      NULL },
    { SDL_SA3_SS0_SA3SS_AM62_SA_UL_ECC_AGGR_SA3_UL_ENCR_CTXRAM_BANK01_ECC_RAM_ID,
      SDL_SA3_SS0_SA3SS_AM62_SA_UL_ECC_AGGR_SA3_UL_ENCR_CTXRAM_BANK01_ECC_INJECT_TYPE,
      SDL_SA3_SS0_SA3SS_AM62_SA_UL_ECC_AGGR_SA3_UL_ENCR_CTXRAM_BANK01_ECC_ECC_TYPE,
      0u,
      NULL },
    { SDL_SA3_SS0_SA3SS_AM62_SA_UL_ECC_AGGR_SA3_UL_ENCR_CTXRAM_BANK23_ECC_RAM_ID,
      SDL_SA3_SS0_SA3SS_AM62_SA_UL_ECC_AGGR_SA3_UL_ENCR_CTXRAM_BANK23_ECC_INJECT_TYPE,
      SDL_SA3_SS0_SA3SS_AM62_SA_UL_ECC_AGGR_SA3_UL_ENCR_CTXRAM_BANK23_ECC_ECC_TYPE,
      0u,
      NULL },
    { SDL_SA3_SS0_SA3SS_AM62_SA_UL_ECC_AGGR_SA3_UL_ENCR_CTXRAM_BANK4_ECC_RAM_ID,
      SDL_SA3_SS0_SA3SS_AM62_SA_UL_ECC_AGGR_SA3_UL_ENCR_CTXRAM_BANK4_ECC_INJECT_TYPE,
      SDL_SA3_SS0_SA3SS_AM62_SA_UL_ECC_AGGR_SA3_UL_ENCR_CTXRAM_BANK4_ECC_ECC_TYPE,
      0u,
      NULL },
    { SDL_SA3_SS0_SA3SS_AM62_SA_UL_ECC_AGGR_SA3_UL_AUTH_CTXRAM_BANK01_ECC_RAM_ID,
      SDL_SA3_SS0_SA3SS_AM62_SA_UL_ECC_AGGR_SA3_UL_AUTH_CTXRAM_BANK01_ECC_INJECT_TYPE,
      SDL_SA3_SS0_SA3SS_AM62_SA_UL_ECC_AGGR_SA3_UL_AUTH_CTXRAM_BANK01_ECC_ECC_TYPE,
      0u,
      NULL },
    { SDL_SA3_SS0_SA3SS_AM62_SA_UL_ECC_AGGR_SA3_UL_AUTH_CTXRAM_BANK23_ECC_RAM_ID,
      SDL_SA3_SS0_SA3SS_AM62_SA_UL_ECC_AGGR_SA3_UL_AUTH_CTXRAM_BANK23_ECC_INJECT_TYPE,
      SDL_SA3_SS0_SA3SS_AM62_SA_UL_ECC_AGGR_SA3_UL_AUTH_CTXRAM_BANK23_ECC_ECC_TYPE,
      0u,
      NULL },
    { SDL_SA3_SS0_SA3SS_AM62_SA_UL_ECC_AGGR_SA3_UL_AUTH_CTXRAM_BANK45_ECC_RAM_ID,
      SDL_SA3_SS0_SA3SS_AM62_SA_UL_ECC_AGGR_SA3_UL_AUTH_CTXRAM_BANK45_ECC_INJECT_TYPE,
      SDL_SA3_SS0_SA3SS_AM62_SA_UL_ECC_AGGR_SA3_UL_AUTH_CTXRAM_BANK45_ECC_ECC_TYPE,
      0u,
      NULL },
    { SDL_SA3_SS0_SA3SS_AM62_SA_UL_ECC_AGGR_SA3_UL_AUTH_CTXRAM_BANK67_ECC_RAM_ID,
      SDL_SA3_SS0_SA3SS_AM62_SA_UL_ECC_AGGR_SA3_UL_AUTH_CTXRAM_BANK67_ECC_INJECT_TYPE,
      SDL_SA3_SS0_SA3SS_AM62_SA_UL_ECC_AGGR_SA3_UL_AUTH_CTXRAM_BANK67_ECC_ECC_TYPE,
      0u,
      NULL },
    { SDL_SA3_SS0_SA3SS_AM62_SA_UL_ECC_AGGR_SA3_UL_AUTH_CTXRAM_BANK89_ECC_RAM_ID,
      SDL_SA3_SS0_SA3SS_AM62_SA_UL_ECC_AGGR_SA3_UL_AUTH_CTXRAM_BANK89_ECC_INJECT_TYPE,
      SDL_SA3_SS0_SA3SS_AM62_SA_UL_ECC_AGGR_SA3_UL_AUTH_CTXRAM_BANK89_ECC_ECC_TYPE,
      0u,
      NULL },
    { SDL_SA3_SS0_SA3SS_AM62_SA_UL_ECC_AGGR_SA3_UL_AUTH_CTXRAM_BANK10_ECC_RAM_ID,
      SDL_SA3_SS0_SA3SS_AM62_SA_UL_ECC_AGGR_SA3_UL_AUTH_CTXRAM_BANK10_ECC_INJECT_TYPE,
      SDL_SA3_SS0_SA3SS_AM62_SA_UL_ECC_AGGR_SA3_UL_AUTH_CTXRAM_BANK10_ECC_ECC_TYPE,
      0u,
      NULL },
};
 
static const SDL_RAMIdEntry_t SDL_DMASS0_DMSS_AM62_ECCAGGR_RamIdTable[SDL_DMASS0_DMSS_AM62_ECCAGGR_NUM_RAMS] =
{
    { SDL_DMASS0_DMSS_AM62_ECCAGGR_DMSS_AM62_PKTDMA_CFG_CONFIG_RAM_ID,
      SDL_DMASS0_DMSS_AM62_ECCAGGR_DMSS_AM62_PKTDMA_CFG_CONFIG_INJECT_TYPE,
      SDL_DMASS0_DMSS_AM62_ECCAGGR_DMSS_AM62_PKTDMA_CFG_CONFIG_ECC_TYPE,
      0u,
      NULL },
    { SDL_DMASS0_DMSS_AM62_ECCAGGR_DMSS_AM62_PKTDMA_CFG_STATE_RAM_ID,
      SDL_DMASS0_DMSS_AM62_ECCAGGR_DMSS_AM62_PKTDMA_CFG_STATE_INJECT_TYPE,
      SDL_DMASS0_DMSS_AM62_ECCAGGR_DMSS_AM62_PKTDMA_CFG_STATE_ECC_TYPE,
      0u,
      NULL },
    { SDL_DMASS0_DMSS_AM62_ECCAGGR_DMSS_AM62_PKTDMA_TPCFIFO_F0_RAM_ID,
      SDL_DMASS0_DMSS_AM62_ECCAGGR_DMSS_AM62_PKTDMA_TPCFIFO_F0_INJECT_TYPE,
      SDL_DMASS0_DMSS_AM62_ECCAGGR_DMSS_AM62_PKTDMA_TPCFIFO_F0_ECC_TYPE,
      0u,
      NULL },
    { SDL_DMASS0_DMSS_AM62_ECCAGGR_DMSS_AM62_PKTDMA_TPCFIFO_F1_RAM_ID,
      SDL_DMASS0_DMSS_AM62_ECCAGGR_DMSS_AM62_PKTDMA_TPCFIFO_F1_INJECT_TYPE,
      SDL_DMASS0_DMSS_AM62_ECCAGGR_DMSS_AM62_PKTDMA_TPCFIFO_F1_ECC_TYPE,
      0u,
      NULL },
    { SDL_DMASS0_DMSS_AM62_ECCAGGR_DMSS_AM62_PKTDMA_RPCFIFO_F0_RAM_ID,
      SDL_DMASS0_DMSS_AM62_ECCAGGR_DMSS_AM62_PKTDMA_RPCFIFO_F0_INJECT_TYPE,
      SDL_DMASS0_DMSS_AM62_ECCAGGR_DMSS_AM62_PKTDMA_RPCFIFO_F0_ECC_TYPE,
      0u,
      NULL },
    { SDL_DMASS0_DMSS_AM62_ECCAGGR_DMSS_AM62_PKTDMA_RPCFIFO_F1_RAM_ID,
      SDL_DMASS0_DMSS_AM62_ECCAGGR_DMSS_AM62_PKTDMA_RPCFIFO_F1_INJECT_TYPE,
      SDL_DMASS0_DMSS_AM62_ECCAGGR_DMSS_AM62_PKTDMA_RPCFIFO_F1_ECC_TYPE,
      0u,
      NULL },
    { SDL_DMASS0_DMSS_AM62_ECCAGGR_DMSS_AM62_PKTDMA_RPCFIFO_WC_RAM_ID,
      SDL_DMASS0_DMSS_AM62_ECCAGGR_DMSS_AM62_PKTDMA_RPCFIFO_WC_INJECT_TYPE,
      SDL_DMASS0_DMSS_AM62_ECCAGGR_DMSS_AM62_PKTDMA_RPCFIFO_WC_ECC_TYPE,
      0u,
      NULL },
    { SDL_DMASS0_DMSS_AM62_ECCAGGR_DMSS_AM62_PKTDMA_STATS_STST0_RAM_ID,
      SDL_DMASS0_DMSS_AM62_ECCAGGR_DMSS_AM62_PKTDMA_STATS_STST0_INJECT_TYPE,
      SDL_DMASS0_DMSS_AM62_ECCAGGR_DMSS_AM62_PKTDMA_STATS_STST0_ECC_TYPE,
      0u,
      NULL },
    { SDL_DMASS0_DMSS_AM62_ECCAGGR_DMSS_AM62_PKTDMA_STATS_STSR0_RAM_ID,
      SDL_DMASS0_DMSS_AM62_ECCAGGR_DMSS_AM62_PKTDMA_STATS_STSR0_INJECT_TYPE,
      SDL_DMASS0_DMSS_AM62_ECCAGGR_DMSS_AM62_PKTDMA_STATS_STSR0_ECC_TYPE,
      0u,
      NULL },
    { SDL_DMASS0_DMSS_AM62_ECCAGGR_DMSS_AM62_PKTDMA_RINGOCC_CNTR_RAM_ID,
      SDL_DMASS0_DMSS_AM62_ECCAGGR_DMSS_AM62_PKTDMA_RINGOCC_CNTR_INJECT_TYPE,
      SDL_DMASS0_DMSS_AM62_ECCAGGR_DMSS_AM62_PKTDMA_RINGOCC_CNTR_ECC_TYPE,
      0u,
      NULL },
    { SDL_DMASS0_DMSS_AM62_ECCAGGR_DMSS_AM62_BCDMA_CFG_CONFIG_RAM_ID,
      SDL_DMASS0_DMSS_AM62_ECCAGGR_DMSS_AM62_BCDMA_CFG_CONFIG_INJECT_TYPE,
      SDL_DMASS0_DMSS_AM62_ECCAGGR_DMSS_AM62_BCDMA_CFG_CONFIG_ECC_TYPE,
      0u,
      NULL },
    { SDL_DMASS0_DMSS_AM62_ECCAGGR_DMSS_AM62_BCDMA_CFG_STATE_RAM_ID,
      SDL_DMASS0_DMSS_AM62_ECCAGGR_DMSS_AM62_BCDMA_CFG_STATE_INJECT_TYPE,
      SDL_DMASS0_DMSS_AM62_ECCAGGR_DMSS_AM62_BCDMA_CFG_STATE_ECC_TYPE,
      0u,
      NULL },
    { SDL_DMASS0_DMSS_AM62_ECCAGGR_DMSS_AM62_BCDMA_PCFIFO_DFIFO_F0_RAM_ID,
      SDL_DMASS0_DMSS_AM62_ECCAGGR_DMSS_AM62_BCDMA_PCFIFO_DFIFO_F0_INJECT_TYPE,
      SDL_DMASS0_DMSS_AM62_ECCAGGR_DMSS_AM62_BCDMA_PCFIFO_DFIFO_F0_ECC_TYPE,
      0u,
      NULL },
    { SDL_DMASS0_DMSS_AM62_ECCAGGR_DMSS_AM62_BCDMA_PCFIFO_DFIFO_F1_RAM_ID,
      SDL_DMASS0_DMSS_AM62_ECCAGGR_DMSS_AM62_BCDMA_PCFIFO_DFIFO_F1_INJECT_TYPE,
      SDL_DMASS0_DMSS_AM62_ECCAGGR_DMSS_AM62_BCDMA_PCFIFO_DFIFO_F1_ECC_TYPE,
      0u,
      NULL },
    { SDL_DMASS0_DMSS_AM62_ECCAGGR_DMSS_AM62_BCDMA_TPCFIFO_F0_RAM_ID,
      SDL_DMASS0_DMSS_AM62_ECCAGGR_DMSS_AM62_BCDMA_TPCFIFO_F0_INJECT_TYPE,
      SDL_DMASS0_DMSS_AM62_ECCAGGR_DMSS_AM62_BCDMA_TPCFIFO_F0_ECC_TYPE,
      0u,
      NULL },
    { SDL_DMASS0_DMSS_AM62_ECCAGGR_DMSS_AM62_BCDMA_TPCFIFO_F1_RAM_ID,
      SDL_DMASS0_DMSS_AM62_ECCAGGR_DMSS_AM62_BCDMA_TPCFIFO_F1_INJECT_TYPE,
      SDL_DMASS0_DMSS_AM62_ECCAGGR_DMSS_AM62_BCDMA_TPCFIFO_F1_ECC_TYPE,
      0u,
      NULL },
    { SDL_DMASS0_DMSS_AM62_ECCAGGR_DMSS_AM62_BCDMA_RPCFIFO_F0_RAM_ID,
      SDL_DMASS0_DMSS_AM62_ECCAGGR_DMSS_AM62_BCDMA_RPCFIFO_F0_INJECT_TYPE,
      SDL_DMASS0_DMSS_AM62_ECCAGGR_DMSS_AM62_BCDMA_RPCFIFO_F0_ECC_TYPE,
      0u,
      NULL },
    { SDL_DMASS0_DMSS_AM62_ECCAGGR_DMSS_AM62_BCDMA_RPCFIFO_F1_RAM_ID,
      SDL_DMASS0_DMSS_AM62_ECCAGGR_DMSS_AM62_BCDMA_RPCFIFO_F1_INJECT_TYPE,
      SDL_DMASS0_DMSS_AM62_ECCAGGR_DMSS_AM62_BCDMA_RPCFIFO_F1_ECC_TYPE,
      0u,
      NULL },
    { SDL_DMASS0_DMSS_AM62_ECCAGGR_DMSS_AM62_BCDMA_RPCFIFO_WC_RAM_ID,
      SDL_DMASS0_DMSS_AM62_ECCAGGR_DMSS_AM62_BCDMA_RPCFIFO_WC_INJECT_TYPE,
      SDL_DMASS0_DMSS_AM62_ECCAGGR_DMSS_AM62_BCDMA_RPCFIFO_WC_ECC_TYPE,
      0u,
      NULL },
    { SDL_DMASS0_DMSS_AM62_ECCAGGR_DMSS_AM62_BCDMA_STATS_STST0_RAM_ID,
      SDL_DMASS0_DMSS_AM62_ECCAGGR_DMSS_AM62_BCDMA_STATS_STST0_INJECT_TYPE,
      SDL_DMASS0_DMSS_AM62_ECCAGGR_DMSS_AM62_BCDMA_STATS_STST0_ECC_TYPE,
      0u,
      NULL },
    { SDL_DMASS0_DMSS_AM62_ECCAGGR_DMSS_AM62_BCDMA_STATS_STSR0_RAM_ID,
      SDL_DMASS0_DMSS_AM62_ECCAGGR_DMSS_AM62_BCDMA_STATS_STSR0_INJECT_TYPE,
      SDL_DMASS0_DMSS_AM62_ECCAGGR_DMSS_AM62_BCDMA_STATS_STSR0_ECC_TYPE,
      0u,
      NULL },
    { SDL_DMASS0_DMSS_AM62_ECCAGGR_DMSS_AM62_BCDMA_RINGOCC_CNTR_RAM_ID,
      SDL_DMASS0_DMSS_AM62_ECCAGGR_DMSS_AM62_BCDMA_RINGOCC_CNTR_INJECT_TYPE,
      SDL_DMASS0_DMSS_AM62_ECCAGGR_DMSS_AM62_BCDMA_RINGOCC_CNTR_ECC_TYPE,
      0u,
      NULL },
    { SDL_DMASS0_DMSS_AM62_ECCAGGR_DMSS_AM62_INTAGGR_STATREG_SR_SPRAM_184X128_SWW_SR_RAM_ID,
      SDL_DMASS0_DMSS_AM62_ECCAGGR_DMSS_AM62_INTAGGR_STATREG_SR_SPRAM_184X128_SWW_SR_INJECT_TYPE,
      SDL_DMASS0_DMSS_AM62_ECCAGGR_DMSS_AM62_INTAGGR_STATREG_SR_SPRAM_184X128_SWW_SR_ECC_TYPE,
      0u,
      NULL },
    { SDL_DMASS0_DMSS_AM62_ECCAGGR_DMSS_AM62_INTAGGR_COMMON_IM_TPRAM_1531X34_SWW_SR_RAM_ID,
      SDL_DMASS0_DMSS_AM62_ECCAGGR_DMSS_AM62_INTAGGR_COMMON_IM_TPRAM_1531X34_SWW_SR_INJECT_TYPE,
      SDL_DMASS0_DMSS_AM62_ECCAGGR_DMSS_AM62_INTAGGR_COMMON_IM_TPRAM_1531X34_SWW_SR_ECC_TYPE,
      0u,
      NULL },
    { SDL_DMASS0_DMSS_AM62_ECCAGGR_DMSS_AM62_IPCSS_RINGACC_STRAM_RAM_ID,
      SDL_DMASS0_DMSS_AM62_ECCAGGR_DMSS_AM62_IPCSS_RINGACC_STRAM_INJECT_TYPE,
      SDL_DMASS0_DMSS_AM62_ECCAGGR_DMSS_AM62_IPCSS_RINGACC_STRAM_ECC_TYPE,
      0u,
      NULL },
    { SDL_DMASS0_DMSS_AM62_ECCAGGR_DMSS_AM62_IPCSS_SEC_PROXY_BUF_STRAM_RAM_ID,
      SDL_DMASS0_DMSS_AM62_ECCAGGR_DMSS_AM62_IPCSS_SEC_PROXY_BUF_STRAM_INJECT_TYPE,
      SDL_DMASS0_DMSS_AM62_ECCAGGR_DMSS_AM62_IPCSS_SEC_PROXY_BUF_STRAM_ECC_TYPE,
      0u,
      NULL },
    { SDL_DMASS0_DMSS_AM62_ECCAGGR_DMSS_AM62_IPCSS_SEC_PROXY_BUF_BUFRAM_RAM_ID,
      SDL_DMASS0_DMSS_AM62_ECCAGGR_DMSS_AM62_IPCSS_SEC_PROXY_BUF_BUFRAM_INJECT_TYPE,
      SDL_DMASS0_DMSS_AM62_ECCAGGR_DMSS_AM62_IPCSS_SEC_PROXY_BUF_BUFRAM_ECC_TYPE,
      0u,
      NULL },
    { SDL_DMASS0_DMSS_AM62_ECCAGGR_DMSS_AM62_IPCSS_MSRAM_ECC0_RAM_ID,
      SDL_DMASS0_DMSS_AM62_ECCAGGR_DMSS_AM62_IPCSS_MSRAM_ECC0_INJECT_TYPE,
      SDL_DMASS0_DMSS_AM62_ECCAGGR_DMSS_AM62_IPCSS_MSRAM_ECC0_ECC_TYPE,
      0u,
      NULL },
};
 
static const SDL_RAMIdEntry_t SDL_PSRAMECC_16K0_PSRAM16KX32E_ECC_AGGR_RamIdTable[SDL_PSRAMECC_16K0_PSRAM16KX32E_ECC_AGGR_NUM_RAMS] =
{
    { SDL_PSRAMECC_16K0_PSRAM16KX32E_ECC_AGGR_PSRAM16KX32E_PSRAM0_ECC_RAM_ID,
      SDL_PSRAMECC_16K0_PSRAM16KX32E_ECC_AGGR_PSRAM16KX32E_PSRAM0_ECC_INJECT_TYPE,
      SDL_PSRAMECC_16K0_PSRAM16KX32E_ECC_AGGR_PSRAM16KX32E_PSRAM0_ECC_ECC_TYPE,
      0u,
      NULL },
};
 
static const SDL_RAMIdEntry_t SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_RamIdTable[SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_NUM_RAMS] =
{
    { SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_EDC_CTRL_0_RAM_ID,
      SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_EDC_CTRL_0_INJECT_TYPE,
      SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_EDC_CTRL_0_ECC_TYPE,
      SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_EDC_CTRL_0_MAX_NUM_CHECKERS,
      SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_EDC_CTRL_0_groupEntries },
    { SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_RX_SHIM_DMA_PSIL_FIFO_RAM_ID,
      SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_RX_SHIM_DMA_PSIL_FIFO_INJECT_TYPE,
      SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_RX_SHIM_DMA_PSIL_FIFO_ECC_TYPE,
      0u,
      NULL },
    { SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_RAM_WRAPPER0_FIFO_RAM_ID,
      SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_RAM_WRAPPER0_FIFO_INJECT_TYPE,
      SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_RAM_WRAPPER0_FIFO_ECC_TYPE,
      0u,
      NULL },
    { SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_RAM_WRAPPER1_FIFO_RAM_ID,
      SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_RAM_WRAPPER1_FIFO_INJECT_TYPE,
      SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_RAM_WRAPPER1_FIFO_ECC_TYPE,
      0u,
      NULL },
    { SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_RAM_WRAPPER2_FIFO_RAM_ID,
      SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_RAM_WRAPPER2_FIFO_INJECT_TYPE,
      SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_RAM_WRAPPER2_FIFO_ECC_TYPE,
      0u,
      NULL },
    { SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_RAM_WRAPPER3_FIFO_RAM_ID,
      SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_RAM_WRAPPER3_FIFO_INJECT_TYPE,
      SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_RAM_WRAPPER3_FIFO_ECC_TYPE,
      0u,
      NULL },
    { SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_VP0_VP_FIFO_RAM_ID,
      SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_VP0_VP_FIFO_INJECT_TYPE,
      SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_VP0_VP_FIFO_ECC_TYPE,
      0u,
      NULL },
    { SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_VP1_VP_FIFO_RAM_ID,
      SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_VP1_VP_FIFO_INJECT_TYPE,
      SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_VP1_VP_FIFO_ECC_TYPE,
      0u,
      NULL },
};
 
static const SDL_RAMIdEntry_t SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_RXMEM_RamIdTable[SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_RXMEM_NUM_RAMS] =
{
    { SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_RXMEM_EMMCSD4SS_SDHC_WRAP_RXMEM_RAM_ID,
      SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_RXMEM_EMMCSD4SS_SDHC_WRAP_RXMEM_INJECT_TYPE,
      SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_RXMEM_EMMCSD4SS_SDHC_WRAP_RXMEM_ECC_TYPE,
      0u,
      NULL },
};
 
static const SDL_RAMIdEntry_t SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_TXMEM_RamIdTable[SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_TXMEM_NUM_RAMS] =
{
    { SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_TXMEM_EMMCSD4SS_SDHC_WRAP_TXMEM_RAM_ID,
      SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_TXMEM_EMMCSD4SS_SDHC_WRAP_TXMEM_INJECT_TYPE,
      SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_TXMEM_EMMCSD4SS_SDHC_WRAP_TXMEM_ECC_TYPE,
      0u,
      NULL },
};
 
static const SDL_RAMIdEntry_t SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_RXMEM_RamIdTable[SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_RXMEM_NUM_RAMS] =
{
    { SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_RXMEM_EMMCSD4SS_SDHC_WRAP_RXMEM_RAM_ID,
      SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_RXMEM_EMMCSD4SS_SDHC_WRAP_RXMEM_INJECT_TYPE,
      SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_RXMEM_EMMCSD4SS_SDHC_WRAP_RXMEM_ECC_TYPE,
      0u,
      NULL },
};
 
static const SDL_RAMIdEntry_t SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_TXMEM_RamIdTable[SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_TXMEM_NUM_RAMS] =
{
    { SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_TXMEM_EMMCSD4SS_SDHC_WRAP_TXMEM_RAM_ID,
      SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_TXMEM_EMMCSD4SS_SDHC_WRAP_TXMEM_INJECT_TYPE,
      SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_TXMEM_EMMCSD4SS_SDHC_WRAP_TXMEM_ECC_TYPE,
      0u,
      NULL },
};
 
static const SDL_RAMIdEntry_t SDL_PDMA0_SAM62_PDMA_SPI_ECCAGGR_RamIdTable[SDL_PDMA0_SAM62_PDMA_SPI_ECCAGGR_NUM_RAMS] =
{
    { SDL_PDMA0_SAM62_PDMA_SPI_ECCAGGR_SAM62_PDMA_SPI_PDMA_CORE_TF0_F0_TPRAM_60X128_SBW_SR_RAM_ID,
      SDL_PDMA0_SAM62_PDMA_SPI_ECCAGGR_SAM62_PDMA_SPI_PDMA_CORE_TF0_F0_TPRAM_60X128_SBW_SR_INJECT_TYPE,
      SDL_PDMA0_SAM62_PDMA_SPI_ECCAGGR_SAM62_PDMA_SPI_PDMA_CORE_TF0_F0_TPRAM_60X128_SBW_SR_ECC_TYPE,
      0u,
      NULL },
    { SDL_PDMA0_SAM62_PDMA_SPI_ECCAGGR_SAM62_PDMA_SPI_PDMA_CORE_TF0_F1_TPRAM_60X128_SBW_SR_RAM_ID,
      SDL_PDMA0_SAM62_PDMA_SPI_ECCAGGR_SAM62_PDMA_SPI_PDMA_CORE_TF0_F1_TPRAM_60X128_SBW_SR_INJECT_TYPE,
      SDL_PDMA0_SAM62_PDMA_SPI_ECCAGGR_SAM62_PDMA_SPI_PDMA_CORE_TF0_F1_TPRAM_60X128_SBW_SR_ECC_TYPE,
      0u,
      NULL },
    { SDL_PDMA0_SAM62_PDMA_SPI_ECCAGGR_SAM62_PDMA_SPI_PDMA_CORE_RF0_F0_TPRAM_60X144_SBW_SR_RAM_ID,
      SDL_PDMA0_SAM62_PDMA_SPI_ECCAGGR_SAM62_PDMA_SPI_PDMA_CORE_RF0_F0_TPRAM_60X144_SBW_SR_INJECT_TYPE,
      SDL_PDMA0_SAM62_PDMA_SPI_ECCAGGR_SAM62_PDMA_SPI_PDMA_CORE_RF0_F0_TPRAM_60X144_SBW_SR_ECC_TYPE,
      0u,
      NULL },
    { SDL_PDMA0_SAM62_PDMA_SPI_ECCAGGR_SAM62_PDMA_SPI_PDMA_CORE_RF0_F1_TPRAM_60X144_SBW_SR_RAM_ID,
      SDL_PDMA0_SAM62_PDMA_SPI_ECCAGGR_SAM62_PDMA_SPI_PDMA_CORE_RF0_F1_TPRAM_60X144_SBW_SR_INJECT_TYPE,
      SDL_PDMA0_SAM62_PDMA_SPI_ECCAGGR_SAM62_PDMA_SPI_PDMA_CORE_RF0_F1_TPRAM_60X144_SBW_SR_ECC_TYPE,
      0u,
      NULL },
};
 
static const SDL_RAMIdEntry_t SDL_MMCSD0_EMMCSD8SS_ECC_AGGR_TXMEM_RamIdTable[SDL_MMCSD0_EMMCSD8SS_ECC_AGGR_TXMEM_NUM_RAMS] =
{
    { SDL_MMCSD0_EMMCSD8SS_ECC_AGGR_TXMEM_EMMCSD8SS_SDHC_WRAP_TXMEM_RAM_ID,
      SDL_MMCSD0_EMMCSD8SS_ECC_AGGR_TXMEM_EMMCSD8SS_SDHC_WRAP_TXMEM_INJECT_TYPE,
      SDL_MMCSD0_EMMCSD8SS_ECC_AGGR_TXMEM_EMMCSD8SS_SDHC_WRAP_TXMEM_ECC_TYPE,
      0u,
      NULL },
};
 
static const SDL_RAMIdEntry_t SDL_MMCSD0_EMMCSD8SS_ECC_AGGR_RXMEM_RamIdTable[SDL_MMCSD0_EMMCSD8SS_ECC_AGGR_RXMEM_NUM_RAMS] =
{
    { SDL_MMCSD0_EMMCSD8SS_ECC_AGGR_RXMEM_EMMCSD8SS_SDHC_WRAP_RXMEM_RAM_ID,
      SDL_MMCSD0_EMMCSD8SS_ECC_AGGR_RXMEM_EMMCSD8SS_SDHC_WRAP_RXMEM_INJECT_TYPE,
      SDL_MMCSD0_EMMCSD8SS_ECC_AGGR_RXMEM_EMMCSD8SS_SDHC_WRAP_RXMEM_ECC_TYPE,
      0u,
      NULL },
};
 
static const SDL_RAMIdEntry_t SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_RamIdTable[SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_NUM_RAMS] =
{
    { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_ITAG_RAM0_RAM_ID,
      SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_ITAG_RAM0_INJECT_TYPE,
      SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_ITAG_RAM0_ECC_TYPE,
      0u,
      NULL },
    { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_ITAG_RAM1_RAM_ID,
      SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_ITAG_RAM1_INJECT_TYPE,
      SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_ITAG_RAM1_ECC_TYPE,
      0u,
      NULL },
    { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_ITAG_RAM2_RAM_ID,
      SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_ITAG_RAM2_INJECT_TYPE,
      SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_ITAG_RAM2_ECC_TYPE,
      0u,
      NULL },
    { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_ITAG_RAM3_RAM_ID,
      SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_ITAG_RAM3_INJECT_TYPE,
      SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_ITAG_RAM3_ECC_TYPE,
      0u,
      NULL },
    { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_IDATA_BANK0_RAM_ID,
      SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_IDATA_BANK0_INJECT_TYPE,
      SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_IDATA_BANK0_ECC_TYPE,
      0u,
      NULL },
    { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_IDATA_BANK1_RAM_ID,
      SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_IDATA_BANK1_INJECT_TYPE,
      SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_IDATA_BANK1_ECC_TYPE,
      0u,
      NULL },
    { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_IDATA_BANK2_RAM_ID,
      SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_IDATA_BANK2_INJECT_TYPE,
      SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_IDATA_BANK2_ECC_TYPE,
      0u,
      NULL },
    { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_IDATA_BANK3_RAM_ID,
      SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_IDATA_BANK3_INJECT_TYPE,
      SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_IDATA_BANK3_ECC_TYPE,
      0u,
      NULL },
    { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DTAG_RAM0_RAM_ID,
      SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DTAG_RAM0_INJECT_TYPE,
      SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DTAG_RAM0_ECC_TYPE,
      0u,
      NULL },
    { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DTAG_RAM1_RAM_ID,
      SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DTAG_RAM1_INJECT_TYPE,
      SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DTAG_RAM1_ECC_TYPE,
      0u,
      NULL },
    { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DTAG_RAM2_RAM_ID,
      SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DTAG_RAM2_INJECT_TYPE,
      SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DTAG_RAM2_ECC_TYPE,
      0u,
      NULL },
    { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DTAG_RAM3_RAM_ID,
      SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DTAG_RAM3_INJECT_TYPE,
      SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DTAG_RAM3_ECC_TYPE,
      0u,
      NULL },
    { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDIRTY_RAM_RAM_ID,
      SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDIRTY_RAM_INJECT_TYPE,
      SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDIRTY_RAM_ECC_TYPE,
      0u,
      NULL },
    { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM0_RAM_ID,
      SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM0_INJECT_TYPE,
      SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM0_ECC_TYPE,
      0u,
      NULL },
    { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM1_RAM_ID,
      SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM1_INJECT_TYPE,
      SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM1_ECC_TYPE,
      0u,
      NULL },
    { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM2_RAM_ID,
      SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM2_INJECT_TYPE,
      SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM2_ECC_TYPE,
      0u,
      NULL },
    { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM3_RAM_ID,
      SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM3_INJECT_TYPE,
      SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM3_ECC_TYPE,
      0u,
      NULL },
    { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM4_RAM_ID,
      SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM4_INJECT_TYPE,
      SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM4_ECC_TYPE,
      0u,
      NULL },
    { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM5_RAM_ID,
      SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM5_INJECT_TYPE,
      SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM5_ECC_TYPE,
      0u,
      NULL },
    { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM6_RAM_ID,
      SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM6_INJECT_TYPE,
      SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM6_ECC_TYPE,
      0u,
      NULL },
    { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM7_RAM_ID,
      SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM7_INJECT_TYPE,
      SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM7_ECC_TYPE,
      0u,
      NULL },
    { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_ATCM0_BANK0_RAM_ID,
      SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_ATCM0_BANK0_INJECT_TYPE,
      SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_ATCM0_BANK0_ECC_TYPE,
      0u,
      NULL },
    { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_ATCM0_BANK1_RAM_ID,
      SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_ATCM0_BANK1_INJECT_TYPE,
      SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_ATCM0_BANK1_ECC_TYPE,
      0u,
      NULL },
    { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_B0TCM0_BANK0_RAM_ID,
      SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_B0TCM0_BANK0_INJECT_TYPE,
      SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_B0TCM0_BANK0_ECC_TYPE,
      0u,
      NULL },
    { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_B0TCM0_BANK1_RAM_ID,
      SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_B0TCM0_BANK1_INJECT_TYPE,
      SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_B0TCM0_BANK1_ECC_TYPE,
      0u,
      NULL },
    { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_B1TCM0_BANK0_RAM_ID,
      SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_B1TCM0_BANK0_INJECT_TYPE,
      SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_B1TCM0_BANK0_ECC_TYPE,
      0u,
      NULL },
    { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_B1TCM0_BANK1_RAM_ID,
      SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_B1TCM0_BANK1_INJECT_TYPE,
      SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_B1TCM0_BANK1_ECC_TYPE,
      0u,
      NULL },
    { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_PULSAR_KS_VIM_COMMON_CORE0_RAM_RAM_ID,
      SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_PULSAR_KS_VIM_COMMON_CORE0_RAM_INJECT_TYPE,
      SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_PULSAR_KS_VIM_COMMON_CORE0_RAM_ECC_TYPE,
      0u,
      NULL },
    { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_MEM_MST0_KSBUS_AXI2VBUSM_R_RDATA_BUFFER_RAM_ID,
      SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_MEM_MST0_KSBUS_AXI2VBUSM_R_RDATA_BUFFER_INJECT_TYPE,
      SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_MEM_MST0_KSBUS_AXI2VBUSM_R_RDATA_BUFFER_ECC_TYPE,
      0u,
      NULL },
};
 
static const SDL_RAMIdEntry_t SDL_SMS0_SMS_HSM_ECC_RamIdTable[SDL_SMS0_SMS_HSM_ECC_NUM_RAMS] =
{
    { SDL_SMS0_SMS_HSM_ECC_ISRAM0_RAMECC_RAM_ID,
      SDL_SMS0_SMS_HSM_ECC_ISRAM0_RAMECC_INJECT_TYPE,
      SDL_SMS0_SMS_HSM_ECC_ISRAM0_RAMECC_ECC_TYPE,
      0u,
      NULL },
    { SDL_SMS0_SMS_HSM_ECC_ISRAM1_RAMECC_RAM_ID,
      SDL_SMS0_SMS_HSM_ECC_ISRAM1_RAMECC_INJECT_TYPE,
      SDL_SMS0_SMS_HSM_ECC_ISRAM1_RAMECC_ECC_TYPE,
      0u,
      NULL },
    { SDL_SMS0_SMS_HSM_ECC_ISRAM0_BUSECC_RAM_ID,
      SDL_SMS0_SMS_HSM_ECC_ISRAM0_BUSECC_INJECT_TYPE,
      SDL_SMS0_SMS_HSM_ECC_ISRAM0_BUSECC_ECC_TYPE,
      SDL_SMS0_SMS_HSM_ECC_ISRAM0_BUSECC_MAX_NUM_CHECKERS,
      SDL_SMS0_SMS_HSM_ECC_ISRAM0_BUSECC_groupEntries },
    { SDL_SMS0_SMS_HSM_ECC_ISRAM1_BUSECC_RAM_ID,
      SDL_SMS0_SMS_HSM_ECC_ISRAM1_BUSECC_INJECT_TYPE,
      SDL_SMS0_SMS_HSM_ECC_ISRAM1_BUSECC_ECC_TYPE,
      SDL_SMS0_SMS_HSM_ECC_ISRAM1_BUSECC_MAX_NUM_CHECKERS,
      SDL_SMS0_SMS_HSM_ECC_ISRAM1_BUSECC_groupEntries },
    { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_RAM_ID,
      SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_INJECT_TYPE,
      SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_ECC_TYPE,
      SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_MAX_NUM_CHECKERS,
      SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_groupEntries },
    { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_RAM_ID,
      SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_INJECT_TYPE,
      SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_ECC_TYPE,
      SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_MAX_NUM_CHECKERS,
      SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_groupEntries },
    { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_RAM_ID,
      SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_INJECT_TYPE,
      SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_ECC_TYPE,
      SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
      SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_groupEntries },
    { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_RAM_ID,
      SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_INJECT_TYPE,
      SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_ECC_TYPE,
      SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
      SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_groupEntries },
    { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_DEFAULT_MMRS_SMS_HSM_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_RAM_ID,
      SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_DEFAULT_MMRS_SMS_HSM_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_INJECT_TYPE,
      SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_DEFAULT_MMRS_SMS_HSM_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_ECC_TYPE,
      SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_DEFAULT_MMRS_SMS_HSM_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
      SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_DEFAULT_MMRS_SMS_HSM_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_groupEntries },
    { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_RAM_ID,
      SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_INJECT_TYPE,
      SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_ECC_TYPE,
      SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
      SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_groupEntries },
    { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_RAM_ID,
      SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_INJECT_TYPE,
      SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_ECC_TYPE,
      SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_MAX_NUM_CHECKERS,
      SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_groupEntries },
    { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_WWRTI_CM_EDC_CTRL_BUSECC_RAM_ID,
      SDL_SMS0_SMS_HSM_ECC_SMS_HSM_WWRTI_CM_EDC_CTRL_BUSECC_INJECT_TYPE,
      SDL_SMS0_SMS_HSM_ECC_SMS_HSM_WWRTI_CM_EDC_CTRL_BUSECC_ECC_TYPE,
      SDL_SMS0_SMS_HSM_ECC_SMS_HSM_WWRTI_CM_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
      SDL_SMS0_SMS_HSM_ECC_SMS_HSM_WWRTI_CM_EDC_CTRL_BUSECC_groupEntries },
    { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_ECC_EDC_CTRL_RAM_ID,
      SDL_SMS0_SMS_HSM_ECC_SMS_HSM_ECC_EDC_CTRL_INJECT_TYPE,
      SDL_SMS0_SMS_HSM_ECC_SMS_HSM_ECC_EDC_CTRL_ECC_TYPE,
      SDL_SMS0_SMS_HSM_ECC_SMS_HSM_ECC_EDC_CTRL_MAX_NUM_CHECKERS,
      SDL_SMS0_SMS_HSM_ECC_SMS_HSM_ECC_EDC_CTRL_groupEntries },
};
 
static const SDL_RAMIdEntry_t SDL_SMS0_SMS_TIFS_ECC_RamIdTable[SDL_SMS0_SMS_TIFS_ECC_NUM_RAMS] =
{
    { SDL_SMS0_SMS_TIFS_ECC_ISRAM0_RAMECC_RAM_ID,
      SDL_SMS0_SMS_TIFS_ECC_ISRAM0_RAMECC_INJECT_TYPE,
      SDL_SMS0_SMS_TIFS_ECC_ISRAM0_RAMECC_ECC_TYPE,
      0u,
      NULL },
    { SDL_SMS0_SMS_TIFS_ECC_ISRAM1_RAMECC_RAM_ID,
      SDL_SMS0_SMS_TIFS_ECC_ISRAM1_RAMECC_INJECT_TYPE,
      SDL_SMS0_SMS_TIFS_ECC_ISRAM1_RAMECC_ECC_TYPE,
      0u,
      NULL },
    { SDL_SMS0_SMS_TIFS_ECC_ISRAM0_BUSECC_RAM_ID,
      SDL_SMS0_SMS_TIFS_ECC_ISRAM0_BUSECC_INJECT_TYPE,
      SDL_SMS0_SMS_TIFS_ECC_ISRAM0_BUSECC_ECC_TYPE,
      SDL_SMS0_SMS_TIFS_ECC_ISRAM0_BUSECC_MAX_NUM_CHECKERS,
      SDL_SMS0_SMS_TIFS_ECC_ISRAM0_BUSECC_groupEntries },
    { SDL_SMS0_SMS_TIFS_ECC_ISRAM1_BUSECC_RAM_ID,
      SDL_SMS0_SMS_TIFS_ECC_ISRAM1_BUSECC_INJECT_TYPE,
      SDL_SMS0_SMS_TIFS_ECC_ISRAM1_BUSECC_ECC_TYPE,
      SDL_SMS0_SMS_TIFS_ECC_ISRAM1_BUSECC_MAX_NUM_CHECKERS,
      SDL_SMS0_SMS_TIFS_ECC_ISRAM1_BUSECC_groupEntries },
    { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_RAM_ID,
      SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_INJECT_TYPE,
      SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_ECC_TYPE,
      SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_MAX_NUM_CHECKERS,
      SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_groupEntries },
    { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_RAM_ID,
      SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_INJECT_TYPE,
      SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_ECC_TYPE,
      SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_MAX_NUM_CHECKERS,
      SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_groupEntries },
    { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_2_RAM_ID,
      SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_2_INJECT_TYPE,
      SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_2_ECC_TYPE,
      SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_2_MAX_NUM_CHECKERS,
      SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_2_groupEntries },
    { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_RAM_ID,
      SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_INJECT_TYPE,
      SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_ECC_TYPE,
      SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_MAX_NUM_CHECKERS,
      SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_groupEntries },
    { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IFWMGR_M_P2P_BRIDGE_IFWMGR_M_BRIDGE_BUSECC_RAM_ID,
      SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IFWMGR_M_P2P_BRIDGE_IFWMGR_M_BRIDGE_BUSECC_INJECT_TYPE,
      SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IFWMGR_M_P2P_BRIDGE_IFWMGR_M_BRIDGE_BUSECC_ECC_TYPE,
      SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IFWMGR_M_P2P_BRIDGE_IFWMGR_M_BRIDGE_BUSECC_MAX_NUM_CHECKERS,
      SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IFWMGR_M_P2P_BRIDGE_IFWMGR_M_BRIDGE_BUSECC_groupEntries },
    { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_RAM_ID,
      SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_INJECT_TYPE,
      SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_ECC_TYPE,
      SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_MAX_NUM_CHECKERS,
      SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_groupEntries },
    { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_RAM_ID,
      SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_INJECT_TYPE,
      SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_ECC_TYPE,
      SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_MAX_NUM_CHECKERS,
      SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_groupEntries },
    { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_RAM_ID,
      SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_INJECT_TYPE,
      SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_ECC_TYPE,
      SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
      SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_groupEntries },
    { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_DEFAULT_MMRS_SMS_TIFS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_RAM_ID,
      SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_DEFAULT_MMRS_SMS_TIFS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_INJECT_TYPE,
      SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_DEFAULT_MMRS_SMS_TIFS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_ECC_TYPE,
      SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_DEFAULT_MMRS_SMS_TIFS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
      SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_DEFAULT_MMRS_SMS_TIFS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_groupEntries },
    { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_RAM_ID,
      SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_INJECT_TYPE,
      SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_ECC_TYPE,
      SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
      SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_groupEntries },
    { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_RAM_ID,
      SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_INJECT_TYPE,
      SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_ECC_TYPE,
      SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_MAX_NUM_CHECKERS,
      SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_groupEntries },
    { SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_RAM_ID,
      SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_INJECT_TYPE,
      SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_ECC_TYPE,
      SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
      SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_groupEntries },
    { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_DMSS_HSM_P2P_BRIDGE_SMS_DMSS_HSM_BRIDGE_BUSECC_RAM_ID,
      SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_DMSS_HSM_P2P_BRIDGE_SMS_DMSS_HSM_BRIDGE_BUSECC_INJECT_TYPE,
      SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_DMSS_HSM_P2P_BRIDGE_SMS_DMSS_HSM_BRIDGE_BUSECC_ECC_TYPE,
      SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_DMSS_HSM_P2P_BRIDGE_SMS_DMSS_HSM_BRIDGE_BUSECC_MAX_NUM_CHECKERS,
      SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_DMSS_HSM_P2P_BRIDGE_SMS_DMSS_HSM_BRIDGE_BUSECC_groupEntries },
    { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_WWRTI_CM_EDC_CTRL_BUSECC_RAM_ID,
      SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_WWRTI_CM_EDC_CTRL_BUSECC_INJECT_TYPE,
      SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_WWRTI_CM_EDC_CTRL_BUSECC_ECC_TYPE,
      SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_WWRTI_CM_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
      SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_WWRTI_CM_EDC_CTRL_BUSECC_groupEntries },
    { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CM_EDC_CTRL_BUSECC_RAM_ID,
      SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CM_EDC_CTRL_BUSECC_INJECT_TYPE,
      SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CM_EDC_CTRL_BUSECC_ECC_TYPE,
      SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CM_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
      SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CM_EDC_CTRL_BUSECC_groupEntries },
    { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_SEC_CM_EDC_CTRL_BUSECC_RAM_ID,
      SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_SEC_CM_EDC_CTRL_BUSECC_INJECT_TYPE,
      SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_SEC_CM_EDC_CTRL_BUSECC_ECC_TYPE,
      SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_SEC_CM_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
      SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_SEC_CM_EDC_CTRL_BUSECC_groupEntries },
    { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_ECC_EDC_CTRL_RAM_ID,
      SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_ECC_EDC_CTRL_INJECT_TYPE,
      SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_ECC_EDC_CTRL_ECC_TYPE,
      SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_ECC_EDC_CTRL_MAX_NUM_CHECKERS,
      SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_ECC_EDC_CTRL_groupEntries },
};
 
static const SDL_RAMIdEntry_t SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_RamIdTable[SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_NUM_RAMS] =
{
    { SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_BLAZAR_VBUSP_M_P2P_DST_BUSECC_RAM_ID,
      SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_BLAZAR_VBUSP_M_P2P_DST_BUSECC_INJECT_TYPE,
      SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_BLAZAR_VBUSP_M_P2P_DST_BUSECC_ECC_TYPE,
      SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_BLAZAR_VBUSP_M_P2P_DST_BUSECC_MAX_NUM_CHECKERS,
      SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_BLAZAR_VBUSP_M_P2P_DST_BUSECC_groupEntries },
    { SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_BLAZAR_VBUSP_M_P2P_SRC_BUSECC_RAM_ID,
      SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_BLAZAR_VBUSP_M_P2P_SRC_BUSECC_INJECT_TYPE,
      SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_BLAZAR_VBUSP_M_P2P_SRC_BUSECC_ECC_TYPE,
      SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_BLAZAR_VBUSP_M_P2P_SRC_BUSECC_MAX_NUM_CHECKERS,
      SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_BLAZAR_VBUSP_M_P2P_SRC_BUSECC_groupEntries },
    { SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_BLAZAR_VBUSP_S_P2P_DST_BUSECC_RAM_ID,
      SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_BLAZAR_VBUSP_S_P2P_DST_BUSECC_INJECT_TYPE,
      SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_BLAZAR_VBUSP_S_P2P_DST_BUSECC_ECC_TYPE,
      SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_BLAZAR_VBUSP_S_P2P_DST_BUSECC_MAX_NUM_CHECKERS,
      SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_BLAZAR_VBUSP_S_P2P_DST_BUSECC_groupEntries },
    { SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_BLAZAR_VBUSP_S_P2P_SRC_BUSECC_RAM_ID,
      SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_BLAZAR_VBUSP_S_P2P_SRC_BUSECC_INJECT_TYPE,
      SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_BLAZAR_VBUSP_S_P2P_SRC_BUSECC_ECC_TYPE,
      SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_BLAZAR_VBUSP_S_P2P_SRC_BUSECC_MAX_NUM_CHECKERS,
      SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_BLAZAR_VBUSP_S_P2P_SRC_BUSECC_groupEntries },
    { SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_IAM62_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM62_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_BUSECC_RAM_ID,
      SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_IAM62_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM62_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_BUSECC_INJECT_TYPE,
      SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_IAM62_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM62_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_BUSECC_ECC_TYPE,
      SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_IAM62_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM62_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_BUSECC_MAX_NUM_CHECKERS,
      SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_IAM62_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM62_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_BUSECC_groupEntries },
    { SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_IBLAZAR_MCU_0_VBUSP_S_P2P_BRIDGE_IBLAZAR_MCU_0_VBUSP_S_BRIDGE_BUSECC_RAM_ID,
      SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_IBLAZAR_MCU_0_VBUSP_S_P2P_BRIDGE_IBLAZAR_MCU_0_VBUSP_S_BRIDGE_BUSECC_INJECT_TYPE,
      SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_IBLAZAR_MCU_0_VBUSP_S_P2P_BRIDGE_IBLAZAR_MCU_0_VBUSP_S_BRIDGE_BUSECC_ECC_TYPE,
      SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_IBLAZAR_MCU_0_VBUSP_S_P2P_BRIDGE_IBLAZAR_MCU_0_VBUSP_S_BRIDGE_BUSECC_MAX_NUM_CHECKERS,
      SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_IBLAZAR_MCU_0_VBUSP_S_P2P_BRIDGE_IBLAZAR_MCU_0_VBUSP_S_BRIDGE_BUSECC_groupEntries },
    { SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_ISAM62_CENTRAL2MCU_VBUSM_GASKET_MCU_0_EDC_CTRL_RAM_ID,
      SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_ISAM62_CENTRAL2MCU_VBUSM_GASKET_MCU_0_EDC_CTRL_INJECT_TYPE,
      SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_ISAM62_CENTRAL2MCU_VBUSM_GASKET_MCU_0_EDC_CTRL_ECC_TYPE,
      SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_ISAM62_CENTRAL2MCU_VBUSM_GASKET_MCU_0_EDC_CTRL_MAX_NUM_CHECKERS,
      SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_ISAM62_CENTRAL2MCU_VBUSM_GASKET_MCU_0_EDC_CTRL_groupEntries },
    { SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_ISAM62_MCU2CENTRAL_VBUSM_GASKET_MCU_0_CFG_P2P_BRIDGE_ISAM62_MCU2CENTRAL_VBUSM_GASKET_MCU_0_CFG_BRIDGE_BUSECC_RAM_ID,
      SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_ISAM62_MCU2CENTRAL_VBUSM_GASKET_MCU_0_CFG_P2P_BRIDGE_ISAM62_MCU2CENTRAL_VBUSM_GASKET_MCU_0_CFG_BRIDGE_BUSECC_INJECT_TYPE,
      SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_ISAM62_MCU2CENTRAL_VBUSM_GASKET_MCU_0_CFG_P2P_BRIDGE_ISAM62_MCU2CENTRAL_VBUSM_GASKET_MCU_0_CFG_BRIDGE_BUSECC_ECC_TYPE,
      SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_ISAM62_MCU2CENTRAL_VBUSM_GASKET_MCU_0_CFG_P2P_BRIDGE_ISAM62_MCU2CENTRAL_VBUSM_GASKET_MCU_0_CFG_BRIDGE_BUSECC_MAX_NUM_CHECKERS,
      SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_ISAM62_MCU2CENTRAL_VBUSM_GASKET_MCU_0_CFG_P2P_BRIDGE_ISAM62_MCU2CENTRAL_VBUSM_GASKET_MCU_0_CFG_BRIDGE_BUSECC_groupEntries },
    { SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_ISAM62_MCU2CENTRAL_VBUSM_GASKET_MCU_0_EDC_CTRL_RAM_ID,
      SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_ISAM62_MCU2CENTRAL_VBUSM_GASKET_MCU_0_EDC_CTRL_INJECT_TYPE,
      SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_ISAM62_MCU2CENTRAL_VBUSM_GASKET_MCU_0_EDC_CTRL_ECC_TYPE,
      SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_ISAM62_MCU2CENTRAL_VBUSM_GASKET_MCU_0_EDC_CTRL_MAX_NUM_CHECKERS,
      SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_ISAM62_MCU2CENTRAL_VBUSM_GASKET_MCU_0_EDC_CTRL_groupEntries },
    { SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_ISAM62_MCU2CENTRAL_VBUSM_GASKET_MCU_0_RD_RAMECC_RAM_ID,
      SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_ISAM62_MCU2CENTRAL_VBUSM_GASKET_MCU_0_RD_RAMECC_INJECT_TYPE,
      SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_ISAM62_MCU2CENTRAL_VBUSM_GASKET_MCU_0_RD_RAMECC_ECC_TYPE,
      0u,
      NULL },
    { SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_ISAM62_MCU2CENTRAL_VBUSM_GASKET_MCU_0_WR_RAMECC_RAM_ID,
      SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_ISAM62_MCU2CENTRAL_VBUSM_GASKET_MCU_0_WR_RAMECC_INJECT_TYPE,
      SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_ISAM62_MCU2CENTRAL_VBUSM_GASKET_MCU_0_WR_RAMECC_ECC_TYPE,
      0u,
      NULL },
    { SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_ISAM62_MCU2DM_VBUSM_GASKET_MCU_1_CFG_P2P_BRIDGE_ISAM62_MCU2DM_VBUSM_GASKET_MCU_1_CFG_BRIDGE_BUSECC_RAM_ID,
      SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_ISAM62_MCU2DM_VBUSM_GASKET_MCU_1_CFG_P2P_BRIDGE_ISAM62_MCU2DM_VBUSM_GASKET_MCU_1_CFG_BRIDGE_BUSECC_INJECT_TYPE,
      SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_ISAM62_MCU2DM_VBUSM_GASKET_MCU_1_CFG_P2P_BRIDGE_ISAM62_MCU2DM_VBUSM_GASKET_MCU_1_CFG_BRIDGE_BUSECC_ECC_TYPE,
      SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_ISAM62_MCU2DM_VBUSM_GASKET_MCU_1_CFG_P2P_BRIDGE_ISAM62_MCU2DM_VBUSM_GASKET_MCU_1_CFG_BRIDGE_BUSECC_MAX_NUM_CHECKERS,
      SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_ISAM62_MCU2DM_VBUSM_GASKET_MCU_1_CFG_P2P_BRIDGE_ISAM62_MCU2DM_VBUSM_GASKET_MCU_1_CFG_BRIDGE_BUSECC_groupEntries },
    { SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_ISAM62_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_RAM_ID,
      SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_ISAM62_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_INJECT_TYPE,
      SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_ISAM62_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_ECC_TYPE,
      SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_ISAM62_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_MAX_NUM_CHECKERS,
      SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_ISAM62_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_groupEntries },
    { SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_ISAM62_MCU2DM_VBUSM_GASKET_MCU_1_RD_RAMECC_RAM_ID,
      SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_ISAM62_MCU2DM_VBUSM_GASKET_MCU_1_RD_RAMECC_INJECT_TYPE,
      SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_ISAM62_MCU2DM_VBUSM_GASKET_MCU_1_RD_RAMECC_ECC_TYPE,
      0u,
      NULL },
    { SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_ISAM62_MCU2DM_VBUSM_GASKET_MCU_1_WR_RAMECC_RAM_ID,
      SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_ISAM62_MCU2DM_VBUSM_GASKET_MCU_1_WR_RAMECC_INJECT_TYPE,
      SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_ISAM62_MCU2DM_VBUSM_GASKET_MCU_1_WR_RAMECC_ECC_TYPE,
      0u,
      NULL },
    { SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_ISAM62_MCU_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM62_MCU_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_RAM_ID,
      SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_ISAM62_MCU_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM62_MCU_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_INJECT_TYPE,
      SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_ISAM62_MCU_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM62_MCU_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_ECC_TYPE,
      SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_ISAM62_MCU_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM62_MCU_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_MAX_NUM_CHECKERS,
      SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_ISAM62_MCU_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM62_MCU_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_groupEntries },
    { SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_RAM_ID,
      SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_INJECT_TYPE,
      SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_ECC_TYPE,
      SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_MAX_NUM_CHECKERS,
      SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_groupEntries },
    { SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_RAM_ID,
      SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_INJECT_TYPE,
      SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_ECC_TYPE,
      SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_MAX_NUM_CHECKERS,
      SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_groupEntries },
    { SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_RAM_ID,
      SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_INJECT_TYPE,
      SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_ECC_TYPE,
      SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_MAX_NUM_CHECKERS,
      SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_groupEntries },
    { SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_RAM_ID,
      SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_INJECT_TYPE,
      SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_ECC_TYPE,
      SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_MAX_NUM_CHECKERS,
      SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_groupEntries },
    { SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_2_RAM_ID,
      SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_2_INJECT_TYPE,
      SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_2_ECC_TYPE,
      SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_2_MAX_NUM_CHECKERS,
      SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_2_groupEntries },
    { SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_RAM_ID,
      SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_INJECT_TYPE,
      SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_ECC_TYPE,
      SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_MAX_NUM_CHECKERS,
      SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_groupEntries },
    { SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_RAM_ID,
      SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_INJECT_TYPE,
      SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_ECC_TYPE,
      SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_MAX_NUM_CHECKERS,
      SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_groupEntries },
    { SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_P2P_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_BRIDGE_DST_BUSECC_RAM_ID,
      SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_P2P_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_BRIDGE_DST_BUSECC_INJECT_TYPE,
      SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_P2P_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_BRIDGE_DST_BUSECC_ECC_TYPE,
      SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_P2P_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS,
      SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_P2P_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_BRIDGE_DST_BUSECC_groupEntries },
    { SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_P2P_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_BRIDGE_SRC_BUSECC_RAM_ID,
      SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_P2P_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_BRIDGE_SRC_BUSECC_INJECT_TYPE,
      SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_P2P_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_BRIDGE_SRC_BUSECC_ECC_TYPE,
      SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_P2P_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS,
      SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_P2P_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_BRIDGE_SRC_BUSECC_groupEntries },
    { SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_CBASS_DEFAULT_ERR_AM62_MCU_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_RAM_ID,
      SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_CBASS_DEFAULT_ERR_AM62_MCU_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_INJECT_TYPE,
      SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_CBASS_DEFAULT_ERR_AM62_MCU_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_ECC_TYPE,
      SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_CBASS_DEFAULT_ERR_AM62_MCU_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
      SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_CBASS_DEFAULT_ERR_AM62_MCU_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_groupEntries },
    { SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_CBASS_DEFAULT_MMRS_AM62_MCU_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_RAM_ID,
      SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_CBASS_DEFAULT_MMRS_AM62_MCU_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_INJECT_TYPE,
      SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_CBASS_DEFAULT_MMRS_AM62_MCU_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_ECC_TYPE,
      SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_CBASS_DEFAULT_MMRS_AM62_MCU_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
      SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_CBASS_DEFAULT_MMRS_AM62_MCU_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_groupEntries },
    { SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_CBASS_INT_DMSC_SCR_AM62_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_RAM_ID,
      SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_CBASS_INT_DMSC_SCR_AM62_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_INJECT_TYPE,
      SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_CBASS_INT_DMSC_SCR_AM62_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_ECC_TYPE,
      SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_CBASS_INT_DMSC_SCR_AM62_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
      SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_CBASS_INT_DMSC_SCR_AM62_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_groupEntries },
    { SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_RAM_ID,
      SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_INJECT_TYPE,
      SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_ECC_TYPE,
      SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_MAX_NUM_CHECKERS,
      SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_groupEntries },
    { SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_ERR_SCR_AM62_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_RAM_ID,
      SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_ERR_SCR_AM62_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_INJECT_TYPE,
      SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_ERR_SCR_AM62_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_ECC_TYPE,
      SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_ERR_SCR_AM62_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
      SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_ERR_SCR_AM62_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_groupEntries },
    { SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_RAM_ID,
      SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_INJECT_TYPE,
      SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_ECC_TYPE,
      SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_MAX_NUM_CHECKERS,
      SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_groupEntries },
    { SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_EXPORT_AM62_MAIN_CENTRAL_CBASS_TO_AM62_MCU_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62_MAIN_CENTRAL_CBASS_TO_AM62_MCU_CBASS_DATA_L0_BRIDGE_BUSECC_RAM_ID,
      SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_EXPORT_AM62_MAIN_CENTRAL_CBASS_TO_AM62_MCU_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62_MAIN_CENTRAL_CBASS_TO_AM62_MCU_CBASS_DATA_L0_BRIDGE_BUSECC_INJECT_TYPE,
      SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_EXPORT_AM62_MAIN_CENTRAL_CBASS_TO_AM62_MCU_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62_MAIN_CENTRAL_CBASS_TO_AM62_MCU_CBASS_DATA_L0_BRIDGE_BUSECC_ECC_TYPE,
      SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_EXPORT_AM62_MAIN_CENTRAL_CBASS_TO_AM62_MCU_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62_MAIN_CENTRAL_CBASS_TO_AM62_MCU_CBASS_DATA_L0_BRIDGE_BUSECC_MAX_NUM_CHECKERS,
      SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_EXPORT_AM62_MAIN_CENTRAL_CBASS_TO_AM62_MCU_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62_MAIN_CENTRAL_CBASS_TO_AM62_MCU_CBASS_DATA_L0_BRIDGE_BUSECC_groupEntries },
    { SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_EXPORT_AM62_MCU_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_P2P_BRIDGE_EXPORT_AM62_MCU_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_DST_BUSECC_RAM_ID,
      SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_EXPORT_AM62_MCU_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_P2P_BRIDGE_EXPORT_AM62_MCU_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_DST_BUSECC_INJECT_TYPE,
      SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_EXPORT_AM62_MCU_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_P2P_BRIDGE_EXPORT_AM62_MCU_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_DST_BUSECC_ECC_TYPE,
      SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_EXPORT_AM62_MCU_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_P2P_BRIDGE_EXPORT_AM62_MCU_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS,
      SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_EXPORT_AM62_MCU_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_P2P_BRIDGE_EXPORT_AM62_MCU_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_DST_BUSECC_groupEntries },
    { SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_EXPORT_AM62_MCU_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_P2P_BRIDGE_EXPORT_AM62_MCU_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_SRC_BUSECC_RAM_ID,
      SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_EXPORT_AM62_MCU_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_P2P_BRIDGE_EXPORT_AM62_MCU_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_SRC_BUSECC_INJECT_TYPE,
      SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_EXPORT_AM62_MCU_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_P2P_BRIDGE_EXPORT_AM62_MCU_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_SRC_BUSECC_ECC_TYPE,
      SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_EXPORT_AM62_MCU_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_P2P_BRIDGE_EXPORT_AM62_MCU_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS,
      SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_AM62_MCU_CBASS_EXPORT_AM62_MCU_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_P2P_BRIDGE_EXPORT_AM62_MCU_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_SRC_BUSECC_groupEntries },
    { SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_SAM62_MCU_ECC_AGGR_EDC_CTRL_RAM_ID,
      SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_SAM62_MCU_ECC_AGGR_EDC_CTRL_INJECT_TYPE,
      SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_SAM62_MCU_ECC_AGGR_EDC_CTRL_ECC_TYPE,
      SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_SAM62_MCU_ECC_AGGR_EDC_CTRL_MAX_NUM_CHECKERS,
      SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_SAM62_MCU_ECC_AGGR_EDC_CTRL_groupEntries },
};
 
static const SDL_RAMIdEntry_t SDL_USB1_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_RamIdTable[SDL_USB1_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_NUM_RAMS] =
{
    { SDL_USB1_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_USB2SS_16FFC_USB2SS_CORE_AXI2VBUSM_MST_KSBUS_AXI2VBUSM_R_RDATA_BUFFER_RAM_ID,
      SDL_USB1_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_USB2SS_16FFC_USB2SS_CORE_AXI2VBUSM_MST_KSBUS_AXI2VBUSM_R_RDATA_BUFFER_INJECT_TYPE,
      SDL_USB1_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_USB2SS_16FFC_USB2SS_CORE_AXI2VBUSM_MST_KSBUS_AXI2VBUSM_R_RDATA_BUFFER_ECC_TYPE,
      0u,
      NULL },
    { SDL_USB1_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_USB2SS_16FFC_USB2SS_CORE_RAMS_MEM_CTRL_RAM0_RAM_ID,
      SDL_USB1_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_USB2SS_16FFC_USB2SS_CORE_RAMS_MEM_CTRL_RAM0_INJECT_TYPE,
      SDL_USB1_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_USB2SS_16FFC_USB2SS_CORE_RAMS_MEM_CTRL_RAM0_ECC_TYPE,
      0u,
      NULL },
};
 
static const SDL_RAMIdEntry_t SDL_USB0_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_RamIdTable[SDL_USB0_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_NUM_RAMS] =
{
    { SDL_USB0_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_USB2SS_16FFC_USB2SS_CORE_AXI2VBUSM_MST_KSBUS_AXI2VBUSM_R_RDATA_BUFFER_RAM_ID,
      SDL_USB0_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_USB2SS_16FFC_USB2SS_CORE_AXI2VBUSM_MST_KSBUS_AXI2VBUSM_R_RDATA_BUFFER_INJECT_TYPE,
      SDL_USB0_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_USB2SS_16FFC_USB2SS_CORE_AXI2VBUSM_MST_KSBUS_AXI2VBUSM_R_RDATA_BUFFER_ECC_TYPE,
      0u,
      NULL },
    { SDL_USB0_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_USB2SS_16FFC_USB2SS_CORE_RAMS_MEM_CTRL_RAM0_RAM_ID,
      SDL_USB0_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_USB2SS_16FFC_USB2SS_CORE_RAMS_MEM_CTRL_RAM0_INJECT_TYPE,
      SDL_USB0_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_USB2SS_16FFC_USB2SS_CORE_RAMS_MEM_CTRL_RAM0_ECC_TYPE,
      0u,
      NULL },
};
 
static const SDL_RAMIdEntry_t SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_RamIdTable[SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_NUM_RAMS] =
{
    { SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_RAM_ID,
      SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_INJECT_TYPE,
      SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_ECC_TYPE,
      SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_MAX_NUM_CHECKERS,
      SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_groupEntries },
    { SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_RAM_ID,
      SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_INJECT_TYPE,
      SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_ECC_TYPE,
      SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_MAX_NUM_CHECKERS,
      SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_groupEntries },
    { SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_PLL_MMR_EDC_CTRL_BUSECC_RAM_ID,
      SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_PLL_MMR_EDC_CTRL_BUSECC_INJECT_TYPE,
      SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_PLL_MMR_EDC_CTRL_BUSECC_ECC_TYPE,
      SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_PLL_MMR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
      SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_MCU_PLL_MMR_EDC_CTRL_BUSECC_groupEntries },
    { SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_RAM_ID,
      SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_INJECT_TYPE,
      SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_ECC_TYPE,
      SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_MAX_NUM_CHECKERS,
      SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_groupEntries },
    { SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_RAM_ID,
      SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_INJECT_TYPE,
      SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_ECC_TYPE,
      SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_MAX_NUM_CHECKERS,
      SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_groupEntries },
    { SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_RAM_ID,
      SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_INJECT_TYPE,
      SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_ECC_TYPE,
      SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_MAX_NUM_CHECKERS,
      SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_groupEntries },
    { SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_IAM62_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM62_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_BRIDGE_BUSECC_RAM_ID,
      SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_IAM62_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM62_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_BRIDGE_BUSECC_INJECT_TYPE,
      SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_IAM62_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM62_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_BRIDGE_BUSECC_ECC_TYPE,
      SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_IAM62_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM62_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_BRIDGE_BUSECC_MAX_NUM_CHECKERS,
      SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_IAM62_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM62_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_BRIDGE_BUSECC_groupEntries },
    { SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_ISAM62_DM2WS_VBUSM_GASKET_MCU_0_EDC_CTRL_RAM_ID,
      SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_ISAM62_DM2WS_VBUSM_GASKET_MCU_0_EDC_CTRL_INJECT_TYPE,
      SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_ISAM62_DM2WS_VBUSM_GASKET_MCU_0_EDC_CTRL_ECC_TYPE,
      SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_ISAM62_DM2WS_VBUSM_GASKET_MCU_0_EDC_CTRL_MAX_NUM_CHECKERS,
      SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_ISAM62_DM2WS_VBUSM_GASKET_MCU_0_EDC_CTRL_groupEntries },
    { SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_ISAM62_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM62_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_BRIDGE_BUSECC_RAM_ID,
      SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_ISAM62_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM62_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_BRIDGE_BUSECC_INJECT_TYPE,
      SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_ISAM62_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM62_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_BRIDGE_BUSECC_ECC_TYPE,
      SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_ISAM62_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM62_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_BRIDGE_BUSECC_MAX_NUM_CHECKERS,
      SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_ISAM62_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM62_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_BRIDGE_BUSECC_groupEntries },
    { SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_RAM_ID,
      SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_INJECT_TYPE,
      SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_ECC_TYPE,
      SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_MAX_NUM_CHECKERS,
      SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_groupEntries },
    { SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_0_RAM_ID,
      SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_0_INJECT_TYPE,
      SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_0_ECC_TYPE,
      SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_0_MAX_NUM_CHECKERS,
      SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_0_groupEntries },
    { SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_1_RAM_ID,
      SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_1_INJECT_TYPE,
      SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_1_ECC_TYPE,
      SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_1_MAX_NUM_CHECKERS,
      SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_AM62_WKUP_SAFE_CBASS_SCRP_SAFE_SCR_EDC_CTRL_BUSECC_1_groupEntries },
    { SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_CBASS_DEFAULT_ERR_AM62_WKUP_SAFE_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_RAM_ID,
      SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_CBASS_DEFAULT_ERR_AM62_WKUP_SAFE_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_INJECT_TYPE,
      SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_CBASS_DEFAULT_ERR_AM62_WKUP_SAFE_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_ECC_TYPE,
      SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_CBASS_DEFAULT_ERR_AM62_WKUP_SAFE_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
      SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_CBASS_DEFAULT_ERR_AM62_WKUP_SAFE_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_groupEntries },
    { SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_ERR_SCR_AM62_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_RAM_ID,
      SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_ERR_SCR_AM62_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_INJECT_TYPE,
      SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_ERR_SCR_AM62_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_ECC_TYPE,
      SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_ERR_SCR_AM62_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
      SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_ERR_SCR_AM62_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_groupEntries },
    { SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_RAM_ID,
      SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_INJECT_TYPE,
      SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_ECC_TYPE,
      SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_MAX_NUM_CHECKERS,
      SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_groupEntries },
    { SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_RAM_ID,
      SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_INJECT_TYPE,
      SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_ECC_TYPE,
      SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_MAX_NUM_CHECKERS,
      SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_AM62_WKUP_SAFE_CBASS_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62_WKUP_DM_CBASS_TO_AM62_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_groupEntries },
    { SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_SAM62_WKUP_SAFE_ECC_AGGR_EDC_CTRL_RAM_ID,
      SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_SAM62_WKUP_SAFE_ECC_AGGR_EDC_CTRL_INJECT_TYPE,
      SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_SAM62_WKUP_SAFE_ECC_AGGR_EDC_CTRL_ECC_TYPE,
      SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_SAM62_WKUP_SAFE_ECC_AGGR_EDC_CTRL_MAX_NUM_CHECKERS,
      SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_SAM62_WKUP_SAFE_ECC_AGGR_EDC_CTRL_groupEntries },
};
 
static const SDL_RAMIdEntry_t SDL_PDMA1_SAM62_PDMA_UART_ECCAGGR_RamIdTable[SDL_PDMA1_SAM62_PDMA_UART_ECCAGGR_NUM_RAMS] =
{
    { SDL_PDMA1_SAM62_PDMA_UART_ECCAGGR_SAM62_PDMA_UART_PDMA_CORE_TF0_F0_TPRAM_28X128_SBW_SR_RAM_ID,
      SDL_PDMA1_SAM62_PDMA_UART_ECCAGGR_SAM62_PDMA_UART_PDMA_CORE_TF0_F0_TPRAM_28X128_SBW_SR_INJECT_TYPE,
      SDL_PDMA1_SAM62_PDMA_UART_ECCAGGR_SAM62_PDMA_UART_PDMA_CORE_TF0_F0_TPRAM_28X128_SBW_SR_ECC_TYPE,
      0u,
      NULL },
    { SDL_PDMA1_SAM62_PDMA_UART_ECCAGGR_SAM62_PDMA_UART_PDMA_CORE_TF0_F1_TPRAM_28X128_SBW_SR_RAM_ID,
      SDL_PDMA1_SAM62_PDMA_UART_ECCAGGR_SAM62_PDMA_UART_PDMA_CORE_TF0_F1_TPRAM_28X128_SBW_SR_INJECT_TYPE,
      SDL_PDMA1_SAM62_PDMA_UART_ECCAGGR_SAM62_PDMA_UART_PDMA_CORE_TF0_F1_TPRAM_28X128_SBW_SR_ECC_TYPE,
      0u,
      NULL },
    { SDL_PDMA1_SAM62_PDMA_UART_ECCAGGR_SAM62_PDMA_UART_PDMA_CORE_RF0_F0_TPRAM_28X144_SBW_SR_RAM_ID,
      SDL_PDMA1_SAM62_PDMA_UART_ECCAGGR_SAM62_PDMA_UART_PDMA_CORE_RF0_F0_TPRAM_28X144_SBW_SR_INJECT_TYPE,
      SDL_PDMA1_SAM62_PDMA_UART_ECCAGGR_SAM62_PDMA_UART_PDMA_CORE_RF0_F0_TPRAM_28X144_SBW_SR_ECC_TYPE,
      0u,
      NULL },
    { SDL_PDMA1_SAM62_PDMA_UART_ECCAGGR_SAM62_PDMA_UART_PDMA_CORE_RF0_F1_TPRAM_28X144_SBW_SR_RAM_ID,
      SDL_PDMA1_SAM62_PDMA_UART_ECCAGGR_SAM62_PDMA_UART_PDMA_CORE_RF0_F1_TPRAM_28X144_SBW_SR_INJECT_TYPE,
      SDL_PDMA1_SAM62_PDMA_UART_ECCAGGR_SAM62_PDMA_UART_PDMA_CORE_RF0_F1_TPRAM_28X144_SBW_SR_ECC_TYPE,
      0u,
      NULL },
};
 
static const SDL_RAMIdEntry_t SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_RamIdTable[SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_NUM_RAMS] =
{
    { SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_ID,
      SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_INJECT_TYPE,
      SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_ECC_TYPE,
      0u,
      NULL },
    { SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_RAM_ID,
      SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_INJECT_TYPE,
      SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_ECC_TYPE,
      SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_MAX_NUM_CHECKERS,
      SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_groupEntries },
};
 
static const SDL_RAMIdEntry_t SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_RamIdTable[SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_NUM_RAMS] =
{
    { SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_IDATA_SPRAM_BANK0_LO_ECC_SVBUS_RAM_ID,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_IDATA_SPRAM_BANK0_LO_ECC_SVBUS_INJECT_TYPE,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_IDATA_SPRAM_BANK0_LO_ECC_SVBUS_ECC_TYPE,
      0u,
      NULL },
    { SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_IDATA_SPRAM_BANK0_HI_ECC_SVBUS_RAM_ID,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_IDATA_SPRAM_BANK0_HI_ECC_SVBUS_INJECT_TYPE,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_IDATA_SPRAM_BANK0_HI_ECC_SVBUS_ECC_TYPE,
      0u,
      NULL },
    { SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_IDATA_SPRAM_BANK1_LO_ECC_SVBUS_RAM_ID,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_IDATA_SPRAM_BANK1_LO_ECC_SVBUS_INJECT_TYPE,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_IDATA_SPRAM_BANK1_LO_ECC_SVBUS_ECC_TYPE,
      0u,
      NULL },
    { SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_IDATA_SPRAM_BANK1_HI_ECC_SVBUS_RAM_ID,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_IDATA_SPRAM_BANK1_HI_ECC_SVBUS_INJECT_TYPE,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_IDATA_SPRAM_BANK1_HI_ECC_SVBUS_ECC_TYPE,
      0u,
      NULL },
    { SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_ITAG_SPRAM_RAM0_ECC_SVBUS_RAM_ID,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_ITAG_SPRAM_RAM0_ECC_SVBUS_INJECT_TYPE,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_ITAG_SPRAM_RAM0_ECC_SVBUS_ECC_TYPE,
      0u,
      NULL },
    { SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_ITAG_SPRAM_RAM1_ECC_SVBUS_RAM_ID,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_ITAG_SPRAM_RAM1_ECC_SVBUS_INJECT_TYPE,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_ITAG_SPRAM_RAM1_ECC_SVBUS_ECC_TYPE,
      0u,
      NULL },
    { SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DDATA_SPRAM_BANK0_ECC_SVBUS_RAM_ID,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DDATA_SPRAM_BANK0_ECC_SVBUS_INJECT_TYPE,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DDATA_SPRAM_BANK0_ECC_SVBUS_ECC_TYPE,
      0u,
      NULL },
    { SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DDATA_SPRAM_BANK1_ECC_SVBUS_RAM_ID,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DDATA_SPRAM_BANK1_ECC_SVBUS_INJECT_TYPE,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DDATA_SPRAM_BANK1_ECC_SVBUS_ECC_TYPE,
      0u,
      NULL },
    { SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DDATA_SPRAM_BANK2_ECC_SVBUS_RAM_ID,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DDATA_SPRAM_BANK2_ECC_SVBUS_INJECT_TYPE,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DDATA_SPRAM_BANK2_ECC_SVBUS_ECC_TYPE,
      0u,
      NULL },
    { SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DDATA_SPRAM_BANK3_ECC_SVBUS_RAM_ID,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DDATA_SPRAM_BANK3_ECC_SVBUS_INJECT_TYPE,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DDATA_SPRAM_BANK3_ECC_SVBUS_ECC_TYPE,
      0u,
      NULL },
    { SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DDATA_SPRAM_BANK4_ECC_SVBUS_RAM_ID,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DDATA_SPRAM_BANK4_ECC_SVBUS_INJECT_TYPE,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DDATA_SPRAM_BANK4_ECC_SVBUS_ECC_TYPE,
      0u,
      NULL },
    { SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DDATA_SPRAM_BANK5_ECC_SVBUS_RAM_ID,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DDATA_SPRAM_BANK5_ECC_SVBUS_INJECT_TYPE,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DDATA_SPRAM_BANK5_ECC_SVBUS_ECC_TYPE,
      0u,
      NULL },
    { SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DDATA_SPRAM_BANK6_ECC_SVBUS_RAM_ID,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DDATA_SPRAM_BANK6_ECC_SVBUS_INJECT_TYPE,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DDATA_SPRAM_BANK6_ECC_SVBUS_ECC_TYPE,
      0u,
      NULL },
    { SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DDATA_SPRAM_BANK7_ECC_SVBUS_RAM_ID,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DDATA_SPRAM_BANK7_ECC_SVBUS_INJECT_TYPE,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DDATA_SPRAM_BANK7_ECC_SVBUS_ECC_TYPE,
      0u,
      NULL },
    { SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DTAG_SPRAM_BANK0_ECC_SVBUS_RAM_ID,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DTAG_SPRAM_BANK0_ECC_SVBUS_INJECT_TYPE,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DTAG_SPRAM_BANK0_ECC_SVBUS_ECC_TYPE,
      0u,
      NULL },
    { SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DTAG_SPRAM_BANK1_ECC_SVBUS_RAM_ID,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DTAG_SPRAM_BANK1_ECC_SVBUS_INJECT_TYPE,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DTAG_SPRAM_BANK1_ECC_SVBUS_ECC_TYPE,
      0u,
      NULL },
    { SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DTAG_SPRAM_BANK2_ECC_SVBUS_RAM_ID,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DTAG_SPRAM_BANK2_ECC_SVBUS_INJECT_TYPE,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DTAG_SPRAM_BANK2_ECC_SVBUS_ECC_TYPE,
      0u,
      NULL },
    { SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DTAG_SPRAM_BANK3_ECC_SVBUS_RAM_ID,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DTAG_SPRAM_BANK3_ECC_SVBUS_INJECT_TYPE,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DTAG_SPRAM_BANK3_ECC_SVBUS_ECC_TYPE,
      0u,
      NULL },
    { SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DDIRTY_SPRAM_ECC_SVBUS_RAM_ID,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DDIRTY_SPRAM_ECC_SVBUS_INJECT_TYPE,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DDIRTY_SPRAM_ECC_SVBUS_ECC_TYPE,
      0u,
      NULL },
    { SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_TLB_SPRAM_BANK0_ECC_SVBUS_RAM_ID,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_TLB_SPRAM_BANK0_ECC_SVBUS_INJECT_TYPE,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_TLB_SPRAM_BANK0_ECC_SVBUS_ECC_TYPE,
      0u,
      NULL },
    { SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_TLB_SPRAM_BANK1_ECC_SVBUS_RAM_ID,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_TLB_SPRAM_BANK1_ECC_SVBUS_INJECT_TYPE,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_TLB_SPRAM_BANK1_ECC_SVBUS_ECC_TYPE,
      0u,
      NULL },
    { SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_TLB_SPRAM_BANK2_ECC_SVBUS_RAM_ID,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_TLB_SPRAM_BANK2_ECC_SVBUS_INJECT_TYPE,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_TLB_SPRAM_BANK2_ECC_SVBUS_ECC_TYPE,
      0u,
      NULL },
    { SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_TLB_SPRAM_BANK3_ECC_SVBUS_RAM_ID,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_TLB_SPRAM_BANK3_ECC_SVBUS_INJECT_TYPE,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_TLB_SPRAM_BANK3_ECC_SVBUS_ECC_TYPE,
      0u,
      NULL },
    { SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY0_ECC_SVBUS_RAM_ID,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY0_ECC_SVBUS_INJECT_TYPE,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY0_ECC_SVBUS_ECC_TYPE,
      0u,
      NULL },
    { SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY1_ECC_SVBUS_RAM_ID,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY1_ECC_SVBUS_INJECT_TYPE,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY1_ECC_SVBUS_ECC_TYPE,
      0u,
      NULL },
    { SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY2_ECC_SVBUS_RAM_ID,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY2_ECC_SVBUS_INJECT_TYPE,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY2_ECC_SVBUS_ECC_TYPE,
      0u,
      NULL },
    { SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY3_ECC_SVBUS_RAM_ID,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY3_ECC_SVBUS_INJECT_TYPE,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY3_ECC_SVBUS_ECC_TYPE,
      0u,
      NULL },
};
 
static const SDL_RAMIdEntry_t SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_RamIdTable[SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_NUM_RAMS] =
{
    { SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_IDATA_SPRAM_BANK0_LO_ECC_SVBUS_RAM_ID,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_IDATA_SPRAM_BANK0_LO_ECC_SVBUS_INJECT_TYPE,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_IDATA_SPRAM_BANK0_LO_ECC_SVBUS_ECC_TYPE,
      0u,
      NULL },
    { SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_IDATA_SPRAM_BANK0_HI_ECC_SVBUS_RAM_ID,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_IDATA_SPRAM_BANK0_HI_ECC_SVBUS_INJECT_TYPE,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_IDATA_SPRAM_BANK0_HI_ECC_SVBUS_ECC_TYPE,
      0u,
      NULL },
    { SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_IDATA_SPRAM_BANK1_LO_ECC_SVBUS_RAM_ID,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_IDATA_SPRAM_BANK1_LO_ECC_SVBUS_INJECT_TYPE,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_IDATA_SPRAM_BANK1_LO_ECC_SVBUS_ECC_TYPE,
      0u,
      NULL },
    { SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_IDATA_SPRAM_BANK1_HI_ECC_SVBUS_RAM_ID,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_IDATA_SPRAM_BANK1_HI_ECC_SVBUS_INJECT_TYPE,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_IDATA_SPRAM_BANK1_HI_ECC_SVBUS_ECC_TYPE,
      0u,
      NULL },
    { SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_ITAG_SPRAM_RAM0_ECC_SVBUS_RAM_ID,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_ITAG_SPRAM_RAM0_ECC_SVBUS_INJECT_TYPE,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_ITAG_SPRAM_RAM0_ECC_SVBUS_ECC_TYPE,
      0u,
      NULL },
    { SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_ITAG_SPRAM_RAM1_ECC_SVBUS_RAM_ID,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_ITAG_SPRAM_RAM1_ECC_SVBUS_INJECT_TYPE,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_ITAG_SPRAM_RAM1_ECC_SVBUS_ECC_TYPE,
      0u,
      NULL },
    { SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DDATA_SPRAM_BANK0_ECC_SVBUS_RAM_ID,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DDATA_SPRAM_BANK0_ECC_SVBUS_INJECT_TYPE,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DDATA_SPRAM_BANK0_ECC_SVBUS_ECC_TYPE,
      0u,
      NULL },
    { SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DDATA_SPRAM_BANK1_ECC_SVBUS_RAM_ID,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DDATA_SPRAM_BANK1_ECC_SVBUS_INJECT_TYPE,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DDATA_SPRAM_BANK1_ECC_SVBUS_ECC_TYPE,
      0u,
      NULL },
    { SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DDATA_SPRAM_BANK2_ECC_SVBUS_RAM_ID,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DDATA_SPRAM_BANK2_ECC_SVBUS_INJECT_TYPE,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DDATA_SPRAM_BANK2_ECC_SVBUS_ECC_TYPE,
      0u,
      NULL },
    { SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DDATA_SPRAM_BANK3_ECC_SVBUS_RAM_ID,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DDATA_SPRAM_BANK3_ECC_SVBUS_INJECT_TYPE,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DDATA_SPRAM_BANK3_ECC_SVBUS_ECC_TYPE,
      0u,
      NULL },
    { SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DDATA_SPRAM_BANK4_ECC_SVBUS_RAM_ID,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DDATA_SPRAM_BANK4_ECC_SVBUS_INJECT_TYPE,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DDATA_SPRAM_BANK4_ECC_SVBUS_ECC_TYPE,
      0u,
      NULL },
    { SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DDATA_SPRAM_BANK5_ECC_SVBUS_RAM_ID,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DDATA_SPRAM_BANK5_ECC_SVBUS_INJECT_TYPE,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DDATA_SPRAM_BANK5_ECC_SVBUS_ECC_TYPE,
      0u,
      NULL },
    { SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DDATA_SPRAM_BANK6_ECC_SVBUS_RAM_ID,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DDATA_SPRAM_BANK6_ECC_SVBUS_INJECT_TYPE,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DDATA_SPRAM_BANK6_ECC_SVBUS_ECC_TYPE,
      0u,
      NULL },
    { SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DDATA_SPRAM_BANK7_ECC_SVBUS_RAM_ID,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DDATA_SPRAM_BANK7_ECC_SVBUS_INJECT_TYPE,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DDATA_SPRAM_BANK7_ECC_SVBUS_ECC_TYPE,
      0u,
      NULL },
    { SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DTAG_SPRAM_BANK0_ECC_SVBUS_RAM_ID,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DTAG_SPRAM_BANK0_ECC_SVBUS_INJECT_TYPE,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DTAG_SPRAM_BANK0_ECC_SVBUS_ECC_TYPE,
      0u,
      NULL },
    { SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DTAG_SPRAM_BANK1_ECC_SVBUS_RAM_ID,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DTAG_SPRAM_BANK1_ECC_SVBUS_INJECT_TYPE,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DTAG_SPRAM_BANK1_ECC_SVBUS_ECC_TYPE,
      0u,
      NULL },
    { SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DTAG_SPRAM_BANK2_ECC_SVBUS_RAM_ID,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DTAG_SPRAM_BANK2_ECC_SVBUS_INJECT_TYPE,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DTAG_SPRAM_BANK2_ECC_SVBUS_ECC_TYPE,
      0u,
      NULL },
    { SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DTAG_SPRAM_BANK3_ECC_SVBUS_RAM_ID,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DTAG_SPRAM_BANK3_ECC_SVBUS_INJECT_TYPE,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DTAG_SPRAM_BANK3_ECC_SVBUS_ECC_TYPE,
      0u,
      NULL },
    { SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DDIRTY_SPRAM_ECC_SVBUS_RAM_ID,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DDIRTY_SPRAM_ECC_SVBUS_INJECT_TYPE,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DDIRTY_SPRAM_ECC_SVBUS_ECC_TYPE,
      0u,
      NULL },
    { SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_TLB_SPRAM_BANK0_ECC_SVBUS_RAM_ID,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_TLB_SPRAM_BANK0_ECC_SVBUS_INJECT_TYPE,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_TLB_SPRAM_BANK0_ECC_SVBUS_ECC_TYPE,
      0u,
      NULL },
    { SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_TLB_SPRAM_BANK1_ECC_SVBUS_RAM_ID,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_TLB_SPRAM_BANK1_ECC_SVBUS_INJECT_TYPE,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_TLB_SPRAM_BANK1_ECC_SVBUS_ECC_TYPE,
      0u,
      NULL },
    { SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_TLB_SPRAM_BANK2_ECC_SVBUS_RAM_ID,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_TLB_SPRAM_BANK2_ECC_SVBUS_INJECT_TYPE,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_TLB_SPRAM_BANK2_ECC_SVBUS_ECC_TYPE,
      0u,
      NULL },
    { SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_TLB_SPRAM_BANK3_ECC_SVBUS_RAM_ID,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_TLB_SPRAM_BANK3_ECC_SVBUS_INJECT_TYPE,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_TLB_SPRAM_BANK3_ECC_SVBUS_ECC_TYPE,
      0u,
      NULL },
    { SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY0_ECC_SVBUS_RAM_ID,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY0_ECC_SVBUS_INJECT_TYPE,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY0_ECC_SVBUS_ECC_TYPE,
      0u,
      NULL },
    { SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY1_ECC_SVBUS_RAM_ID,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY1_ECC_SVBUS_INJECT_TYPE,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY1_ECC_SVBUS_ECC_TYPE,
      0u,
      NULL },
    { SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY2_ECC_SVBUS_RAM_ID,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY2_ECC_SVBUS_INJECT_TYPE,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY2_ECC_SVBUS_ECC_TYPE,
      0u,
      NULL },
    { SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY3_ECC_SVBUS_RAM_ID,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY3_ECC_SVBUS_INJECT_TYPE,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY3_ECC_SVBUS_ECC_TYPE,
      0u,
      NULL },
};
 
static const SDL_RAMIdEntry_t SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_RamIdTable[SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_NUM_RAMS] =
{
    { SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_IDATA_SPRAM_BANK0_LO_ECC_SVBUS_RAM_ID,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_IDATA_SPRAM_BANK0_LO_ECC_SVBUS_INJECT_TYPE,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_IDATA_SPRAM_BANK0_LO_ECC_SVBUS_ECC_TYPE,
      0u,
      NULL },
    { SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_IDATA_SPRAM_BANK0_HI_ECC_SVBUS_RAM_ID,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_IDATA_SPRAM_BANK0_HI_ECC_SVBUS_INJECT_TYPE,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_IDATA_SPRAM_BANK0_HI_ECC_SVBUS_ECC_TYPE,
      0u,
      NULL },
    { SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_IDATA_SPRAM_BANK1_LO_ECC_SVBUS_RAM_ID,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_IDATA_SPRAM_BANK1_LO_ECC_SVBUS_INJECT_TYPE,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_IDATA_SPRAM_BANK1_LO_ECC_SVBUS_ECC_TYPE,
      0u,
      NULL },
    { SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_IDATA_SPRAM_BANK1_HI_ECC_SVBUS_RAM_ID,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_IDATA_SPRAM_BANK1_HI_ECC_SVBUS_INJECT_TYPE,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_IDATA_SPRAM_BANK1_HI_ECC_SVBUS_ECC_TYPE,
      0u,
      NULL },
    { SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_ITAG_SPRAM_RAM0_ECC_SVBUS_RAM_ID,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_ITAG_SPRAM_RAM0_ECC_SVBUS_INJECT_TYPE,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_ITAG_SPRAM_RAM0_ECC_SVBUS_ECC_TYPE,
      0u,
      NULL },
    { SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_ITAG_SPRAM_RAM1_ECC_SVBUS_RAM_ID,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_ITAG_SPRAM_RAM1_ECC_SVBUS_INJECT_TYPE,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_ITAG_SPRAM_RAM1_ECC_SVBUS_ECC_TYPE,
      0u,
      NULL },
    { SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DDATA_SPRAM_BANK0_ECC_SVBUS_RAM_ID,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DDATA_SPRAM_BANK0_ECC_SVBUS_INJECT_TYPE,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DDATA_SPRAM_BANK0_ECC_SVBUS_ECC_TYPE,
      0u,
      NULL },
    { SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DDATA_SPRAM_BANK1_ECC_SVBUS_RAM_ID,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DDATA_SPRAM_BANK1_ECC_SVBUS_INJECT_TYPE,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DDATA_SPRAM_BANK1_ECC_SVBUS_ECC_TYPE,
      0u,
      NULL },
    { SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DDATA_SPRAM_BANK2_ECC_SVBUS_RAM_ID,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DDATA_SPRAM_BANK2_ECC_SVBUS_INJECT_TYPE,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DDATA_SPRAM_BANK2_ECC_SVBUS_ECC_TYPE,
      0u,
      NULL },
    { SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DDATA_SPRAM_BANK3_ECC_SVBUS_RAM_ID,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DDATA_SPRAM_BANK3_ECC_SVBUS_INJECT_TYPE,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DDATA_SPRAM_BANK3_ECC_SVBUS_ECC_TYPE,
      0u,
      NULL },
    { SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DDATA_SPRAM_BANK4_ECC_SVBUS_RAM_ID,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DDATA_SPRAM_BANK4_ECC_SVBUS_INJECT_TYPE,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DDATA_SPRAM_BANK4_ECC_SVBUS_ECC_TYPE,
      0u,
      NULL },
    { SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DDATA_SPRAM_BANK5_ECC_SVBUS_RAM_ID,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DDATA_SPRAM_BANK5_ECC_SVBUS_INJECT_TYPE,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DDATA_SPRAM_BANK5_ECC_SVBUS_ECC_TYPE,
      0u,
      NULL },
    { SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DDATA_SPRAM_BANK6_ECC_SVBUS_RAM_ID,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DDATA_SPRAM_BANK6_ECC_SVBUS_INJECT_TYPE,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DDATA_SPRAM_BANK6_ECC_SVBUS_ECC_TYPE,
      0u,
      NULL },
    { SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DDATA_SPRAM_BANK7_ECC_SVBUS_RAM_ID,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DDATA_SPRAM_BANK7_ECC_SVBUS_INJECT_TYPE,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DDATA_SPRAM_BANK7_ECC_SVBUS_ECC_TYPE,
      0u,
      NULL },
    { SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DTAG_SPRAM_BANK0_ECC_SVBUS_RAM_ID,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DTAG_SPRAM_BANK0_ECC_SVBUS_INJECT_TYPE,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DTAG_SPRAM_BANK0_ECC_SVBUS_ECC_TYPE,
      0u,
      NULL },
    { SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DTAG_SPRAM_BANK1_ECC_SVBUS_RAM_ID,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DTAG_SPRAM_BANK1_ECC_SVBUS_INJECT_TYPE,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DTAG_SPRAM_BANK1_ECC_SVBUS_ECC_TYPE,
      0u,
      NULL },
    { SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DTAG_SPRAM_BANK2_ECC_SVBUS_RAM_ID,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DTAG_SPRAM_BANK2_ECC_SVBUS_INJECT_TYPE,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DTAG_SPRAM_BANK2_ECC_SVBUS_ECC_TYPE,
      0u,
      NULL },
    { SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DTAG_SPRAM_BANK3_ECC_SVBUS_RAM_ID,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DTAG_SPRAM_BANK3_ECC_SVBUS_INJECT_TYPE,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DTAG_SPRAM_BANK3_ECC_SVBUS_ECC_TYPE,
      0u,
      NULL },
    { SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DDIRTY_SPRAM_ECC_SVBUS_RAM_ID,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DDIRTY_SPRAM_ECC_SVBUS_INJECT_TYPE,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DDIRTY_SPRAM_ECC_SVBUS_ECC_TYPE,
      0u,
      NULL },
    { SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_TLB_SPRAM_BANK0_ECC_SVBUS_RAM_ID,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_TLB_SPRAM_BANK0_ECC_SVBUS_INJECT_TYPE,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_TLB_SPRAM_BANK0_ECC_SVBUS_ECC_TYPE,
      0u,
      NULL },
    { SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_TLB_SPRAM_BANK1_ECC_SVBUS_RAM_ID,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_TLB_SPRAM_BANK1_ECC_SVBUS_INJECT_TYPE,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_TLB_SPRAM_BANK1_ECC_SVBUS_ECC_TYPE,
      0u,
      NULL },
    { SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_TLB_SPRAM_BANK2_ECC_SVBUS_RAM_ID,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_TLB_SPRAM_BANK2_ECC_SVBUS_INJECT_TYPE,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_TLB_SPRAM_BANK2_ECC_SVBUS_ECC_TYPE,
      0u,
      NULL },
    { SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_TLB_SPRAM_BANK3_ECC_SVBUS_RAM_ID,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_TLB_SPRAM_BANK3_ECC_SVBUS_INJECT_TYPE,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_TLB_SPRAM_BANK3_ECC_SVBUS_ECC_TYPE,
      0u,
      NULL },
    { SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY0_ECC_SVBUS_RAM_ID,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY0_ECC_SVBUS_INJECT_TYPE,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY0_ECC_SVBUS_ECC_TYPE,
      0u,
      NULL },
    { SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY1_ECC_SVBUS_RAM_ID,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY1_ECC_SVBUS_INJECT_TYPE,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY1_ECC_SVBUS_ECC_TYPE,
      0u,
      NULL },
    { SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY2_ECC_SVBUS_RAM_ID,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY2_ECC_SVBUS_INJECT_TYPE,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY2_ECC_SVBUS_ECC_TYPE,
      0u,
      NULL },
    { SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY3_ECC_SVBUS_RAM_ID,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY3_ECC_SVBUS_INJECT_TYPE,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY3_ECC_SVBUS_ECC_TYPE,
      0u,
      NULL },
};
 
static const SDL_RAMIdEntry_t SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_RamIdTable[SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_NUM_RAMS] =
{
    { SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_IDATA_SPRAM_BANK0_LO_ECC_SVBUS_RAM_ID,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_IDATA_SPRAM_BANK0_LO_ECC_SVBUS_INJECT_TYPE,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_IDATA_SPRAM_BANK0_LO_ECC_SVBUS_ECC_TYPE,
      0u,
      NULL },
    { SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_IDATA_SPRAM_BANK0_HI_ECC_SVBUS_RAM_ID,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_IDATA_SPRAM_BANK0_HI_ECC_SVBUS_INJECT_TYPE,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_IDATA_SPRAM_BANK0_HI_ECC_SVBUS_ECC_TYPE,
      0u,
      NULL },
    { SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_IDATA_SPRAM_BANK1_LO_ECC_SVBUS_RAM_ID,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_IDATA_SPRAM_BANK1_LO_ECC_SVBUS_INJECT_TYPE,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_IDATA_SPRAM_BANK1_LO_ECC_SVBUS_ECC_TYPE,
      0u,
      NULL },
    { SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_IDATA_SPRAM_BANK1_HI_ECC_SVBUS_RAM_ID,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_IDATA_SPRAM_BANK1_HI_ECC_SVBUS_INJECT_TYPE,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_IDATA_SPRAM_BANK1_HI_ECC_SVBUS_ECC_TYPE,
      0u,
      NULL },
    { SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_ITAG_SPRAM_RAM0_ECC_SVBUS_RAM_ID,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_ITAG_SPRAM_RAM0_ECC_SVBUS_INJECT_TYPE,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_ITAG_SPRAM_RAM0_ECC_SVBUS_ECC_TYPE,
      0u,
      NULL },
    { SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_ITAG_SPRAM_RAM1_ECC_SVBUS_RAM_ID,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_ITAG_SPRAM_RAM1_ECC_SVBUS_INJECT_TYPE,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_ITAG_SPRAM_RAM1_ECC_SVBUS_ECC_TYPE,
      0u,
      NULL },
    { SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DDATA_SPRAM_BANK0_ECC_SVBUS_RAM_ID,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DDATA_SPRAM_BANK0_ECC_SVBUS_INJECT_TYPE,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DDATA_SPRAM_BANK0_ECC_SVBUS_ECC_TYPE,
      0u,
      NULL },
    { SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DDATA_SPRAM_BANK1_ECC_SVBUS_RAM_ID,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DDATA_SPRAM_BANK1_ECC_SVBUS_INJECT_TYPE,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DDATA_SPRAM_BANK1_ECC_SVBUS_ECC_TYPE,
      0u,
      NULL },
    { SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DDATA_SPRAM_BANK2_ECC_SVBUS_RAM_ID,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DDATA_SPRAM_BANK2_ECC_SVBUS_INJECT_TYPE,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DDATA_SPRAM_BANK2_ECC_SVBUS_ECC_TYPE,
      0u,
      NULL },
    { SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DDATA_SPRAM_BANK3_ECC_SVBUS_RAM_ID,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DDATA_SPRAM_BANK3_ECC_SVBUS_INJECT_TYPE,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DDATA_SPRAM_BANK3_ECC_SVBUS_ECC_TYPE,
      0u,
      NULL },
    { SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DDATA_SPRAM_BANK4_ECC_SVBUS_RAM_ID,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DDATA_SPRAM_BANK4_ECC_SVBUS_INJECT_TYPE,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DDATA_SPRAM_BANK4_ECC_SVBUS_ECC_TYPE,
      0u,
      NULL },
    { SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DDATA_SPRAM_BANK5_ECC_SVBUS_RAM_ID,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DDATA_SPRAM_BANK5_ECC_SVBUS_INJECT_TYPE,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DDATA_SPRAM_BANK5_ECC_SVBUS_ECC_TYPE,
      0u,
      NULL },
    { SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DDATA_SPRAM_BANK6_ECC_SVBUS_RAM_ID,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DDATA_SPRAM_BANK6_ECC_SVBUS_INJECT_TYPE,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DDATA_SPRAM_BANK6_ECC_SVBUS_ECC_TYPE,
      0u,
      NULL },
    { SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DDATA_SPRAM_BANK7_ECC_SVBUS_RAM_ID,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DDATA_SPRAM_BANK7_ECC_SVBUS_INJECT_TYPE,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DDATA_SPRAM_BANK7_ECC_SVBUS_ECC_TYPE,
      0u,
      NULL },
    { SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DTAG_SPRAM_BANK0_ECC_SVBUS_RAM_ID,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DTAG_SPRAM_BANK0_ECC_SVBUS_INJECT_TYPE,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DTAG_SPRAM_BANK0_ECC_SVBUS_ECC_TYPE,
      0u,
      NULL },
    { SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DTAG_SPRAM_BANK1_ECC_SVBUS_RAM_ID,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DTAG_SPRAM_BANK1_ECC_SVBUS_INJECT_TYPE,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DTAG_SPRAM_BANK1_ECC_SVBUS_ECC_TYPE,
      0u,
      NULL },
    { SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DTAG_SPRAM_BANK2_ECC_SVBUS_RAM_ID,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DTAG_SPRAM_BANK2_ECC_SVBUS_INJECT_TYPE,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DTAG_SPRAM_BANK2_ECC_SVBUS_ECC_TYPE,
      0u,
      NULL },
    { SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DTAG_SPRAM_BANK3_ECC_SVBUS_RAM_ID,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DTAG_SPRAM_BANK3_ECC_SVBUS_INJECT_TYPE,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DTAG_SPRAM_BANK3_ECC_SVBUS_ECC_TYPE,
      0u,
      NULL },
    { SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DDIRTY_SPRAM_ECC_SVBUS_RAM_ID,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DDIRTY_SPRAM_ECC_SVBUS_INJECT_TYPE,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DDIRTY_SPRAM_ECC_SVBUS_ECC_TYPE,
      0u,
      NULL },
    { SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_TLB_SPRAM_BANK0_ECC_SVBUS_RAM_ID,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_TLB_SPRAM_BANK0_ECC_SVBUS_INJECT_TYPE,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_TLB_SPRAM_BANK0_ECC_SVBUS_ECC_TYPE,
      0u,
      NULL },
    { SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_TLB_SPRAM_BANK1_ECC_SVBUS_RAM_ID,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_TLB_SPRAM_BANK1_ECC_SVBUS_INJECT_TYPE,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_TLB_SPRAM_BANK1_ECC_SVBUS_ECC_TYPE,
      0u,
      NULL },
    { SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_TLB_SPRAM_BANK2_ECC_SVBUS_RAM_ID,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_TLB_SPRAM_BANK2_ECC_SVBUS_INJECT_TYPE,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_TLB_SPRAM_BANK2_ECC_SVBUS_ECC_TYPE,
      0u,
      NULL },
    { SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_TLB_SPRAM_BANK3_ECC_SVBUS_RAM_ID,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_TLB_SPRAM_BANK3_ECC_SVBUS_INJECT_TYPE,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_TLB_SPRAM_BANK3_ECC_SVBUS_ECC_TYPE,
      0u,
      NULL },
    { SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY0_ECC_SVBUS_RAM_ID,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY0_ECC_SVBUS_INJECT_TYPE,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY0_ECC_SVBUS_ECC_TYPE,
      0u,
      NULL },
    { SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY1_ECC_SVBUS_RAM_ID,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY1_ECC_SVBUS_INJECT_TYPE,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY1_ECC_SVBUS_ECC_TYPE,
      0u,
      NULL },
    { SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY2_ECC_SVBUS_RAM_ID,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY2_ECC_SVBUS_INJECT_TYPE,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY2_ECC_SVBUS_ECC_TYPE,
      0u,
      NULL },
    { SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY3_ECC_SVBUS_RAM_ID,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY3_ECC_SVBUS_INJECT_TYPE,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY3_ECC_SVBUS_ECC_TYPE,
      0u,
      NULL },
};
 
static const SDL_RAMIdEntry_t SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_RamIdTable[SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_NUM_RAMS] =
{
    { SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY0_ECC_SVBUS_RAM_ID,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY0_ECC_SVBUS_INJECT_TYPE,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY0_ECC_SVBUS_ECC_TYPE,
      0u,
      NULL },
    { SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY1_ECC_SVBUS_RAM_ID,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY1_ECC_SVBUS_INJECT_TYPE,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY1_ECC_SVBUS_ECC_TYPE,
      0u,
      NULL },
    { SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY2_ECC_SVBUS_RAM_ID,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY2_ECC_SVBUS_INJECT_TYPE,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY2_ECC_SVBUS_ECC_TYPE,
      0u,
      NULL },
    { SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY3_ECC_SVBUS_RAM_ID,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY3_ECC_SVBUS_INJECT_TYPE,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY3_ECC_SVBUS_ECC_TYPE,
      0u,
      NULL },
    { SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY4_ECC_SVBUS_RAM_ID,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY4_ECC_SVBUS_INJECT_TYPE,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY4_ECC_SVBUS_ECC_TYPE,
      0u,
      NULL },
    { SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY5_ECC_SVBUS_RAM_ID,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY5_ECC_SVBUS_INJECT_TYPE,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY5_ECC_SVBUS_ECC_TYPE,
      0u,
      NULL },
    { SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY6_ECC_SVBUS_RAM_ID,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY6_ECC_SVBUS_INJECT_TYPE,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY6_ECC_SVBUS_ECC_TYPE,
      0u,
      NULL },
    { SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY7_ECC_SVBUS_RAM_ID,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY7_ECC_SVBUS_INJECT_TYPE,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY7_ECC_SVBUS_ECC_TYPE,
      0u,
      NULL },
    { SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY8_ECC_SVBUS_RAM_ID,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY8_ECC_SVBUS_INJECT_TYPE,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY8_ECC_SVBUS_ECC_TYPE,
      0u,
      NULL },
    { SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY9_ECC_SVBUS_RAM_ID,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY9_ECC_SVBUS_INJECT_TYPE,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY9_ECC_SVBUS_ECC_TYPE,
      0u,
      NULL },
    { SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY10_ECC_SVBUS_RAM_ID,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY10_ECC_SVBUS_INJECT_TYPE,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY10_ECC_SVBUS_ECC_TYPE,
      0u,
      NULL },
    { SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY11_ECC_SVBUS_RAM_ID,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY11_ECC_SVBUS_INJECT_TYPE,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY11_ECC_SVBUS_ECC_TYPE,
      0u,
      NULL },
    { SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY12_ECC_SVBUS_RAM_ID,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY12_ECC_SVBUS_INJECT_TYPE,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY12_ECC_SVBUS_ECC_TYPE,
      0u,
      NULL },
    { SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY13_ECC_SVBUS_RAM_ID,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY13_ECC_SVBUS_INJECT_TYPE,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY13_ECC_SVBUS_ECC_TYPE,
      0u,
      NULL },
    { SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY14_ECC_SVBUS_RAM_ID,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY14_ECC_SVBUS_INJECT_TYPE,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY14_ECC_SVBUS_ECC_TYPE,
      0u,
      NULL },
    { SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY15_ECC_SVBUS_RAM_ID,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY15_ECC_SVBUS_INJECT_TYPE,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY15_ECC_SVBUS_ECC_TYPE,
      0u,
      NULL },
    { SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_DATARAM_SPRAM_0_ECC_SVBUS_RAM_ID,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_DATARAM_SPRAM_0_ECC_SVBUS_INJECT_TYPE,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_DATARAM_SPRAM_0_ECC_SVBUS_ECC_TYPE,
      0u,
      NULL },
    { SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_DATARAM_SPRAM_1_ECC_SVBUS_RAM_ID,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_DATARAM_SPRAM_1_ECC_SVBUS_INJECT_TYPE,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_DATARAM_SPRAM_1_ECC_SVBUS_ECC_TYPE,
      0u,
      NULL },
    { SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_DATARAM_SPRAM_2_ECC_SVBUS_RAM_ID,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_DATARAM_SPRAM_2_ECC_SVBUS_INJECT_TYPE,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_DATARAM_SPRAM_2_ECC_SVBUS_ECC_TYPE,
      0u,
      NULL },
    { SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_DATARAM_SPRAM_3_ECC_SVBUS_RAM_ID,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_DATARAM_SPRAM_3_ECC_SVBUS_INJECT_TYPE,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_DATARAM_SPRAM_3_ECC_SVBUS_ECC_TYPE,
      0u,
      NULL },
    { SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_DATARAM_SPRAM_4_ECC_SVBUS_RAM_ID,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_DATARAM_SPRAM_4_ECC_SVBUS_INJECT_TYPE,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_DATARAM_SPRAM_4_ECC_SVBUS_ECC_TYPE,
      0u,
      NULL },
    { SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_DATARAM_SPRAM_5_ECC_SVBUS_RAM_ID,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_DATARAM_SPRAM_5_ECC_SVBUS_INJECT_TYPE,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_DATARAM_SPRAM_5_ECC_SVBUS_ECC_TYPE,
      0u,
      NULL },
    { SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_DATARAM_SPRAM_6_ECC_SVBUS_RAM_ID,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_DATARAM_SPRAM_6_ECC_SVBUS_INJECT_TYPE,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_DATARAM_SPRAM_6_ECC_SVBUS_ECC_TYPE,
      0u,
      NULL },
    { SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_DATARAM_SPRAM_7_ECC_SVBUS_RAM_ID,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_DATARAM_SPRAM_7_ECC_SVBUS_INJECT_TYPE,
      SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_DATARAM_SPRAM_7_ECC_SVBUS_ECC_TYPE,
      0u,
      NULL },
};
 
static const SDL_RAMIdEntry_t SDL_MCU_M4FSS0_BLAZAR_ECC_RamIdTable[SDL_MCU_M4FSS0_BLAZAR_ECC_NUM_RAMS] =
{
    { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IIRAM_ECC_RAM_ID,
      SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IIRAM_ECC_INJECT_TYPE,
      SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IIRAM_ECC_ECC_TYPE,
      0u,
      NULL },
    { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IDRAM_ECC_RAM_ID,
      SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IDRAM_ECC_INJECT_TYPE,
      SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IDRAM_ECC_ECC_TYPE,
      0u,
      NULL },
    { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IIRAM_EDC_CTRL_0_RAM_ID,
      SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IIRAM_EDC_CTRL_0_INJECT_TYPE,
      SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IIRAM_EDC_CTRL_0_ECC_TYPE,
      SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IIRAM_EDC_CTRL_0_MAX_NUM_CHECKERS,
      SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IIRAM_EDC_CTRL_0_groupEntries },
    { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IDRAM_EDC_CTRL_0_RAM_ID,
      SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IDRAM_EDC_CTRL_0_INJECT_TYPE,
      SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IDRAM_EDC_CTRL_0_ECC_TYPE,
      SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IDRAM_EDC_CTRL_0_MAX_NUM_CHECKERS,
      SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IDRAM_EDC_CTRL_0_groupEntries },
    { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_RAT_EDC_CTRL_0_RAM_ID,
      SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_RAT_EDC_CTRL_0_INJECT_TYPE,
      SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_RAT_EDC_CTRL_0_ECC_TYPE,
      SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_RAT_EDC_CTRL_0_MAX_NUM_CHECKERS,
      SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_RAT_EDC_CTRL_0_groupEntries },
    { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_VBUSP_S_P2P_BRIDGE_VBUSP_S_BRIDGE_BUSECC_RAM_ID,
      SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_VBUSP_S_P2P_BRIDGE_VBUSP_S_BRIDGE_BUSECC_INJECT_TYPE,
      SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_VBUSP_S_P2P_BRIDGE_VBUSP_S_BRIDGE_BUSECC_ECC_TYPE,
      SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_VBUSP_S_P2P_BRIDGE_VBUSP_S_BRIDGE_BUSECC_MAX_NUM_CHECKERS,
      SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_VBUSP_S_P2P_BRIDGE_VBUSP_S_BRIDGE_BUSECC_groupEntries },
    { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_RAM_ID,
      SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_INJECT_TYPE,
      SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_ECC_TYPE,
      SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_MAX_NUM_CHECKERS,
      SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_groupEntries },
    { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_RAM_ID,
      SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_INJECT_TYPE,
      SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_ECC_TYPE,
      SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
      SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_groupEntries },
    { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_RAM_ID,
      SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_INJECT_TYPE,
      SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_ECC_TYPE,
      SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_MAX_NUM_CHECKERS,
      SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_groupEntries },
    { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_SYS_SCR_VBUS_CLK_EDC_CTRL_0_RAM_ID,
      SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_SYS_SCR_VBUS_CLK_EDC_CTRL_0_INJECT_TYPE,
      SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_SYS_SCR_VBUS_CLK_EDC_CTRL_0_ECC_TYPE,
      SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_SYS_SCR_VBUS_CLK_EDC_CTRL_0_MAX_NUM_CHECKERS,
      SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_SYS_SCR_VBUS_CLK_EDC_CTRL_0_groupEntries },
    { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IA2V_I_EDC_CTRL_0_RAM_ID,
      SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IA2V_I_EDC_CTRL_0_INJECT_TYPE,
      SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IA2V_I_EDC_CTRL_0_ECC_TYPE,
      SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IA2V_I_EDC_CTRL_0_MAX_NUM_CHECKERS,
      SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IA2V_I_EDC_CTRL_0_groupEntries },
    { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IA2V_D_EDC_CTRL_0_RAM_ID,
      SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IA2V_D_EDC_CTRL_0_INJECT_TYPE,
      SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IA2V_D_EDC_CTRL_0_ECC_TYPE,
      SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IA2V_D_EDC_CTRL_0_MAX_NUM_CHECKERS,
      SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IA2V_D_EDC_CTRL_0_groupEntries },
    { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_SYS_GASKET_EDC_CTRL_0_RAM_ID,
      SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_SYS_GASKET_EDC_CTRL_0_INJECT_TYPE,
      SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_SYS_GASKET_EDC_CTRL_0_ECC_TYPE,
      SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_SYS_GASKET_EDC_CTRL_0_MAX_NUM_CHECKERS,
      SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_SYS_GASKET_EDC_CTRL_0_groupEntries },
    { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_ECC_EDC_CTRL_RAM_ID,
      SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_ECC_EDC_CTRL_INJECT_TYPE,
      SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_ECC_EDC_CTRL_ECC_TYPE,
      SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_ECC_EDC_CTRL_MAX_NUM_CHECKERS,
      SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_ECC_EDC_CTRL_groupEntries },
};
 
static const SDL_RAMIdEntry_t SDL_MCU_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_RamIdTable[SDL_MCU_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_NUM_RAMS] =
{
    { SDL_MCU_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_ID,
      SDL_MCU_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_INJECT_TYPE,
      SDL_MCU_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_ECC_TYPE,
      0u,
      NULL },
    { SDL_MCU_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_RAM_ID,
      SDL_MCU_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_INJECT_TYPE,
      SDL_MCU_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_ECC_TYPE,
      SDL_MCU_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_MAX_NUM_CHECKERS,
      SDL_MCU_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_groupEntries },
};
 
static const SDL_RAMIdEntry_t SDL_MCU_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_RamIdTable[SDL_MCU_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_NUM_RAMS] =
{
    { SDL_MCU_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_ID,
      SDL_MCU_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_INJECT_TYPE,
      SDL_MCU_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_ECC_TYPE,
      0u,
      NULL },
    { SDL_MCU_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_RAM_ID,
      SDL_MCU_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_INJECT_TYPE,
      SDL_MCU_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_ECC_TYPE,
      SDL_MCU_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_MAX_NUM_CHECKERS,
      SDL_MCU_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_groupEntries },
};
static SDL_ecc_aggrRegs * const SDL_ECC_aggrBaseAddressTable[SDL_ECC_Base_Address_TOTAL_ENTRIES] =
{
    ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_COMPUTE_CLUSTER0_CORE0_ECC_AGGR_BASE)),
    ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_COMPUTE_CLUSTER0_CORE1_ECC_AGGR_BASE)),
    ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_COMPUTE_CLUSTER0_CORE2_ECC_AGGR_BASE)),
    ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_COMPUTE_CLUSTER0_CORE3_ECC_AGGR_BASE)),
    ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_COMPUTE_CLUSTER0_SS_ECC_AGGR_BASE)),
    ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_CSI_RX_IF0_ECC_AGGR_CFG_BASE)),
    ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_DMASS0_ECCAGGR_BASE)),
    ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_ECC_AGGR0_ECC_AGGR_BASE)),
    ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_FSS0_OSPI0_ECC_AGGR_BASE)),
    ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_GICSS0_REGS_BASE)),
    ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_ICSSM0_ECC_AGGR_BASE)),
    ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_MCAN0_ECC_AGGR_BASE)),
    ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_MCU_ECC_AGGR0_ECC_AGGR_BASE)),
#if defined (R5F_CORE)
    ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_MAIN_MCU_M4FSS0_ECC_AGGR_BASE)),
#endif
#if defined (M4F_CORE)
    ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_MCU_M4FSS0_ECC_AGGR_BASE)),
#endif
    ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_MCU_MCAN0_ECC_AGGR_BASE)),
    ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_MCU_MCAN1_ECC_AGGR_BASE)),
    ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_MMCSD0_ECC_AGGR_RXMEM_BASE)),
    ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_MMCSD0_ECC_AGGR_TXMEM_BASE)),
    ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_MMCSD1_ECC_AGGR_RXMEM_BASE)),
    ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_MMCSD1_ECC_AGGR_TXMEM_BASE)),
    ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_MMCSD2_ECC_AGGR_RXMEM_BASE)),
    ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_MMCSD2_ECC_AGGR_TXMEM_BASE)),
    ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_PDMA0_BASE)),
    ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_PDMA1_BASE)),
    ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_PSRAMECC_16K0_ECC_AGGR_BASE)),
    ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_PSRAMECC0_ECC_AGGR_BASE)),
    ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_SA3_SS0_REGS_BASE)),
    ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_SA3_SS0_ECC_AGGR_BASE)),
    ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_SMS0_HSM_SRAM0_0_BASE)),
    ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_SMS0_ECC_AGGR_BASE)),
    ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_USB0_ECC_AGGR_BASE)),
    ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_USB1_ECC_AGGR_BASE)),
    ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_WKUP_ECC_AGGR0_ECC_AGGR_BASE)),
    ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_WKUP_R5FSS0_CORE0_ECC_AGGR_BASE)),
    ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_WKUP_SAFE_ECC_AGGR0_ECC_AGGR_BASE)),
    ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_WKUP_VTM0_ECCAGGR_CFG_BASE)),
    ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_CPSW0_ECC_BASE)),
 
};
 
SDL_ecc_aggrRegs * SDL_ECC_aggrTransBaseAddressTable[SDL_ECC_MEMTYPE_MAX];
static const SDL_EccAggrEntry_t SDL_ECC_aggrTable[SDL_ECC_MEMTYPE_MAX] =
{
 
  /* SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0 (0) */
    {
        SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_NUM_RAMS,
        SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_RamIdTable,
        SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_RAM_IDS_TOTAL_ENTRIES,
        SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_MemEntries,
        SDL_ESM_INST_MAIN_ESM0,
        SDLR_ESM0_ESM_LVL_EVENT_A53SS0_ECC_ECCAGGR0_CORRECTED_ERR_LEVEL_0,
        SDLR_ESM0_ESM_LVL_EVENT_A53SS0_ECC_ECCAGGR0_UNCORRECTED_ERR_LEVEL_0
    },
    /* Index: SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1 (1)*/
    {
        SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_NUM_RAMS,
        SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_RamIdTable,
        SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_RAM_IDS_TOTAL_ENTRIES,
        SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_MemEntries,
        SDL_ESM_INST_MAIN_ESM0,
        SDLR_ESM0_ESM_LVL_EVENT_A53SS0_ECC_ECCAGGR1_CORRECTED_ERR_LEVEL_0,
        SDLR_ESM0_ESM_LVL_EVENT_A53SS0_ECC_ECCAGGR1_UNCORRECTED_ERR_LEVEL_0
    },
    /* Index: SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2 (2)*/
    {
        SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_NUM_RAMS,
        SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_RamIdTable,
        SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_RAM_IDS_TOTAL_ENTRIES,
        SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_MemEntries,
        SDL_ESM_INST_MAIN_ESM0,
        SDLR_ESM0_ESM_LVL_EVENT_A53SS0_ECC_ECCAGGR2_CORRECTED_ERR_LEVEL_0,
        SDLR_ESM0_ESM_LVL_EVENT_A53SS0_ECC_ECCAGGR2_UNCORRECTED_ERR_LEVEL_0
    },
    /* Index: SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3 (3u) */
    {
        SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_NUM_RAMS,
        SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_RamIdTable,
        SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_RAM_IDS_TOTAL_ENTRIES,
        SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_MemEntries,
        SDL_ESM_INST_MAIN_ESM0,
        SDLR_ESM0_ESM_LVL_EVENT_A53SS0_ECC_ECCAGGR3_CORRECTED_ERR_LEVEL_0,
        SDLR_ESM0_ESM_LVL_EVENT_A53SS0_ECC_ECCAGGR3_CORRECTED_ERR_LEVEL_0
    },
    /* Index: SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC (4u) */
    {
        SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_NUM_RAMS,
        SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_RamIdTable,
        SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_RAM_IDS_TOTAL_ENTRIES,
        SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_MemEntries,
        SDL_ESM_INST_MAIN_ESM0,
        SDLR_ESM0_ESM_LVL_EVENT_A53SS0_ECC_ECCAGGR_COREPAC_CORRECTED_ERR_LEVEL_0,
        SDLR_ESM0_ESM_LVL_EVENT_A53SS0_ECC_ECCAGGR_COREPAC_UNCORRECTED_ERR_LEVEL_0
    },
 
    /* Index: SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR (5u) */
    {
        SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_NUM_RAMS,
        SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_RamIdTable,
        SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES,
        SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_MemEntries,
        SDL_ESM_INST_MAIN_ESM0,
        SDLR_ESM0_ESM_LVL_EVENT_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CORR_LEVEL_0,
        SDLR_ESM0_ESM_LVL_EVENT_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_UNCORR_LEVEL_0
    },
 
    /* Index: SDL_DMASS0_DMSS_AM62_ECCAGGR  (6u) */
    {
        SDL_DMASS0_DMSS_AM62_ECCAGGR_NUM_RAMS,
        SDL_DMASS0_DMSS_AM62_ECCAGGR_RamIdTable,
        SDL_DMASS0_DMSS_AM62_ECCAGGR_RAM_IDS_TOTAL_ENTRIES,
        SDL_DMASS0_DMSS_AM62_ECCAGGR_MemEntries,
        SDL_ESM_INST_MAIN_ESM0,
        SDLR_ESM0_ESM_LVL_EVENT_DMASS0_ECC_AGGR_0_ECC_CORRECTED_ERR_LEVEL_0,
        SDLR_ESM0_ESM_LVL_EVENT_DMASS0_ECC_AGGR_0_ECC_UNCORRECTED_ERR_LEVEL_0
    },
 
  /* Index: SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR    (7) */
  {
        SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_NUM_RAMS,
        SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_RamIdTable,
        SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES,
        SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR_MemEntries,
        SDL_ESM_INST_MAIN_ESM0,
        SDLR_ESM0_ESM_LVL_EVENT_ECC_AGGR0_SAM62_SEC_ECC_AGGR_CORR_LEVEL_0,
        SDLR_ESM0_ESM_LVL_EVENT_ECC_AGGR0_SAM62_SEC_ECC_AGGR_UNCORR_LEVEL_0
  },
 
/* Index: SDL_FSS0_FSS_UL_OSPI0_OSPI_WRAP_ECC_AGGR  (8u) */
    {
        SDL_FSS0_FSS_UL_OSPI0_OSPI_WRAP_ECC_AGGR_NUM_RAMS,
        SDL_FSS0_FSS_UL_OSPI0_OSPI_WRAP_ECC_AGGR_RamIdTable,
        SDL_FSS0_FSS_UL_OSPI0_OSPI_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES,
        SDL_FSS0_FSS_UL_OSPI0_OSPI_WRAP_ECC_AGGR_MemEntries,
        SDL_ESM_INST_MAIN_ESM0,
        SDLR_ESM0_ESM_LVL_EVENT_FSS0_OSPI_0_OSPI_ECC_CORR_LVL_INTR_0,
        SDLR_ESM0_ESM_LVL_EVENT_FSS0_OSPI_0_OSPI_ECC_UNCORR_LVL_INTR_0
    },
 
  /* Index: SDL_GICSS0_GIC500SS_1_4_ECC_AGGR   (9) */
    {
        SDL_GICSS0_GIC500SS_1_4_ECC_AGGR_NUM_RAMS,
        SDL_GICSS0_GIC500SS_1_4_ECC_AGGR_RamIdTable,
        SDL_GICSS0_GIC500SS_1_4_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES,
        SDL_GICSS0_GIC500SS_1_4_ECC_AGGR_MemEntries,
        SDL_ESM_INST_MAIN_ESM0,
        SDLR_ESM0_ESM_LVL_EVENT_GICSS0_GIC500SS_1_4_ECC_AGGR_ECC_AGGR_CORR_LEVEL_0,
        SDLR_ESM0_ESM_LVL_EVENT_GICSS0_GIC500SS_1_4_ECC_AGGR_ECC_AGGR_UNCORR_LEVEL_0
    },
 
    /* Index: SDL_ICSSM0_ICSS_M_CORE_BORG_ECC_AGGR  (10) */
    {
        SDL_ICSSM0_ICSS_M_CORE_BORG_ECC_AGGR_NUM_RAMS,
        SDL_ICSSM0_ICSS_M_CORE_BORG_ECC_AGGR_RamIdTable,
        SDL_ICSSM0_ICSS_M_CORE_BORG_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES,
        SDL_ICSSM0_ICSS_M_CORE_BORG_ECC_AGGR_MemEntries,
        SDL_ESM_INST_MAIN_ESM0,
        SDLR_ESM0_ESM_LVL_EVENT_ICSSM0_ICSS_M_CORE_BORG_ECC_AGGR_PR1_ECC_SEC_ERR_PEND_0,
        SDLR_ESM0_ESM_LVL_EVENT_ICSSM0_ICSS_M_CORE_BORG_ECC_AGGR_PR1_ECC_DED_ERR_PEND_0
    },
  /* Index: SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR  (11) */
  {
        SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_NUM_RAMS,
        SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_RamIdTable,
        SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES,
        SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_MemEntries,
        SDL_ESM_INST_MAIN_ESM0,
        SDLR_ESM0_ESM_LVL_EVENT_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_ECC_CORR_LVL_INT_0,
        SDLR_ESM0_ESM_LVL_EVENT_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_ECC_UNCORR_LVL_INT_0
    },
 /* Index: SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR  (12) */
    {
        SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_NUM_RAMS,
        SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_RamIdTable,
        SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES,
        SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_MemEntries,
        SDL_ESM_INST_WKUP_ESM0,
        SDLR_WKUP_ESM0_ESM_LVL_EVENT_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_CORR_LEVEL_0,
        SDLR_WKUP_ESM0_ESM_LVL_EVENT_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR_UNCORR_LEVEL_0
      },
  /* Index: SDL_MCU_M4FSS0_BLAZAR_ECC  (13) */
     {
        SDL_MCU_M4FSS0_BLAZAR_ECC_NUM_RAMS,
        SDL_MCU_M4FSS0_BLAZAR_ECC_RamIdTable,
        SDL_MCU_M4FSS0_BLAZAR_ECC_RAM_IDS_TOTAL_ENTRIES,
        SDL_MCU_M4FSS0_BLAZAR_ECC_MemEntries,
        SDL_ESM_INST_WKUP_ESM0,
        SDLR_WKUP_ESM0_ESM_LVL_EVENT_MCU_M4FSS0_ECC_AGGR_0_ECC_CORRECTED_ERR_LEVEL_0,
        SDLR_WKUP_ESM0_ESM_LVL_EVENT_MCU_M4FSS0_ECC_AGGR_0_ECC_UNCORRECTED_ERR_LEVEL_0
      },
  /* Index: SDL_MCU_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR (14) */
    {
        SDL_MCU_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_NUM_RAMS,
        SDL_MCU_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_RamIdTable,
        SDL_MCU_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES,
        SDL_MCU_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_MemEntries,
        SDL_ESM_INST_WKUP_ESM0,
        SDLR_WKUP_ESM0_ESM_LVL_EVENT_MCU_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_ECC_CORR_LVL_INT_0,
        SDLR_WKUP_ESM0_ESM_LVL_EVENT_MCU_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_ECC_UNCORR_LVL_INT_0
    },
    /* Index: SDL_MCU_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR (15) */
    {
        SDL_MCU_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_NUM_RAMS,
        SDL_MCU_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_RamIdTable,
        SDL_MCU_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES,
        SDL_MCU_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_MemEntries,
        SDL_ESM_INST_WKUP_ESM0,
        SDLR_WKUP_ESM0_ESM_LVL_EVENT_MCU_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_ECC_CORR_LVL_INT_0,
        SDLR_WKUP_ESM0_ESM_LVL_EVENT_MCU_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_ECC_UNCORR_LVL_INT_0
    },
    /* Index: SDL_MMCSD0_EMMCSD8SS_ECC_AGGR_RXMEM (16) */
    {
        SDL_MMCSD0_EMMCSD8SS_ECC_AGGR_RXMEM_NUM_RAMS,
        SDL_MMCSD0_EMMCSD8SS_ECC_AGGR_RXMEM_RamIdTable,
        SDL_MMCSD0_EMMCSD8SS_ECC_AGGR_RXMEM_RAM_IDS_TOTAL_ENTRIES,
        SDL_MMCSD0_EMMCSD8SS_ECC_AGGR_RXMEM_MemEntries,
        SDL_ESM_INST_MAIN_ESM0,
        SDLR_ESM0_ESM_LVL_EVENT_MMCSD0_EMMCSD8SS_ECC_AGGR_RXMEM_EMMCSDSS_RXMEM_CORR_ERR_LVL_0,
        SDLR_ESM0_ESM_LVL_EVENT_MMCSD0_EMMCSD8SS_ECC_AGGR_RXMEM_EMMCSDSS_RXMEM_UNCORR_ERR_LVL_0
    },
    /* Index: SDL_MMCSD0_EMMCSD8SS_ECC_AGGR_TXMEM (17u) */
    {
        SDL_MMCSD0_EMMCSD8SS_ECC_AGGR_TXMEM_NUM_RAMS,
        SDL_MMCSD0_EMMCSD8SS_ECC_AGGR_TXMEM_RamIdTable,
        SDL_MMCSD0_EMMCSD8SS_ECC_AGGR_TXMEM_RAM_IDS_TOTAL_ENTRIES,
        SDL_MMCSD0_EMMCSD8SS_ECC_AGGR_TXMEM_MemEntries,
        SDL_ESM_INST_MAIN_ESM0,
        SDLR_ESM0_ESM_LVL_EVENT_MMCSD0_EMMCSD8SS_ECC_AGGR_TXMEM_EMMCSDSS_TXMEM_CORR_ERR_LVL_0,
        SDLR_ESM0_ESM_LVL_EVENT_MMCSD0_EMMCSD8SS_ECC_AGGR_TXMEM_EMMCSDSS_TXMEM_UNCORR_ERR_LVL_0
    },
    /* Index: SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_RXMEM (18u) */
    {
        SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_RXMEM_NUM_RAMS,
        SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_RXMEM_RamIdTable,
        SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_RXMEM_RAM_IDS_TOTAL_ENTRIES,
        SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_RXMEM_MemEntries,
        SDL_ESM_INST_MAIN_ESM0,
        SDLR_ESM0_ESM_LVL_EVENT_MMCSD1_EMMCSD4SS_ECC_AGGR_RXMEM_EMMCSDSS_RXMEM_CORR_ERR_LVL_0,
        SDLR_ESM0_ESM_LVL_EVENT_MMCSD1_EMMCSD4SS_ECC_AGGR_RXMEM_EMMCSDSS_RXMEM_UNCORR_ERR_LVL_0
    },
 
    /* Index: SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_TXMEM (19u) */
    {
        SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_TXMEM_NUM_RAMS,
        SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_TXMEM_RamIdTable,
        SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_TXMEM_RAM_IDS_TOTAL_ENTRIES,
        SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_TXMEM_MemEntries,
        SDL_ESM_INST_MAIN_ESM0,
        SDLR_ESM0_ESM_LVL_EVENT_MMCSD1_EMMCSD4SS_ECC_AGGR_TXMEM_EMMCSDSS_TXMEM_CORR_ERR_LVL_0,
        SDLR_ESM0_ESM_LVL_EVENT_MMCSD1_EMMCSD4SS_ECC_AGGR_TXMEM_EMMCSDSS_TXMEM_UNCORR_ERR_LVL_0
    },
 
    /* Index: SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_RXMEM  (20u) */
    {
        SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_RXMEM_NUM_RAMS,
        SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_RXMEM_RamIdTable,
        SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_RXMEM_RAM_IDS_TOTAL_ENTRIES,
        SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_RXMEM_MemEntries,
        SDL_ESM_INST_MAIN_ESM0,
        SDLR_ESM0_ESM_LVL_EVENT_MMCSD2_EMMCSD4SS_ECC_AGGR_RXMEM_EMMCSDSS_RXMEM_CORR_ERR_LVL_0,
        SDLR_ESM0_ESM_LVL_EVENT_MMCSD2_EMMCSD4SS_ECC_AGGR_RXMEM_EMMCSDSS_RXMEM_UNCORR_ERR_LVL_0
    },
 
  /* Index: SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_TXMEM    (21) */
  {
        SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_TXMEM_NUM_RAMS,
        SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_TXMEM_RamIdTable,
        SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_TXMEM_RAM_IDS_TOTAL_ENTRIES,
        SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_TXMEM_MemEntries,
        SDL_ESM_INST_MAIN_ESM0,
        SDLR_ESM0_ESM_LVL_EVENT_MMCSD2_EMMCSD4SS_ECC_AGGR_TXMEM_EMMCSDSS_TXMEM_CORR_ERR_LVL_0,
        SDLR_ESM0_ESM_LVL_EVENT_MMCSD2_EMMCSD4SS_ECC_AGGR_TXMEM_EMMCSDSS_TXMEM_UNCORR_ERR_LVL_0
  },
 
/* Index: SDL_PDMA0_SAM62_PDMA_SPI_ECCAGGR  (22u) */
    {
        SDL_PDMA0_SAM62_PDMA_SPI_ECCAGGR_NUM_RAMS,
        SDL_PDMA0_SAM62_PDMA_SPI_ECCAGGR_RamIdTable,
        SDL_PDMA0_SAM62_PDMA_SPI_ECCAGGR_RAM_IDS_TOTAL_ENTRIES,
        SDL_PDMA0_SAM62_PDMA_SPI_ECCAGGR_MemEntries,
        SDL_ESM_INST_MAIN_ESM0,
        SDLR_ESM0_ESM_LVL_EVENT_PDMA0_SAM62_PDMA_SPI_ECCAGGR_ECC_SEC_PEND_0,
        SDLR_ESM0_ESM_LVL_EVENT_PDMA0_SAM62_PDMA_SPI_ECCAGGR_ECC_DED_PEND_0
    },
 
  /* Index: SDL_PDMA1_SAM62_PDMA_UART_ECCAGGR   (23) */
    {
        SDL_PDMA1_SAM62_PDMA_UART_ECCAGGR_NUM_RAMS,
        SDL_PDMA1_SAM62_PDMA_UART_ECCAGGR_RamIdTable,
        SDL_PDMA1_SAM62_PDMA_UART_ECCAGGR_RAM_IDS_TOTAL_ENTRIES,
        SDL_PDMA1_SAM62_PDMA_UART_ECCAGGR_MemEntries,
        SDL_ESM_INST_MAIN_ESM0,
        SDLR_ESM0_ESM_LVL_EVENT_PDMA1_SAM62_PDMA_UART_ECCAGGR_ECC_SEC_PEND_0,
        SDLR_ESM0_ESM_LVL_EVENT_PDMA1_SAM62_PDMA_UART_ECCAGGR_ECC_DED_PEND_0
    },
 
    /* Index: SDL_PSRAMECC_16K0_PSRAM16KX32E_ECC_AGGR  (24) */
    {
        SDL_PSRAMECC_16K0_PSRAM16KX32E_ECC_AGGR_NUM_RAMS,
        SDL_PSRAMECC_16K0_PSRAM16KX32E_ECC_AGGR_RamIdTable,
        SDL_PSRAMECC_16K0_PSRAM16KX32E_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES,
        SDL_PSRAMECC_16K0_PSRAM16KX32E_ECC_AGGR_MemEntries,
        SDL_ESM_INST_MAIN_ESM0,
        SDLR_ESM0_ESM_LVL_EVENT_PSRAMECC_16K0_PSRAM16KX32E_ECC_AGGR_ECC_CORR_LEVEL_0,
        SDLR_ESM0_ESM_LVL_EVENT_PSRAMECC_16K0_PSRAM16KX32E_ECC_AGGR_ECC_UNCORR_LEVEL_0
    },
  /* Index: SDL_PSRAMECC0_PSRAM256X32E_ECC_AGGR  (25) */
  {
        SDL_PSRAMECC0_PSRAM256X32E_ECC_AGGR_NUM_RAMS,
        SDL_PSRAMECC0_PSRAM256X32E_ECC_AGGR_RamIdTable,
        SDL_PSRAMECC0_PSRAM256X32E_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES,
        SDL_PSRAMECC0_PSRAM256X32E_ECC_AGGR_MemEntries,
        SDL_ESM_INST_MAIN_ESM0,
        SDLR_ESM0_ESM_LVL_EVENT_PSRAMECC0_PSRAM256X32E_ECC_AGGR_ECC_CORR_LEVEL_0,
        SDLR_ESM0_ESM_LVL_EVENT_PSRAMECC0_PSRAM256X32E_ECC_AGGR_ECC_UNCORR_LEVEL_0
    },
 /* Index: SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR  (26) */
    {
        SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_NUM_RAMS,
        SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_RamIdTable,
        SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_RAM_IDS_TOTAL_ENTRIES,
        SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR_MemEntries,
        SDL_ESM_INST_MAIN_ESM0,
        SDLR_ESM0_ESM_LVL_EVENT_SA3_SS0_DMSS_ECCAGGR_0_DMSS_ECC_SEC_PEND_0,
        SDLR_ESM0_ESM_LVL_EVENT_SA3_SS0_DMSS_ECCAGGR_0_DMSS_ECC_DED_PEND_0
      },
  /* Index: SDL_SA3_SS0_SA3SS_AM62_SA_UL_ECC_AGGR  (27) */
     {
        SDL_SA3_SS0_SA3SS_AM62_SA_UL_ECC_AGGR_NUM_RAMS,
        SDL_SA3_SS0_SA3SS_AM62_SA_UL_ECC_AGGR_RamIdTable,
        SDL_SA3_SS0_SA3SS_AM62_SA_UL_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES,
        SDL_SA3_SS0_SA3SS_AM62_SA_UL_ECC_AGGR_MemEntries,
        SDL_ESM_INST_MAIN_ESM0,
        SDLR_ESM0_ESM_LVL_EVENT_SA3_SS0_SA_UL_0_SA_UL_ECC_CORR_LEVEL_0,
        SDLR_ESM0_ESM_LVL_EVENT_SA3_SS0_SA_UL_0_SA_UL_ECC_UNCORR_LEVEL_0
      },
  /* Index: SDL_SMS0_SMS_HSM_ECC (28) */
    {
        SDL_SMS0_SMS_HSM_ECC_NUM_RAMS,
        SDL_SMS0_SMS_HSM_ECC_RamIdTable,
        SDL_SMS0_SMS_HSM_ECC_RAM_IDS_TOTAL_ENTRIES,
        SDL_SMS0_SMS_HSM_ECC_MemEntries,
        SDL_ESM_INST_MAIN_ESM0,
        SDLR_ESM0_ESM_LVL_EVENT_SMS0_ECC_AGGR_0_ECC_CORRECTED_LEVEL_0,
        SDLR_ESM0_ESM_LVL_EVENT_SMS0_ECC_AGGR_0_ECC_UNCORRECTED_LEVEL_0
    },
    /* Index: SDL_SMS0_SMS_TIFS_ECC (29) */
    {
        SDL_SMS0_SMS_TIFS_ECC_NUM_RAMS,
        SDL_SMS0_SMS_TIFS_ECC_RamIdTable,
        SDL_SMS0_SMS_TIFS_ECC_RAM_IDS_TOTAL_ENTRIES,
        SDL_SMS0_SMS_TIFS_ECC_MemEntries,
        SDL_ESM_INST_MAIN_ESM0,
        SDLR_ESM0_ESM_LVL_EVENT_SMS0_ECC_AGGR_0_ECC_CORRECTED_LEVEL_0,
        SDLR_ESM0_ESM_LVL_EVENT_SMS0_ECC_AGGR_0_ECC_UNCORRECTED_LEVEL_0
    },
    /* Index: SDL_USB0_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR (30) */
    {
        SDL_USB0_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_NUM_RAMS,
        SDL_USB0_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_RamIdTable,
        SDL_USB0_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES,
        SDL_USB0_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_MemEntries,
        SDL_ESM_INST_MAIN_ESM0,
        SDLR_ESM0_ESM_LVL_EVENT_USB0_USB2SSC_USB2SS_CORE_ECC_AGGR_A_ECC_AGGR_CORRECTED_ERR_LEVEL_0,
        SDLR_ESM0_ESM_LVL_EVENT_USB0_USB2SSC_USB2SS_CORE_ECC_AGGR_A_ECC_AGGR_UNCORRECTED_ERR_LEVEL_0
    },
    /* Index: SDL_USB1_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR (31u) */
    {
        SDL_USB1_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_NUM_RAMS,
        SDL_USB1_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_RamIdTable,
        SDL_USB1_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES,
        SDL_USB1_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_MemEntries,
        SDL_ESM_INST_MAIN_ESM0,
        SDLR_ESM0_ESM_LVL_EVENT_USB1_USB2SSC_USB2SS_CORE_ECC_AGGR_A_ECC_AGGR_CORRECTED_ERR_LEVEL_0,
        SDLR_ESM0_ESM_LVL_EVENT_USB1_USB2SSC_USB2SS_CORE_ECC_AGGR_A_ECC_AGGR_UNCORRECTED_ERR_LEVEL_0
    },
    /* Index: SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR (32u) */
    {
        SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_NUM_RAMS,
        SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_RamIdTable,
        SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES,
        NULL,
        SDL_ESM_INST_WKUP_ESM0,
        SDLR_WKUP_ESM0_ESM_LVL_EVENT_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_CORR_LEVEL_0,
        SDLR_WKUP_ESM0_ESM_LVL_EVENT_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR_UNCORR_LEVEL_0
 
    },
    /* SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR (33) */
      {
          SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_NUM_RAMS,
          SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_RamIdTable,
          SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES,
          SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_MemEntries,
          SDL_ESM_INST_MAIN_ESM0,
          SDLR_ESM0_ESM_LVL_EVENT_R5FSS0_CORE0_ECC_CORRECTED_LEVEL_0,
          SDLR_ESM0_ESM_LVL_EVENT_R5FSS0_CORE0_ECC_UNCORRECTED_LEVEL_0
        },
    /* SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR (34) */
      {
          SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_NUM_RAMS,
          SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_RamIdTable,
          SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES,
          NULL,
          SDL_ESM_INST_WKUP_ESM0,
          SDLR_WKUP_ESM0_ESM_LVL_EVENT_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_CORR_LEVEL_0,
          SDLR_WKUP_ESM0_ESM_LVL_EVENT_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR_UNCORR_LEVEL_0
      },
    /* SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR (35) */
      {
          SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_NUM_RAMS,
          SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_RamIdTable,
          SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_RAM_IDS_TOTAL_ENTRIES,
          NULL,
          SDL_ESM_INST_WKUP_ESM0,
          SDLR_WKUP_ESM0_ESM_LVL_EVENT_WKUP_VTM0_K3VTM_NC_ECCAGGR_CORR_LEVEL_0,
          SDLR_WKUP_ESM0_ESM_LVL_EVENT_WKUP_VTM0_K3VTM_NC_ECCAGGR_UNCORR_LEVEL_0
      },
    /* SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR (36) */
      {
          SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR_SPECIAL_NUM_RAMS,
          SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR_RamIdTable,
          SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES,
          SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR_MemEntries,
          SDL_ESM_INST_MAIN_ESM0,
          SDLR_ESM0_ESM_LVL_EVENT_CPSW0_ECC_SEC_PEND_0,
          SDLR_ESM0_ESM_LVL_EVENT_CPSW0_ECC_DED_PEND_0
      },
};
 #endif /* INCLUDE_SDL_ECC_SOC_H_ */