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AM62x MCU+ SDK
08.05.00
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41 #ifndef SCICLIENT_FMWMSGPARAMS_H_
42 #define SCICLIENT_FMWMSGPARAMS_H_
59 #define TISCI_PARAM_UNDEF (0xFFFFFFFFU)
69 #define SCICLIENT_FIRMWARE_ABI_MAJOR (3U)
74 #define SCICLIENT_FIRMWARE_ABI_MINOR (5U)
84 #define SCICLIENT_CONTEXT_R5_SEC_0 (0U)
86 #define SCICLIENT_CONTEXT_R5_NONSEC_0 (1U)
88 #define SCICLIENT_CONTEXT_R5_SEC_1 (2U)
90 #define SCICLIENT_CONTEXT_R5_NONSEC_1 (3U)
92 #define SCICLIENT_CONTEXT_A53_SEC_0 (4U)
94 #define SCICLIENT_CONTEXT_A53_SEC_1 (5U)
96 #define SCICLIENT_CONTEXT_A53_NONSEC_0 (6U)
98 #define SCICLIENT_CONTEXT_A53_NONSEC_1 (7U)
100 #define SCICLIENT_CONTEXT_M4_NONSEC_0 (8U)
102 #define SCICLIENT_CONTEXT_GPU_NONSEC_0 (9U)
104 #define SCICLIENT_CONTEXT_A53_NONSEC_2 (10U)
107 #define SCICLIENT_CONTEXT_MAX_NUM (11U)
118 #define SCICLIENT_PROC_ID_A53SS0_CORE_0 (0x20U)
120 #define SCICLIENT_PROC_ID_A53SS0_CORE_1 (0x21U)
122 #define SCICLIENT_PROC_ID_A53SS0_CORE_2 (0x22U)
124 #define SCICLIENT_PROC_ID_A53SS0_CORE_3 (0x23U)
126 #define SCICLIENT_PROC_ID_R5FSS0_CORE0 (0x01U)
128 #define SCICLIENT_PROC_ID_MCU_M4FSS0_CORE0 (0x18U)
130 #define SCICLIENT_PROC_ID_HSM_M4FSS0_CORE0 (0x80U)
133 #define SOC_NUM_SCICLIENT_PROCESSORS (0x07U)
140 #define TISCI_MSG_VALUE_RM_NULL_RING_TYPE (0xFFFFu)
141 #define TISCI_MSG_VALUE_RM_NULL_RING_INDEX (0xFFFFFFFFu)
142 #define TISCI_MSG_VALUE_RM_NULL_RING_ADDR (0xFFFFFFFFu)
143 #define TISCI_MSG_VALUE_RM_NULL_RING_COUNT (0xFFFFFFFFu)
149 #define TISCI_MSG_VALUE_RM_NULL_RING_MODE (0xFFu)
150 #define TISCI_MSG_VALUE_RM_NULL_RING_SIZE (0xFFu)
151 #define TISCI_MSG_VALUE_RM_NULL_ORDER_ID (0xFFu)
152 #define TISCI_MSG_VALUE_RM_UDMAP_NULL_CH_TYPE (0xFFu)
153 #define TISCI_MSG_VALUE_RM_UDMAP_NULL_CH_INDEX (0xFFFFFFFFu)
181 #define TISCI_RINGACC0_OES_IRQ_SRC_IDX_START (20U)
182 #define TISCI_RINGACC0_EOES_IRQ_SRC_IDX_START (32U)
183 #define TISCI_TIMERMGR_OES_IRQ_SRC_IDX_START (0U)
184 #define TISCI_PKTDMA0_TX_EOES_IRQ_SRC_IDX_START (4096U)
185 #define TISCI_PKTDMA0_TX_FLOW_OES_IRQ_SRC_IDX_START (4608U)
186 #define TISCI_PKTDMA0_RX_EOES_IRQ_SRC_IDX_START (5120U)
187 #define TISCI_PKTDMA0_RX_FLOW_OES_IRQ_SRC_IDX_START (5632U)
188 #define TISCI_PKTDMA0_RX_FLOW_SOES_IRQ_SRC_IDX_START (6144U)
189 #define TISCI_PKTDMA0_RX_FLOW_FOES_IRQ_SRC_IDX_START (6656U)
190 #define TISCI_BCDMA0_BC_EOES_IRQ_SRC_IDX_START (8192U)
191 #define TISCI_BCDMA0_BC_DC_OES_IRQ_SRC_IDX_START (8704U)
192 #define TISCI_BCDMA0_BC_RC_OES_IRQ_SRC_IDX_START (9216U)
193 #define TISCI_BCDMA0_TX_EOES_IRQ_SRC_IDX_START (9728U)
194 #define TISCI_BCDMA0_TX_DC_OES_IRQ_SRC_IDX_START (10240U)
195 #define TISCI_BCDMA0_TX_RC_OES_IRQ_SRC_IDX_START (10752U)
196 #define TISCI_BCDMA0_RX_EOES_IRQ_SRC_IDX_START (11264U)
197 #define TISCI_BCDMA0_RX_DC_OES_IRQ_SRC_IDX_START (11776U)
198 #define TISCI_BCDMA0_RX_RC_OES_IRQ_SRC_IDX_START (12288U)
208 #define SCICLIENT_DEV_MCU_R5FSS0_CORE0 (TISCI_DEV_R5FSS0_CORE0)
209 #define SCICLIENT_DEV_MCU_R5FSS0_CORE1 (TISCI_DEV_R5FSS0_CORE0)
218 #define SCICLIENT_DEV_MCU_R5FSS0_CORE0_PROCID \
219 (SCICLIENT_PROC_ID_R5FSS0_CORE0)
220 #define SCICLIENT_DEV_MCU_R5FSS0_CORE1_PROCID \
221 (SCICLIENT_PROC_ID_R5FSS0_CORE0)
225 #define SCICLIENT_ALLOWED_BOARDCFG_BASE_START 1
227 #define SCICLIENT_ALLOWED_BOARDCFG_BASE_END 0xFFFFFFFF