docs/api_guide_am62x/tisci__resasg__types_8h_source.html

/*

 *  Copyright (C) 2017-2022 Texas Instruments Incorporated

 *

 *  Redistribution and use in source and binary forms, with or without

 *  modification, are permitted provided that the following conditions

 *  are met:

 *

 *    Redistributions of source code must retain the above copyright

 *    notice, this list of conditions and the following disclaimer.

 *

 *    Redistributions in binary form must reproduce the above copyright

 *    notice, this list of conditions and the following disclaimer in the

 *    documentation and/or other materials provided with the

 *    distribution.

 *

 *    Neither the name of Texas Instruments Incorporated nor the names of

 *    its contributors may be used to endorse or promote products derived

 *    from this software without specific prior written permission.

 *

 *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS

 *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT

 *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR

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 */

#ifndef TISCI_RESASG_TYPES_H

#define TISCI_RESASG_TYPES_H


#ifdef __cplusplus

extern "C"

{

#endif


#define TISCI_RESASG_TYPE_SHIFT (0x0006U)


#define TISCI_RESASG_TYPE_MASK (0xFFC0U)


#define TISCI_RESASG_SUBTYPE_SHIFT (0x0000U)


#define TISCI_RESASG_SUBTYPE_MASK (0x003FU)


#define TISCI_RESASG_UTYPE(type, subtype) \

    (((type << TISCI_RESASG_TYPE_SHIFT) & TISCI_RESASG_TYPE_MASK) | \

     ((subtype << TISCI_RESASG_SUBTYPE_SHIFT) & TISCI_RESASG_SUBTYPE_MASK))


#define TISCI_RESASG_SUBTYPE_IA_VINT (0x000AU)

#define TISCI_RESASG_SUBTYPE_GLOBAL_EVENT_GEVT (0x000BU)

#define TISCI_RESASG_SUBTYPE_GLOBAL_EVENT_MEVT (0x000CU)

#define TISCI_RESASG_SUBTYPE_GLOBAL_EVENT_SEVT (0x000DU)

#define TISCI_RESASG_SUBTYPE_GLOBAL_EVENT_LEVT (0x000EU)

#define TISCI_RESASG_SUBTYPE_IA_TIMERMGR_EVT_OES (0x000FU)

#define TISCI_RESASG_SUBTYPE_IA_PKTDMA_TX_CHAN_ERROR_OES (0x0010U)

#define TISCI_RESASG_SUBTYPE_IA_PKTDMA_TX_FLOW_COMPLETION_OES (0x0011U)

#define TISCI_RESASG_SUBTYPE_IA_PKTDMA_RX_CHAN_ERROR_OES (0x0012U)

#define TISCI_RESASG_SUBTYPE_IA_PKTDMA_RX_FLOW_COMPLETION_OES (0x0013U)

#define TISCI_RESASG_SUBTYPE_IA_PKTDMA_RX_FLOW_STARVATION_OES (0x0014U)

#define TISCI_RESASG_SUBTYPE_IA_PKTDMA_RX_FLOW_FIREWALL_OES (0x0015U)

#define TISCI_RESASG_SUBTYPE_IA_BCDMA_CHAN_ERROR_OES (0x0016U)

#define TISCI_RESASG_SUBTYPE_IA_BCDMA_CHAN_DATA_COMPLETION_OES (0x0017U)

#define TISCI_RESASG_SUBTYPE_IA_BCDMA_CHAN_RING_COMPLETION_OES (0x0018U)

#define TISCI_RESASG_SUBTYPE_IA_BCDMA_TX_CHAN_ERROR_OES (0x0019U)

#define TISCI_RESASG_SUBTYPE_IA_BCDMA_TX_CHAN_DATA_COMPLETION_OES (0x001AU)

#define TISCI_RESASG_SUBTYPE_IA_BCDMA_TX_CHAN_RING_COMPLETION_OES (0x001BU)

#define TISCI_RESASG_SUBTYPE_IA_BCDMA_RX_CHAN_ERROR_OES (0x001CU)

#define TISCI_RESASG_SUBTYPE_IA_BCDMA_RX_CHAN_DATA_COMPLETION_OES (0x001DU)

#define TISCI_RESASG_SUBTYPE_IA_BCDMA_RX_CHAN_RING_COMPLETION_OES (0x001EU)

#define TISCI_RESASG_SUBTYPES_IA_CNT (0x0015U)


#define TISCI_RESASG_SUBTYPE_IR_OUTPUT (0x0000U)

#define TISCI_RESASG_SUBTYPES_IR_CNT (0x0001U)


#define TISCI_RESASG_SUBTYPE_RA_ERROR_OES (0x0000U)

#define TISCI_RESASG_SUBTYPE_RA_VIRTID (0x000AU)

#define TISCI_RESASG_SUBTYPE_BCDMA_RING_BLOCK_COPY_CHAN (0x000DU)

#define TISCI_RESASG_SUBTYPE_BCDMA_RING_SPLIT_TR_RX_CHAN (0x000EU)

#define TISCI_RESASG_SUBTYPE_BCDMA_RING_SPLIT_TR_TX_CHAN (0x000FU)

#define TISCI_RESASG_SUBTYPE_PKTDMA_RING_UNMAPPED_TX_CHAN (0x0010U)

#define TISCI_RESASG_SUBTYPE_PKTDMA_RING_CPSW_TX_CHAN (0x0011U)

#define TISCI_RESASG_SUBTYPE_PKTDMA_RING_SAUL_TX_0_CHAN (0x0012U)

#define TISCI_RESASG_SUBTYPE_PKTDMA_RING_SAUL_TX_1_CHAN (0x0013U)

#define TISCI_RESASG_SUBTYPE_PKTDMA_RING_UNMAPPED_RX_CHAN (0x0016U)

#define TISCI_RESASG_SUBTYPE_PKTDMA_RING_CPSW_RX_CHAN (0x0017U)

#define TISCI_RESASG_SUBTYPE_PKTDMA_RING_SAUL_RX_0_CHAN (0x0018U)

#define TISCI_RESASG_SUBTYPE_PKTDMA_RING_SAUL_RX_1_CHAN (0x0019U)

#define TISCI_RESASG_SUBTYPE_PKTDMA_RING_SAUL_RX_2_CHAN (0x001AU)

#define TISCI_RESASG_SUBTYPE_PKTDMA_RING_SAUL_RX_3_CHAN (0x001BU)

#define TISCI_RESASG_SUBTYPES_RA_CNT (0x000FU)


#define TISCI_RESASG_SUBTYPE_GLOBAL_EVENT_TRIGGER (0x0002U)

#define TISCI_RESASG_SUBTYPE_UDMAP_GLOBAL_CONFIG (0x0003U)

#define TISCI_RESASG_SUBTYPE_BCDMA_BLOCK_COPY_CHAN (0x0020U)

#define TISCI_RESASG_SUBTYPE_BCDMA_SPLIT_TR_RX_CHAN (0x0021U)

#define TISCI_RESASG_SUBTYPE_BCDMA_SPLIT_TR_TX_CHAN (0x0022U)

#define TISCI_RESASG_SUBTYPE_PKTDMA_UNMAPPED_TX_CHAN (0x0023U)

#define TISCI_RESASG_SUBTYPE_PKTDMA_CPSW_TX_CHAN (0x0024U)

#define TISCI_RESASG_SUBTYPE_PKTDMA_SAUL_TX_0_CHAN (0x0025U)

#define TISCI_RESASG_SUBTYPE_PKTDMA_SAUL_TX_1_CHAN (0x0026U)

#define TISCI_RESASG_SUBTYPE_PKTDMA_UNMAPPED_RX_CHAN (0x0029U)

#define TISCI_RESASG_SUBTYPE_PKTDMA_FLOW_UNMAPPED_RX_CHAN (0x002AU)

#define TISCI_RESASG_SUBTYPE_PKTDMA_CPSW_RX_CHAN (0x002BU)

#define TISCI_RESASG_SUBTYPE_PKTDMA_FLOW_CPSW_RX_CHAN (0x002CU)

#define TISCI_RESASG_SUBTYPE_PKTDMA_SAUL_RX_0_CHAN (0x002DU)

#define TISCI_RESASG_SUBTYPE_PKTDMA_FLOW_SAUL_RX_0_CHAN (0x002EU)

#define TISCI_RESASG_SUBTYPE_PKTDMA_SAUL_RX_1_CHAN (0x002FU)

#define TISCI_RESASG_SUBTYPE_PKTDMA_FLOW_SAUL_RX_1_CHAN (0x0030U)

#define TISCI_RESASG_SUBTYPE_PKTDMA_SAUL_RX_2_CHAN (0x0031U)

#define TISCI_RESASG_SUBTYPE_PKTDMA_FLOW_SAUL_RX_2_CHAN (0x0032U)

#define TISCI_RESASG_SUBTYPE_PKTDMA_SAUL_RX_3_CHAN (0x0033U)

#define TISCI_RESASG_SUBTYPE_PKTDMA_FLOW_SAUL_RX_3_CHAN (0x0034U)

#define TISCI_RESASG_SUBTYPES_UDMAP_CNT (0x0015U)


#define TISCI_RESASG_UTYPE_CNT 61U


#define TISCI_RESASG_ENTRIES_MAX (TISCI_RESASG_UTYPE_CNT * 5U)


#ifdef __cplusplus

}

#endif


#endif /* TISCI_RESASG_TYPES_H */