tisci_procboot.h

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/*
 *  Copyright (C) 2017-2022 Texas Instruments Incorporated
 *
 *  Redistribution and use in source and binary forms, with or without
 *  modification, are permitted provided that the following conditions
 *  are met:
 *
 *    Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 *
 *    Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the
 *    distribution.
 *
 *    Neither the name of Texas Instruments Incorporated nor the names of
 *    its contributors may be used to endorse or promote products derived
 *    from this software without specific prior written permission.
 *
 *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
 *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
 *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
 *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
 *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
 */
#ifndef TISCI_PROCBOOT_H_
#define TISCI_PROCBOOT_H_
 
#ifdef __cplusplus
extern "C"
{
#endif
 
 
 
struct tisci_msg_proc_request_req {
    struct tisci_header    hdr;
    uint8_t            processor_id;
} __attribute__((__packed__));
 
struct tisci_msg_proc_request_resp {
    struct tisci_header hdr;
} __attribute__((__packed__));
 
struct tisci_msg_proc_release_req {
    struct tisci_header    hdr;
    uint8_t            processor_id;
} __attribute__((__packed__));
 
struct tisci_msg_proc_release_resp {
    struct tisci_header hdr;
} __attribute__((__packed__));
 
struct tisci_msg_proc_handover_req {
    struct tisci_header    hdr;
    uint8_t            processor_id;
    uint8_t            host_id;
} __attribute__((__packed__));
 
struct tisci_msg_proc_handover_resp {
    struct tisci_header hdr;
} __attribute__((__packed__));
 
/* A53 Config Flags */
 
#define TISCI_MSG_VAL_PROC_BOOT_CFG_FLAG_ARMV8_DBG_EN         (0x00000001U)
 
#define TISCI_MSG_VAL_PROC_BOOT_CFG_FLAG_ARMV8_DBG_NIDEN      (0x00000002U)
 
#define TISCI_MSG_VAL_PROC_BOOT_CFG_FLAG_ARMV8_DBG_SPIDEN     (0x00000004U)
 
#define TISCI_MSG_VAL_PROC_BOOT_CFG_FLAG_ARMV8_DBG_SPNIDEN    (0x00000008U)
 
#define TISCI_MSG_VAL_PROC_BOOT_CFG_FLAG_ARMV8_AARCH32        (0x00000100U)
 
/* R5 Config Flags */
 
#define TISCI_MSG_VAL_PROC_BOOT_CFG_FLAG_R5_DBG_EN            (0x00000001U)
 
#define TISCI_MSG_VAL_PROC_BOOT_CFG_FLAG_R5_DBG_NIDEN         (0x00000002U)
 
#define TISCI_MSG_VAL_PROC_BOOT_CFG_FLAG_R5_LOCKSTEP          (0x00000100U)
 
#define TISCI_MSG_VAL_PROC_BOOT_CFG_FLAG_R5_TEINIT            (0x00000200U)
 
#define TISCI_MSG_VAL_PROC_BOOT_CFG_FLAG_R5_NMFI_EN           (0x00000400U)
 
#define TISCI_MSG_VAL_PROC_BOOT_CFG_FLAG_R5_TCM_RSTBASE       (0x00000800U)
 
#define TISCI_MSG_VAL_PROC_BOOT_CFG_FLAG_R5_BTCM_EN           (0x00001000U)
 
#define TISCI_MSG_VAL_PROC_BOOT_CFG_FLAG_R5_ATCM_EN           (0x00002000U)
 
#define TISCI_MSG_VAL_PROC_BOOT_CFG_FLAG_R5_MEM_INIT_DIS      (0x00004000U)
 
#define TISCI_MSG_VAL_PROC_BOOT_CFG_FLAG_R5_SINGLE_CORE       (0x00008000U)
 
/* C7x Config Flags */
 
/* L2_PIPELINE_LATENCY_VALUE */
#define TISCI_MSG_VAL_PROC_BOOT_CFG_FLAG_C7X_L2PL_MASK        (0x0000000FU)
 
#define TISCI_MSG_VAL_PROC_BOOT_CFG_FLAG_C7X_L2PL_SHIFT       (0x00000000U)
 
#define TISCI_MSG_VAL_PROC_BOOT_CFG_FLAG_C7X_L2PL_1           (0x00000001U)
 
#define TISCI_MSG_VAL_PROC_BOOT_CFG_FLAG_C7X_L2PL_2           (0x00000002U)
 
#define TISCI_MSG_VAL_PROC_BOOT_CFG_FLAG_C7X_L2PL_3           (0x00000003U)
 
#define TISCI_MSG_VAL_PROC_BOOT_CFG_FLAG_C7X_L2PL_4           (0x00000004U)
 
#define TISCI_MSG_VAL_PROC_BOOT_CFG_FLAG_C7X_L2PL_5           (0x00000005U)
 
/* L2_ACCESS_LATENCY_VALUE */
#define TISCI_MSG_VAL_PROC_BOOT_CFG_FLAG_C7X_L2AL_MASK        (0x000000F0U)
 
#define TISCI_MSG_VAL_PROC_BOOT_CFG_FLAG_C7X_L2AL_SHIFT       (0x00000004U)
 
#define TISCI_MSG_VAL_PROC_BOOT_CFG_FLAG_C7X_L2AL_2           (0x00000020U)
 
#define TISCI_MSG_VAL_PROC_BOOT_CFG_FLAG_C7X_L2AL_3           (0x00000030U)
 
#define TISCI_MSG_VAL_PROC_BOOT_CFG_FLAG_C7X_L2AL_4           (0x00000040U)
 
#define TISCI_MSG_VAL_PROC_BOOT_CFG_FLAG_C7X_L2AL_5           (0x00000050U)
 
/* C6x Config Flags */
 
/* SSCLK_MODE_DIV_CLK_MODE_VALUE values
 *
 * NOTE: Values are 1 more than actual programmed values to avoid '0' as a
 * valid value that we pass via flags.
 */
#define TISCI_MSG_VAL_PROC_BOOT_CFG_FLAG_C6X_SSCLKMV_MASK    (0x00000007U)
 
#define TISCI_MSG_VAL_PROC_BOOT_CFG_FLAG_C6X_SSCLKMV_SHIFT   (0x00000000U)
 
#define TISCI_MSG_VAL_PROC_BOOT_CFG_FLAG_C6X_SSCLKMV_DIV2    (0x00000001U)
 
#define TISCI_MSG_VAL_PROC_BOOT_CFG_FLAG_C6X_SSCLKMV_DIV3    (0x00000002U)
 
#define TISCI_MSG_VAL_PROC_BOOT_CFG_FLAG_C6X_SSCLKMV_DIV4    (0x00000003U)
 
/* M4F Config Flags */
 
#define TISCI_MSG_VAL_PROC_BOOT_CFG_FLAG_M4F_DBG_EN            (0x00000001U)
 
#define TISCI_MSG_VAL_PROC_BOOT_CFG_FLAG_M4F_DBG_NIDEN         (0x00000002U)
 
struct tisci_msg_proc_set_config_req {
    struct tisci_header    hdr;
    uint8_t            processor_id;
    uint32_t            bootvector_lo;
    uint32_t            bootvector_hi;
    uint32_t            config_flags_1_set;
    uint32_t            config_flags_1_clear;
} __attribute__((__packed__));
 
struct tisci_msg_proc_set_config_resp {
    struct tisci_header hdr;
} __attribute__((__packed__));
 
/* ARMV8 Control Flags */
 
#define TISCI_MSG_VAL_PROC_BOOT_CTRL_FLAG_ARMV8_ACINACTM                (0x00000001U)
 
#define TISCI_MSG_VAL_PROC_BOOT_CTRL_FLAG_ARMV8_AINACTS                 (0x00000002U)
 
#define TISCI_MSG_VAL_PROC_BOOT_CTRL_FLAG_ARMV8_L2FLUSHREQ              (0x00000100U)
 
/* R5 Control Flags */
 
#define TISCI_MSG_VAL_PROC_BOOT_CTRL_FLAG_R5_CORE_HALT                (0x00000001U)
 
#define TISCI_MSG_VAL_PROC_BOOT_CTRL_FLAG_R5_LPSC                     (0x00000002U)
 
#define TISCI_MSG_VAL_PROC_BOOT_CTRL_FLAG_R5_RESET                    (0x00000004U)
 
/* HSM Control Flags */
#define TISCI_MSG_VAL_PROC_BOOT_CTRL_FLAG_HSM_M4_RESET                (0x00000001U)
 
struct tisci_msg_proc_set_control_req {
    struct tisci_header    hdr;
    uint8_t            processor_id;
    uint32_t            control_flags_1_set;
    uint32_t            control_flags_1_clear;
} __attribute__((__packed__));
 
struct tisci_msg_proc_set_control_resp {
    struct tisci_header hdr;
} __attribute__((__packed__));
 
struct tisci_msg_proc_auth_boot_req {
    struct tisci_header    hdr;
    uint32_t            certificate_address_lo;
    uint32_t            certificate_address_hi;
} __attribute__((__packed__));
 
struct tisci_msg_proc_auth_boot_resp {
    struct tisci_header    hdr;
    uint32_t            image_address_lo;
    uint32_t            image_address_hi;
    uint32_t            image_size;
} __attribute__((__packed__));
 
struct tisci_msg_proc_get_status_req {
    struct tisci_header    hdr;
    uint8_t            processor_id;
} __attribute__((__packed__));
 
/* ARMV8 Status Flags */
 
#define TISCI_MSG_VAL_PROC_BOOT_STATUS_FLAG_ARMV8_WFE         (0x00000001U)
 
#define TISCI_MSG_VAL_PROC_BOOT_STATUS_FLAG_ARMV8_WFI         (0x00000002U)
 
#define TISCI_MSG_VAL_PROC_BOOT_STATUS_FLAG_ARMV8_L2F_DONE    (0x00000010U)
 
#define TISCI_MSG_VAL_PROC_BOOT_STATUS_FLAG_ARMV8_STANDBYWFIL2       (0x00000020U)
 
/* R5 Status Flags */
 
#define TISCI_MSG_VAL_PROC_BOOT_STATUS_FLAG_R5_WFE            (0x00000001U)
 
#define TISCI_MSG_VAL_PROC_BOOT_STATUS_FLAG_R5_WFI            (0x00000002U)
 
#define TISCI_MSG_VAL_PROC_BOOT_STATUS_FLAG_R5_CLK_GATED      (0x00000004U)
 
#define TISCI_MSG_VAL_PROC_BOOT_STATUS_FLAG_R5_LOCKSTEP_PERMITTED     (0x00000100U)
 
#define TISCI_MSG_VAL_PROC_BOOT_STATUS_FLAG_R5_SINGLECORE_ONLY        (0x00000200U)
 
/* C7x Status Flags */
 
#define TISCI_MSG_VAL_PROC_BOOT_STATUS_FLAG_C7X_WFE         (0x00000001U)
 
#define TISCI_MSG_VAL_PROC_BOOT_STATUS_FLAG_C7X_WFI         (0x00000002U)
 
/* M4F Status Flags */
 
#define TISCI_MSG_VAL_PROC_BOOT_STATUS_FLAG_M4F_WFI            (0x00000002U)
 
struct tisci_msg_proc_get_status_resp {
    struct tisci_header    hdr;
    uint8_t            processor_id;
    uint32_t            bootvector_lo;
    uint32_t            bootvector_hi;
    uint32_t            config_flags_1;
    uint32_t            control_flags_1;
    uint32_t            status_flags_1;
} __attribute__((__packed__));
 
struct tisci_msg_proc_status_wait_req {
    struct tisci_header    hdr;
    uint8_t            processor_id;
    uint8_t            num_wait_iterations;
    uint8_t            num_match_iterations;
    uint8_t            delay_per_iteration_us;
    uint8_t            delay_before_iteration_loop_start_us;
    uint32_t            status_flags_1_set_all_wait;
    uint32_t            status_flags_1_set_any_wait;
    uint32_t            status_flags_1_clr_all_wait;
    uint32_t            status_flags_1_clr_any_wait;
} __attribute__((__packed__));
 
struct tisci_msg_proc_status_wait_resp {
    struct tisci_header hdr;
} __attribute__((__packed__));
 
 
#ifdef __cplusplus
}
#endif
 
#endif /* TISCI_SECURITY_H_ */