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AM62Px MCU+ SDK
09.02.01
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50 #ifndef SDL_IP_PBIST_H_
51 #define SDL_IP_PBIST_H_
60 #include <sdl/pbist/v0/soc/sdl_soc_pbist.h>
uint32_t RAMT
Definition: sdl_ip_pbist.h:161
Definition: sdlr_pbist.h:53
uint32_t I0
Definition: sdl_ip_pbist.h:145
Definition: sdl_soc_pbist.h:121
int32_t SDL_PBIST_checkResult(const SDL_pbistRegs *pPBISTRegs, bool *pResult)
PBIST check result.
uint32_t I1
Definition: sdl_ip_pbist.h:149
int32_t SDL_PBIST_getPOSTStatus(SDL_PBIST_postResult *pResult)
PBIST POST result status.
uint64_t scrambleValue
Definition: sdl_ip_pbist.h:89
uint32_t I2
Definition: sdl_ip_pbist.h:153
uint32_t CMS
Definition: sdl_ip_pbist.h:137
uint64_t memoryGroupsBitMap
Definition: sdl_ip_pbist.h:85
int32_t SDL_PBIST_releaseTestMode(SDL_pbistRegs *pPBISTRegs)
PBIST Release Test mode.
uint32_t CSR
Definition: sdl_ip_pbist.h:141
This structure contains the different configuration used for PBIST.
Definition: sdl_ip_pbist.h:71
uint32_t CL3
Definition: sdl_ip_pbist.h:133
uint32_t CA2
Definition: sdl_ip_pbist.h:113
uint32_t CA1
Definition: sdl_ip_pbist.h:109
uint32_t CL0
Definition: sdl_ip_pbist.h:121
uint32_t CA0
Definition: sdl_ip_pbist.h:105
int32_t SDL_PBIST_start(SDL_pbistRegs *pPBISTRegs, const SDL_PBIST_config *pConfig)
PBIST Start.
uint32_t CL2
Definition: sdl_ip_pbist.h:129
uint32_t algorithmsBitMap
Definition: sdl_ip_pbist.h:81
int32_t SDL_PBIST_softReset(SDL_pbistRegs *pPBISTRegs)
PBIST Soft reset.
uint32_t CA3
Definition: sdl_ip_pbist.h:117
uint32_t CL1
Definition: sdl_ip_pbist.h:125
This structure contains the different configuration used for PBIST for the failure insertion test to ...
Definition: sdl_ip_pbist.h:102
uint32_t I3
Definition: sdl_ip_pbist.h:157
int32_t SDL_PBIST_startNeg(SDL_pbistRegs *pPBISTRegs, const SDL_PBIST_configNeg *pConfig)
PBIST Failure Insertion Test Start.