46 #ifndef SAFETY_CHECKERS_PM_SOC_H_
47 #define SAFETY_CHECKERS_PM_SOC_H_
72 #define SAFETY_CHECKERS_PM_WKUP_PSC_BASE_ADDRESS (CSL_WKUP_PSC0_BASE)
75 #define SAFETY_CHECKERS_PM_PSC_PD_STAT_OFFSET (0x200U)
77 #define SAFETY_CHECKERS_PM_PSC_MD_STAT_OFFSET (0x800U)
80 #define SAFETY_CHECKERS_PM_PLL_BASE_ADDRESS(i) (SAFETY_CHECKERS_PM_PLL_CFG_BASE_ADDRESS + (0x1000U * (uint32_t)i))
81 #define SAFETY_CHECKERS_PM_MCU_PLL_BASE_ADDRESS(i) (SAFETY_CHECKERS_PM_MCU_PLL_CFG_BASE_ADDRESS + (0x1000U * (uint32_t)i))
84 #define SAFETY_CHECKERS_PM_KICK_LOCK (0x00000000U)
85 #define SAFETY_CHECKERS_PM_LOCK_KEY0_OFFSET (0x10U)
86 #define SAFETY_CHECKERS_PM_LOCK_KEY1_OFFSET (0x14U)
107 {0x00U, 0x08U, 0x20U, 0x24U, 0x30U, 0x34U, 0x38U,
108 0x40U, 0x44U, 0x80U, 0x84U, 0x88U, 0x8cU, 0x90U,
109 0x94U, 0x98U, 0x9cU, 0xA0U, 0xA4U};
112 {0x00U, 0x08U, 0x20U, 0x24U, 0x30U, 0x34U, 0x38U,
113 0x40U, 0x44U, 0x60U, 0x80U, 0x84U};
116 {0x00U, 0x08U, 0x20U, 0x24U, 0x38U, 0x50U, 0x60U,
117 0x64U, 0x80U, 0x84U};
120 {0x00U, 0x08U, 0x20U, 0x24U, 0x30U, 0x34U, 0x38U,
121 0x40U, 0x44U, 0x60U, 0x64U, 0x80U, 0x84U, 0x88U,
122 0x8CU, 0x90U, 0x94U, 0x98U, 0x9CU, 0xA0U, 0xA4U,
126 {0x00U, 0x08U, 0x20U, 0x24U, 0x30U, 0x34U, 0x38U,
127 0x40U, 0x44U, 0x80U, 0x84U, 0x88U, 0x8cU, 0x90U,
128 0x94U, 0x9cU, 0xA0U};
131 {0x00U, 0x08U, 0x20U, 0x24U, 0x30U, 0x34U, 0x38U,
132 0x40U, 0x44U, 0x80U, 0x84U, 0x88U, 0x8cU, 0x90U,