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AM62Px MCU+ SDK
09.02.01
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◆ gSafetyCheckers_PmPllData
Initial value:
Structure defines PLL register base address and the total length of registers.
◆ gSafetyCheckers_PmPscData
Initial value:
Structure defines PSC register base address and the total length of registers.
◆ gSafetyCheckers_RmRegData
Initial value:=
{
{
SAFETY_CHECKERS_RM_BA0_IR,
SAFETY_CHECKERS_RM_IR_SUBMOD0_NUM,
SAFETY_CHECKERS_RM_IR_REG0_NUM,
SAFETY_CHECKERS_RM_REG_HEX4, {0X0U, 0x4U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U}},
{
SAFETY_CHECKERS_RM_BA1_IR,
SAFETY_CHECKERS_RM_IR_SUBMOD0_NUM,
SAFETY_CHECKERS_RM_IR_REG1_NUM,
SAFETY_CHECKERS_RM_REG_HEX4, {0X0U, 0x4U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U}},
{
SAFETY_CHECKERS_RM_BA2_IR,
SAFETY_CHECKERS_RM_IR_SUBMOD0_NUM,
SAFETY_CHECKERS_RM_IR_REG2_NUM,
SAFETY_CHECKERS_RM_REG_HEX4, {0X0U, 0x4U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U}},
{
SAFETY_CHECKERS_RM_BA0_IA_IMAP,
SAFETY_CHECKERS_RM_SUBMOD0_IA_IMAP,
SAFETY_CHECKERS_RM_REG0_IA_IMAP,
SAFETY_CHECKERS_RM_REG_HEX8, {0X0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U}},
{
SAFETY_CHECKERS_RM_BA1_IA_IMAP,
SAFETY_CHECKERS_RM_SUBMOD0_IA_IMAP,
SAFETY_CHECKERS_RM_REG1_IA_IMAP,
SAFETY_CHECKERS_RM_REG_HEX8, {0X0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U}},
{
SAFETY_CHECKERS_RM_BA0_RA,
SAFETY_CHECKERS_RM_SUBMOD0_RA,
SAFETY_CHECKERS_RM_RA_REG0_NUM,
SAFETY_CHECKERS_RM_REG_HEX100, {0x40U, 0x44U, 0x48U,0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U}},
{
SAFETY_CHECKERS_RM_BA1_RA,
SAFETY_CHECKERS_RM_SUBMOD0_RA,
SAFETY_CHECKERS_RM_RA_REG1_NUM,
SAFETY_CHECKERS_RM_REG_HEX100, {0x40U, 0x44U, 0x48U,0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U}},
{
SAFETY_CHECKERS_RM_BA2_RA,
SAFETY_CHECKERS_RM_RA_SUBMOD1,
SAFETY_CHECKERS_RM_RA_REG2_NUM,
SAFETY_CHECKERS_RM_REG_HEX100, {0x40U, 0x44U, 0x48U, 0x4CU, 0x50U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U}},
{
SAFETY_CHECKERS_RM_BA3_RA,
SAFETY_CHECKERS_RM_SUBMOD0_RA,
SAFETY_CHECKERS_RM_RA_REG3_NUM,
SAFETY_CHECKERS_RM_REG_HEX100, {0x40U, 0x44U, 0x48U,0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U}},
{
SAFETY_CHECKERS_RM_BA0_UDMA_TX,
SAFETY_CHECKERS_RM_SUBMOD0_UDMA_TX,
SAFETY_CHECKERS_RM_REG0_UDMA_TX,
SAFETY_CHECKERS_RM_REG_HEX100, {0x0U, 0x64U, 0x68U, 0x70U, 0x80U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U}},
{
SAFETY_CHECKERS_RM_BA1_UDMA_TX,
SAFETY_CHECKERS_RM_SUBMOD0_UDMA_TX,
SAFETY_CHECKERS_RM_REG1_UDMA_TX,
SAFETY_CHECKERS_RM_REG_HEX100, {0x0U, 0x64U, 0x68U, 0x70U, 0x80U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U}},
{
SAFETY_CHECKERS_RM_BA0_UDMA_RX,
SAFETY_CHECKERS_RM_SUBMOD0_UDMA_RX,
SAFETY_CHECKERS_RM_REG0_UDMA_RX,
SAFETY_CHECKERS_RM_REG_HEX100, {0x0U, 0x64U, 0x68U, 0x80U, 0X0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U}},
{
SAFETY_CHECKERS_RM_BA1_UDMA_RX,
SAFETY_CHECKERS_RM_SUBMOD0_UDMA_RX,
SAFETY_CHECKERS_RM_REG1_UDMA_RX,
SAFETY_CHECKERS_RM_REG_HEX100, {0x0U, 0x64U, 0x68U, 0x80U, 0X0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U}},
{
SAFETY_CHECKERS_RM_BA2_UDMA_RX,
SAFETY_CHECKERS_RM_SUBMOD0_UDMA_RX,
SAFETY_CHECKERS_RM_REG2_UDMA_RX,
SAFETY_CHECKERS_RM_REG_HEX100, {0x0U, 0x64U, 0x68U, 0x80U, 0X0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U}},
{
SAFETY_CHECKERS_RM_BA0_UDMA_FLW,
SAFETY_CHECKERS_RM_SUBMOD0_UDMA_FLW,
SAFETY_CHECKERS_RM_REG0_UDMA_FLW,
SAFETY_CHECKERS_RM_REG_HEX40, {0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U}},
{
SAFETY_CHECKERS_RM_BA0_UDMA_GCFG,
SAFETY_CHECKERS_RM_SUBMOD0_UDMA_GCFG,
SAFETY_CHECKERS_RM_REG0_UDMA_GCFG,
SAFETY_CHECKERS_RM_REG_HEX0, {0x0U, 0x04U, 0X08U, 0x10U, 0x20U, 0x24U, 0x28U, 0x2CU, 0x30U, 0x60U, 0x64U, 0x78U, 0x7CU, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U}},
{
SAFETY_CHECKERS_RM_BA1_UDMA_GCFG,
SAFETY_CHECKERS_RM_SUBMOD1_UDMA_GCFG,
SAFETY_CHECKERS_RM_REG1_UDMA_GCFG,
SAFETY_CHECKERS_RM_REG_HEX0, {0x0U, 0x04U, 0X08U, 0x10U, 0x20U, 0x24U, 0x28U, 0x2CU, 0x30U, 0x60U, 0x64U, 0x78U, 0x7CU, 0x88U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U}},
{
SAFETY_CHECKERS_RM_BA2_UDMA_GCFG,
SAFETY_CHECKERS_RM_SUBMOD2_UDMA_GCFG,
SAFETY_CHECKERS_RM_REG2_UDMA_GCFG,
SAFETY_CHECKERS_RM_REG_HEX0, {0x0U, 0x04U, 0X08U, 0x10U, 0x20U, 0x24U, 0x28U, 0x2CU, 0x30U, 0x60U, 0x64U, 0x78U, 0x7CU, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U}},
}
Structure defines RM module register base address and the total length of registers.
#define SAFETY_CHECKERS_RM_BA0_UDMA_TX
RM UDMA TX module base addresses.
Definition: safety_checkers_soc.h:168
#define SAFETY_CHECKERS_RM_REG2_UDMA_GCFG
Definition: safety_checkers_soc.h:208
#define SAFETY_CHECKERS_PM_PLL6_LENGTH
Definition: safety_checkers_soc.h:87
#define SAFETY_CHECKERS_RM_IR_REG0_NUM
Formula input of IR module to read relevant registers from register group.
Definition: safety_checkers_soc.h:133
#define SAFETY_CHECKERS_RM_SUBMOD0_UDMA_GCFG
Number of registers in UDMA GCFG register group.
Definition: safety_checkers_soc.h:211
#define SAFETY_CHECKERS_PM_PD_STAT_NUM
Definition: safety_checkers_soc.h:79
#define SAFETY_CHECKERS_RM_BA1_UDMA_TX
Definition: safety_checkers_soc.h:169
static uint32_t gSafetyCheckers_PmPllRegOffset3[]
Definition: safety_checkers_pm_soc.h:119
#define SAFETY_CHECKERS_RM_REG2_UDMA_RX
Definition: safety_checkers_soc.h:186
#define SAFETY_CHECKERS_RM_SUBMOD0_UDMA_RX
Number of registers in UDMA RX register group.
Definition: safety_checkers_soc.h:189
#define SAFETY_CHECKERS_RM_SUBMOD0_IA_IMAP
Number of registers in IAIMAP register group.
Definition: safety_checkers_soc.h:149
#define SAFETY_CHECKERS_RM_REG0_UDMA_RX
Formula input of UDMA RX to read relevant registers from register group.
Definition: safety_checkers_soc.h:184
#define SAFETY_CHECKERS_PM_PLL_BASE_ADDRESS(i)
Each PLL base addresses.
Definition: safety_checkers_pm_soc.h:80
#define SAFETY_CHECKERS_RM_BA0_IA_IMAP
RM IAIMAP module base addresses.
Definition: safety_checkers_soc.h:141
#define SAFETY_CHECKERS_RM_REG0_UDMA_GCFG
Formula input of UDMA GCFG to read relevant registers from register group.
Definition: safety_checkers_soc.h:206
#define SAFETY_CHECKERS_PM_PLL2_LENGTH
Definition: safety_checkers_soc.h:85
#define SAFETY_CHECKERS_RM_REG1_UDMA_GCFG
Definition: safety_checkers_soc.h:207
#define SAFETY_CHECKERS_RM_SUBMOD1_UDMA_GCFG
Definition: safety_checkers_soc.h:212
#define SAFETY_CHECKERS_RM_SUBMOD0_RA
Number of registers in RA register group.
Definition: safety_checkers_soc.h:164
#define SAFETY_CHECKERS_RM_BA1_RA
Definition: safety_checkers_soc.h:153
#define SAFETY_CHECKERS_RM_BA2_UDMA_RX
Definition: safety_checkers_soc.h:181
#define SAFETY_CHECKERS_RM_REG1_IA_IMAP
Definition: safety_checkers_soc.h:146
#define SAFETY_CHECKERS_RM_IR_REG2_NUM
Definition: safety_checkers_soc.h:135
#define SAFETY_CHECKERS_PM_PLL1_LENGTH
Definition: safety_checkers_soc.h:84
#define SAFETY_CHECKERS_RM_RA_REG1_NUM
Definition: safety_checkers_soc.h:159
#define SAFETY_CHECKERS_RM_BA1_IR
Definition: safety_checkers_soc.h:129
#define SAFETY_CHECKERS_PM_PLL17_LENGTH
Definition: safety_checkers_soc.h:93
#define SAFETY_CHECKERS_RM_SUBMOD0_UDMA_TX
Number of registers in UDMA TX register group.
Definition: safety_checkers_soc.h:176
#define SAFETY_CHECKERS_RM_IR_SUBMOD0_NUM
Number of registers in IR register group.
Definition: safety_checkers_soc.h:138
#define SAFETY_CHECKERS_PM_WKUP_MD_STAT_NUM
Definition: safety_checkers_soc.h:78
#define SAFETY_CHECKERS_RM_SUBMOD2_UDMA_GCFG
Definition: safety_checkers_soc.h:213
#define SAFETY_CHECKERS_PM_PLL15_LENGTH
Definition: safety_checkers_soc.h:91
#define SAFETY_CHECKERS_PM_PLL12_LENGTH
Definition: safety_checkers_soc.h:90
#define SAFETY_CHECKERS_RM_BA3_RA
Definition: safety_checkers_soc.h:155
#define SAFETY_CHECKERS_RM_BA2_RA
Definition: safety_checkers_soc.h:154
#define SAFETY_CHECKERS_PM_PLL7_LENGTH
Definition: safety_checkers_soc.h:88
#define SAFETY_CHECKERS_PM_WKUP_PSC_BASE_ADDRESS
WKUP PSC base address.
Definition: safety_checkers_pm_soc.h:72
#define SAFETY_CHECKERS_RM_REG0_UDMA_TX
Formula input of UDMA TX to read relevant registers from register group.
Definition: safety_checkers_soc.h:172
#define SAFETY_CHECKERS_RM_REG1_UDMA_TX
Definition: safety_checkers_soc.h:173
#define SAFETY_CHECKERS_RM_BA1_UDMA_GCFG
Definition: safety_checkers_soc.h:202
#define SAFETY_CHECKERS_RM_RA_REG2_NUM
Definition: safety_checkers_soc.h:160
#define SAFETY_CHECKERS_PM_WKUP_PD_STAT_NUM
PD STAT and MD STAT registers details for PSC.
Definition: safety_checkers_soc.h:77
#define SAFETY_CHECKERS_PM_PSC_BASE_ADDRESS
PLL and PSC base addresses.
Definition: safety_checkers_soc.h:72
#define SAFETY_CHECKERS_PM_MD_STAT_NUM
Definition: safety_checkers_soc.h:80
#define SAFETY_CHECKERS_RM_BA0_UDMA_RX
RM UDMA RX module base addresses.
Definition: safety_checkers_soc.h:179
#define SAFETY_CHECKERS_RM_BA2_UDMA_GCFG
Definition: safety_checkers_soc.h:203
#define SAFETY_CHECKERS_RM_BA1_UDMA_RX
Definition: safety_checkers_soc.h:180
#define SAFETY_CHECKERS_RM_BA2_IR
Definition: safety_checkers_soc.h:130
#define SAFETY_CHECKERS_PM_MCU_PLL_BASE_ADDRESS(i)
Definition: safety_checkers_pm_soc.h:81
#define SAFETY_CHECKERS_RM_REG0_UDMA_FLW
Formula input of UDMA FLOW to read relevant registers from register group.
Definition: safety_checkers_soc.h:195
#define SAFETY_CHECKERS_PM_PLL0_LENGTH
PLL register details.
Definition: safety_checkers_soc.h:83
#define SAFETY_CHECKERS_RM_BA0_RA
RM RA module base addresses.
Definition: safety_checkers_soc.h:152
#define SAFETY_CHECKERS_RM_REG_HEX8
Definition: safety_checkers_rm_soc.h:72
#define SAFETY_CHECKERS_PM_MCU_PLL0_LENGTH
Definition: safety_checkers_soc.h:95
#define SAFETY_CHECKERS_RM_BA1_IA_IMAP
Definition: safety_checkers_soc.h:142
#define SAFETY_CHECKERS_RM_REG_HEX100
Definition: safety_checkers_rm_soc.h:74
#define SAFETY_CHECKERS_RM_REG0_IA_IMAP
Formula input of IAIMAP module to read relevant registers from register group.
Definition: safety_checkers_soc.h:145
#define SAFETY_CHECKERS_PM_PLL8_LENGTH
Definition: safety_checkers_soc.h:89
#define SAFETY_CHECKERS_RM_REG_HEX40
Definition: safety_checkers_rm_soc.h:73
#define SAFETY_CHECKERS_RM_RA_SUBMOD1
Definition: safety_checkers_soc.h:165
#define SAFETY_CHECKERS_RM_RA_REG3_NUM
Definition: safety_checkers_soc.h:161
#define SAFETY_CHECKERS_RM_SUBMOD0_UDMA_FLW
Number of registers in UDMA FLOW register group.
Definition: safety_checkers_soc.h:198
#define SAFETY_CHECKERS_RM_RA_REG0_NUM
Formula input of RA module to read relevant registers from register group.
Definition: safety_checkers_soc.h:158
#define SAFETY_CHECKERS_RM_REG_HEX4
Definition: safety_checkers_rm_soc.h:71
#define SAFETY_CHECKERS_RM_REG1_UDMA_RX
Definition: safety_checkers_soc.h:185
#define SAFETY_CHECKERS_RM_BA0_UDMA_GCFG
RM UDMA GCFG module base addresses.
Definition: safety_checkers_soc.h:201
#define SAFETY_CHECKERS_RM_REG_HEX0
Offsets for RM register blobs.
Definition: safety_checkers_rm_soc.h:70
#define SAFETY_CHECKERS_RM_BA0_UDMA_FLW
RM UDMA FLOW module base addresses.
Definition: safety_checkers_soc.h:192
#define SAFETY_CHECKERS_PM_PLL5_LENGTH
Definition: safety_checkers_soc.h:86
#define SAFETY_CHECKERS_RM_BA0_IR
RM IR module base addresses.
Definition: safety_checkers_soc.h:128
#define SAFETY_CHECKERS_RM_IR_REG1_NUM
Definition: safety_checkers_soc.h:134