- Attention
- See also FreeRTOS, NO RTOS for list of CPU specific supported and unsupported features.
Features Supported
- Register a interrupt callback to a specific CPU number
- Ability to pass user specific argument to the interrupt callback
- Enable, disable, restore and clear specific CPU interrupts
- Enable, disable, restore global CPU interrupt
- For ARM R5,
- Ability to specify interrupt as FIQ or IRQ, level or pulse
- Ability to specify interrupt priority
- For ARM M4,
- Ability to specify interrupt priority
- Ability to specify systick ISR and NVIC external interrupt ISR
Features NOT Supported
See also FreeRTOS, NO RTOS for list of unsupported features.
Important Usage Guidelines
- For ARM R5,
- TI VIM is the interrupt controller that is supported.
- HwiP_disable, HwiP_restore, HwiP_enable only affect state of IRQ. FIQ state is not changed
- Refer ARMv7-R Architecture reference manual and SOC TRM for more details.
- For ARM M4,
- ARM NVIC is the interrupt controller that is supported.
- Interrupt numbers 0 to 15 are for internal interrupts, like reset (1), NMI (2), fault handlers (3-6), SVC (11), PendSV (14), SysTick (15)
- Interrupt numbers 16 to 80 are used as external NVIC interrupts. The TRM will document M4F interrupt numbers as xxx_M4FSSx_COREx_NVIC_IN_n. This corresponds to interrupt number (16 + n) at NVIC and (16 + n) is used as input to the HwiP APIs
- Refer ARMv7-M Architecture reference manual and SOC TRM for more details.
Example Usage
Include the below file to access the APIs,
Example ISR,
void myISR(void *args)
{
}
Example to register a ISR for CPU interrupt 10,
Example to disable and restore interrupts across a crtical section
API
APIs for HW Interrupts