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AM62Px MCU+ SDK
10.01.00
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42 #if (!defined(SOC_AM62AX)) && (!defined(SOC_AM62DX))
43 #if defined(_TMS320C6X)
44 #include <kernel/dpl/CacheP_c6x.h>
62 #define CacheP_CACHELINE_ALIGNMENT (128U)
72 #define CacheP_TYPE_L1P (0x0001u)
73 #define CacheP_TYPE_L1D (0x0002u)
74 #define CacheP_TYPE_L2P (0x0004u)
75 #define CacheP_TYPE_L2D (0x0008u)
76 #define CacheP_TYPE_L1 ((CacheP_TYPE_L1P)|(CacheP_TYPE_L1D))
77 #define CacheP_TYPE_L2 ((CacheP_TYPE_L2P)|(CacheP_TYPE_L2D))
78 #define CacheP_TYPE_ALLP ((CacheP_TYPE_L1P)|(CacheP_TYPE_L2P))
79 #define CacheP_TYPE_ALLD ((CacheP_TYPE_L1D)|(CacheP_TYPE_L2D))
80 #define CacheP_TYPE_ALL (((CacheP_TYPE_L1P)|(CacheP_TYPE_L1D))|((CacheP_TYPE_L2P)|(CacheP_TYPE_L2D)))
87 typedef struct CacheP_Config_ {
void CacheP_enable(uint32_t type)
Cache enable.
void CacheP_disable(uint32_t type)
Cache disable.
uint16_t size
Definition: tisci_boardcfg.h:1
uint32_t enableForceWrThru
Definition: CacheP.h:90
Cache config structure, this used by SysConfig and not to be used by end-users directly.
Definition: CacheP.h:87
void CacheP_wbAll(uint32_t type)
Cache writeback for full cache.
void CacheP_wbInvAll(uint32_t type)
Cache writeback and invalidate for full cache.
void CacheP_init(void)
Initialize Cache sub-system, called by SysConfig, not to be called by end users.
uint16_t type
Definition: tisci_rm_core.h:1
uint64_t addr
Definition: csl_udmap_tr.h:3
void CacheP_wbInv(void *addr, uint32_t size, uint32_t type)
Cache writeback and invalidate for a specified region.
void CacheP_inv(void *addr, uint32_t size, uint32_t type)
Cache invalidate for a specified region.
uint32_t enable
Definition: CacheP.h:89
uint32_t CacheP_getEnabled(void)
Get cache enabled bits.
CacheP_Config gCacheConfig
Externally defined Cache configuration.
void CacheP_wb(void *addr, uint32_t size, uint32_t type)
Cache writeback for a specified region.