|
AM62Px MCU+ SDK
09.02.01
|
|
Go to the documentation of this file.
46 #ifndef SAFETY_CHECKERS_SOC_H_
47 #define SAFETY_CHECKERS_SOC_H_
72 #define SAFETY_CHECKERS_PM_PSC_BASE_ADDRESS (0x400000UL)
73 #define SAFETY_CHECKERS_PM_PLL_CFG_BASE_ADDRESS (0x680000UL)
74 #define SAFETY_CHECKERS_PM_MCU_PLL_CFG_BASE_ADDRESS (0x4040000UL)
77 #define SAFETY_CHECKERS_PM_WKUP_PD_STAT_NUM (0x02U)
78 #define SAFETY_CHECKERS_PM_WKUP_MD_STAT_NUM (0x0BU)
79 #define SAFETY_CHECKERS_PM_PD_STAT_NUM (0x16U)
80 #define SAFETY_CHECKERS_PM_MD_STAT_NUM (0x60U)
83 #define SAFETY_CHECKERS_PM_PLL0_LENGTH (0xA8U)
84 #define SAFETY_CHECKERS_PM_PLL1_LENGTH (0x9CU)
85 #define SAFETY_CHECKERS_PM_PLL2_LENGTH (0xA8U)
86 #define SAFETY_CHECKERS_PM_PLL5_LENGTH (0x8CU)
87 #define SAFETY_CHECKERS_PM_PLL6_LENGTH (0x84U)
88 #define SAFETY_CHECKERS_PM_PLL7_LENGTH (0x88U)
89 #define SAFETY_CHECKERS_PM_PLL8_LENGTH (0x84U)
90 #define SAFETY_CHECKERS_PM_PLL12_LENGTH (0x84U)
91 #define SAFETY_CHECKERS_PM_PLL15_LENGTH (0x90U)
92 #define SAFETY_CHECKERS_PM_PLL16_LENGTH (0x84U)
93 #define SAFETY_CHECKERS_PM_PLL17_LENGTH (0x84U)
94 #define SAFETY_CHECKERS_PM_PLL18_LENGTH (0x84U)
95 #define SAFETY_CHECKERS_PM_MCU_PLL0_LENGTH (0x9CU)
98 #define TIFS_CHECKER_FWL_MAX_NUM (0x16U)
104 #define SAFETY_CHECKERS_PM_PSC_REGDUMP_SIZE (SAFETY_CHECKERS_PM_WKUP_PD_STAT_NUM + \
105 SAFETY_CHECKERS_PM_WKUP_MD_STAT_NUM + \
106 SAFETY_CHECKERS_PM_PD_STAT_NUM + \
107 SAFETY_CHECKERS_PM_MD_STAT_NUM)
117 #define SAFETY_CHECKERS_PM_PLL_REGDUMP_SIZE (192U)
125 #define SAFETY_CHECKERS_RM_REGDUMP_SIZE (3215U)
128 #define SAFETY_CHECKERS_RM_BA0_IR (CSL_TIMESYNC_EVENT_INTROUTER0_INTR_ROUTER_CFG_BASE)
129 #define SAFETY_CHECKERS_RM_BA1_IR (CSL_WKUP_MCU_GPIOMUX_INTROUTER0_INTR_ROUTER_CFG_BASE)
130 #define SAFETY_CHECKERS_RM_BA2_IR (CSL_MAIN_GPIOMUX_INTROUTER0_INTR_ROUTER_CFG_BASE)
133 #define SAFETY_CHECKERS_RM_IR_REG0_NUM (26U)
134 #define SAFETY_CHECKERS_RM_IR_REG1_NUM (16U)
135 #define SAFETY_CHECKERS_RM_IR_REG2_NUM (36U)
138 #define SAFETY_CHECKERS_RM_IR_SUBMOD0_NUM (2U)
141 #define SAFETY_CHECKERS_RM_BA0_IA_IMAP (CSL_DMASS0_INTAGGR_IMAP_BASE)
142 #define SAFETY_CHECKERS_RM_BA1_IA_IMAP (CSL_DMASS1_INTAGGR_IMAP_BASE)
145 #define SAFETY_CHECKERS_RM_REG0_IA_IMAP (1536U)
146 #define SAFETY_CHECKERS_RM_REG1_IA_IMAP (128U)
149 #define SAFETY_CHECKERS_RM_SUBMOD0_IA_IMAP (1U)
152 #define SAFETY_CHECKERS_RM_BA0_RA (CSL_DMASS0_BCDMA_RING_BASE)
153 #define SAFETY_CHECKERS_RM_BA1_RA (CSL_DMASS0_PKTDMA_RING_BASE)
154 #define SAFETY_CHECKERS_RM_BA2_RA (CSL_DMASS0_RINGACC_CFG_BASE)
155 #define SAFETY_CHECKERS_RM_BA3_RA (CSL_DMASS1_BCDMA_RING_BASE)
158 #define SAFETY_CHECKERS_RM_RA_REG0_NUM (82U)
159 #define SAFETY_CHECKERS_RM_RA_REG1_NUM (150U)
160 #define SAFETY_CHECKERS_RM_RA_REG2_NUM (20U)
161 #define SAFETY_CHECKERS_RM_RA_REG3_NUM (6U)
164 #define SAFETY_CHECKERS_RM_SUBMOD0_RA (3U)
165 #define SAFETY_CHECKERS_RM_RA_SUBMOD1 (5U)
168 #define SAFETY_CHECKERS_RM_BA0_UDMA_TX (CSL_DMASS0_BCDMA_TCHAN_BASE)
169 #define SAFETY_CHECKERS_RM_BA1_UDMA_TX (CSL_DMASS0_PKTDMA_TCHAN_BASE)
172 #define SAFETY_CHECKERS_RM_REG0_UDMA_TX (25U)
173 #define SAFETY_CHECKERS_RM_REG1_UDMA_TX (29U)
176 #define SAFETY_CHECKERS_RM_SUBMOD0_UDMA_TX (5U)
179 #define SAFETY_CHECKERS_RM_BA0_UDMA_RX (CSL_DMASS0_BCDMA_RCHAN_BASE)
180 #define SAFETY_CHECKERS_RM_BA1_UDMA_RX (CSL_DMASS0_PKTDMA_RCHAN_BASE)
181 #define SAFETY_CHECKERS_RM_BA2_UDMA_RX (CSL_DMASS1_BCDMA_RCHAN_BASE)
184 #define SAFETY_CHECKERS_RM_REG0_UDMA_RX (25U)
185 #define SAFETY_CHECKERS_RM_REG1_UDMA_RX (24U)
186 #define SAFETY_CHECKERS_RM_REG2_UDMA_RX (6U)
189 #define SAFETY_CHECKERS_RM_SUBMOD0_UDMA_RX (4U)
192 #define SAFETY_CHECKERS_RM_BA0_UDMA_FLW (CSL_DMASS0_PKTDMA_RFLOW_BASE)
195 #define SAFETY_CHECKERS_RM_REG0_UDMA_FLW (51U)
198 #define SAFETY_CHECKERS_RM_SUBMOD0_UDMA_FLW (1U)
201 #define SAFETY_CHECKERS_RM_BA0_UDMA_GCFG (CSL_DMASS0_BCDMA_GCFG_BASE)
202 #define SAFETY_CHECKERS_RM_BA1_UDMA_GCFG (CSL_DMASS0_PKTDMA_GCFG_BASE)
203 #define SAFETY_CHECKERS_RM_BA2_UDMA_GCFG (CSL_DMASS1_BCDMA_GCFG_BASE)
206 #define SAFETY_CHECKERS_RM_REG0_UDMA_GCFG (1U)
207 #define SAFETY_CHECKERS_RM_REG1_UDMA_GCFG (1U)
208 #define SAFETY_CHECKERS_RM_REG2_UDMA_GCFG (1U)
211 #define SAFETY_CHECKERS_RM_SUBMOD0_UDMA_GCFG (13U)
212 #define SAFETY_CHECKERS_RM_SUBMOD1_UDMA_GCFG (14U)
213 #define SAFETY_CHECKERS_RM_SUBMOD2_UDMA_GCFG (13U)
275 {
SAFETY_CHECKERS_RM_BA0_IR,
SAFETY_CHECKERS_RM_IR_SUBMOD0_NUM,
SAFETY_CHECKERS_RM_IR_REG0_NUM,
SAFETY_CHECKERS_RM_REG_HEX4, {0X0U, 0x4U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U}},
276 {
SAFETY_CHECKERS_RM_BA1_IR,
SAFETY_CHECKERS_RM_IR_SUBMOD0_NUM,
SAFETY_CHECKERS_RM_IR_REG1_NUM,
SAFETY_CHECKERS_RM_REG_HEX4, {0X0U, 0x4U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U}},
277 {
SAFETY_CHECKERS_RM_BA2_IR,
SAFETY_CHECKERS_RM_IR_SUBMOD0_NUM,
SAFETY_CHECKERS_RM_IR_REG2_NUM,
SAFETY_CHECKERS_RM_REG_HEX4, {0X0U, 0x4U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U}},
279 {
SAFETY_CHECKERS_RM_BA0_IA_IMAP,
SAFETY_CHECKERS_RM_SUBMOD0_IA_IMAP,
SAFETY_CHECKERS_RM_REG0_IA_IMAP,
SAFETY_CHECKERS_RM_REG_HEX8, {0X0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U}},
280 {
SAFETY_CHECKERS_RM_BA1_IA_IMAP,
SAFETY_CHECKERS_RM_SUBMOD0_IA_IMAP,
SAFETY_CHECKERS_RM_REG1_IA_IMAP,
SAFETY_CHECKERS_RM_REG_HEX8, {0X0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U}},
282 {
SAFETY_CHECKERS_RM_BA0_RA,
SAFETY_CHECKERS_RM_SUBMOD0_RA,
SAFETY_CHECKERS_RM_RA_REG0_NUM,
SAFETY_CHECKERS_RM_REG_HEX100, {0x40U, 0x44U, 0x48U,0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U}},
283 {
SAFETY_CHECKERS_RM_BA1_RA,
SAFETY_CHECKERS_RM_SUBMOD0_RA,
SAFETY_CHECKERS_RM_RA_REG1_NUM,
SAFETY_CHECKERS_RM_REG_HEX100, {0x40U, 0x44U, 0x48U,0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U}},
284 {
SAFETY_CHECKERS_RM_BA2_RA,
SAFETY_CHECKERS_RM_RA_SUBMOD1,
SAFETY_CHECKERS_RM_RA_REG2_NUM,
SAFETY_CHECKERS_RM_REG_HEX100, {0x40U, 0x44U, 0x48U, 0x4CU, 0x50U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U}},
285 {
SAFETY_CHECKERS_RM_BA3_RA,
SAFETY_CHECKERS_RM_SUBMOD0_RA,
SAFETY_CHECKERS_RM_RA_REG3_NUM,
SAFETY_CHECKERS_RM_REG_HEX100, {0x40U, 0x44U, 0x48U,0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U}},
287 {
SAFETY_CHECKERS_RM_BA0_UDMA_TX,
SAFETY_CHECKERS_RM_SUBMOD0_UDMA_TX,
SAFETY_CHECKERS_RM_REG0_UDMA_TX,
SAFETY_CHECKERS_RM_REG_HEX100, {0x0U, 0x64U, 0x68U, 0x70U, 0x80U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U}},
288 {
SAFETY_CHECKERS_RM_BA1_UDMA_TX,
SAFETY_CHECKERS_RM_SUBMOD0_UDMA_TX,
SAFETY_CHECKERS_RM_REG1_UDMA_TX,
SAFETY_CHECKERS_RM_REG_HEX100, {0x0U, 0x64U, 0x68U, 0x70U, 0x80U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U}},
290 {
SAFETY_CHECKERS_RM_BA0_UDMA_RX,
SAFETY_CHECKERS_RM_SUBMOD0_UDMA_RX,
SAFETY_CHECKERS_RM_REG0_UDMA_RX,
SAFETY_CHECKERS_RM_REG_HEX100, {0x0U, 0x64U, 0x68U, 0x80U, 0X0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U}},
291 {
SAFETY_CHECKERS_RM_BA1_UDMA_RX,
SAFETY_CHECKERS_RM_SUBMOD0_UDMA_RX,
SAFETY_CHECKERS_RM_REG1_UDMA_RX,
SAFETY_CHECKERS_RM_REG_HEX100, {0x0U, 0x64U, 0x68U, 0x80U, 0X0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U}},
292 {
SAFETY_CHECKERS_RM_BA2_UDMA_RX,
SAFETY_CHECKERS_RM_SUBMOD0_UDMA_RX,
SAFETY_CHECKERS_RM_REG2_UDMA_RX,
SAFETY_CHECKERS_RM_REG_HEX100, {0x0U, 0x64U, 0x68U, 0x80U, 0X0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U}},
294 {
SAFETY_CHECKERS_RM_BA0_UDMA_FLW,
SAFETY_CHECKERS_RM_SUBMOD0_UDMA_FLW,
SAFETY_CHECKERS_RM_REG0_UDMA_FLW,
SAFETY_CHECKERS_RM_REG_HEX40, {0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U}},
296 {
SAFETY_CHECKERS_RM_BA0_UDMA_GCFG,
SAFETY_CHECKERS_RM_SUBMOD0_UDMA_GCFG,
SAFETY_CHECKERS_RM_REG0_UDMA_GCFG,
SAFETY_CHECKERS_RM_REG_HEX0, {0x0U, 0x04U, 0X08U, 0x10U, 0x20U, 0x24U, 0x28U, 0x2CU, 0x30U, 0x60U, 0x64U, 0x78U, 0x7CU, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U}},
297 {
SAFETY_CHECKERS_RM_BA1_UDMA_GCFG,
SAFETY_CHECKERS_RM_SUBMOD1_UDMA_GCFG,
SAFETY_CHECKERS_RM_REG1_UDMA_GCFG,
SAFETY_CHECKERS_RM_REG_HEX0, {0x0U, 0x04U, 0X08U, 0x10U, 0x20U, 0x24U, 0x28U, 0x2CU, 0x30U, 0x60U, 0x64U, 0x78U, 0x7CU, 0x88U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U}},
298 {
SAFETY_CHECKERS_RM_BA2_UDMA_GCFG,
SAFETY_CHECKERS_RM_SUBMOD2_UDMA_GCFG,
SAFETY_CHECKERS_RM_REG2_UDMA_GCFG,
SAFETY_CHECKERS_RM_REG_HEX0, {0x0U, 0x04U, 0X08U, 0x10U, 0x20U, 0x24U, 0x28U, 0x2CU, 0x30U, 0x60U, 0x64U, 0x78U, 0x7CU, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U}},
#define SAFETY_CHECKERS_RM_BA0_UDMA_TX
RM UDMA TX module base addresses.
Definition: safety_checkers_soc.h:168
static SafetyCheckers_PmPllData gSafetyCheckers_PmPllData[]
Structure defines PLL register base address and the total length of registers.
Definition: safety_checkers_soc.h:239
#define SAFETY_CHECKERS_RM_REG2_UDMA_GCFG
Definition: safety_checkers_soc.h:208
#define SAFETY_CHECKERS_PM_PLL6_LENGTH
Definition: safety_checkers_soc.h:87
#define SAFETY_CHECKERS_RM_IR_REG0_NUM
Formula input of IR module to read relevant registers from register group.
Definition: safety_checkers_soc.h:133
#define SAFETY_CHECKERS_RM_SUBMOD0_UDMA_GCFG
Number of registers in UDMA GCFG register group.
Definition: safety_checkers_soc.h:211
#define SAFETY_CHECKERS_PM_PD_STAT_NUM
Definition: safety_checkers_soc.h:79
#define SAFETY_CHECKERS_RM_BA1_UDMA_TX
Definition: safety_checkers_soc.h:169
static uint32_t gSafetyCheckers_PmPllRegOffset3[]
Definition: safety_checkers_pm_soc.h:119
#define SAFETY_CHECKERS_RM_REG2_UDMA_RX
Definition: safety_checkers_soc.h:186
Structure to hold the base address and the number of Module Domain(MD) stat and Power Domain(PD) stat...
Definition: safety_checkers_pm.h:98
static SafetyCheckers_RmRegData gSafetyCheckers_RmRegData[]
Structure defines RM module register base address and the total length of registers.
Definition: safety_checkers_soc.h:273
#define SAFETY_CHECKERS_RM_SUBMOD0_UDMA_RX
Number of registers in UDMA RX register group.
Definition: safety_checkers_soc.h:189
#define SAFETY_CHECKERS_RM_SUBMOD0_IA_IMAP
Number of registers in IAIMAP register group.
Definition: safety_checkers_soc.h:149
#define SAFETY_CHECKERS_RM_REG0_UDMA_RX
Formula input of UDMA RX to read relevant registers from register group.
Definition: safety_checkers_soc.h:184
#define SAFETY_CHECKERS_PM_PLL_BASE_ADDRESS(i)
Each PLL base addresses.
Definition: safety_checkers_pm_soc.h:80
#define SAFETY_CHECKERS_RM_BA0_IA_IMAP
RM IAIMAP module base addresses.
Definition: safety_checkers_soc.h:141
#define SAFETY_CHECKERS_RM_REG0_UDMA_GCFG
Formula input of UDMA GCFG to read relevant registers from register group.
Definition: safety_checkers_soc.h:206
#define SAFETY_CHECKERS_PM_PLL2_LENGTH
Definition: safety_checkers_soc.h:85
#define SAFETY_CHECKERS_RM_REG1_UDMA_GCFG
Definition: safety_checkers_soc.h:207
#define SAFETY_CHECKERS_RM_SUBMOD1_UDMA_GCFG
Definition: safety_checkers_soc.h:212
#define SAFETY_CHECKERS_RM_SUBMOD0_RA
Number of registers in RA register group.
Definition: safety_checkers_soc.h:164
#define SAFETY_CHECKERS_RM_BA1_RA
Definition: safety_checkers_soc.h:153
#define SAFETY_CHECKERS_RM_BA2_UDMA_RX
Definition: safety_checkers_soc.h:181
#define SAFETY_CHECKERS_RM_REG1_IA_IMAP
Definition: safety_checkers_soc.h:146
#define SAFETY_CHECKERS_RM_IR_REG2_NUM
Definition: safety_checkers_soc.h:135
#define SAFETY_CHECKERS_PM_PLL1_LENGTH
Definition: safety_checkers_soc.h:84
#define SAFETY_CHECKERS_RM_RA_REG1_NUM
Definition: safety_checkers_soc.h:159
#define SAFETY_CHECKERS_RM_BA1_IR
Definition: safety_checkers_soc.h:129
Structure to hold the base address and the length of PLLs.
Definition: safety_checkers_pm.h:82
#define SAFETY_CHECKERS_PM_PLL17_LENGTH
Definition: safety_checkers_soc.h:93
#define SAFETY_CHECKERS_RM_SUBMOD0_UDMA_TX
Number of registers in UDMA TX register group.
Definition: safety_checkers_soc.h:176
#define SAFETY_CHECKERS_RM_IR_SUBMOD0_NUM
Number of registers in IR register group.
Definition: safety_checkers_soc.h:138
#define SAFETY_CHECKERS_PM_WKUP_MD_STAT_NUM
Definition: safety_checkers_soc.h:78
#define SAFETY_CHECKERS_RM_SUBMOD2_UDMA_GCFG
Definition: safety_checkers_soc.h:213
#define SAFETY_CHECKERS_PM_PLL15_LENGTH
Definition: safety_checkers_soc.h:91
#define SAFETY_CHECKERS_PM_PLL12_LENGTH
Definition: safety_checkers_soc.h:90
#define SAFETY_CHECKERS_RM_BA3_RA
Definition: safety_checkers_soc.h:155
#define SAFETY_CHECKERS_RM_BA2_RA
Definition: safety_checkers_soc.h:154
#define SAFETY_CHECKERS_PM_PLL7_LENGTH
Definition: safety_checkers_soc.h:88
#define SAFETY_CHECKERS_PM_WKUP_PSC_BASE_ADDRESS
WKUP PSC base address.
Definition: safety_checkers_pm_soc.h:72
#define SAFETY_CHECKERS_RM_REG0_UDMA_TX
Formula input of UDMA TX to read relevant registers from register group.
Definition: safety_checkers_soc.h:172
#define SAFETY_CHECKERS_RM_REG1_UDMA_TX
Definition: safety_checkers_soc.h:173
#define SAFETY_CHECKERS_RM_BA1_UDMA_GCFG
Definition: safety_checkers_soc.h:202
#define SAFETY_CHECKERS_RM_RA_REG2_NUM
Definition: safety_checkers_soc.h:160
#define SAFETY_CHECKERS_PM_WKUP_PD_STAT_NUM
PD STAT and MD STAT registers details for PSC.
Definition: safety_checkers_soc.h:77
#define SAFETY_CHECKERS_PM_PSC_BASE_ADDRESS
PLL and PSC base addresses.
Definition: safety_checkers_soc.h:72
#define SAFETY_CHECKERS_PM_MD_STAT_NUM
Definition: safety_checkers_soc.h:80
#define SAFETY_CHECKERS_RM_BA0_UDMA_RX
RM UDMA RX module base addresses.
Definition: safety_checkers_soc.h:179
#define SAFETY_CHECKERS_RM_BA2_UDMA_GCFG
Definition: safety_checkers_soc.h:203
#define SAFETY_CHECKERS_RM_BA1_UDMA_RX
Definition: safety_checkers_soc.h:180
Structure to hold the base address and the register details of RM control module registers.
Definition: safety_checkers_rm.h:99
#define SAFETY_CHECKERS_RM_BA2_IR
Definition: safety_checkers_soc.h:130
#define SAFETY_CHECKERS_PM_MCU_PLL_BASE_ADDRESS(i)
Definition: safety_checkers_pm_soc.h:81
#define SAFETY_CHECKERS_RM_REG0_UDMA_FLW
Formula input of UDMA FLOW to read relevant registers from register group.
Definition: safety_checkers_soc.h:195
#define SAFETY_CHECKERS_PM_PLL0_LENGTH
PLL register details.
Definition: safety_checkers_soc.h:83
#define SAFETY_CHECKERS_RM_BA0_RA
RM RA module base addresses.
Definition: safety_checkers_soc.h:152
#define SAFETY_CHECKERS_RM_REG_HEX8
Definition: safety_checkers_rm_soc.h:72
#define SAFETY_CHECKERS_PM_MCU_PLL0_LENGTH
Definition: safety_checkers_soc.h:95
#define SAFETY_CHECKERS_RM_BA1_IA_IMAP
Definition: safety_checkers_soc.h:142
#define SAFETY_CHECKERS_RM_REG_HEX100
Definition: safety_checkers_rm_soc.h:74
#define SAFETY_CHECKERS_RM_REG0_IA_IMAP
Formula input of IAIMAP module to read relevant registers from register group.
Definition: safety_checkers_soc.h:145
#define SAFETY_CHECKERS_PM_PLL8_LENGTH
Definition: safety_checkers_soc.h:89
static SafetyCheckers_PmPscData gSafetyCheckers_PmPscData[]
Structure defines PSC register base address and the total length of registers.
Definition: safety_checkers_soc.h:262
#define SAFETY_CHECKERS_RM_REG_HEX40
Definition: safety_checkers_rm_soc.h:73
#define SAFETY_CHECKERS_RM_RA_SUBMOD1
Definition: safety_checkers_soc.h:165
#define SAFETY_CHECKERS_RM_RA_REG3_NUM
Definition: safety_checkers_soc.h:161
#define SAFETY_CHECKERS_RM_SUBMOD0_UDMA_FLW
Number of registers in UDMA FLOW register group.
Definition: safety_checkers_soc.h:198
This file contains data structures for PM safety checker module.
#define SAFETY_CHECKERS_RM_RA_REG0_NUM
Formula input of RA module to read relevant registers from register group.
Definition: safety_checkers_soc.h:158
#define SAFETY_CHECKERS_RM_REG_HEX4
Definition: safety_checkers_rm_soc.h:71
#define SAFETY_CHECKERS_RM_REG1_UDMA_RX
Definition: safety_checkers_soc.h:185
This file contains data structures for RM safety checker module.
#define SAFETY_CHECKERS_RM_BA0_UDMA_GCFG
RM UDMA GCFG module base addresses.
Definition: safety_checkers_soc.h:201
#define SAFETY_CHECKERS_RM_REG_HEX0
Offsets for RM register blobs.
Definition: safety_checkers_rm_soc.h:70
#define SAFETY_CHECKERS_RM_BA0_UDMA_FLW
RM UDMA FLOW module base addresses.
Definition: safety_checkers_soc.h:192
#define SAFETY_CHECKERS_PM_PLL5_LENGTH
Definition: safety_checkers_soc.h:86
#define SAFETY_CHECKERS_RM_BA0_IR
RM IR module base addresses.
Definition: safety_checkers_soc.h:128
#define SAFETY_CHECKERS_RM_IR_REG1_NUM
Definition: safety_checkers_soc.h:134