AM62Px MCU+ SDK  09.02.00
sdl_ecc_soc.h
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1 /*
2  * Copyright (C) 2023-2024 Texas Instruments Incorporated
3  *
4  * Redistribution and use in source and binary forms, with or without
5  * modification, are permitted provided that the following conditions
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12  * notice, this list of conditions and the following disclaimer in the
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31  */
41 #ifndef INCLUDE_SDL_ECC_SOC_H_
42 #define INCLUDE_SDL_ECC_SOC_H_
43 
44 
45 #include <stdint.h>
46 #include <sdl/sdl_ecc.h>
47 #include <sdl/ecc/sdl_ip_ecc.h>
48 #include <sdl/include/sdl_types.h>
49 #include <sdl/esm/soc/am62px/sdl_esm_core.h>
50 #include <sdl/esm/soc/am62px/sdl_esm_soc.h>
51 #include <sdl/ecc/sdl_ecc_priv.h>
52 #include <sdl/include/am62px/sdlr_soc_ecc_aggr.h>
53 #include <sdl/include/am62px/sdlr_intr_esm0.h>
54 #include <sdl/include/am62px/sdlr_intr_wkup_esm0.h>
55 #include <sdl/include/am62px/sdlr_soc_baseaddress.h>
56 
57 /* define Max memEntries for each aggregator (i.e. the number of RAM ID's with * Wrapper type) */
58 #define SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (29U)
59 #define SDL_DSS_DSI0_K3_DSS_DSI_DSI_TOP_ECC_AGGR_SYS_RAM_IDS_TOTAL_ENTRIES (0U)
60 #define SDL_PSRAMECC0_PSRAM256X32E_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (1U)
61 #define SDL_PSRAMECC1_PSRAM256X32E_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (1U)
62 #define SDL_MSRAM_64K0_MSRAM2KX256E_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (1U)
63 #define SDL_WKUP_ECC_AGGR2_RAM_IDS_TOTAL_ENTRIES (0U)
64 #define SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (1U)
65 #define SDL_DMASS1_DMSS_CSI_AM62A_ECCAGGR_RAM_IDS_TOTAL_ENTRIES (9U)
66 #define SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (1U)
67 #define SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_RAM_IDS_TOTAL_ENTRIES (0U)
68 #define SDL_WKUP_ECC_AGGR1_RAM_IDS_TOTAL_ENTRIES (0U)
69 #define SDL_FSS0_FSS_UL_OSPI0_OSPI_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (1U)
70 #define SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (29U)
71 #define SDL_GICSS0_GIC500SS_1_4_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (3U)
72 #define SDL_CPSW0_CPSW_3GUSS_AM67_CORE_ECC_CPSW_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (8U)
73 #define SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (7U)
74 #define SDL_PSCSS0_SAM67_MAIN_PSC_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (1U)
75 #define SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_RXMEM_RAM_IDS_TOTAL_ENTRIES (1U)
76 #define SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_TXMEM_RAM_IDS_TOTAL_ENTRIES (1U)
77 #define SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_RAM_IDS_TOTAL_ENTRIES (16U)
78 #define SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (12U)
79 #define SDL_MCU_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (1U)
80 #define SDL_WKUP_ECC_AGGR0_RAM_IDS_TOTAL_ENTRIES (0U)
81 #define SDL_DMASS0_ECC_AGGR_0_RAM_IDS_TOTAL_ENTRIES (28U)
82 #define SDL_PDMA0_SAM67_PDMA_SPI_ECCAGGR_RAM_IDS_TOTAL_ENTRIES (4U)
83 #define SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (0U)
84 #define SDL_USB1_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (2U)
85 #define SDL_USB0_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (2U)
86 #define SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (1U)
87 #define SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_RXMEM_RAM_IDS_TOTAL_ENTRIES (1U)
88 #define SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_TXMEM_RAM_IDS_TOTAL_ENTRIES (1U)
89 #define SDL_WKUP_PSRAMECC_8K0_PSRAM8KX32E_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (1U)
90 #define SDL_PDMA1_SAM62_PDMA_UART_ECCAGGR_RAM_IDS_TOTAL_ENTRIES (4U)
91 #define SDL_MCU_ECC_AGGR0_RAM_IDS_TOTAL_ENTRIES (2U)
92 #define SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (1U)
93 #define SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (1U)
94 #define SDL_MMCSD0_EMMC8SS_16FFC_ECC_AGGR_TXMEM_RAM_IDS_TOTAL_ENTRIES (1U)
95 #define SDL_MMCSD0_EMMC8SS_16FFC_ECC_AGGR_RXMEM_RAM_IDS_TOTAL_ENTRIES (1U)
96 #define SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_RAM_IDS_TOTAL_ENTRIES (27U)
97 #define SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_RAM_IDS_TOTAL_ENTRIES (27U)
98 #define SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_RAM_IDS_TOTAL_ENTRIES (27U)
99 #define SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_RAM_IDS_TOTAL_ENTRIES (27U)
100 #define SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_RAM_IDS_TOTAL_ENTRIES (24U)
101 #define SDL_MCU_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (1U)
102 #define SDL_ECC_Base_Address_TOTAL_ENTRIES (44U)
103 
104 static SDL_ecc_aggrRegs * const SDL_ECC_aggrBaseAddressTable[SDL_ECC_Base_Address_TOTAL_ENTRIES] =
105 {
106  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_WKUP_R5FSS0_CORE0_ECC_AGGR_BASE)),
107  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_DSS_DSI0_DSI_TOP_ECC_AGGR_SYS_CFG_BASE)),
108  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_PSRAMECC0_ECC_AGGR_BASE)),
109  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_PSRAMECC1_ECC_AGGR_BASE)),
110  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_MSRAM_64K0_ECC_AGGR_REGS_BASE)),
111  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_WKUP_ECC_AGGR2_ECC_AGGR_BASE)),
112  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_ECC_AGGR0_ECC_AGGR_BASE)),
113  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_DMASS1_ECCAGGR_BASE)),
114  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_MCU_MSRAM_256K1_ECC_AGGR_REGS_BASE)),
115  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_WKUP_VTM0_ECCAGGR_CFG_BASE)),
116  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_WKUP_ECC_AGGR1_ECC_AGGR_BASE)),
117  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_FSS0_OSPI0_ECC_AGGR_BASE)),
118  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_MCU_R5FSS0_CORE0_ECC_AGGR_BASE)),
119  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_GICSS0_REGS_BASE)),
120  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_CPSW0_ECC_BASE)),
121  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_CSI_RX_IF0_ECC_AGGR_CFG_BASE)),
122  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_PSCSS0_REGS_BASE)),
123  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_MMCSD2_ECC_AGGR_RXMEM_BASE)),
124  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_MMCSD2_ECC_AGGR_TXMEM_BASE )),
125  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_SMS0_ECC_AGGR_BASE)),
126  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_SA3_SS0_ECCAGGR_CFG_BASE)),
127  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_MCU_MCAN1_ECC_AGGR_BASE)),
128  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_WKUP_ECC_AGGR0_ECC_AGGR_BASE)),
129  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_DMASS0_ECCAGGR_BASE)),
130  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_PDMA0_BASE)),
131  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_MCU_ECC_AGGR1_ECC_AGGR_BASE)),
132  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_USB1_ECC_AGGR_BASE )),
133  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_USB0_ECC_AGGR_BASE)),
134  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_MCU_MSRAM_256K0_ECC_AGGR_REGS_BASE)),
135  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_MMCSD1_ECC_AGGR_RXMEM_BASE)),
136  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_MMCSD1_ECC_AGGR_TXMEM_BASE)),
137  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_WKUP_PSRAMECC_8K0_REGS_BASE)),
138  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_PDMA1_BASE)),
139  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_MCU_ECC_AGGR0_ECC_AGGR_BASE)),
140  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_MCAN1_ECC_AGGR_BASE)),
141  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_MCAN0_ECC_AGGR_BASE)),
142  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_MMCSD0_ECC_AGGR_TXMEM_BASE)),
143  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_MMCSD0_ECC_AGGR_RXMEM_BASE)),
144  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_COMPUTE_CLUSTER0_CORE0_ECC_AGGR_BASE)),
145  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_COMPUTE_CLUSTER0_CORE1_ECC_AGGR_BASE )),
146  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_COMPUTE_CLUSTER0_CORE2_ECC_AGGR_BASE )),
147  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_COMPUTE_CLUSTER0_CORE3_ECC_AGGR_BASE)),
148  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_COMPUTE_CLUSTER0_SS_ECC_AGGR_BASE)),
149  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_MCU_MCAN0_ECC_AGGR_BASE )),
150 };
151 
152 SDL_ecc_aggrRegs * SDL_ECC_aggrTransBaseAddressTable[SDL_ECC_MEMTYPE_MAX];
153 
158 static const SDL_MemConfig_t SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_MemEntries[SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES] =
159 {
160  { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_ITAG_RAM0_RAM_ID, 0u,
161  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_ITAG_RAM0_RAM_SIZE, 4u,
162  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_ITAG_RAM0_ROW_WIDTH, ((bool)false) },
163  { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_ITAG_RAM1_RAM_ID, 0u,
164  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_ITAG_RAM1_RAM_SIZE, 4u,
165  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_ITAG_RAM1_ROW_WIDTH, ((bool)false) },
166  { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_ITAG_RAM2_RAM_ID, 0u,
167  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_ITAG_RAM2_RAM_SIZE, 4u,
168  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_ITAG_RAM2_ROW_WIDTH, ((bool)false) },
169  { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_ITAG_RAM3_RAM_ID, 0u,
170  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_ITAG_RAM3_RAM_SIZE, 4u,
171  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_ITAG_RAM3_ROW_WIDTH, ((bool)false) },
172  { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_IDATA_BANK0_RAM_ID, 0u,
173  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_IDATA_BANK0_RAM_SIZE, 4u,
174  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_IDATA_BANK0_ROW_WIDTH, ((bool)true) },
175  { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_IDATA_BANK1_RAM_ID, 0u,
176  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_IDATA_BANK1_RAM_SIZE, 4u,
177  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_IDATA_BANK1_ROW_WIDTH, ((bool)true) },
178  { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_IDATA_BANK2_RAM_ID, 0u,
179  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_IDATA_BANK2_RAM_SIZE, 4u,
180  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_IDATA_BANK2_ROW_WIDTH, ((bool)true) },
181  { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_IDATA_BANK3_RAM_ID, 0u,
182  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_IDATA_BANK3_RAM_SIZE, 4u,
183  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_IDATA_BANK3_ROW_WIDTH, ((bool)true) },
184  { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DTAG_RAM0_RAM_ID, 0u,
185  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DTAG_RAM0_RAM_SIZE, 4u,
186  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DTAG_RAM0_ROW_WIDTH, ((bool)false) },
187  { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DTAG_RAM1_RAM_ID, 0u,
188  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DTAG_RAM1_RAM_SIZE, 4u,
189  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DTAG_RAM1_ROW_WIDTH, ((bool)false) },
190  { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DTAG_RAM2_RAM_ID, 0u,
191  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DTAG_RAM2_RAM_SIZE, 4u,
192  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DTAG_RAM2_ROW_WIDTH, ((bool)false) },
193  { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DTAG_RAM3_RAM_ID, 0u,
194  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DTAG_RAM3_RAM_SIZE, 4u,
195  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DTAG_RAM3_ROW_WIDTH, ((bool)false) },
196  { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDIRTY_RAM_RAM_ID, 0u,
197  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDIRTY_RAM_RAM_SIZE, 4u,
198  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDIRTY_RAM_ROW_WIDTH, ((bool)false) },
199  { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM0_RAM_ID, 0u,
200  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM0_RAM_SIZE, 4u,
201  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM0_ROW_WIDTH, ((bool)true) },
202  { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM1_RAM_ID, 0u,
203  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM1_RAM_SIZE, 4u,
204  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM1_ROW_WIDTH, ((bool)true) },
205  { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM2_RAM_ID, 0u,
206  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM2_RAM_SIZE, 4u,
207  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM2_ROW_WIDTH, ((bool)true) },
208  { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM3_RAM_ID, 0u,
209  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM3_RAM_SIZE, 4u,
210  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM3_ROW_WIDTH, ((bool)true) },
211  { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM4_RAM_ID, 0u,
212  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM4_RAM_SIZE, 4u,
213  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM4_ROW_WIDTH, ((bool)true) },
214  { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM5_RAM_ID, 0u,
215  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM5_RAM_SIZE, 4u,
216  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM5_ROW_WIDTH, ((bool)true) },
217  { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM6_RAM_ID, 0u,
218  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM6_RAM_SIZE, 4u,
219  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM6_ROW_WIDTH, ((bool)true) },
220  { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM7_RAM_ID, 0u,
221  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM7_RAM_SIZE, 4u,
222  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM7_ROW_WIDTH, ((bool)true) },
223  { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_ATCM0_BANK0_RAM_ID, 0u,
224  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_ATCM0_BANK0_RAM_SIZE, 4u,
225  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_ATCM0_BANK0_ROW_WIDTH, ((bool)true) },
226  { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_ATCM0_BANK1_RAM_ID, 0u,
227  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_ATCM0_BANK1_RAM_SIZE, 4u,
228  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_ATCM0_BANK1_ROW_WIDTH, ((bool)true) },
229  { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_B0TCM0_BANK0_RAM_ID, 0u,
230  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_B0TCM0_BANK0_RAM_SIZE, 4u,
231  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_B0TCM0_BANK0_ROW_WIDTH, ((bool)true) },
232  { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_B0TCM0_BANK1_RAM_ID, 0u,
233  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_B0TCM0_BANK1_RAM_SIZE, 4u,
234  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_B0TCM0_BANK1_ROW_WIDTH, ((bool)true) },
235  { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_B1TCM0_BANK0_RAM_ID, 0u,
236  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_B1TCM0_BANK0_RAM_SIZE, 4u,
237  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_B1TCM0_BANK0_ROW_WIDTH, ((bool)true) },
238  { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_B1TCM0_BANK1_RAM_ID, 0u,
239  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_B1TCM0_BANK1_RAM_SIZE, 4u,
240  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_B1TCM0_BANK1_ROW_WIDTH, ((bool)true) },
241  { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_PULSAR_KS_VIM_COMMON_CORE0_RAM_RAM_ID, 0u,
242  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_PULSAR_KS_VIM_COMMON_CORE0_RAM_RAM_SIZE, 4u,
243  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_PULSAR_KS_VIM_COMMON_CORE0_RAM_ROW_WIDTH, ((bool)false) },
244  { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_MEM_MST0_KSBUS_AXI2VBUSM_R_RDATA_BUFFER_RAM_ID, 0u,
245  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_MEM_MST0_KSBUS_AXI2VBUSM_R_RDATA_BUFFER_RAM_SIZE, 4u,
246  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_MEM_MST0_KSBUS_AXI2VBUSM_R_RDATA_BUFFER_ROW_WIDTH, ((bool)false) },
247 };
248 
254 static const SDL_GrpChkConfig_t SDL_DSS_DSI0_K3_DSS_DSI_DSI_TOP_ECC_AGGR_SYS_K3_DSS_DSI_DSI_TOP_DSI_EDC_CTRL_SYS_EDC_CTRL_0_groupEntries[SDL_DSS_DSI0_K3_DSS_DSI_DSI_TOP_ECC_AGGR_SYS_K3_DSS_DSI_DSI_TOP_DSI_EDC_CTRL_SYS_EDC_CTRL_0_MAX_NUM_CHECKERS] =
255 {
256  { SDL_DSS_DSI0_K3_DSS_DSI_DSI_TOP_ECC_AGGR_SYS_K3_DSS_DSI_DSI_TOP_DSI_EDC_CTRL_SYS_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
257  SDL_DSS_DSI0_K3_DSS_DSI_DSI_TOP_ECC_AGGR_SYS_K3_DSS_DSI_DSI_TOP_DSI_EDC_CTRL_SYS_EDC_CTRL_0_GROUP_0_WIDTH },
258  { SDL_DSS_DSI0_K3_DSS_DSI_DSI_TOP_ECC_AGGR_SYS_K3_DSS_DSI_DSI_TOP_DSI_EDC_CTRL_SYS_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
259  SDL_DSS_DSI0_K3_DSS_DSI_DSI_TOP_ECC_AGGR_SYS_K3_DSS_DSI_DSI_TOP_DSI_EDC_CTRL_SYS_EDC_CTRL_0_GROUP_1_WIDTH },
260 };
261 
266 static const SDL_MemConfig_t SDL_PSRAMECC0_PSRAM256X32E_ECC_AGGR_MemEntries[SDL_PSRAMECC0_PSRAM256X32E_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES] =
267 {
268  { SDL_PSRAMECC0_PSRAM256X32E_ECC_AGGR_PSRAM256X32E_PSRAM0_ECC_RAM_ID, 0u,
269  SDL_PSRAMECC0_PSRAM256X32E_ECC_AGGR_PSRAM256X32E_PSRAM0_ECC_RAM_SIZE, 4u,
270  SDL_PSRAMECC0_PSRAM256X32E_ECC_AGGR_PSRAM256X32E_PSRAM0_ECC_ROW_WIDTH, ((bool)true) },
271 };
272 
277 static const SDL_MemConfig_t SDL_PSRAMECC1_PSRAM256X32E_ECC_AGGR_MemEntries[SDL_PSRAMECC1_PSRAM256X32E_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES] =
278 {
279  { SDL_PSRAMECC1_PSRAM256X32E_ECC_AGGR_PSRAM256X32E_PSRAM0_ECC_RAM_ID, 0x0000900000u,
280  SDL_PSRAMECC1_PSRAM256X32E_ECC_AGGR_PSRAM256X32E_PSRAM0_ECC_RAM_SIZE, 4u,
281  SDL_PSRAMECC1_PSRAM256X32E_ECC_AGGR_PSRAM256X32E_PSRAM0_ECC_ROW_WIDTH, ((bool)true) },
282 };
283 
288 static const SDL_MemConfig_t SDL_MSRAM_64K0_MSRAM2KX256E_ECC_AGGR_MemEntries[SDL_MSRAM_64K0_MSRAM2KX256E_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES] =
289 {
290  { SDL_MSRAM_64K0_MSRAM2KX256E_ECC_AGGR_MSRAM2KX256E_MSRAM0_ECC0_RAM_ID, 0x0043C40000u,
291  SDL_MSRAM_64K0_MSRAM2KX256E_ECC_AGGR_MSRAM2KX256E_MSRAM0_ECC0_RAM_SIZE, 4u,
292  SDL_MSRAM_64K0_MSRAM2KX256E_ECC_AGGR_MSRAM2KX256E_MSRAM0_ECC0_ROW_WIDTH, ((bool)true) },
293 };
294 
300 static const SDL_GrpChkConfig_t SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_groupEntries[SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_MAX_NUM_CHECKERS] =
301 {
302  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_0_CHECKER_TYPE,
303  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_0_WIDTH },
304  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_1_CHECKER_TYPE,
305  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_1_WIDTH },
306  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_2_CHECKER_TYPE,
307  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_2_WIDTH },
308  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_3_CHECKER_TYPE,
309  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_3_WIDTH },
310  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_4_CHECKER_TYPE,
311  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_4_WIDTH },
312  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_5_CHECKER_TYPE,
313  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_5_WIDTH },
314  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_6_CHECKER_TYPE,
315  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_6_WIDTH },
316  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_7_CHECKER_TYPE,
317  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_7_WIDTH },
318  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_8_CHECKER_TYPE,
319  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_8_WIDTH },
320  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_9_CHECKER_TYPE,
321  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_9_WIDTH },
322  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_10_CHECKER_TYPE,
323  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_10_WIDTH },
324  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_11_CHECKER_TYPE,
325  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_11_WIDTH },
326  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_12_CHECKER_TYPE,
327  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_12_WIDTH },
328  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_13_CHECKER_TYPE,
329  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_13_WIDTH },
330  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_14_CHECKER_TYPE,
331  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_14_WIDTH },
332  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_15_CHECKER_TYPE,
333  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_15_WIDTH },
334  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_16_CHECKER_TYPE,
335  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_16_WIDTH },
336  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_17_CHECKER_TYPE,
337  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_17_WIDTH },
338  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_18_CHECKER_TYPE,
339  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_18_WIDTH },
340  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_19_CHECKER_TYPE,
341  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_19_WIDTH },
342  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_20_CHECKER_TYPE,
343  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_20_WIDTH },
344  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_21_CHECKER_TYPE,
345  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_21_WIDTH },
346  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_22_CHECKER_TYPE,
347  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_22_WIDTH },
348  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_23_CHECKER_TYPE,
349  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_23_WIDTH },
350  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_24_CHECKER_TYPE,
351  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_24_WIDTH },
352  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_25_CHECKER_TYPE,
353  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_25_WIDTH },
354  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_26_CHECKER_TYPE,
355  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_26_WIDTH },
356  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_27_CHECKER_TYPE,
357  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_27_WIDTH },
358  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_28_CHECKER_TYPE,
359  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_28_WIDTH },
360  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_29_CHECKER_TYPE,
361  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_29_WIDTH },
362  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_30_CHECKER_TYPE,
363  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_30_WIDTH },
364  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_31_CHECKER_TYPE,
365  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_31_WIDTH },
366  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_32_CHECKER_TYPE,
367  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_32_WIDTH },
368  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_33_CHECKER_TYPE,
369  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_33_WIDTH },
370  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_34_CHECKER_TYPE,
371  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_34_WIDTH },
372  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_35_CHECKER_TYPE,
373  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_35_WIDTH },
374  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_36_CHECKER_TYPE,
375  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_36_WIDTH },
376  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_37_CHECKER_TYPE,
377  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_37_WIDTH },
378  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_38_CHECKER_TYPE,
379  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_38_WIDTH },
380  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_39_CHECKER_TYPE,
381  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_39_WIDTH },
382  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_40_CHECKER_TYPE,
383  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_40_WIDTH },
384  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_41_CHECKER_TYPE,
385  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_41_WIDTH },
386  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_42_CHECKER_TYPE,
387  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_42_WIDTH },
388  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_43_CHECKER_TYPE,
389  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_43_WIDTH },
390  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_44_CHECKER_TYPE,
391  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_44_WIDTH },
392  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_45_CHECKER_TYPE,
393  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_45_WIDTH },
394  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_46_CHECKER_TYPE,
395  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_46_WIDTH },
396  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_47_CHECKER_TYPE,
397  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_47_WIDTH },
398  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_48_CHECKER_TYPE,
399  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_48_WIDTH },
400  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_49_CHECKER_TYPE,
401  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_49_WIDTH },
402  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_50_CHECKER_TYPE,
403  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_50_WIDTH },
404  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_51_CHECKER_TYPE,
405  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_51_WIDTH },
406  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_52_CHECKER_TYPE,
407  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_52_WIDTH },
408  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_53_CHECKER_TYPE,
409  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_53_WIDTH },
410  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_54_CHECKER_TYPE,
411  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_54_WIDTH },
412  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_55_CHECKER_TYPE,
413  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_55_WIDTH },
414  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_56_CHECKER_TYPE,
415  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_56_WIDTH },
416  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_57_CHECKER_TYPE,
417  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_57_WIDTH },
418  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_58_CHECKER_TYPE,
419  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_58_WIDTH },
420  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_59_CHECKER_TYPE,
421  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_59_WIDTH },
422  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_60_CHECKER_TYPE,
423  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_60_WIDTH },
424  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_61_CHECKER_TYPE,
425  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_61_WIDTH },
426  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_62_CHECKER_TYPE,
427  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_62_WIDTH },
428  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_63_CHECKER_TYPE,
429  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_63_WIDTH },
430  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_64_CHECKER_TYPE,
431  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_64_WIDTH },
432  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_65_CHECKER_TYPE,
433  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_65_WIDTH },
434  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_66_CHECKER_TYPE,
435  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_66_WIDTH },
436  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_67_CHECKER_TYPE,
437  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_67_WIDTH },
438  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_68_CHECKER_TYPE,
439  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_68_WIDTH },
440  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_69_CHECKER_TYPE,
441  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_69_WIDTH },
442  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_70_CHECKER_TYPE,
443  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_70_WIDTH },
444  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_71_CHECKER_TYPE,
445  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_71_WIDTH },
446  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_72_CHECKER_TYPE,
447  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_72_WIDTH },
448  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_73_CHECKER_TYPE,
449  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_73_WIDTH },
450  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_74_CHECKER_TYPE,
451  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_74_WIDTH },
452  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_75_CHECKER_TYPE,
453  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_75_WIDTH },
454  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_76_CHECKER_TYPE,
455  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_76_WIDTH },
456  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_77_CHECKER_TYPE,
457  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_77_WIDTH },
458  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_78_CHECKER_TYPE,
459  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_78_WIDTH },
460  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_79_CHECKER_TYPE,
461  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_79_WIDTH },
462  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_80_CHECKER_TYPE,
463  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_80_WIDTH },
464  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_81_CHECKER_TYPE,
465  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_81_WIDTH },
466  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_82_CHECKER_TYPE,
467  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_82_WIDTH },
468  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_83_CHECKER_TYPE,
469  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_83_WIDTH },
470  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_84_CHECKER_TYPE,
471  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_84_WIDTH },
472  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_85_CHECKER_TYPE,
473  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_85_WIDTH },
474  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_86_CHECKER_TYPE,
475  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_86_WIDTH },
476  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_87_CHECKER_TYPE,
477  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_87_WIDTH },
478  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_88_CHECKER_TYPE,
479  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_88_WIDTH },
480  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_89_CHECKER_TYPE,
481  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_89_WIDTH },
482  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_90_CHECKER_TYPE,
483  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_90_WIDTH },
484  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_91_CHECKER_TYPE,
485  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_91_WIDTH },
486  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_92_CHECKER_TYPE,
487  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_92_WIDTH },
488  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_93_CHECKER_TYPE,
489  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_93_WIDTH },
490  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_94_CHECKER_TYPE,
491  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_94_WIDTH },
492  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_95_CHECKER_TYPE,
493  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_95_WIDTH },
494  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_96_CHECKER_TYPE,
495  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_96_WIDTH },
496  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_97_CHECKER_TYPE,
497  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_97_WIDTH },
498  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_98_CHECKER_TYPE,
499  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_98_WIDTH },
500  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_99_CHECKER_TYPE,
501  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_99_WIDTH },
502  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_100_CHECKER_TYPE,
503  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_100_WIDTH },
504  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_101_CHECKER_TYPE,
505  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_101_WIDTH },
506  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_102_CHECKER_TYPE,
507  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_102_WIDTH },
508  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_103_CHECKER_TYPE,
509  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_103_WIDTH },
510  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_104_CHECKER_TYPE,
511  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_104_WIDTH },
512  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_105_CHECKER_TYPE,
513  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_105_WIDTH },
514  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_106_CHECKER_TYPE,
515  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_106_WIDTH },
516  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_107_CHECKER_TYPE,
517  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_107_WIDTH },
518  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_108_CHECKER_TYPE,
519  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_108_WIDTH },
520  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_109_CHECKER_TYPE,
521  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_109_WIDTH },
522  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_110_CHECKER_TYPE,
523  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_110_WIDTH },
524  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_111_CHECKER_TYPE,
525  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_111_WIDTH },
526  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_112_CHECKER_TYPE,
527  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_112_WIDTH },
528  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_113_CHECKER_TYPE,
529  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_113_WIDTH },
530  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_114_CHECKER_TYPE,
531  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_114_WIDTH },
532  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_115_CHECKER_TYPE,
533  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_115_WIDTH },
534  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_116_CHECKER_TYPE,
535  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_116_WIDTH },
536  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_117_CHECKER_TYPE,
537  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_117_WIDTH },
538  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_118_CHECKER_TYPE,
539  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_118_WIDTH },
540  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_119_CHECKER_TYPE,
541  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_119_WIDTH },
542  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_120_CHECKER_TYPE,
543  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_120_WIDTH },
544  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_121_CHECKER_TYPE,
545  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_121_WIDTH },
546  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_122_CHECKER_TYPE,
547  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_122_WIDTH },
548  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_123_CHECKER_TYPE,
549  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_123_WIDTH },
550  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_124_CHECKER_TYPE,
551  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_124_WIDTH },
552  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_125_CHECKER_TYPE,
553  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_125_WIDTH },
554  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_126_CHECKER_TYPE,
555  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_126_WIDTH },
556  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_127_CHECKER_TYPE,
557  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_127_WIDTH },
558  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_128_CHECKER_TYPE,
559  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_128_WIDTH },
560  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_129_CHECKER_TYPE,
561  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_129_WIDTH },
562  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_130_CHECKER_TYPE,
563  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_130_WIDTH },
564  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_131_CHECKER_TYPE,
565  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_131_WIDTH },
566  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_132_CHECKER_TYPE,
567  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_132_WIDTH },
568  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_133_CHECKER_TYPE,
569  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_133_WIDTH },
570  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_134_CHECKER_TYPE,
571  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_134_WIDTH },
572  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_135_CHECKER_TYPE,
573  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_135_WIDTH },
574  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_136_CHECKER_TYPE,
575  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_136_WIDTH },
576  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_137_CHECKER_TYPE,
577  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_137_WIDTH },
578  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_138_CHECKER_TYPE,
579  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_138_WIDTH },
580  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_139_CHECKER_TYPE,
581  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_139_WIDTH },
582  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_140_CHECKER_TYPE,
583  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_140_WIDTH },
584  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_141_CHECKER_TYPE,
585  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_141_WIDTH },
586  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_142_CHECKER_TYPE,
587  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_142_WIDTH },
588  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_143_CHECKER_TYPE,
589  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_143_WIDTH },
590  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_144_CHECKER_TYPE,
591  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_144_WIDTH },
592  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_145_CHECKER_TYPE,
593  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_145_WIDTH },
594  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_146_CHECKER_TYPE,
595  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_146_WIDTH },
596  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_147_CHECKER_TYPE,
597  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_147_WIDTH },
598  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_148_CHECKER_TYPE,
599  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_148_WIDTH },
600  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_149_CHECKER_TYPE,
601  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_149_WIDTH },
602  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_150_CHECKER_TYPE,
603  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_150_WIDTH },
604  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_151_CHECKER_TYPE,
605  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_151_WIDTH },
606  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_152_CHECKER_TYPE,
607  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_152_WIDTH },
608  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_153_CHECKER_TYPE,
609  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_153_WIDTH },
610  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_154_CHECKER_TYPE,
611  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_154_WIDTH },
612  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_155_CHECKER_TYPE,
613  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_155_WIDTH },
614  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_156_CHECKER_TYPE,
615  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_156_WIDTH },
616  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_157_CHECKER_TYPE,
617  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_157_WIDTH },
618  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_158_CHECKER_TYPE,
619  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_158_WIDTH },
620  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_159_CHECKER_TYPE,
621  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_159_WIDTH },
622  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_160_CHECKER_TYPE,
623  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_160_WIDTH },
624  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_161_CHECKER_TYPE,
625  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_161_WIDTH },
626  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_162_CHECKER_TYPE,
627  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_162_WIDTH },
628  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_163_CHECKER_TYPE,
629  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_163_WIDTH },
630  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_164_CHECKER_TYPE,
631  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_164_WIDTH },
632  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_165_CHECKER_TYPE,
633  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_165_WIDTH },
634  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_166_CHECKER_TYPE,
635  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_166_WIDTH },
636  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_167_CHECKER_TYPE,
637  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_167_WIDTH },
638  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_168_CHECKER_TYPE,
639  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_168_WIDTH },
640  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_169_CHECKER_TYPE,
641  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_169_WIDTH },
642  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_170_CHECKER_TYPE,
643  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_170_WIDTH },
644  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_171_CHECKER_TYPE,
645  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_171_WIDTH },
646  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_172_CHECKER_TYPE,
647  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_172_WIDTH },
648  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_173_CHECKER_TYPE,
649  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_173_WIDTH },
650  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_174_CHECKER_TYPE,
651  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_174_WIDTH },
652  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_175_CHECKER_TYPE,
653  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_175_WIDTH },
654  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_176_CHECKER_TYPE,
655  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_176_WIDTH },
656  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_177_CHECKER_TYPE,
657  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_177_WIDTH },
658  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_178_CHECKER_TYPE,
659  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_178_WIDTH },
660  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_179_CHECKER_TYPE,
661  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_179_WIDTH },
662  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_180_CHECKER_TYPE,
663  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_180_WIDTH },
664  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_181_CHECKER_TYPE,
665  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_181_WIDTH },
666  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_182_CHECKER_TYPE,
667  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_182_WIDTH },
668  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_183_CHECKER_TYPE,
669  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_183_WIDTH },
670  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_184_CHECKER_TYPE,
671  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_184_WIDTH },
672  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_185_CHECKER_TYPE,
673  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_185_WIDTH },
674  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_186_CHECKER_TYPE,
675  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_186_WIDTH },
676  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_187_CHECKER_TYPE,
677  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_187_WIDTH },
678  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_188_CHECKER_TYPE,
679  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_188_WIDTH },
680  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_189_CHECKER_TYPE,
681  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_189_WIDTH },
682  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_190_CHECKER_TYPE,
683  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_190_WIDTH },
684  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_191_CHECKER_TYPE,
685  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_191_WIDTH },
686  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_192_CHECKER_TYPE,
687  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_192_WIDTH },
688  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_193_CHECKER_TYPE,
689  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_193_WIDTH },
690  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_194_CHECKER_TYPE,
691  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_194_WIDTH },
692  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_195_CHECKER_TYPE,
693  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_195_WIDTH },
694  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_196_CHECKER_TYPE,
695  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_196_WIDTH },
696  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_197_CHECKER_TYPE,
697  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_197_WIDTH },
698  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_198_CHECKER_TYPE,
699  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_198_WIDTH },
700  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_199_CHECKER_TYPE,
701  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_199_WIDTH },
702  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_200_CHECKER_TYPE,
703  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_200_WIDTH },
704  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_201_CHECKER_TYPE,
705  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_201_WIDTH },
706  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_202_CHECKER_TYPE,
707  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_202_WIDTH },
708  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_203_CHECKER_TYPE,
709  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_203_WIDTH },
710  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_204_CHECKER_TYPE,
711  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_204_WIDTH },
712  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_205_CHECKER_TYPE,
713  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_205_WIDTH },
714  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_206_CHECKER_TYPE,
715  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_206_WIDTH },
716  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_207_CHECKER_TYPE,
717  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_207_WIDTH },
718  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_208_CHECKER_TYPE,
719  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_208_WIDTH },
720  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_209_CHECKER_TYPE,
721  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_209_WIDTH },
722  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_210_CHECKER_TYPE,
723  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_210_WIDTH },
724  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_211_CHECKER_TYPE,
725  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_211_WIDTH },
726  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_212_CHECKER_TYPE,
727  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_212_WIDTH },
728  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_213_CHECKER_TYPE,
729  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_213_WIDTH },
730  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_214_CHECKER_TYPE,
731  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_214_WIDTH },
732  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_215_CHECKER_TYPE,
733  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_215_WIDTH },
734  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_216_CHECKER_TYPE,
735  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_216_WIDTH },
736  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_217_CHECKER_TYPE,
737  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_217_WIDTH },
738  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_218_CHECKER_TYPE,
739  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_218_WIDTH },
740  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_219_CHECKER_TYPE,
741  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_219_WIDTH },
742  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_220_CHECKER_TYPE,
743  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_220_WIDTH },
744  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_221_CHECKER_TYPE,
745  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_221_WIDTH },
746  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_222_CHECKER_TYPE,
747  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_222_WIDTH },
748  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_223_CHECKER_TYPE,
749  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_223_WIDTH },
750  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_224_CHECKER_TYPE,
751  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_224_WIDTH },
752  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_225_CHECKER_TYPE,
753  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_225_WIDTH },
754  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_226_CHECKER_TYPE,
755  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_226_WIDTH },
756  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_227_CHECKER_TYPE,
757  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_227_WIDTH },
758  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_228_CHECKER_TYPE,
759  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_228_WIDTH },
760  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_229_CHECKER_TYPE,
761  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_229_WIDTH },
762  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_230_CHECKER_TYPE,
763  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_230_WIDTH },
764  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_231_CHECKER_TYPE,
765  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_231_WIDTH },
766  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_232_CHECKER_TYPE,
767  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_232_WIDTH },
768  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_233_CHECKER_TYPE,
769  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_233_WIDTH },
770  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_234_CHECKER_TYPE,
771  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_234_WIDTH },
772  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_235_CHECKER_TYPE,
773  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_235_WIDTH },
774  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_236_CHECKER_TYPE,
775  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_236_WIDTH },
776  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_237_CHECKER_TYPE,
777  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_237_WIDTH },
778  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_238_CHECKER_TYPE,
779  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_238_WIDTH },
780  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_239_CHECKER_TYPE,
781  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_239_WIDTH },
782  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_240_CHECKER_TYPE,
783  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_240_WIDTH },
784  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_241_CHECKER_TYPE,
785  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_241_WIDTH },
786  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_242_CHECKER_TYPE,
787  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_242_WIDTH },
788  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_243_CHECKER_TYPE,
789  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_243_WIDTH },
790  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_244_CHECKER_TYPE,
791  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_244_WIDTH },
792  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_245_CHECKER_TYPE,
793  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_245_WIDTH },
794  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_246_CHECKER_TYPE,
795  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_246_WIDTH },
796  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_247_CHECKER_TYPE,
797  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_247_WIDTH },
798  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_248_CHECKER_TYPE,
799  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_248_WIDTH },
800  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_249_CHECKER_TYPE,
801  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_249_WIDTH },
802  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_250_CHECKER_TYPE,
803  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_250_WIDTH },
804  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_251_CHECKER_TYPE,
805  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_251_WIDTH },
806  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_252_CHECKER_TYPE,
807  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_252_WIDTH },
808  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_253_CHECKER_TYPE,
809  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_253_WIDTH },
810  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_254_CHECKER_TYPE,
811  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_254_WIDTH },
812  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_255_CHECKER_TYPE,
813  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_255_WIDTH },
814 };
815 
821 static const SDL_GrpChkConfig_t SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_groupEntries[SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_MAX_NUM_CHECKERS] =
822 {
823  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_0_CHECKER_TYPE,
824  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_0_WIDTH },
825  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_1_CHECKER_TYPE,
826  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_1_WIDTH },
827  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_2_CHECKER_TYPE,
828  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_2_WIDTH },
829  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_3_CHECKER_TYPE,
830  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_3_WIDTH },
831  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_4_CHECKER_TYPE,
832  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_4_WIDTH },
833  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_5_CHECKER_TYPE,
834  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_5_WIDTH },
835  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_6_CHECKER_TYPE,
836  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_6_WIDTH },
837  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_7_CHECKER_TYPE,
838  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_7_WIDTH },
839  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_8_CHECKER_TYPE,
840  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_8_WIDTH },
841  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_9_CHECKER_TYPE,
842  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_9_WIDTH },
843  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_10_CHECKER_TYPE,
844  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_10_WIDTH },
845  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_11_CHECKER_TYPE,
846  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_11_WIDTH },
847  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_12_CHECKER_TYPE,
848  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_12_WIDTH },
849  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_13_CHECKER_TYPE,
850  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_13_WIDTH },
851  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_14_CHECKER_TYPE,
852  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_14_WIDTH },
853  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_15_CHECKER_TYPE,
854  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_15_WIDTH },
855  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_16_CHECKER_TYPE,
856  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_16_WIDTH },
857  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_17_CHECKER_TYPE,
858  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_17_WIDTH },
859  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_18_CHECKER_TYPE,
860  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_18_WIDTH },
861  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_19_CHECKER_TYPE,
862  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_19_WIDTH },
863  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_20_CHECKER_TYPE,
864  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_20_WIDTH },
865  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_21_CHECKER_TYPE,
866  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_21_WIDTH },
867  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_22_CHECKER_TYPE,
868  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_22_WIDTH },
869  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_23_CHECKER_TYPE,
870  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_23_WIDTH },
871  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_24_CHECKER_TYPE,
872  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_24_WIDTH },
873  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_25_CHECKER_TYPE,
874  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_25_WIDTH },
875  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_26_CHECKER_TYPE,
876  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_26_WIDTH },
877  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_27_CHECKER_TYPE,
878  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_27_WIDTH },
879  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_28_CHECKER_TYPE,
880  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_28_WIDTH },
881  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_29_CHECKER_TYPE,
882  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_29_WIDTH },
883  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_30_CHECKER_TYPE,
884  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_30_WIDTH },
885  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_31_CHECKER_TYPE,
886  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_31_WIDTH },
887  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_32_CHECKER_TYPE,
888  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_32_WIDTH },
889  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_33_CHECKER_TYPE,
890  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_33_WIDTH },
891  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_34_CHECKER_TYPE,
892  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_34_WIDTH },
893  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_35_CHECKER_TYPE,
894  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_35_WIDTH },
895  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_36_CHECKER_TYPE,
896  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_36_WIDTH },
897  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_37_CHECKER_TYPE,
898  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_37_WIDTH },
899  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_38_CHECKER_TYPE,
900  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_38_WIDTH },
901  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_39_CHECKER_TYPE,
902  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_39_WIDTH },
903  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_40_CHECKER_TYPE,
904  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_40_WIDTH },
905  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_41_CHECKER_TYPE,
906  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_41_WIDTH },
907  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_42_CHECKER_TYPE,
908  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_42_WIDTH },
909  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_43_CHECKER_TYPE,
910  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_43_WIDTH },
911  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_44_CHECKER_TYPE,
912  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_44_WIDTH },
913  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_45_CHECKER_TYPE,
914  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_45_WIDTH },
915  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_46_CHECKER_TYPE,
916  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_46_WIDTH },
917  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_47_CHECKER_TYPE,
918  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_47_WIDTH },
919  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_48_CHECKER_TYPE,
920  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_48_WIDTH },
921  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_49_CHECKER_TYPE,
922  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_49_WIDTH },
923  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_50_CHECKER_TYPE,
924  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_50_WIDTH },
925  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_51_CHECKER_TYPE,
926  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_51_WIDTH },
927  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_52_CHECKER_TYPE,
928  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_52_WIDTH },
929  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_53_CHECKER_TYPE,
930  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_53_WIDTH },
931  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_54_CHECKER_TYPE,
932  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_54_WIDTH },
933  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_55_CHECKER_TYPE,
934  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_55_WIDTH },
935  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_56_CHECKER_TYPE,
936  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_56_WIDTH },
937  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_57_CHECKER_TYPE,
938  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_57_WIDTH },
939  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_58_CHECKER_TYPE,
940  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_58_WIDTH },
941  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_59_CHECKER_TYPE,
942  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_59_WIDTH },
943  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_60_CHECKER_TYPE,
944  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_60_WIDTH },
945  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_61_CHECKER_TYPE,
946  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_61_WIDTH },
947  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_62_CHECKER_TYPE,
948  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_62_WIDTH },
949  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_63_CHECKER_TYPE,
950  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_63_WIDTH },
951  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_64_CHECKER_TYPE,
952  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_64_WIDTH },
953  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_65_CHECKER_TYPE,
954  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_65_WIDTH },
955  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_66_CHECKER_TYPE,
956  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_66_WIDTH },
957  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_67_CHECKER_TYPE,
958  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_67_WIDTH },
959  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_68_CHECKER_TYPE,
960  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_68_WIDTH },
961  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_69_CHECKER_TYPE,
962  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_69_WIDTH },
963  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_70_CHECKER_TYPE,
964  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_70_WIDTH },
965  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_71_CHECKER_TYPE,
966  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_71_WIDTH },
967  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_72_CHECKER_TYPE,
968  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_72_WIDTH },
969  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_73_CHECKER_TYPE,
970  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_73_WIDTH },
971  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_74_CHECKER_TYPE,
972  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_74_WIDTH },
973  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_75_CHECKER_TYPE,
974  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_75_WIDTH },
975  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_76_CHECKER_TYPE,
976  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_76_WIDTH },
977  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_77_CHECKER_TYPE,
978  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_77_WIDTH },
979  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_78_CHECKER_TYPE,
980  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_78_WIDTH },
981  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_79_CHECKER_TYPE,
982  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_79_WIDTH },
983  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_80_CHECKER_TYPE,
984  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_80_WIDTH },
985  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_81_CHECKER_TYPE,
986  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_81_WIDTH },
987  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_82_CHECKER_TYPE,
988  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_82_WIDTH },
989  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_83_CHECKER_TYPE,
990  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_83_WIDTH },
991  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_84_CHECKER_TYPE,
992  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_84_WIDTH },
993  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_85_CHECKER_TYPE,
994  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_85_WIDTH },
995  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_86_CHECKER_TYPE,
996  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_86_WIDTH },
997  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_87_CHECKER_TYPE,
998  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_87_WIDTH },
999  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_88_CHECKER_TYPE,
1000  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_88_WIDTH },
1001  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_89_CHECKER_TYPE,
1002  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_89_WIDTH },
1003  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_90_CHECKER_TYPE,
1004  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_90_WIDTH },
1005  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_91_CHECKER_TYPE,
1006  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_91_WIDTH },
1007  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_92_CHECKER_TYPE,
1008  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_92_WIDTH },
1009  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_93_CHECKER_TYPE,
1010  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_93_WIDTH },
1011  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_94_CHECKER_TYPE,
1012  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_94_WIDTH },
1013  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_95_CHECKER_TYPE,
1014  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_95_WIDTH },
1015  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_96_CHECKER_TYPE,
1016  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_96_WIDTH },
1017  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_97_CHECKER_TYPE,
1018  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_97_WIDTH },
1019  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_98_CHECKER_TYPE,
1020  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_98_WIDTH },
1021  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_99_CHECKER_TYPE,
1022  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_99_WIDTH },
1023  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_100_CHECKER_TYPE,
1024  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_100_WIDTH },
1025  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_101_CHECKER_TYPE,
1026  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_101_WIDTH },
1027  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_102_CHECKER_TYPE,
1028  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_102_WIDTH },
1029  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_103_CHECKER_TYPE,
1030  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_103_WIDTH },
1031  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_104_CHECKER_TYPE,
1032  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_104_WIDTH },
1033  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_105_CHECKER_TYPE,
1034  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_105_WIDTH },
1035  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_106_CHECKER_TYPE,
1036  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_106_WIDTH },
1037  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_107_CHECKER_TYPE,
1038  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_107_WIDTH },
1039  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_108_CHECKER_TYPE,
1040  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_108_WIDTH },
1041  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_109_CHECKER_TYPE,
1042  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_109_WIDTH },
1043  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_110_CHECKER_TYPE,
1044  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_110_WIDTH },
1045  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_111_CHECKER_TYPE,
1046  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_111_WIDTH },
1047  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_112_CHECKER_TYPE,
1048  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_112_WIDTH },
1049  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_113_CHECKER_TYPE,
1050  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_113_WIDTH },
1051  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_114_CHECKER_TYPE,
1052  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_114_WIDTH },
1053  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_115_CHECKER_TYPE,
1054  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_115_WIDTH },
1055  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_116_CHECKER_TYPE,
1056  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_116_WIDTH },
1057  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_117_CHECKER_TYPE,
1058  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_117_WIDTH },
1059  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_118_CHECKER_TYPE,
1060  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_118_WIDTH },
1061  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_119_CHECKER_TYPE,
1062  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_119_WIDTH },
1063  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_120_CHECKER_TYPE,
1064  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_120_WIDTH },
1065  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_121_CHECKER_TYPE,
1066  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_121_WIDTH },
1067  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_122_CHECKER_TYPE,
1068  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_122_WIDTH },
1069  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_123_CHECKER_TYPE,
1070  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_123_WIDTH },
1071  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_124_CHECKER_TYPE,
1072  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_124_WIDTH },
1073  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_125_CHECKER_TYPE,
1074  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_125_WIDTH },
1075  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_126_CHECKER_TYPE,
1076  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_126_WIDTH },
1077  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_127_CHECKER_TYPE,
1078  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_127_WIDTH },
1079  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_128_CHECKER_TYPE,
1080  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_128_WIDTH },
1081  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_129_CHECKER_TYPE,
1082  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_129_WIDTH },
1083  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_130_CHECKER_TYPE,
1084  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_130_WIDTH },
1085  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_131_CHECKER_TYPE,
1086  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_131_WIDTH },
1087  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_132_CHECKER_TYPE,
1088  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_132_WIDTH },
1089  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_133_CHECKER_TYPE,
1090  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_133_WIDTH },
1091  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_134_CHECKER_TYPE,
1092  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_134_WIDTH },
1093  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_135_CHECKER_TYPE,
1094  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_135_WIDTH },
1095  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_136_CHECKER_TYPE,
1096  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_136_WIDTH },
1097  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_137_CHECKER_TYPE,
1098  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_137_WIDTH },
1099  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_138_CHECKER_TYPE,
1100  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_138_WIDTH },
1101  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_139_CHECKER_TYPE,
1102  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_139_WIDTH },
1103  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_140_CHECKER_TYPE,
1104  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_140_WIDTH },
1105  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_141_CHECKER_TYPE,
1106  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_141_WIDTH },
1107  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_142_CHECKER_TYPE,
1108  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_142_WIDTH },
1109  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_143_CHECKER_TYPE,
1110  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_143_WIDTH },
1111  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_144_CHECKER_TYPE,
1112  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_144_WIDTH },
1113  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_145_CHECKER_TYPE,
1114  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_145_WIDTH },
1115  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_146_CHECKER_TYPE,
1116  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_146_WIDTH },
1117  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_147_CHECKER_TYPE,
1118  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_147_WIDTH },
1119  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_148_CHECKER_TYPE,
1120  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_148_WIDTH },
1121  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_149_CHECKER_TYPE,
1122  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_149_WIDTH },
1123  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_150_CHECKER_TYPE,
1124  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_150_WIDTH },
1125  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_151_CHECKER_TYPE,
1126  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_151_WIDTH },
1127  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_152_CHECKER_TYPE,
1128  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_152_WIDTH },
1129  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_153_CHECKER_TYPE,
1130  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_153_WIDTH },
1131  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_154_CHECKER_TYPE,
1132  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_154_WIDTH },
1133  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_155_CHECKER_TYPE,
1134  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_155_WIDTH },
1135  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_156_CHECKER_TYPE,
1136  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_156_WIDTH },
1137  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_157_CHECKER_TYPE,
1138  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_157_WIDTH },
1139  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_158_CHECKER_TYPE,
1140  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_158_WIDTH },
1141  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_159_CHECKER_TYPE,
1142  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_159_WIDTH },
1143  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_160_CHECKER_TYPE,
1144  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_160_WIDTH },
1145  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_161_CHECKER_TYPE,
1146  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_161_WIDTH },
1147  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_162_CHECKER_TYPE,
1148  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_162_WIDTH },
1149  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_163_CHECKER_TYPE,
1150  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_163_WIDTH },
1151  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_164_CHECKER_TYPE,
1152  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_164_WIDTH },
1153  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_165_CHECKER_TYPE,
1154  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_165_WIDTH },
1155  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_166_CHECKER_TYPE,
1156  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_166_WIDTH },
1157  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_167_CHECKER_TYPE,
1158  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_167_WIDTH },
1159  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_168_CHECKER_TYPE,
1160  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_168_WIDTH },
1161  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_169_CHECKER_TYPE,
1162  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_169_WIDTH },
1163  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_170_CHECKER_TYPE,
1164  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_170_WIDTH },
1165  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_171_CHECKER_TYPE,
1166  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_171_WIDTH },
1167  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_172_CHECKER_TYPE,
1168  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_172_WIDTH },
1169  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_173_CHECKER_TYPE,
1170  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_173_WIDTH },
1171  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_174_CHECKER_TYPE,
1172  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_174_WIDTH },
1173  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_175_CHECKER_TYPE,
1174  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_175_WIDTH },
1175  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_176_CHECKER_TYPE,
1176  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_176_WIDTH },
1177  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_177_CHECKER_TYPE,
1178  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_177_WIDTH },
1179  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_178_CHECKER_TYPE,
1180  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_178_WIDTH },
1181  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_179_CHECKER_TYPE,
1182  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_179_WIDTH },
1183  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_180_CHECKER_TYPE,
1184  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_180_WIDTH },
1185  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_181_CHECKER_TYPE,
1186  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_181_WIDTH },
1187  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_182_CHECKER_TYPE,
1188  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_182_WIDTH },
1189  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_183_CHECKER_TYPE,
1190  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_183_WIDTH },
1191  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_184_CHECKER_TYPE,
1192  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_184_WIDTH },
1193  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_185_CHECKER_TYPE,
1194  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_185_WIDTH },
1195  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_186_CHECKER_TYPE,
1196  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_186_WIDTH },
1197  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_187_CHECKER_TYPE,
1198  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_187_WIDTH },
1199  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_188_CHECKER_TYPE,
1200  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_188_WIDTH },
1201  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_189_CHECKER_TYPE,
1202  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_189_WIDTH },
1203  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_190_CHECKER_TYPE,
1204  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_190_WIDTH },
1205  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_191_CHECKER_TYPE,
1206  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_191_WIDTH },
1207  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_192_CHECKER_TYPE,
1208  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_192_WIDTH },
1209  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_193_CHECKER_TYPE,
1210  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_193_WIDTH },
1211  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_194_CHECKER_TYPE,
1212  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_194_WIDTH },
1213  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_195_CHECKER_TYPE,
1214  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_195_WIDTH },
1215  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_196_CHECKER_TYPE,
1216  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_196_WIDTH },
1217  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_197_CHECKER_TYPE,
1218  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_197_WIDTH },
1219  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_198_CHECKER_TYPE,
1220  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_198_WIDTH },
1221  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_199_CHECKER_TYPE,
1222  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_199_WIDTH },
1223  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_200_CHECKER_TYPE,
1224  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_200_WIDTH },
1225  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_201_CHECKER_TYPE,
1226  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_201_WIDTH },
1227  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_202_CHECKER_TYPE,
1228  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_202_WIDTH },
1229  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_203_CHECKER_TYPE,
1230  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_203_WIDTH },
1231  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_204_CHECKER_TYPE,
1232  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_204_WIDTH },
1233  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_205_CHECKER_TYPE,
1234  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_205_WIDTH },
1235  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_206_CHECKER_TYPE,
1236  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_206_WIDTH },
1237  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_207_CHECKER_TYPE,
1238  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_207_WIDTH },
1239  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_208_CHECKER_TYPE,
1240  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_208_WIDTH },
1241  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_209_CHECKER_TYPE,
1242  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_209_WIDTH },
1243  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_210_CHECKER_TYPE,
1244  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_210_WIDTH },
1245  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_211_CHECKER_TYPE,
1246  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_211_WIDTH },
1247  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_212_CHECKER_TYPE,
1248  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_212_WIDTH },
1249  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_213_CHECKER_TYPE,
1250  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_213_WIDTH },
1251  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_214_CHECKER_TYPE,
1252  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_214_WIDTH },
1253  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_215_CHECKER_TYPE,
1254  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_215_WIDTH },
1255  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_216_CHECKER_TYPE,
1256  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_216_WIDTH },
1257  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_217_CHECKER_TYPE,
1258  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_217_WIDTH },
1259  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_218_CHECKER_TYPE,
1260  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_218_WIDTH },
1261  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_219_CHECKER_TYPE,
1262  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_219_WIDTH },
1263  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_220_CHECKER_TYPE,
1264  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_220_WIDTH },
1265  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_221_CHECKER_TYPE,
1266  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_221_WIDTH },
1267  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_222_CHECKER_TYPE,
1268  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_222_WIDTH },
1269  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_223_CHECKER_TYPE,
1270  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_223_WIDTH },
1271  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_224_CHECKER_TYPE,
1272  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_224_WIDTH },
1273  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_225_CHECKER_TYPE,
1274  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_225_WIDTH },
1275  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_226_CHECKER_TYPE,
1276  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_226_WIDTH },
1277  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_227_CHECKER_TYPE,
1278  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_227_WIDTH },
1279  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_228_CHECKER_TYPE,
1280  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_228_WIDTH },
1281  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_229_CHECKER_TYPE,
1282  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_229_WIDTH },
1283  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_230_CHECKER_TYPE,
1284  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_230_WIDTH },
1285  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_231_CHECKER_TYPE,
1286  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_231_WIDTH },
1287  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_232_CHECKER_TYPE,
1288  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_232_WIDTH },
1289  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_233_CHECKER_TYPE,
1290  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_233_WIDTH },
1291  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_234_CHECKER_TYPE,
1292  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_234_WIDTH },
1293  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_235_CHECKER_TYPE,
1294  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_235_WIDTH },
1295  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_236_CHECKER_TYPE,
1296  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_236_WIDTH },
1297  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_237_CHECKER_TYPE,
1298  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_237_WIDTH },
1299 };
1300 
1306 static const SDL_GrpChkConfig_t SDL_WKUP_ECC_AGGR2_AM67_MCU_PLL_MMR_EDC_CTRL_BUSECC_groupEntries[SDL_WKUP_ECC_AGGR2_AM67_MCU_PLL_MMR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS] =
1307 {
1308  { SDL_WKUP_ECC_AGGR2_AM67_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
1309  SDL_WKUP_ECC_AGGR2_AM67_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
1310  { SDL_WKUP_ECC_AGGR2_AM67_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
1311  SDL_WKUP_ECC_AGGR2_AM67_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
1312  { SDL_WKUP_ECC_AGGR2_AM67_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
1313  SDL_WKUP_ECC_AGGR2_AM67_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
1314  { SDL_WKUP_ECC_AGGR2_AM67_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
1315  SDL_WKUP_ECC_AGGR2_AM67_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
1316  { SDL_WKUP_ECC_AGGR2_AM67_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
1317  SDL_WKUP_ECC_AGGR2_AM67_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
1318  { SDL_WKUP_ECC_AGGR2_AM67_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_5_CHECKER_TYPE,
1319  SDL_WKUP_ECC_AGGR2_AM67_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_5_WIDTH },
1320  { SDL_WKUP_ECC_AGGR2_AM67_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_6_CHECKER_TYPE,
1321  SDL_WKUP_ECC_AGGR2_AM67_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_6_WIDTH },
1322  { SDL_WKUP_ECC_AGGR2_AM67_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_7_CHECKER_TYPE,
1323  SDL_WKUP_ECC_AGGR2_AM67_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_7_WIDTH },
1324  { SDL_WKUP_ECC_AGGR2_AM67_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_8_CHECKER_TYPE,
1325  SDL_WKUP_ECC_AGGR2_AM67_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_8_WIDTH },
1326  { SDL_WKUP_ECC_AGGR2_AM67_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_9_CHECKER_TYPE,
1327  SDL_WKUP_ECC_AGGR2_AM67_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_9_WIDTH },
1328  { SDL_WKUP_ECC_AGGR2_AM67_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_10_CHECKER_TYPE,
1329  SDL_WKUP_ECC_AGGR2_AM67_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_10_WIDTH },
1330  { SDL_WKUP_ECC_AGGR2_AM67_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_11_CHECKER_TYPE,
1331  SDL_WKUP_ECC_AGGR2_AM67_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_11_WIDTH },
1332  { SDL_WKUP_ECC_AGGR2_AM67_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_12_CHECKER_TYPE,
1333  SDL_WKUP_ECC_AGGR2_AM67_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_12_WIDTH },
1334  { SDL_WKUP_ECC_AGGR2_AM67_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_13_CHECKER_TYPE,
1335  SDL_WKUP_ECC_AGGR2_AM67_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_13_WIDTH },
1336  { SDL_WKUP_ECC_AGGR2_AM67_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_14_CHECKER_TYPE,
1337  SDL_WKUP_ECC_AGGR2_AM67_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_14_WIDTH },
1338  { SDL_WKUP_ECC_AGGR2_AM67_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_15_CHECKER_TYPE,
1339  SDL_WKUP_ECC_AGGR2_AM67_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_15_WIDTH },
1340  { SDL_WKUP_ECC_AGGR2_AM67_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_16_CHECKER_TYPE,
1341  SDL_WKUP_ECC_AGGR2_AM67_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_16_WIDTH },
1342  { SDL_WKUP_ECC_AGGR2_AM67_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_17_CHECKER_TYPE,
1343  SDL_WKUP_ECC_AGGR2_AM67_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_17_WIDTH },
1344  { SDL_WKUP_ECC_AGGR2_AM67_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_18_CHECKER_TYPE,
1345  SDL_WKUP_ECC_AGGR2_AM67_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_18_WIDTH },
1346  { SDL_WKUP_ECC_AGGR2_AM67_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_19_CHECKER_TYPE,
1347  SDL_WKUP_ECC_AGGR2_AM67_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_19_WIDTH },
1348  { SDL_WKUP_ECC_AGGR2_AM67_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_20_CHECKER_TYPE,
1349  SDL_WKUP_ECC_AGGR2_AM67_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_20_WIDTH },
1350  { SDL_WKUP_ECC_AGGR2_AM67_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_21_CHECKER_TYPE,
1351  SDL_WKUP_ECC_AGGR2_AM67_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_21_WIDTH },
1352  { SDL_WKUP_ECC_AGGR2_AM67_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_22_CHECKER_TYPE,
1353  SDL_WKUP_ECC_AGGR2_AM67_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_22_WIDTH },
1354  { SDL_WKUP_ECC_AGGR2_AM67_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_23_CHECKER_TYPE,
1355  SDL_WKUP_ECC_AGGR2_AM67_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_23_WIDTH },
1356  { SDL_WKUP_ECC_AGGR2_AM67_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_24_CHECKER_TYPE,
1357  SDL_WKUP_ECC_AGGR2_AM67_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_24_WIDTH },
1358  { SDL_WKUP_ECC_AGGR2_AM67_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_25_CHECKER_TYPE,
1359  SDL_WKUP_ECC_AGGR2_AM67_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_25_WIDTH },
1360  { SDL_WKUP_ECC_AGGR2_AM67_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_26_CHECKER_TYPE,
1361  SDL_WKUP_ECC_AGGR2_AM67_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_26_WIDTH },
1362  { SDL_WKUP_ECC_AGGR2_AM67_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_27_CHECKER_TYPE,
1363  SDL_WKUP_ECC_AGGR2_AM67_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_27_WIDTH },
1364  { SDL_WKUP_ECC_AGGR2_AM67_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_28_CHECKER_TYPE,
1365  SDL_WKUP_ECC_AGGR2_AM67_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_28_WIDTH },
1366  { SDL_WKUP_ECC_AGGR2_AM67_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_29_CHECKER_TYPE,
1367  SDL_WKUP_ECC_AGGR2_AM67_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_29_WIDTH },
1368  { SDL_WKUP_ECC_AGGR2_AM67_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_30_CHECKER_TYPE,
1369  SDL_WKUP_ECC_AGGR2_AM67_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_30_WIDTH },
1370  { SDL_WKUP_ECC_AGGR2_AM67_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_31_CHECKER_TYPE,
1371  SDL_WKUP_ECC_AGGR2_AM67_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_31_WIDTH },
1372  { SDL_WKUP_ECC_AGGR2_AM67_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_32_CHECKER_TYPE,
1373  SDL_WKUP_ECC_AGGR2_AM67_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_32_WIDTH },
1374  { SDL_WKUP_ECC_AGGR2_AM67_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_33_CHECKER_TYPE,
1375  SDL_WKUP_ECC_AGGR2_AM67_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_33_WIDTH },
1376  { SDL_WKUP_ECC_AGGR2_AM67_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_34_CHECKER_TYPE,
1377  SDL_WKUP_ECC_AGGR2_AM67_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_34_WIDTH },
1378  { SDL_WKUP_ECC_AGGR2_AM67_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_35_CHECKER_TYPE,
1379  SDL_WKUP_ECC_AGGR2_AM67_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_35_WIDTH },
1380  { SDL_WKUP_ECC_AGGR2_AM67_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_36_CHECKER_TYPE,
1381  SDL_WKUP_ECC_AGGR2_AM67_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_36_WIDTH },
1382  { SDL_WKUP_ECC_AGGR2_AM67_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_37_CHECKER_TYPE,
1383  SDL_WKUP_ECC_AGGR2_AM67_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_37_WIDTH },
1384  { SDL_WKUP_ECC_AGGR2_AM67_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_38_CHECKER_TYPE,
1385  SDL_WKUP_ECC_AGGR2_AM67_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_38_WIDTH },
1386  { SDL_WKUP_ECC_AGGR2_AM67_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_39_CHECKER_TYPE,
1387  SDL_WKUP_ECC_AGGR2_AM67_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_39_WIDTH },
1388  { SDL_WKUP_ECC_AGGR2_AM67_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_40_CHECKER_TYPE,
1389  SDL_WKUP_ECC_AGGR2_AM67_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_40_WIDTH },
1390  { SDL_WKUP_ECC_AGGR2_AM67_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_41_CHECKER_TYPE,
1391  SDL_WKUP_ECC_AGGR2_AM67_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_41_WIDTH },
1392  { SDL_WKUP_ECC_AGGR2_AM67_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_42_CHECKER_TYPE,
1393  SDL_WKUP_ECC_AGGR2_AM67_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_42_WIDTH },
1394  { SDL_WKUP_ECC_AGGR2_AM67_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_43_CHECKER_TYPE,
1395  SDL_WKUP_ECC_AGGR2_AM67_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_43_WIDTH },
1396  { SDL_WKUP_ECC_AGGR2_AM67_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_44_CHECKER_TYPE,
1397  SDL_WKUP_ECC_AGGR2_AM67_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_44_WIDTH },
1398  { SDL_WKUP_ECC_AGGR2_AM67_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_45_CHECKER_TYPE,
1399  SDL_WKUP_ECC_AGGR2_AM67_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_45_WIDTH },
1400  { SDL_WKUP_ECC_AGGR2_AM67_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_46_CHECKER_TYPE,
1401  SDL_WKUP_ECC_AGGR2_AM67_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_46_WIDTH },
1402  { SDL_WKUP_ECC_AGGR2_AM67_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_47_CHECKER_TYPE,
1403  SDL_WKUP_ECC_AGGR2_AM67_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_47_WIDTH },
1404  { SDL_WKUP_ECC_AGGR2_AM67_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_48_CHECKER_TYPE,
1405  SDL_WKUP_ECC_AGGR2_AM67_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_48_WIDTH },
1406  { SDL_WKUP_ECC_AGGR2_AM67_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_49_CHECKER_TYPE,
1407  SDL_WKUP_ECC_AGGR2_AM67_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_49_WIDTH },
1408  { SDL_WKUP_ECC_AGGR2_AM67_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_50_CHECKER_TYPE,
1409  SDL_WKUP_ECC_AGGR2_AM67_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_50_WIDTH },
1410  { SDL_WKUP_ECC_AGGR2_AM67_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_51_CHECKER_TYPE,
1411  SDL_WKUP_ECC_AGGR2_AM67_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_51_WIDTH },
1412  { SDL_WKUP_ECC_AGGR2_AM67_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_52_CHECKER_TYPE,
1413  SDL_WKUP_ECC_AGGR2_AM67_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_52_WIDTH },
1414 };
1415 
1421 static const SDL_GrpChkConfig_t SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_groupEntries[SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_MAX_NUM_CHECKERS] =
1422 {
1423  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_0_CHECKER_TYPE,
1424  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_0_WIDTH },
1425  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_1_CHECKER_TYPE,
1426  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_1_WIDTH },
1427  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_2_CHECKER_TYPE,
1428  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_2_WIDTH },
1429  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_3_CHECKER_TYPE,
1430  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_3_WIDTH },
1431  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_4_CHECKER_TYPE,
1432  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_4_WIDTH },
1433  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_5_CHECKER_TYPE,
1434  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_5_WIDTH },
1435  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_6_CHECKER_TYPE,
1436  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_6_WIDTH },
1437  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_7_CHECKER_TYPE,
1438  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_7_WIDTH },
1439  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_8_CHECKER_TYPE,
1440  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_8_WIDTH },
1441  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_9_CHECKER_TYPE,
1442  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_9_WIDTH },
1443  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_10_CHECKER_TYPE,
1444  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_10_WIDTH },
1445  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_11_CHECKER_TYPE,
1446  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_11_WIDTH },
1447  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_12_CHECKER_TYPE,
1448  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_12_WIDTH },
1449  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_13_CHECKER_TYPE,
1450  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_13_WIDTH },
1451  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_14_CHECKER_TYPE,
1452  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_14_WIDTH },
1453  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_15_CHECKER_TYPE,
1454  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_15_WIDTH },
1455  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_16_CHECKER_TYPE,
1456  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_16_WIDTH },
1457  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_17_CHECKER_TYPE,
1458  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_17_WIDTH },
1459  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_18_CHECKER_TYPE,
1460  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_18_WIDTH },
1461  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_19_CHECKER_TYPE,
1462  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_19_WIDTH },
1463  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_20_CHECKER_TYPE,
1464  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_20_WIDTH },
1465  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_21_CHECKER_TYPE,
1466  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_21_WIDTH },
1467  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_22_CHECKER_TYPE,
1468  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_22_WIDTH },
1469  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_23_CHECKER_TYPE,
1470  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_23_WIDTH },
1471  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_24_CHECKER_TYPE,
1472  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_24_WIDTH },
1473  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_25_CHECKER_TYPE,
1474  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_25_WIDTH },
1475  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_26_CHECKER_TYPE,
1476  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_26_WIDTH },
1477  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_27_CHECKER_TYPE,
1478  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_27_WIDTH },
1479  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_28_CHECKER_TYPE,
1480  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_28_WIDTH },
1481  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_29_CHECKER_TYPE,
1482  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_29_WIDTH },
1483  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_30_CHECKER_TYPE,
1484  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_30_WIDTH },
1485  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_31_CHECKER_TYPE,
1486  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_31_WIDTH },
1487  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_32_CHECKER_TYPE,
1488  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_32_WIDTH },
1489  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_33_CHECKER_TYPE,
1490  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_33_WIDTH },
1491  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_34_CHECKER_TYPE,
1492  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_34_WIDTH },
1493  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_35_CHECKER_TYPE,
1494  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_35_WIDTH },
1495  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_36_CHECKER_TYPE,
1496  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_36_WIDTH },
1497  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_37_CHECKER_TYPE,
1498  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_37_WIDTH },
1499  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_38_CHECKER_TYPE,
1500  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_38_WIDTH },
1501  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_39_CHECKER_TYPE,
1502  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_39_WIDTH },
1503  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_40_CHECKER_TYPE,
1504  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_40_WIDTH },
1505  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_41_CHECKER_TYPE,
1506  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_41_WIDTH },
1507  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_42_CHECKER_TYPE,
1508  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_42_WIDTH },
1509  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_43_CHECKER_TYPE,
1510  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_43_WIDTH },
1511  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_44_CHECKER_TYPE,
1512  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_44_WIDTH },
1513  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_45_CHECKER_TYPE,
1514  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_45_WIDTH },
1515  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_46_CHECKER_TYPE,
1516  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_46_WIDTH },
1517  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_47_CHECKER_TYPE,
1518  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_47_WIDTH },
1519  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_48_CHECKER_TYPE,
1520  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_48_WIDTH },
1521  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_49_CHECKER_TYPE,
1522  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_49_WIDTH },
1523  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_50_CHECKER_TYPE,
1524  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_50_WIDTH },
1525  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_51_CHECKER_TYPE,
1526  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_51_WIDTH },
1527  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_52_CHECKER_TYPE,
1528  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_52_WIDTH },
1529  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_53_CHECKER_TYPE,
1530  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_53_WIDTH },
1531  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_54_CHECKER_TYPE,
1532  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_54_WIDTH },
1533  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_55_CHECKER_TYPE,
1534  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_55_WIDTH },
1535  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_56_CHECKER_TYPE,
1536  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_56_WIDTH },
1537  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_57_CHECKER_TYPE,
1538  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_57_WIDTH },
1539  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_58_CHECKER_TYPE,
1540  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_58_WIDTH },
1541  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_59_CHECKER_TYPE,
1542  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_59_WIDTH },
1543  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_60_CHECKER_TYPE,
1544  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_60_WIDTH },
1545  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_61_CHECKER_TYPE,
1546  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_61_WIDTH },
1547  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_62_CHECKER_TYPE,
1548  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_62_WIDTH },
1549  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_63_CHECKER_TYPE,
1550  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_63_WIDTH },
1551  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_64_CHECKER_TYPE,
1552  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_64_WIDTH },
1553  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_65_CHECKER_TYPE,
1554  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_65_WIDTH },
1555  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_66_CHECKER_TYPE,
1556  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_66_WIDTH },
1557  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_67_CHECKER_TYPE,
1558  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_67_WIDTH },
1559  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_68_CHECKER_TYPE,
1560  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_68_WIDTH },
1561  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_69_CHECKER_TYPE,
1562  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_69_WIDTH },
1563  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_70_CHECKER_TYPE,
1564  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_70_WIDTH },
1565  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_71_CHECKER_TYPE,
1566  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_71_WIDTH },
1567  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_72_CHECKER_TYPE,
1568  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_72_WIDTH },
1569  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_73_CHECKER_TYPE,
1570  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_73_WIDTH },
1571  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_74_CHECKER_TYPE,
1572  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_74_WIDTH },
1573  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_75_CHECKER_TYPE,
1574  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_75_WIDTH },
1575  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_76_CHECKER_TYPE,
1576  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_76_WIDTH },
1577  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_77_CHECKER_TYPE,
1578  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_77_WIDTH },
1579  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_78_CHECKER_TYPE,
1580  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_78_WIDTH },
1581  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_79_CHECKER_TYPE,
1582  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_79_WIDTH },
1583  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_80_CHECKER_TYPE,
1584  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_80_WIDTH },
1585  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_81_CHECKER_TYPE,
1586  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_81_WIDTH },
1587  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_82_CHECKER_TYPE,
1588  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_82_WIDTH },
1589  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_83_CHECKER_TYPE,
1590  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_83_WIDTH },
1591  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_84_CHECKER_TYPE,
1592  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_84_WIDTH },
1593  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_85_CHECKER_TYPE,
1594  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_85_WIDTH },
1595  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_86_CHECKER_TYPE,
1596  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_86_WIDTH },
1597  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_87_CHECKER_TYPE,
1598  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_87_WIDTH },
1599  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_88_CHECKER_TYPE,
1600  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_88_WIDTH },
1601  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_89_CHECKER_TYPE,
1602  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_89_WIDTH },
1603  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_90_CHECKER_TYPE,
1604  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_90_WIDTH },
1605  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_91_CHECKER_TYPE,
1606  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_91_WIDTH },
1607  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_92_CHECKER_TYPE,
1608  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_92_WIDTH },
1609  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_93_CHECKER_TYPE,
1610  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_93_WIDTH },
1611  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_94_CHECKER_TYPE,
1612  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_94_WIDTH },
1613  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_95_CHECKER_TYPE,
1614  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_95_WIDTH },
1615  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_96_CHECKER_TYPE,
1616  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_96_WIDTH },
1617  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_97_CHECKER_TYPE,
1618  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_97_WIDTH },
1619  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_98_CHECKER_TYPE,
1620  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_98_WIDTH },
1621  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_99_CHECKER_TYPE,
1622  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_99_WIDTH },
1623  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_100_CHECKER_TYPE,
1624  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_100_WIDTH },
1625  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_101_CHECKER_TYPE,
1626  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_101_WIDTH },
1627  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_102_CHECKER_TYPE,
1628  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_102_WIDTH },
1629  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_103_CHECKER_TYPE,
1630  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_103_WIDTH },
1631  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_104_CHECKER_TYPE,
1632  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_104_WIDTH },
1633  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_105_CHECKER_TYPE,
1634  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_105_WIDTH },
1635  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_106_CHECKER_TYPE,
1636  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_106_WIDTH },
1637  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_107_CHECKER_TYPE,
1638  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_107_WIDTH },
1639  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_108_CHECKER_TYPE,
1640  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_108_WIDTH },
1641  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_109_CHECKER_TYPE,
1642  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_109_WIDTH },
1643  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_110_CHECKER_TYPE,
1644  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_110_WIDTH },
1645  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_111_CHECKER_TYPE,
1646  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_111_WIDTH },
1647  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_112_CHECKER_TYPE,
1648  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_112_WIDTH },
1649  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_113_CHECKER_TYPE,
1650  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_113_WIDTH },
1651  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_114_CHECKER_TYPE,
1652  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_114_WIDTH },
1653  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_115_CHECKER_TYPE,
1654  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_115_WIDTH },
1655  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_116_CHECKER_TYPE,
1656  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_116_WIDTH },
1657  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_117_CHECKER_TYPE,
1658  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_117_WIDTH },
1659  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_118_CHECKER_TYPE,
1660  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_118_WIDTH },
1661  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_119_CHECKER_TYPE,
1662  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_119_WIDTH },
1663  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_120_CHECKER_TYPE,
1664  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_120_WIDTH },
1665  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_121_CHECKER_TYPE,
1666  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_121_WIDTH },
1667  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_122_CHECKER_TYPE,
1668  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_122_WIDTH },
1669  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_123_CHECKER_TYPE,
1670  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_123_WIDTH },
1671  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_124_CHECKER_TYPE,
1672  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_124_WIDTH },
1673  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_125_CHECKER_TYPE,
1674  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_125_WIDTH },
1675  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_126_CHECKER_TYPE,
1676  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_126_WIDTH },
1677  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_127_CHECKER_TYPE,
1678  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_127_WIDTH },
1679  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_128_CHECKER_TYPE,
1680  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_128_WIDTH },
1681  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_129_CHECKER_TYPE,
1682  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_129_WIDTH },
1683  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_130_CHECKER_TYPE,
1684  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_130_WIDTH },
1685  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_131_CHECKER_TYPE,
1686  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_131_WIDTH },
1687  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_132_CHECKER_TYPE,
1688  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_132_WIDTH },
1689  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_133_CHECKER_TYPE,
1690  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_133_WIDTH },
1691  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_134_CHECKER_TYPE,
1692  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_134_WIDTH },
1693  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_135_CHECKER_TYPE,
1694  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_135_WIDTH },
1695  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_136_CHECKER_TYPE,
1696  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_136_WIDTH },
1697  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_137_CHECKER_TYPE,
1698  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_137_WIDTH },
1699  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_138_CHECKER_TYPE,
1700  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_138_WIDTH },
1701  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_139_CHECKER_TYPE,
1702  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_139_WIDTH },
1703  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_140_CHECKER_TYPE,
1704  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_140_WIDTH },
1705  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_141_CHECKER_TYPE,
1706  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_141_WIDTH },
1707  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_142_CHECKER_TYPE,
1708  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_142_WIDTH },
1709  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_143_CHECKER_TYPE,
1710  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_143_WIDTH },
1711  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_144_CHECKER_TYPE,
1712  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_144_WIDTH },
1713  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_145_CHECKER_TYPE,
1714  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_145_WIDTH },
1715  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_146_CHECKER_TYPE,
1716  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_146_WIDTH },
1717  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_147_CHECKER_TYPE,
1718  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_147_WIDTH },
1719  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_148_CHECKER_TYPE,
1720  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_148_WIDTH },
1721  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_149_CHECKER_TYPE,
1722  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_149_WIDTH },
1723  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_150_CHECKER_TYPE,
1724  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_150_WIDTH },
1725  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_151_CHECKER_TYPE,
1726  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_151_WIDTH },
1727  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_152_CHECKER_TYPE,
1728  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_152_WIDTH },
1729  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_153_CHECKER_TYPE,
1730  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_153_WIDTH },
1731  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_154_CHECKER_TYPE,
1732  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_154_WIDTH },
1733  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_155_CHECKER_TYPE,
1734  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_155_WIDTH },
1735  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_156_CHECKER_TYPE,
1736  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_156_WIDTH },
1737  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_157_CHECKER_TYPE,
1738  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_157_WIDTH },
1739  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_158_CHECKER_TYPE,
1740  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_158_WIDTH },
1741  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_159_CHECKER_TYPE,
1742  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_159_WIDTH },
1743  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_160_CHECKER_TYPE,
1744  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_160_WIDTH },
1745  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_161_CHECKER_TYPE,
1746  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_161_WIDTH },
1747  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_162_CHECKER_TYPE,
1748  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_162_WIDTH },
1749  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_163_CHECKER_TYPE,
1750  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_163_WIDTH },
1751  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_164_CHECKER_TYPE,
1752  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_164_WIDTH },
1753  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_165_CHECKER_TYPE,
1754  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_165_WIDTH },
1755  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_166_CHECKER_TYPE,
1756  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_166_WIDTH },
1757  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_167_CHECKER_TYPE,
1758  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_167_WIDTH },
1759  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_168_CHECKER_TYPE,
1760  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_168_WIDTH },
1761  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_169_CHECKER_TYPE,
1762  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_169_WIDTH },
1763  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_170_CHECKER_TYPE,
1764  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_170_WIDTH },
1765  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_171_CHECKER_TYPE,
1766  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_171_WIDTH },
1767  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_172_CHECKER_TYPE,
1768  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_172_WIDTH },
1769  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_173_CHECKER_TYPE,
1770  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_173_WIDTH },
1771  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_174_CHECKER_TYPE,
1772  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_174_WIDTH },
1773  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_175_CHECKER_TYPE,
1774  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_175_WIDTH },
1775  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_176_CHECKER_TYPE,
1776  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_176_WIDTH },
1777  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_177_CHECKER_TYPE,
1778  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_177_WIDTH },
1779  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_178_CHECKER_TYPE,
1780  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_178_WIDTH },
1781  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_179_CHECKER_TYPE,
1782  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_179_WIDTH },
1783  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_180_CHECKER_TYPE,
1784  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_180_WIDTH },
1785  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_181_CHECKER_TYPE,
1786  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_181_WIDTH },
1787  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_182_CHECKER_TYPE,
1788  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_182_WIDTH },
1789  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_183_CHECKER_TYPE,
1790  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_183_WIDTH },
1791  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_184_CHECKER_TYPE,
1792  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_184_WIDTH },
1793  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_185_CHECKER_TYPE,
1794  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_185_WIDTH },
1795  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_186_CHECKER_TYPE,
1796  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_186_WIDTH },
1797  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_187_CHECKER_TYPE,
1798  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_187_WIDTH },
1799  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_188_CHECKER_TYPE,
1800  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_188_WIDTH },
1801  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_189_CHECKER_TYPE,
1802  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_189_WIDTH },
1803  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_190_CHECKER_TYPE,
1804  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_190_WIDTH },
1805  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_191_CHECKER_TYPE,
1806  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_191_WIDTH },
1807  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_192_CHECKER_TYPE,
1808  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_192_WIDTH },
1809  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_193_CHECKER_TYPE,
1810  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_193_WIDTH },
1811  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_194_CHECKER_TYPE,
1812  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_194_WIDTH },
1813  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_195_CHECKER_TYPE,
1814  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_195_WIDTH },
1815  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_196_CHECKER_TYPE,
1816  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_196_WIDTH },
1817  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_197_CHECKER_TYPE,
1818  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_197_WIDTH },
1819  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_198_CHECKER_TYPE,
1820  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_198_WIDTH },
1821  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_199_CHECKER_TYPE,
1822  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_199_WIDTH },
1823  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_200_CHECKER_TYPE,
1824  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_200_WIDTH },
1825  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_201_CHECKER_TYPE,
1826  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_201_WIDTH },
1827  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_202_CHECKER_TYPE,
1828  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_202_WIDTH },
1829  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_203_CHECKER_TYPE,
1830  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_203_WIDTH },
1831  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_204_CHECKER_TYPE,
1832  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_204_WIDTH },
1833  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_205_CHECKER_TYPE,
1834  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_205_WIDTH },
1835  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_206_CHECKER_TYPE,
1836  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_206_WIDTH },
1837  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_207_CHECKER_TYPE,
1838  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_207_WIDTH },
1839  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_208_CHECKER_TYPE,
1840  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_208_WIDTH },
1841  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_209_CHECKER_TYPE,
1842  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_209_WIDTH },
1843  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_210_CHECKER_TYPE,
1844  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_210_WIDTH },
1845  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_211_CHECKER_TYPE,
1846  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_211_WIDTH },
1847  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_212_CHECKER_TYPE,
1848  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_212_WIDTH },
1849  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_213_CHECKER_TYPE,
1850  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_213_WIDTH },
1851  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_214_CHECKER_TYPE,
1852  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_214_WIDTH },
1853  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_215_CHECKER_TYPE,
1854  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_215_WIDTH },
1855  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_216_CHECKER_TYPE,
1856  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_216_WIDTH },
1857  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_217_CHECKER_TYPE,
1858  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_217_WIDTH },
1859  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_218_CHECKER_TYPE,
1860  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_218_WIDTH },
1861  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_219_CHECKER_TYPE,
1862  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_219_WIDTH },
1863  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_220_CHECKER_TYPE,
1864  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_220_WIDTH },
1865  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_221_CHECKER_TYPE,
1866  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_221_WIDTH },
1867  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_222_CHECKER_TYPE,
1868  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_222_WIDTH },
1869  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_223_CHECKER_TYPE,
1870  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_223_WIDTH },
1871  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_224_CHECKER_TYPE,
1872  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_224_WIDTH },
1873  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_225_CHECKER_TYPE,
1874  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_225_WIDTH },
1875  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_226_CHECKER_TYPE,
1876  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_226_WIDTH },
1877  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_227_CHECKER_TYPE,
1878  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_227_WIDTH },
1879  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_228_CHECKER_TYPE,
1880  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_228_WIDTH },
1881  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_229_CHECKER_TYPE,
1882  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_229_WIDTH },
1883  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_230_CHECKER_TYPE,
1884  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_230_WIDTH },
1885  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_231_CHECKER_TYPE,
1886  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_231_WIDTH },
1887  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_232_CHECKER_TYPE,
1888  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_232_WIDTH },
1889  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_233_CHECKER_TYPE,
1890  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_233_WIDTH },
1891  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_234_CHECKER_TYPE,
1892  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_234_WIDTH },
1893  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_235_CHECKER_TYPE,
1894  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_235_WIDTH },
1895  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_236_CHECKER_TYPE,
1896  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_236_WIDTH },
1897  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_237_CHECKER_TYPE,
1898  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_237_WIDTH },
1899  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_238_CHECKER_TYPE,
1900  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_238_WIDTH },
1901  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_239_CHECKER_TYPE,
1902  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_239_WIDTH },
1903  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_240_CHECKER_TYPE,
1904  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_240_WIDTH },
1905  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_241_CHECKER_TYPE,
1906  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_241_WIDTH },
1907  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_242_CHECKER_TYPE,
1908  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_242_WIDTH },
1909  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_243_CHECKER_TYPE,
1910  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_243_WIDTH },
1911  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_244_CHECKER_TYPE,
1912  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_244_WIDTH },
1913  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_245_CHECKER_TYPE,
1914  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_245_WIDTH },
1915  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_246_CHECKER_TYPE,
1916  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_246_WIDTH },
1917  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_247_CHECKER_TYPE,
1918  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_247_WIDTH },
1919  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_248_CHECKER_TYPE,
1920  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_248_WIDTH },
1921  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_249_CHECKER_TYPE,
1922  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_249_WIDTH },
1923  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_250_CHECKER_TYPE,
1924  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_250_WIDTH },
1925  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_251_CHECKER_TYPE,
1926  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_251_WIDTH },
1927  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_252_CHECKER_TYPE,
1928  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_252_WIDTH },
1929  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_253_CHECKER_TYPE,
1930  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_253_WIDTH },
1931  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_254_CHECKER_TYPE,
1932  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_254_WIDTH },
1933  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_255_CHECKER_TYPE,
1934  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_255_WIDTH },
1935 };
1936 
1942 static const SDL_GrpChkConfig_t SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_groupEntries[SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_MAX_NUM_CHECKERS] =
1943 {
1944  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_0_CHECKER_TYPE,
1945  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_0_WIDTH },
1946  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_1_CHECKER_TYPE,
1947  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_1_WIDTH },
1948  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_2_CHECKER_TYPE,
1949  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_2_WIDTH },
1950  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_3_CHECKER_TYPE,
1951  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_3_WIDTH },
1952  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_4_CHECKER_TYPE,
1953  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_4_WIDTH },
1954  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_5_CHECKER_TYPE,
1955  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_5_WIDTH },
1956  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_6_CHECKER_TYPE,
1957  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_6_WIDTH },
1958  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_7_CHECKER_TYPE,
1959  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_7_WIDTH },
1960  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_8_CHECKER_TYPE,
1961  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_8_WIDTH },
1962  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_9_CHECKER_TYPE,
1963  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_9_WIDTH },
1964  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_10_CHECKER_TYPE,
1965  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_10_WIDTH },
1966  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_11_CHECKER_TYPE,
1967  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_11_WIDTH },
1968  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_12_CHECKER_TYPE,
1969  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_12_WIDTH },
1970  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_13_CHECKER_TYPE,
1971  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_13_WIDTH },
1972  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_14_CHECKER_TYPE,
1973  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_14_WIDTH },
1974  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_15_CHECKER_TYPE,
1975  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_15_WIDTH },
1976  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_16_CHECKER_TYPE,
1977  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_16_WIDTH },
1978  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_17_CHECKER_TYPE,
1979  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_17_WIDTH },
1980  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_18_CHECKER_TYPE,
1981  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_18_WIDTH },
1982  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_19_CHECKER_TYPE,
1983  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_19_WIDTH },
1984  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_20_CHECKER_TYPE,
1985  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_20_WIDTH },
1986  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_21_CHECKER_TYPE,
1987  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_21_WIDTH },
1988  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_22_CHECKER_TYPE,
1989  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_22_WIDTH },
1990  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_23_CHECKER_TYPE,
1991  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_23_WIDTH },
1992  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_24_CHECKER_TYPE,
1993  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_24_WIDTH },
1994  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_25_CHECKER_TYPE,
1995  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_25_WIDTH },
1996  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_26_CHECKER_TYPE,
1997  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_26_WIDTH },
1998  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_27_CHECKER_TYPE,
1999  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_27_WIDTH },
2000  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_28_CHECKER_TYPE,
2001  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_28_WIDTH },
2002  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_29_CHECKER_TYPE,
2003  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_29_WIDTH },
2004  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_30_CHECKER_TYPE,
2005  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_30_WIDTH },
2006  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_31_CHECKER_TYPE,
2007  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_31_WIDTH },
2008  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_32_CHECKER_TYPE,
2009  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_32_WIDTH },
2010  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_33_CHECKER_TYPE,
2011  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_33_WIDTH },
2012  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_34_CHECKER_TYPE,
2013  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_34_WIDTH },
2014  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_35_CHECKER_TYPE,
2015  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_35_WIDTH },
2016  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_36_CHECKER_TYPE,
2017  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_36_WIDTH },
2018  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_37_CHECKER_TYPE,
2019  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_37_WIDTH },
2020  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_38_CHECKER_TYPE,
2021  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_38_WIDTH },
2022  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_39_CHECKER_TYPE,
2023  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_39_WIDTH },
2024  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_40_CHECKER_TYPE,
2025  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_40_WIDTH },
2026  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_41_CHECKER_TYPE,
2027  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_41_WIDTH },
2028  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_42_CHECKER_TYPE,
2029  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_42_WIDTH },
2030  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_43_CHECKER_TYPE,
2031  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_43_WIDTH },
2032  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_44_CHECKER_TYPE,
2033  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_44_WIDTH },
2034  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_45_CHECKER_TYPE,
2035  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_45_WIDTH },
2036  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_46_CHECKER_TYPE,
2037  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_46_WIDTH },
2038  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_47_CHECKER_TYPE,
2039  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_47_WIDTH },
2040  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_48_CHECKER_TYPE,
2041  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_48_WIDTH },
2042  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_49_CHECKER_TYPE,
2043  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_49_WIDTH },
2044  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_50_CHECKER_TYPE,
2045  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_50_WIDTH },
2046  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_51_CHECKER_TYPE,
2047  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_51_WIDTH },
2048  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_52_CHECKER_TYPE,
2049  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_52_WIDTH },
2050  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_53_CHECKER_TYPE,
2051  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_53_WIDTH },
2052  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_54_CHECKER_TYPE,
2053  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_54_WIDTH },
2054  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_55_CHECKER_TYPE,
2055  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_55_WIDTH },
2056  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_56_CHECKER_TYPE,
2057  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_56_WIDTH },
2058  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_57_CHECKER_TYPE,
2059  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_57_WIDTH },
2060  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_58_CHECKER_TYPE,
2061  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_58_WIDTH },
2062  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_59_CHECKER_TYPE,
2063  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_59_WIDTH },
2064  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_60_CHECKER_TYPE,
2065  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_60_WIDTH },
2066  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_61_CHECKER_TYPE,
2067  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_61_WIDTH },
2068  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_62_CHECKER_TYPE,
2069  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_62_WIDTH },
2070  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_63_CHECKER_TYPE,
2071  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_63_WIDTH },
2072  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_64_CHECKER_TYPE,
2073  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_64_WIDTH },
2074  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_65_CHECKER_TYPE,
2075  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_65_WIDTH },
2076  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_66_CHECKER_TYPE,
2077  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_66_WIDTH },
2078  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_67_CHECKER_TYPE,
2079  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_67_WIDTH },
2080  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_68_CHECKER_TYPE,
2081  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_68_WIDTH },
2082  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_69_CHECKER_TYPE,
2083  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_69_WIDTH },
2084  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_70_CHECKER_TYPE,
2085  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_70_WIDTH },
2086  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_71_CHECKER_TYPE,
2087  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_71_WIDTH },
2088  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_72_CHECKER_TYPE,
2089  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_72_WIDTH },
2090  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_73_CHECKER_TYPE,
2091  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_73_WIDTH },
2092  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_74_CHECKER_TYPE,
2093  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_74_WIDTH },
2094  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_75_CHECKER_TYPE,
2095  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_75_WIDTH },
2096  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_76_CHECKER_TYPE,
2097  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_76_WIDTH },
2098  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_77_CHECKER_TYPE,
2099  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_77_WIDTH },
2100  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_78_CHECKER_TYPE,
2101  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_78_WIDTH },
2102  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_79_CHECKER_TYPE,
2103  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_79_WIDTH },
2104  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_80_CHECKER_TYPE,
2105  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_80_WIDTH },
2106  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_81_CHECKER_TYPE,
2107  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_81_WIDTH },
2108  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_82_CHECKER_TYPE,
2109  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_82_WIDTH },
2110  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_83_CHECKER_TYPE,
2111  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_83_WIDTH },
2112  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_84_CHECKER_TYPE,
2113  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_84_WIDTH },
2114  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_85_CHECKER_TYPE,
2115  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_85_WIDTH },
2116  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_86_CHECKER_TYPE,
2117  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_86_WIDTH },
2118  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_87_CHECKER_TYPE,
2119  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_87_WIDTH },
2120  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_88_CHECKER_TYPE,
2121  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_88_WIDTH },
2122  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_89_CHECKER_TYPE,
2123  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_89_WIDTH },
2124  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_90_CHECKER_TYPE,
2125  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_90_WIDTH },
2126  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_91_CHECKER_TYPE,
2127  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_91_WIDTH },
2128  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_92_CHECKER_TYPE,
2129  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_92_WIDTH },
2130  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_93_CHECKER_TYPE,
2131  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_93_WIDTH },
2132  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_94_CHECKER_TYPE,
2133  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_94_WIDTH },
2134  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_95_CHECKER_TYPE,
2135  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_95_WIDTH },
2136  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_96_CHECKER_TYPE,
2137  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_96_WIDTH },
2138  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_97_CHECKER_TYPE,
2139  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_97_WIDTH },
2140  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_98_CHECKER_TYPE,
2141  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_98_WIDTH },
2142  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_99_CHECKER_TYPE,
2143  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_99_WIDTH },
2144  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_100_CHECKER_TYPE,
2145  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_100_WIDTH },
2146  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_101_CHECKER_TYPE,
2147  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_101_WIDTH },
2148  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_102_CHECKER_TYPE,
2149  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_102_WIDTH },
2150  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_103_CHECKER_TYPE,
2151  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_103_WIDTH },
2152  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_104_CHECKER_TYPE,
2153  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_104_WIDTH },
2154  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_105_CHECKER_TYPE,
2155  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_105_WIDTH },
2156  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_106_CHECKER_TYPE,
2157  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_106_WIDTH },
2158  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_107_CHECKER_TYPE,
2159  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_107_WIDTH },
2160  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_108_CHECKER_TYPE,
2161  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_108_WIDTH },
2162  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_109_CHECKER_TYPE,
2163  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_109_WIDTH },
2164  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_110_CHECKER_TYPE,
2165  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_110_WIDTH },
2166  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_111_CHECKER_TYPE,
2167  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_111_WIDTH },
2168  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_112_CHECKER_TYPE,
2169  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_112_WIDTH },
2170  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_113_CHECKER_TYPE,
2171  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_113_WIDTH },
2172  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_114_CHECKER_TYPE,
2173  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_114_WIDTH },
2174  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_115_CHECKER_TYPE,
2175  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_115_WIDTH },
2176  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_116_CHECKER_TYPE,
2177  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_116_WIDTH },
2178  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_117_CHECKER_TYPE,
2179  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_117_WIDTH },
2180  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_118_CHECKER_TYPE,
2181  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_118_WIDTH },
2182  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_119_CHECKER_TYPE,
2183  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_119_WIDTH },
2184  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_120_CHECKER_TYPE,
2185  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_120_WIDTH },
2186  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_121_CHECKER_TYPE,
2187  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_121_WIDTH },
2188  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_122_CHECKER_TYPE,
2189  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_122_WIDTH },
2190  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_123_CHECKER_TYPE,
2191  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_123_WIDTH },
2192  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_124_CHECKER_TYPE,
2193  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_124_WIDTH },
2194  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_125_CHECKER_TYPE,
2195  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_125_WIDTH },
2196  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_126_CHECKER_TYPE,
2197  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_126_WIDTH },
2198  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_127_CHECKER_TYPE,
2199  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_127_WIDTH },
2200  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_128_CHECKER_TYPE,
2201  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_128_WIDTH },
2202  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_129_CHECKER_TYPE,
2203  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_129_WIDTH },
2204  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_130_CHECKER_TYPE,
2205  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_130_WIDTH },
2206  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_131_CHECKER_TYPE,
2207  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_131_WIDTH },
2208  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_132_CHECKER_TYPE,
2209  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_132_WIDTH },
2210  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_133_CHECKER_TYPE,
2211  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_133_WIDTH },
2212  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_134_CHECKER_TYPE,
2213  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_134_WIDTH },
2214  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_135_CHECKER_TYPE,
2215  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_135_WIDTH },
2216  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_136_CHECKER_TYPE,
2217  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_136_WIDTH },
2218  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_137_CHECKER_TYPE,
2219  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_137_WIDTH },
2220  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_138_CHECKER_TYPE,
2221  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_138_WIDTH },
2222  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_139_CHECKER_TYPE,
2223  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_139_WIDTH },
2224  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_140_CHECKER_TYPE,
2225  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_140_WIDTH },
2226  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_141_CHECKER_TYPE,
2227  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_141_WIDTH },
2228  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_142_CHECKER_TYPE,
2229  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_142_WIDTH },
2230  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_143_CHECKER_TYPE,
2231  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_143_WIDTH },
2232  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_144_CHECKER_TYPE,
2233  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_144_WIDTH },
2234  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_145_CHECKER_TYPE,
2235  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_145_WIDTH },
2236  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_146_CHECKER_TYPE,
2237  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_146_WIDTH },
2238  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_147_CHECKER_TYPE,
2239  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_147_WIDTH },
2240  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_148_CHECKER_TYPE,
2241  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_148_WIDTH },
2242  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_149_CHECKER_TYPE,
2243  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_149_WIDTH },
2244  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_150_CHECKER_TYPE,
2245  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_150_WIDTH },
2246  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_151_CHECKER_TYPE,
2247  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_151_WIDTH },
2248  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_152_CHECKER_TYPE,
2249  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_152_WIDTH },
2250  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_153_CHECKER_TYPE,
2251  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_153_WIDTH },
2252  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_154_CHECKER_TYPE,
2253  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_154_WIDTH },
2254  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_155_CHECKER_TYPE,
2255  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_155_WIDTH },
2256  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_156_CHECKER_TYPE,
2257  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_156_WIDTH },
2258  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_157_CHECKER_TYPE,
2259  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_157_WIDTH },
2260  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_158_CHECKER_TYPE,
2261  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_158_WIDTH },
2262  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_159_CHECKER_TYPE,
2263  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_159_WIDTH },
2264  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_160_CHECKER_TYPE,
2265  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_160_WIDTH },
2266  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_161_CHECKER_TYPE,
2267  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_161_WIDTH },
2268  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_162_CHECKER_TYPE,
2269  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_162_WIDTH },
2270  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_163_CHECKER_TYPE,
2271  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_163_WIDTH },
2272  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_164_CHECKER_TYPE,
2273  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_164_WIDTH },
2274  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_165_CHECKER_TYPE,
2275  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_165_WIDTH },
2276  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_166_CHECKER_TYPE,
2277  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_166_WIDTH },
2278  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_167_CHECKER_TYPE,
2279  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_167_WIDTH },
2280  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_168_CHECKER_TYPE,
2281  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_168_WIDTH },
2282  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_169_CHECKER_TYPE,
2283  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_169_WIDTH },
2284  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_170_CHECKER_TYPE,
2285  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_170_WIDTH },
2286  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_171_CHECKER_TYPE,
2287  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_171_WIDTH },
2288  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_172_CHECKER_TYPE,
2289  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_172_WIDTH },
2290  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_173_CHECKER_TYPE,
2291  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_173_WIDTH },
2292  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_174_CHECKER_TYPE,
2293  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_174_WIDTH },
2294  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_175_CHECKER_TYPE,
2295  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_175_WIDTH },
2296  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_176_CHECKER_TYPE,
2297  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_176_WIDTH },
2298  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_177_CHECKER_TYPE,
2299  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_177_WIDTH },
2300  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_178_CHECKER_TYPE,
2301  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_178_WIDTH },
2302  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_179_CHECKER_TYPE,
2303  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_179_WIDTH },
2304  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_180_CHECKER_TYPE,
2305  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_180_WIDTH },
2306  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_181_CHECKER_TYPE,
2307  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_181_WIDTH },
2308  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_182_CHECKER_TYPE,
2309  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_182_WIDTH },
2310  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_183_CHECKER_TYPE,
2311  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_183_WIDTH },
2312  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_184_CHECKER_TYPE,
2313  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_184_WIDTH },
2314  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_185_CHECKER_TYPE,
2315  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_185_WIDTH },
2316  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_186_CHECKER_TYPE,
2317  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_186_WIDTH },
2318  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_187_CHECKER_TYPE,
2319  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_187_WIDTH },
2320  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_188_CHECKER_TYPE,
2321  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_188_WIDTH },
2322  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_189_CHECKER_TYPE,
2323  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_189_WIDTH },
2324  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_190_CHECKER_TYPE,
2325  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_190_WIDTH },
2326  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_191_CHECKER_TYPE,
2327  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_191_WIDTH },
2328  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_192_CHECKER_TYPE,
2329  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_192_WIDTH },
2330  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_193_CHECKER_TYPE,
2331  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_193_WIDTH },
2332  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_194_CHECKER_TYPE,
2333  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_194_WIDTH },
2334  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_195_CHECKER_TYPE,
2335  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_195_WIDTH },
2336  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_196_CHECKER_TYPE,
2337  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_196_WIDTH },
2338  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_197_CHECKER_TYPE,
2339  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_197_WIDTH },
2340  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_198_CHECKER_TYPE,
2341  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_198_WIDTH },
2342  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_199_CHECKER_TYPE,
2343  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_199_WIDTH },
2344  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_200_CHECKER_TYPE,
2345  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_200_WIDTH },
2346  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_201_CHECKER_TYPE,
2347  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_201_WIDTH },
2348  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_202_CHECKER_TYPE,
2349  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_202_WIDTH },
2350  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_203_CHECKER_TYPE,
2351  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_203_WIDTH },
2352  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_204_CHECKER_TYPE,
2353  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_204_WIDTH },
2354  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_205_CHECKER_TYPE,
2355  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_205_WIDTH },
2356  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_206_CHECKER_TYPE,
2357  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_206_WIDTH },
2358  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_207_CHECKER_TYPE,
2359  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_207_WIDTH },
2360  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_208_CHECKER_TYPE,
2361  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_208_WIDTH },
2362  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_209_CHECKER_TYPE,
2363  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_209_WIDTH },
2364  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_210_CHECKER_TYPE,
2365  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_210_WIDTH },
2366  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_211_CHECKER_TYPE,
2367  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_211_WIDTH },
2368  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_212_CHECKER_TYPE,
2369  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_212_WIDTH },
2370  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_213_CHECKER_TYPE,
2371  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_213_WIDTH },
2372  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_214_CHECKER_TYPE,
2373  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_214_WIDTH },
2374  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_215_CHECKER_TYPE,
2375  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_215_WIDTH },
2376  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_216_CHECKER_TYPE,
2377  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_216_WIDTH },
2378  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_217_CHECKER_TYPE,
2379  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_217_WIDTH },
2380  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_218_CHECKER_TYPE,
2381  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_218_WIDTH },
2382  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_219_CHECKER_TYPE,
2383  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_219_WIDTH },
2384  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_220_CHECKER_TYPE,
2385  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_220_WIDTH },
2386  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_221_CHECKER_TYPE,
2387  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_221_WIDTH },
2388  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_222_CHECKER_TYPE,
2389  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_222_WIDTH },
2390  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_223_CHECKER_TYPE,
2391  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_223_WIDTH },
2392  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_224_CHECKER_TYPE,
2393  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_224_WIDTH },
2394  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_225_CHECKER_TYPE,
2395  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_225_WIDTH },
2396  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_226_CHECKER_TYPE,
2397  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_226_WIDTH },
2398  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_227_CHECKER_TYPE,
2399  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_227_WIDTH },
2400  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_228_CHECKER_TYPE,
2401  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_228_WIDTH },
2402  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_229_CHECKER_TYPE,
2403  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_229_WIDTH },
2404  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_230_CHECKER_TYPE,
2405  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_230_WIDTH },
2406  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_231_CHECKER_TYPE,
2407  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_231_WIDTH },
2408  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_232_CHECKER_TYPE,
2409  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_232_WIDTH },
2410  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_233_CHECKER_TYPE,
2411  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_233_WIDTH },
2412  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_234_CHECKER_TYPE,
2413  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_234_WIDTH },
2414  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_235_CHECKER_TYPE,
2415  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_235_WIDTH },
2416  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_236_CHECKER_TYPE,
2417  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_236_WIDTH },
2418  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_237_CHECKER_TYPE,
2419  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_237_WIDTH },
2420  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_238_CHECKER_TYPE,
2421  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_238_WIDTH },
2422  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_239_CHECKER_TYPE,
2423  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_239_WIDTH },
2424  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_240_CHECKER_TYPE,
2425  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_240_WIDTH },
2426  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_241_CHECKER_TYPE,
2427  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_241_WIDTH },
2428  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_242_CHECKER_TYPE,
2429  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_242_WIDTH },
2430  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_243_CHECKER_TYPE,
2431  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_243_WIDTH },
2432  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_244_CHECKER_TYPE,
2433  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_244_WIDTH },
2434  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_245_CHECKER_TYPE,
2435  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_245_WIDTH },
2436  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_246_CHECKER_TYPE,
2437  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_246_WIDTH },
2438  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_247_CHECKER_TYPE,
2439  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_247_WIDTH },
2440  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_248_CHECKER_TYPE,
2441  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_248_WIDTH },
2442  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_249_CHECKER_TYPE,
2443  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_249_WIDTH },
2444  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_250_CHECKER_TYPE,
2445  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_250_WIDTH },
2446  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_251_CHECKER_TYPE,
2447  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_251_WIDTH },
2448  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_252_CHECKER_TYPE,
2449  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_252_WIDTH },
2450  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_253_CHECKER_TYPE,
2451  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_253_WIDTH },
2452  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_254_CHECKER_TYPE,
2453  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_254_WIDTH },
2454  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_255_CHECKER_TYPE,
2455  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_255_WIDTH },
2456 };
2457 
2463 static const SDL_GrpChkConfig_t SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_groupEntries[SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_MAX_NUM_CHECKERS] =
2464 {
2465  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_0_CHECKER_TYPE,
2466  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_0_WIDTH },
2467  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_1_CHECKER_TYPE,
2468  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_1_WIDTH },
2469  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_2_CHECKER_TYPE,
2470  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_2_WIDTH },
2471  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_3_CHECKER_TYPE,
2472  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_3_WIDTH },
2473  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_4_CHECKER_TYPE,
2474  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_4_WIDTH },
2475  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_5_CHECKER_TYPE,
2476  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_5_WIDTH },
2477  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_6_CHECKER_TYPE,
2478  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_6_WIDTH },
2479  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_7_CHECKER_TYPE,
2480  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_7_WIDTH },
2481  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_8_CHECKER_TYPE,
2482  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_8_WIDTH },
2483  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_9_CHECKER_TYPE,
2484  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_9_WIDTH },
2485  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_10_CHECKER_TYPE,
2486  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_10_WIDTH },
2487  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_11_CHECKER_TYPE,
2488  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_11_WIDTH },
2489  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_12_CHECKER_TYPE,
2490  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_12_WIDTH },
2491  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_13_CHECKER_TYPE,
2492  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_13_WIDTH },
2493  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_14_CHECKER_TYPE,
2494  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_14_WIDTH },
2495  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_15_CHECKER_TYPE,
2496  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_15_WIDTH },
2497  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_16_CHECKER_TYPE,
2498  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_16_WIDTH },
2499  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_17_CHECKER_TYPE,
2500  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_17_WIDTH },
2501  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_18_CHECKER_TYPE,
2502  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_18_WIDTH },
2503  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_19_CHECKER_TYPE,
2504  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_19_WIDTH },
2505  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_20_CHECKER_TYPE,
2506  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_20_WIDTH },
2507  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_21_CHECKER_TYPE,
2508  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_21_WIDTH },
2509  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_22_CHECKER_TYPE,
2510  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_22_WIDTH },
2511  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_23_CHECKER_TYPE,
2512  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_23_WIDTH },
2513  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_24_CHECKER_TYPE,
2514  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_24_WIDTH },
2515  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_25_CHECKER_TYPE,
2516  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_25_WIDTH },
2517  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_26_CHECKER_TYPE,
2518  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_26_WIDTH },
2519  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_27_CHECKER_TYPE,
2520  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_27_WIDTH },
2521  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_28_CHECKER_TYPE,
2522  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_28_WIDTH },
2523  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_29_CHECKER_TYPE,
2524  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_29_WIDTH },
2525  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_30_CHECKER_TYPE,
2526  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_30_WIDTH },
2527  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_31_CHECKER_TYPE,
2528  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_31_WIDTH },
2529  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_32_CHECKER_TYPE,
2530  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_32_WIDTH },
2531  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_33_CHECKER_TYPE,
2532  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_33_WIDTH },
2533  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_34_CHECKER_TYPE,
2534  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_34_WIDTH },
2535  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_35_CHECKER_TYPE,
2536  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_35_WIDTH },
2537  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_36_CHECKER_TYPE,
2538  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_36_WIDTH },
2539  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_37_CHECKER_TYPE,
2540  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_37_WIDTH },
2541  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_38_CHECKER_TYPE,
2542  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_38_WIDTH },
2543  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_39_CHECKER_TYPE,
2544  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_39_WIDTH },
2545  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_40_CHECKER_TYPE,
2546  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_40_WIDTH },
2547  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_41_CHECKER_TYPE,
2548  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_41_WIDTH },
2549  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_42_CHECKER_TYPE,
2550  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_42_WIDTH },
2551  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_43_CHECKER_TYPE,
2552  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_43_WIDTH },
2553  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_44_CHECKER_TYPE,
2554  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_44_WIDTH },
2555  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_45_CHECKER_TYPE,
2556  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_45_WIDTH },
2557  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_46_CHECKER_TYPE,
2558  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_46_WIDTH },
2559  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_47_CHECKER_TYPE,
2560  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_47_WIDTH },
2561  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_48_CHECKER_TYPE,
2562  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_48_WIDTH },
2563  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_49_CHECKER_TYPE,
2564  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_49_WIDTH },
2565  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_50_CHECKER_TYPE,
2566  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_50_WIDTH },
2567  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_51_CHECKER_TYPE,
2568  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_51_WIDTH },
2569  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_52_CHECKER_TYPE,
2570  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_52_WIDTH },
2571  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_53_CHECKER_TYPE,
2572  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_53_WIDTH },
2573  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_54_CHECKER_TYPE,
2574  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_54_WIDTH },
2575  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_55_CHECKER_TYPE,
2576  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_55_WIDTH },
2577  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_56_CHECKER_TYPE,
2578  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_56_WIDTH },
2579  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_57_CHECKER_TYPE,
2580  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_57_WIDTH },
2581  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_58_CHECKER_TYPE,
2582  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_58_WIDTH },
2583  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_59_CHECKER_TYPE,
2584  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_59_WIDTH },
2585  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_60_CHECKER_TYPE,
2586  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_60_WIDTH },
2587  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_61_CHECKER_TYPE,
2588  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_61_WIDTH },
2589  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_62_CHECKER_TYPE,
2590  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_62_WIDTH },
2591  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_63_CHECKER_TYPE,
2592  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_63_WIDTH },
2593  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_64_CHECKER_TYPE,
2594  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_64_WIDTH },
2595  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_65_CHECKER_TYPE,
2596  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_65_WIDTH },
2597  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_66_CHECKER_TYPE,
2598  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_66_WIDTH },
2599  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_67_CHECKER_TYPE,
2600  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_67_WIDTH },
2601  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_68_CHECKER_TYPE,
2602  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_68_WIDTH },
2603  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_69_CHECKER_TYPE,
2604  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_69_WIDTH },
2605  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_70_CHECKER_TYPE,
2606  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_70_WIDTH },
2607  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_71_CHECKER_TYPE,
2608  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_71_WIDTH },
2609  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_72_CHECKER_TYPE,
2610  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_72_WIDTH },
2611  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_73_CHECKER_TYPE,
2612  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_73_WIDTH },
2613  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_74_CHECKER_TYPE,
2614  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_74_WIDTH },
2615  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_75_CHECKER_TYPE,
2616  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_75_WIDTH },
2617  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_76_CHECKER_TYPE,
2618  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_76_WIDTH },
2619  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_77_CHECKER_TYPE,
2620  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_77_WIDTH },
2621  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_78_CHECKER_TYPE,
2622  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_78_WIDTH },
2623  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_79_CHECKER_TYPE,
2624  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_79_WIDTH },
2625  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_80_CHECKER_TYPE,
2626  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_80_WIDTH },
2627  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_81_CHECKER_TYPE,
2628  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_81_WIDTH },
2629  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_82_CHECKER_TYPE,
2630  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_82_WIDTH },
2631  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_83_CHECKER_TYPE,
2632  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_83_WIDTH },
2633  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_84_CHECKER_TYPE,
2634  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_84_WIDTH },
2635  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_85_CHECKER_TYPE,
2636  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_85_WIDTH },
2637  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_86_CHECKER_TYPE,
2638  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_86_WIDTH },
2639  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_87_CHECKER_TYPE,
2640  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_87_WIDTH },
2641  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_88_CHECKER_TYPE,
2642  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_88_WIDTH },
2643  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_89_CHECKER_TYPE,
2644  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_89_WIDTH },
2645  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_90_CHECKER_TYPE,
2646  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_90_WIDTH },
2647  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_91_CHECKER_TYPE,
2648  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_91_WIDTH },
2649  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_92_CHECKER_TYPE,
2650  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_92_WIDTH },
2651  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_93_CHECKER_TYPE,
2652  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_93_WIDTH },
2653  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_94_CHECKER_TYPE,
2654  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_94_WIDTH },
2655  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_95_CHECKER_TYPE,
2656  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_95_WIDTH },
2657  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_96_CHECKER_TYPE,
2658  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_96_WIDTH },
2659  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_97_CHECKER_TYPE,
2660  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_97_WIDTH },
2661  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_98_CHECKER_TYPE,
2662  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_98_WIDTH },
2663  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_99_CHECKER_TYPE,
2664  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_99_WIDTH },
2665  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_100_CHECKER_TYPE,
2666  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_100_WIDTH },
2667  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_101_CHECKER_TYPE,
2668  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_101_WIDTH },
2669  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_102_CHECKER_TYPE,
2670  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_102_WIDTH },
2671  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_103_CHECKER_TYPE,
2672  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_103_WIDTH },
2673  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_104_CHECKER_TYPE,
2674  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_104_WIDTH },
2675  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_105_CHECKER_TYPE,
2676  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_105_WIDTH },
2677  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_106_CHECKER_TYPE,
2678  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_106_WIDTH },
2679  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_107_CHECKER_TYPE,
2680  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_107_WIDTH },
2681  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_108_CHECKER_TYPE,
2682  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_108_WIDTH },
2683  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_109_CHECKER_TYPE,
2684  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_109_WIDTH },
2685  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_110_CHECKER_TYPE,
2686  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_110_WIDTH },
2687  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_111_CHECKER_TYPE,
2688  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_111_WIDTH },
2689  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_112_CHECKER_TYPE,
2690  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_112_WIDTH },
2691  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_113_CHECKER_TYPE,
2692  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_113_WIDTH },
2693  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_114_CHECKER_TYPE,
2694  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_114_WIDTH },
2695  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_115_CHECKER_TYPE,
2696  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_115_WIDTH },
2697  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_116_CHECKER_TYPE,
2698  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_116_WIDTH },
2699  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_117_CHECKER_TYPE,
2700  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_117_WIDTH },
2701  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_118_CHECKER_TYPE,
2702  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_118_WIDTH },
2703  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_119_CHECKER_TYPE,
2704  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_119_WIDTH },
2705  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_120_CHECKER_TYPE,
2706  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_120_WIDTH },
2707  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_121_CHECKER_TYPE,
2708  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_121_WIDTH },
2709  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_122_CHECKER_TYPE,
2710  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_122_WIDTH },
2711  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_123_CHECKER_TYPE,
2712  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_123_WIDTH },
2713  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_124_CHECKER_TYPE,
2714  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_124_WIDTH },
2715  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_125_CHECKER_TYPE,
2716  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_125_WIDTH },
2717  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_126_CHECKER_TYPE,
2718  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_126_WIDTH },
2719  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_127_CHECKER_TYPE,
2720  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_127_WIDTH },
2721  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_128_CHECKER_TYPE,
2722  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_128_WIDTH },
2723  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_129_CHECKER_TYPE,
2724  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_129_WIDTH },
2725  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_130_CHECKER_TYPE,
2726  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_130_WIDTH },
2727  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_131_CHECKER_TYPE,
2728  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_131_WIDTH },
2729  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_132_CHECKER_TYPE,
2730  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_132_WIDTH },
2731  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_133_CHECKER_TYPE,
2732  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_133_WIDTH },
2733  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_134_CHECKER_TYPE,
2734  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_134_WIDTH },
2735  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_135_CHECKER_TYPE,
2736  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_135_WIDTH },
2737  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_136_CHECKER_TYPE,
2738  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_136_WIDTH },
2739  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_137_CHECKER_TYPE,
2740  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_137_WIDTH },
2741  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_138_CHECKER_TYPE,
2742  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_138_WIDTH },
2743  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_139_CHECKER_TYPE,
2744  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_139_WIDTH },
2745  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_140_CHECKER_TYPE,
2746  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_140_WIDTH },
2747  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_141_CHECKER_TYPE,
2748  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_141_WIDTH },
2749  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_142_CHECKER_TYPE,
2750  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_142_WIDTH },
2751  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_143_CHECKER_TYPE,
2752  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_143_WIDTH },
2753  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_144_CHECKER_TYPE,
2754  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_144_WIDTH },
2755  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_145_CHECKER_TYPE,
2756  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_145_WIDTH },
2757  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_146_CHECKER_TYPE,
2758  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_146_WIDTH },
2759  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_147_CHECKER_TYPE,
2760  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_147_WIDTH },
2761  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_148_CHECKER_TYPE,
2762  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_148_WIDTH },
2763  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_149_CHECKER_TYPE,
2764  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_149_WIDTH },
2765  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_150_CHECKER_TYPE,
2766  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_150_WIDTH },
2767  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_151_CHECKER_TYPE,
2768  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_151_WIDTH },
2769  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_152_CHECKER_TYPE,
2770  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_152_WIDTH },
2771  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_153_CHECKER_TYPE,
2772  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_153_WIDTH },
2773  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_154_CHECKER_TYPE,
2774  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_154_WIDTH },
2775  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_155_CHECKER_TYPE,
2776  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_155_WIDTH },
2777  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_156_CHECKER_TYPE,
2778  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_156_WIDTH },
2779  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_157_CHECKER_TYPE,
2780  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_157_WIDTH },
2781  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_158_CHECKER_TYPE,
2782  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_158_WIDTH },
2783  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_159_CHECKER_TYPE,
2784  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_159_WIDTH },
2785  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_160_CHECKER_TYPE,
2786  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_160_WIDTH },
2787  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_161_CHECKER_TYPE,
2788  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_161_WIDTH },
2789  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_162_CHECKER_TYPE,
2790  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_162_WIDTH },
2791  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_163_CHECKER_TYPE,
2792  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_163_WIDTH },
2793  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_164_CHECKER_TYPE,
2794  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_164_WIDTH },
2795  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_165_CHECKER_TYPE,
2796  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_165_WIDTH },
2797  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_166_CHECKER_TYPE,
2798  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_166_WIDTH },
2799  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_167_CHECKER_TYPE,
2800  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_167_WIDTH },
2801  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_168_CHECKER_TYPE,
2802  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_168_WIDTH },
2803  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_169_CHECKER_TYPE,
2804  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_169_WIDTH },
2805  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_170_CHECKER_TYPE,
2806  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_170_WIDTH },
2807  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_171_CHECKER_TYPE,
2808  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_171_WIDTH },
2809 };
2810 
2816 static const SDL_GrpChkConfig_t SDL_WKUP_ECC_AGGR2_ISAM67_DM2WS_VBUSM_GASKET_MCU_0_EDC_CTRL_groupEntries[SDL_WKUP_ECC_AGGR2_ISAM67_DM2WS_VBUSM_GASKET_MCU_0_EDC_CTRL_MAX_NUM_CHECKERS] =
2817 {
2818  { SDL_WKUP_ECC_AGGR2_ISAM67_DM2WS_VBUSM_GASKET_MCU_0_EDC_CTRL_GROUP_0_CHECKER_TYPE,
2819  SDL_WKUP_ECC_AGGR2_ISAM67_DM2WS_VBUSM_GASKET_MCU_0_EDC_CTRL_GROUP_0_WIDTH },
2820 };
2821 
2827 static const SDL_GrpChkConfig_t SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_groupEntries[SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_MAX_NUM_CHECKERS] =
2828 {
2829  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_0_CHECKER_TYPE,
2830  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_0_WIDTH },
2831  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_1_CHECKER_TYPE,
2832  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_1_WIDTH },
2833  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_2_CHECKER_TYPE,
2834  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_2_WIDTH },
2835  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_3_CHECKER_TYPE,
2836  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_3_WIDTH },
2837  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_4_CHECKER_TYPE,
2838  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_4_WIDTH },
2839  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_5_CHECKER_TYPE,
2840  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_5_WIDTH },
2841  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_6_CHECKER_TYPE,
2842  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_6_WIDTH },
2843  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_7_CHECKER_TYPE,
2844  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_7_WIDTH },
2845  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_8_CHECKER_TYPE,
2846  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_8_WIDTH },
2847  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_9_CHECKER_TYPE,
2848  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_9_WIDTH },
2849  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_10_CHECKER_TYPE,
2850  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_10_WIDTH },
2851  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_11_CHECKER_TYPE,
2852  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_11_WIDTH },
2853  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_12_CHECKER_TYPE,
2854  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_12_WIDTH },
2855  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_13_CHECKER_TYPE,
2856  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_13_WIDTH },
2857  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_14_CHECKER_TYPE,
2858  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_14_WIDTH },
2859  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_15_CHECKER_TYPE,
2860  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_15_WIDTH },
2861  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_16_CHECKER_TYPE,
2862  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_16_WIDTH },
2863  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_17_CHECKER_TYPE,
2864  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_17_WIDTH },
2865  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_18_CHECKER_TYPE,
2866  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_18_WIDTH },
2867  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_19_CHECKER_TYPE,
2868  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_19_WIDTH },
2869  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_20_CHECKER_TYPE,
2870  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_20_WIDTH },
2871  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_21_CHECKER_TYPE,
2872  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_21_WIDTH },
2873  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_22_CHECKER_TYPE,
2874  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_22_WIDTH },
2875  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_23_CHECKER_TYPE,
2876  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_23_WIDTH },
2877  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_24_CHECKER_TYPE,
2878  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_24_WIDTH },
2879  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_25_CHECKER_TYPE,
2880  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_25_WIDTH },
2881  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_26_CHECKER_TYPE,
2882  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_26_WIDTH },
2883  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_27_CHECKER_TYPE,
2884  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_27_WIDTH },
2885  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_28_CHECKER_TYPE,
2886  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_28_WIDTH },
2887  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_29_CHECKER_TYPE,
2888  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_29_WIDTH },
2889  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_30_CHECKER_TYPE,
2890  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_30_WIDTH },
2891 };
2892 
2898 static const SDL_GrpChkConfig_t SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ISAM67_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM67_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_BRIDGE_BUSECC_groupEntries[SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ISAM67_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM67_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_BRIDGE_BUSECC_MAX_NUM_CHECKERS] =
2899 {
2900  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ISAM67_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM67_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_BRIDGE_BUSECC_GROUP_0_CHECKER_TYPE,
2901  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ISAM67_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM67_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_BRIDGE_BUSECC_GROUP_0_WIDTH },
2902  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ISAM67_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM67_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_BRIDGE_BUSECC_GROUP_1_CHECKER_TYPE,
2903  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ISAM67_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM67_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_BRIDGE_BUSECC_GROUP_1_WIDTH },
2904  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ISAM67_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM67_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_BRIDGE_BUSECC_GROUP_2_CHECKER_TYPE,
2905  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ISAM67_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM67_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_BRIDGE_BUSECC_GROUP_2_WIDTH },
2906  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ISAM67_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM67_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_BRIDGE_BUSECC_GROUP_3_CHECKER_TYPE,
2907  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ISAM67_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM67_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_BRIDGE_BUSECC_GROUP_3_WIDTH },
2908  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ISAM67_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM67_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_BRIDGE_BUSECC_GROUP_4_CHECKER_TYPE,
2909  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ISAM67_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM67_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_BRIDGE_BUSECC_GROUP_4_WIDTH },
2910  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ISAM67_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM67_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_BRIDGE_BUSECC_GROUP_5_CHECKER_TYPE,
2911  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ISAM67_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM67_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_BRIDGE_BUSECC_GROUP_5_WIDTH },
2912  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ISAM67_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM67_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_BRIDGE_BUSECC_GROUP_6_CHECKER_TYPE,
2913  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ISAM67_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM67_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_BRIDGE_BUSECC_GROUP_6_WIDTH },
2914  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ISAM67_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM67_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_BRIDGE_BUSECC_GROUP_7_CHECKER_TYPE,
2915  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ISAM67_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM67_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_BRIDGE_BUSECC_GROUP_7_WIDTH },
2916  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ISAM67_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM67_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_BRIDGE_BUSECC_GROUP_8_CHECKER_TYPE,
2917  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ISAM67_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM67_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_BRIDGE_BUSECC_GROUP_8_WIDTH },
2918  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ISAM67_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM67_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_BRIDGE_BUSECC_GROUP_9_CHECKER_TYPE,
2919  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ISAM67_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM67_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_BRIDGE_BUSECC_GROUP_9_WIDTH },
2920  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ISAM67_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM67_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_BRIDGE_BUSECC_GROUP_10_CHECKER_TYPE,
2921  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ISAM67_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM67_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_BRIDGE_BUSECC_GROUP_10_WIDTH },
2922  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ISAM67_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM67_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_BRIDGE_BUSECC_GROUP_11_CHECKER_TYPE,
2923  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ISAM67_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM67_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_BRIDGE_BUSECC_GROUP_11_WIDTH },
2924  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ISAM67_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM67_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_BRIDGE_BUSECC_GROUP_12_CHECKER_TYPE,
2925  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ISAM67_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM67_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_BRIDGE_BUSECC_GROUP_12_WIDTH },
2926 };
2927 
2933 static const SDL_GrpChkConfig_t SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_IAM67_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM67_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_BRIDGE_BUSECC_groupEntries[SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_IAM67_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM67_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_BRIDGE_BUSECC_MAX_NUM_CHECKERS] =
2934 {
2935  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_IAM67_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM67_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_BRIDGE_BUSECC_GROUP_0_CHECKER_TYPE,
2936  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_IAM67_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM67_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_BRIDGE_BUSECC_GROUP_0_WIDTH },
2937  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_IAM67_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM67_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_BRIDGE_BUSECC_GROUP_1_CHECKER_TYPE,
2938  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_IAM67_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM67_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_BRIDGE_BUSECC_GROUP_1_WIDTH },
2939  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_IAM67_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM67_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_BRIDGE_BUSECC_GROUP_2_CHECKER_TYPE,
2940  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_IAM67_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM67_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_BRIDGE_BUSECC_GROUP_2_WIDTH },
2941  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_IAM67_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM67_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_BRIDGE_BUSECC_GROUP_3_CHECKER_TYPE,
2942  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_IAM67_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM67_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_BRIDGE_BUSECC_GROUP_3_WIDTH },
2943  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_IAM67_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM67_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_BRIDGE_BUSECC_GROUP_4_CHECKER_TYPE,
2944  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_IAM67_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM67_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_BRIDGE_BUSECC_GROUP_4_WIDTH },
2945  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_IAM67_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM67_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_BRIDGE_BUSECC_GROUP_5_CHECKER_TYPE,
2946  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_IAM67_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM67_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_BRIDGE_BUSECC_GROUP_5_WIDTH },
2947  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_IAM67_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM67_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_BRIDGE_BUSECC_GROUP_6_CHECKER_TYPE,
2948  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_IAM67_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM67_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_BRIDGE_BUSECC_GROUP_6_WIDTH },
2949  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_IAM67_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM67_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_BRIDGE_BUSECC_GROUP_7_CHECKER_TYPE,
2950  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_IAM67_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM67_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_BRIDGE_BUSECC_GROUP_7_WIDTH },
2951  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_IAM67_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM67_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_BRIDGE_BUSECC_GROUP_8_CHECKER_TYPE,
2952  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_IAM67_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM67_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_BRIDGE_BUSECC_GROUP_8_WIDTH },
2953  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_IAM67_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM67_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_BRIDGE_BUSECC_GROUP_9_CHECKER_TYPE,
2954  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_IAM67_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM67_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_BRIDGE_BUSECC_GROUP_9_WIDTH },
2955  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_IAM67_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM67_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_BRIDGE_BUSECC_GROUP_10_CHECKER_TYPE,
2956  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_IAM67_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM67_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_BRIDGE_BUSECC_GROUP_10_WIDTH },
2957  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_IAM67_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM67_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_BRIDGE_BUSECC_GROUP_11_CHECKER_TYPE,
2958  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_IAM67_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM67_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_BRIDGE_BUSECC_GROUP_11_WIDTH },
2959  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_IAM67_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM67_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_BRIDGE_BUSECC_GROUP_12_CHECKER_TYPE,
2960  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_IAM67_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM67_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_BRIDGE_BUSECC_GROUP_12_WIDTH },
2961 };
2962 
2968 static const SDL_GrpChkConfig_t SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_groupEntries[SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_MAX_NUM_CHECKERS] =
2969 {
2970  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_0_CHECKER_TYPE,
2971  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_0_WIDTH },
2972  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_1_CHECKER_TYPE,
2973  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_1_WIDTH },
2974  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_2_CHECKER_TYPE,
2975  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_2_WIDTH },
2976  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_3_CHECKER_TYPE,
2977  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_3_WIDTH },
2978  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_4_CHECKER_TYPE,
2979  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_4_WIDTH },
2980  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_5_CHECKER_TYPE,
2981  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_5_WIDTH },
2982  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_6_CHECKER_TYPE,
2983  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_6_WIDTH },
2984  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_7_CHECKER_TYPE,
2985  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_7_WIDTH },
2986  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_8_CHECKER_TYPE,
2987  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_8_WIDTH },
2988  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_9_CHECKER_TYPE,
2989  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_9_WIDTH },
2990  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_10_CHECKER_TYPE,
2991  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_10_WIDTH },
2992  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_11_CHECKER_TYPE,
2993  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_11_WIDTH },
2994  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_12_CHECKER_TYPE,
2995  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_12_WIDTH },
2996  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_13_CHECKER_TYPE,
2997  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_13_WIDTH },
2998  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_14_CHECKER_TYPE,
2999  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_14_WIDTH },
3000  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_15_CHECKER_TYPE,
3001  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_15_WIDTH },
3002  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_16_CHECKER_TYPE,
3003  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_16_WIDTH },
3004  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_17_CHECKER_TYPE,
3005  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_17_WIDTH },
3006  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_18_CHECKER_TYPE,
3007  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_18_WIDTH },
3008  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_19_CHECKER_TYPE,
3009  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_19_WIDTH },
3010  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_20_CHECKER_TYPE,
3011  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_20_WIDTH },
3012  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_21_CHECKER_TYPE,
3013  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_21_WIDTH },
3014  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_22_CHECKER_TYPE,
3015  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_22_WIDTH },
3016  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_23_CHECKER_TYPE,
3017  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_23_WIDTH },
3018  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_24_CHECKER_TYPE,
3019  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_24_WIDTH },
3020  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_25_CHECKER_TYPE,
3021  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_25_WIDTH },
3022  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_26_CHECKER_TYPE,
3023  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_26_WIDTH },
3024  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_27_CHECKER_TYPE,
3025  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_27_WIDTH },
3026  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_28_CHECKER_TYPE,
3027  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_28_WIDTH },
3028  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_29_CHECKER_TYPE,
3029  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_29_WIDTH },
3030  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_30_CHECKER_TYPE,
3031  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_30_WIDTH },
3032  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_31_CHECKER_TYPE,
3033  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_31_WIDTH },
3034  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_32_CHECKER_TYPE,
3035  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_32_WIDTH },
3036  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_33_CHECKER_TYPE,
3037  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_33_WIDTH },
3038  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_34_CHECKER_TYPE,
3039  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_34_WIDTH },
3040  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_35_CHECKER_TYPE,
3041  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_35_WIDTH },
3042  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_36_CHECKER_TYPE,
3043  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_36_WIDTH },
3044  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_37_CHECKER_TYPE,
3045  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_37_WIDTH },
3046  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_38_CHECKER_TYPE,
3047  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_38_WIDTH },
3048  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_39_CHECKER_TYPE,
3049  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_39_WIDTH },
3050  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_40_CHECKER_TYPE,
3051  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_40_WIDTH },
3052  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_41_CHECKER_TYPE,
3053  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_41_WIDTH },
3054  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_42_CHECKER_TYPE,
3055  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_42_WIDTH },
3056  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_43_CHECKER_TYPE,
3057  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_43_WIDTH },
3058  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_44_CHECKER_TYPE,
3059  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_44_WIDTH },
3060  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_45_CHECKER_TYPE,
3061  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_45_WIDTH },
3062  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_46_CHECKER_TYPE,
3063  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_46_WIDTH },
3064  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_47_CHECKER_TYPE,
3065  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_47_WIDTH },
3066  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_48_CHECKER_TYPE,
3067  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_48_WIDTH },
3068  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_49_CHECKER_TYPE,
3069  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_49_WIDTH },
3070  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_50_CHECKER_TYPE,
3071  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_50_WIDTH },
3072  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_51_CHECKER_TYPE,
3073  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_51_WIDTH },
3074  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_52_CHECKER_TYPE,
3075  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_52_WIDTH },
3076  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_53_CHECKER_TYPE,
3077  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_53_WIDTH },
3078  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_54_CHECKER_TYPE,
3079  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_54_WIDTH },
3080  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_55_CHECKER_TYPE,
3081  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_55_WIDTH },
3082  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_56_CHECKER_TYPE,
3083  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_56_WIDTH },
3084  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_57_CHECKER_TYPE,
3085  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_57_WIDTH },
3086  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_58_CHECKER_TYPE,
3087  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_58_WIDTH },
3088  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_59_CHECKER_TYPE,
3089  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_59_WIDTH },
3090  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_60_CHECKER_TYPE,
3091  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_60_WIDTH },
3092  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_61_CHECKER_TYPE,
3093  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_61_WIDTH },
3094  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_62_CHECKER_TYPE,
3095  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_62_WIDTH },
3096  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_63_CHECKER_TYPE,
3097  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_63_WIDTH },
3098  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_64_CHECKER_TYPE,
3099  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_64_WIDTH },
3100  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_65_CHECKER_TYPE,
3101  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_65_WIDTH },
3102  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_66_CHECKER_TYPE,
3103  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_66_WIDTH },
3104  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_67_CHECKER_TYPE,
3105  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_67_WIDTH },
3106  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_68_CHECKER_TYPE,
3107  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_68_WIDTH },
3108  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_69_CHECKER_TYPE,
3109  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_69_WIDTH },
3110  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_70_CHECKER_TYPE,
3111  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_70_WIDTH },
3112  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_71_CHECKER_TYPE,
3113  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_71_WIDTH },
3114  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_72_CHECKER_TYPE,
3115  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_72_WIDTH },
3116  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_73_CHECKER_TYPE,
3117  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_73_WIDTH },
3118  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_74_CHECKER_TYPE,
3119  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_74_WIDTH },
3120  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_75_CHECKER_TYPE,
3121  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_75_WIDTH },
3122  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_76_CHECKER_TYPE,
3123  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_76_WIDTH },
3124  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_77_CHECKER_TYPE,
3125  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_77_WIDTH },
3126  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_78_CHECKER_TYPE,
3127  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_78_WIDTH },
3128  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_79_CHECKER_TYPE,
3129  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_79_WIDTH },
3130  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_80_CHECKER_TYPE,
3131  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_80_WIDTH },
3132  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_81_CHECKER_TYPE,
3133  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_81_WIDTH },
3134  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_82_CHECKER_TYPE,
3135  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_82_WIDTH },
3136  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_83_CHECKER_TYPE,
3137  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_83_WIDTH },
3138  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_84_CHECKER_TYPE,
3139  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_84_WIDTH },
3140  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_85_CHECKER_TYPE,
3141  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_85_WIDTH },
3142  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_86_CHECKER_TYPE,
3143  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_86_WIDTH },
3144  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_87_CHECKER_TYPE,
3145  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_87_WIDTH },
3146  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_88_CHECKER_TYPE,
3147  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_88_WIDTH },
3148  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_89_CHECKER_TYPE,
3149  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_89_WIDTH },
3150  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_90_CHECKER_TYPE,
3151  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_90_WIDTH },
3152  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_91_CHECKER_TYPE,
3153  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_91_WIDTH },
3154  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_92_CHECKER_TYPE,
3155  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_92_WIDTH },
3156  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_93_CHECKER_TYPE,
3157  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_93_WIDTH },
3158  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_94_CHECKER_TYPE,
3159  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_94_WIDTH },
3160  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_95_CHECKER_TYPE,
3161  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_95_WIDTH },
3162  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_96_CHECKER_TYPE,
3163  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_96_WIDTH },
3164  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_97_CHECKER_TYPE,
3165  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_97_WIDTH },
3166  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_98_CHECKER_TYPE,
3167  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_98_WIDTH },
3168  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_99_CHECKER_TYPE,
3169  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_99_WIDTH },
3170  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_100_CHECKER_TYPE,
3171  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_100_WIDTH },
3172  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_101_CHECKER_TYPE,
3173  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_101_WIDTH },
3174  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_102_CHECKER_TYPE,
3175  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_102_WIDTH },
3176  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_103_CHECKER_TYPE,
3177  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_103_WIDTH },
3178  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_104_CHECKER_TYPE,
3179  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_104_WIDTH },
3180  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_105_CHECKER_TYPE,
3181  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_105_WIDTH },
3182  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_106_CHECKER_TYPE,
3183  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_106_WIDTH },
3184  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_107_CHECKER_TYPE,
3185  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_107_WIDTH },
3186  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_108_CHECKER_TYPE,
3187  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_108_WIDTH },
3188  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_109_CHECKER_TYPE,
3189  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_109_WIDTH },
3190  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_110_CHECKER_TYPE,
3191  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_110_WIDTH },
3192  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_111_CHECKER_TYPE,
3193  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_111_WIDTH },
3194  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_112_CHECKER_TYPE,
3195  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_112_WIDTH },
3196  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_113_CHECKER_TYPE,
3197  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_113_WIDTH },
3198  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_114_CHECKER_TYPE,
3199  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_114_WIDTH },
3200  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_115_CHECKER_TYPE,
3201  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_115_WIDTH },
3202  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_116_CHECKER_TYPE,
3203  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_116_WIDTH },
3204  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_117_CHECKER_TYPE,
3205  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_117_WIDTH },
3206  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_118_CHECKER_TYPE,
3207  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_118_WIDTH },
3208  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_119_CHECKER_TYPE,
3209  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_119_WIDTH },
3210  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_120_CHECKER_TYPE,
3211  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_120_WIDTH },
3212  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_121_CHECKER_TYPE,
3213  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_121_WIDTH },
3214  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_122_CHECKER_TYPE,
3215  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_122_WIDTH },
3216  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_123_CHECKER_TYPE,
3217  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_123_WIDTH },
3218  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_124_CHECKER_TYPE,
3219  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_124_WIDTH },
3220  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_125_CHECKER_TYPE,
3221  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_125_WIDTH },
3222  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_126_CHECKER_TYPE,
3223  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_126_WIDTH },
3224  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_127_CHECKER_TYPE,
3225  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_127_WIDTH },
3226  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_128_CHECKER_TYPE,
3227  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_128_WIDTH },
3228  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_129_CHECKER_TYPE,
3229  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_129_WIDTH },
3230  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_130_CHECKER_TYPE,
3231  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_130_WIDTH },
3232  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_131_CHECKER_TYPE,
3233  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_131_WIDTH },
3234  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_132_CHECKER_TYPE,
3235  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_132_WIDTH },
3236  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_133_CHECKER_TYPE,
3237  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_133_WIDTH },
3238  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_134_CHECKER_TYPE,
3239  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_134_WIDTH },
3240  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_135_CHECKER_TYPE,
3241  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_135_WIDTH },
3242  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_136_CHECKER_TYPE,
3243  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_136_WIDTH },
3244  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_137_CHECKER_TYPE,
3245  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_137_WIDTH },
3246  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_138_CHECKER_TYPE,
3247  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_138_WIDTH },
3248  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_139_CHECKER_TYPE,
3249  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_139_WIDTH },
3250  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_140_CHECKER_TYPE,
3251  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_140_WIDTH },
3252  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_141_CHECKER_TYPE,
3253  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_141_WIDTH },
3254  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_142_CHECKER_TYPE,
3255  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_142_WIDTH },
3256  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_143_CHECKER_TYPE,
3257  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_143_WIDTH },
3258  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_144_CHECKER_TYPE,
3259  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_144_WIDTH },
3260  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_145_CHECKER_TYPE,
3261  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_145_WIDTH },
3262  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_146_CHECKER_TYPE,
3263  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_146_WIDTH },
3264  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_147_CHECKER_TYPE,
3265  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_147_WIDTH },
3266  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_148_CHECKER_TYPE,
3267  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_148_WIDTH },
3268  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_149_CHECKER_TYPE,
3269  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_149_WIDTH },
3270  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_150_CHECKER_TYPE,
3271  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_150_WIDTH },
3272  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_151_CHECKER_TYPE,
3273  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_151_WIDTH },
3274  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_152_CHECKER_TYPE,
3275  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_152_WIDTH },
3276  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_153_CHECKER_TYPE,
3277  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_153_WIDTH },
3278  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_154_CHECKER_TYPE,
3279  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_154_WIDTH },
3280  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_155_CHECKER_TYPE,
3281  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_155_WIDTH },
3282  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_156_CHECKER_TYPE,
3283  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_156_WIDTH },
3284  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_157_CHECKER_TYPE,
3285  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_157_WIDTH },
3286  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_158_CHECKER_TYPE,
3287  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_158_WIDTH },
3288  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_159_CHECKER_TYPE,
3289  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_159_WIDTH },
3290  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_160_CHECKER_TYPE,
3291  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_160_WIDTH },
3292  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_161_CHECKER_TYPE,
3293  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_161_WIDTH },
3294  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_162_CHECKER_TYPE,
3295  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_162_WIDTH },
3296  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_163_CHECKER_TYPE,
3297  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_163_WIDTH },
3298  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_164_CHECKER_TYPE,
3299  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_164_WIDTH },
3300  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_165_CHECKER_TYPE,
3301  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_165_WIDTH },
3302  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_166_CHECKER_TYPE,
3303  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_166_WIDTH },
3304  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_167_CHECKER_TYPE,
3305  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_167_WIDTH },
3306  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_168_CHECKER_TYPE,
3307  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_168_WIDTH },
3308  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_169_CHECKER_TYPE,
3309  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_169_WIDTH },
3310  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_170_CHECKER_TYPE,
3311  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_170_WIDTH },
3312  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_171_CHECKER_TYPE,
3313  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_171_WIDTH },
3314  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_172_CHECKER_TYPE,
3315  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_172_WIDTH },
3316  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_173_CHECKER_TYPE,
3317  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_173_WIDTH },
3318  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_174_CHECKER_TYPE,
3319  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_174_WIDTH },
3320  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_175_CHECKER_TYPE,
3321  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_175_WIDTH },
3322  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_176_CHECKER_TYPE,
3323  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_176_WIDTH },
3324  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_177_CHECKER_TYPE,
3325  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_177_WIDTH },
3326  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_178_CHECKER_TYPE,
3327  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_178_WIDTH },
3328  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_179_CHECKER_TYPE,
3329  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_179_WIDTH },
3330  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_180_CHECKER_TYPE,
3331  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_180_WIDTH },
3332  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_181_CHECKER_TYPE,
3333  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_181_WIDTH },
3334  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_182_CHECKER_TYPE,
3335  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_182_WIDTH },
3336  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_183_CHECKER_TYPE,
3337  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_183_WIDTH },
3338  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_184_CHECKER_TYPE,
3339  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_184_WIDTH },
3340  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_185_CHECKER_TYPE,
3341  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_185_WIDTH },
3342  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_186_CHECKER_TYPE,
3343  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_186_WIDTH },
3344  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_187_CHECKER_TYPE,
3345  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_187_WIDTH },
3346  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_188_CHECKER_TYPE,
3347  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_188_WIDTH },
3348  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_189_CHECKER_TYPE,
3349  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_189_WIDTH },
3350  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_190_CHECKER_TYPE,
3351  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_190_WIDTH },
3352  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_191_CHECKER_TYPE,
3353  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_191_WIDTH },
3354  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_192_CHECKER_TYPE,
3355  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_192_WIDTH },
3356  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_193_CHECKER_TYPE,
3357  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_193_WIDTH },
3358  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_194_CHECKER_TYPE,
3359  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_194_WIDTH },
3360  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_195_CHECKER_TYPE,
3361  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_195_WIDTH },
3362  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_196_CHECKER_TYPE,
3363  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_196_WIDTH },
3364  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_197_CHECKER_TYPE,
3365  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_197_WIDTH },
3366  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_198_CHECKER_TYPE,
3367  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_198_WIDTH },
3368  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_199_CHECKER_TYPE,
3369  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_199_WIDTH },
3370  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_200_CHECKER_TYPE,
3371  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_200_WIDTH },
3372  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_201_CHECKER_TYPE,
3373  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_201_WIDTH },
3374  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_202_CHECKER_TYPE,
3375  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_202_WIDTH },
3376  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_203_CHECKER_TYPE,
3377  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_203_WIDTH },
3378  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_204_CHECKER_TYPE,
3379  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_204_WIDTH },
3380  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_205_CHECKER_TYPE,
3381  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_205_WIDTH },
3382  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_206_CHECKER_TYPE,
3383  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_206_WIDTH },
3384  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_207_CHECKER_TYPE,
3385  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_207_WIDTH },
3386  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_208_CHECKER_TYPE,
3387  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_208_WIDTH },
3388  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_209_CHECKER_TYPE,
3389  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_209_WIDTH },
3390  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_210_CHECKER_TYPE,
3391  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_210_WIDTH },
3392  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_211_CHECKER_TYPE,
3393  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_211_WIDTH },
3394  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_212_CHECKER_TYPE,
3395  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_212_WIDTH },
3396  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_213_CHECKER_TYPE,
3397  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_213_WIDTH },
3398  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_214_CHECKER_TYPE,
3399  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_214_WIDTH },
3400  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_215_CHECKER_TYPE,
3401  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_215_WIDTH },
3402  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_216_CHECKER_TYPE,
3403  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_216_WIDTH },
3404  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_217_CHECKER_TYPE,
3405  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_217_WIDTH },
3406  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_218_CHECKER_TYPE,
3407  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_218_WIDTH },
3408  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_219_CHECKER_TYPE,
3409  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_219_WIDTH },
3410  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_220_CHECKER_TYPE,
3411  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_220_WIDTH },
3412  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_221_CHECKER_TYPE,
3413  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_221_WIDTH },
3414  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_222_CHECKER_TYPE,
3415  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_222_WIDTH },
3416  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_223_CHECKER_TYPE,
3417  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_223_WIDTH },
3418  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_224_CHECKER_TYPE,
3419  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_224_WIDTH },
3420  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_225_CHECKER_TYPE,
3421  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_225_WIDTH },
3422  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_226_CHECKER_TYPE,
3423  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_226_WIDTH },
3424  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_227_CHECKER_TYPE,
3425  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_227_WIDTH },
3426  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_228_CHECKER_TYPE,
3427  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_228_WIDTH },
3428  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_229_CHECKER_TYPE,
3429  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_229_WIDTH },
3430  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_230_CHECKER_TYPE,
3431  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_230_WIDTH },
3432  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_231_CHECKER_TYPE,
3433  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_231_WIDTH },
3434  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_232_CHECKER_TYPE,
3435  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_232_WIDTH },
3436  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_233_CHECKER_TYPE,
3437  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_233_WIDTH },
3438  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_234_CHECKER_TYPE,
3439  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_234_WIDTH },
3440  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_235_CHECKER_TYPE,
3441  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_235_WIDTH },
3442  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_236_CHECKER_TYPE,
3443  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_236_WIDTH },
3444  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_237_CHECKER_TYPE,
3445  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_237_WIDTH },
3446  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_238_CHECKER_TYPE,
3447  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_238_WIDTH },
3448  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_239_CHECKER_TYPE,
3449  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_239_WIDTH },
3450  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_240_CHECKER_TYPE,
3451  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_240_WIDTH },
3452  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_241_CHECKER_TYPE,
3453  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_241_WIDTH },
3454  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_242_CHECKER_TYPE,
3455  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_242_WIDTH },
3456  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_243_CHECKER_TYPE,
3457  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_243_WIDTH },
3458  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_244_CHECKER_TYPE,
3459  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_244_WIDTH },
3460  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_245_CHECKER_TYPE,
3461  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_245_WIDTH },
3462  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_246_CHECKER_TYPE,
3463  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_246_WIDTH },
3464  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_247_CHECKER_TYPE,
3465  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_247_WIDTH },
3466  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_248_CHECKER_TYPE,
3467  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_248_WIDTH },
3468  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_249_CHECKER_TYPE,
3469  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_249_WIDTH },
3470  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_250_CHECKER_TYPE,
3471  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_250_WIDTH },
3472  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_251_CHECKER_TYPE,
3473  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_251_WIDTH },
3474  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_252_CHECKER_TYPE,
3475  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_252_WIDTH },
3476  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_253_CHECKER_TYPE,
3477  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_253_WIDTH },
3478  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_254_CHECKER_TYPE,
3479  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_254_WIDTH },
3480  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_255_CHECKER_TYPE,
3481  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_255_WIDTH },
3482 };
3483 
3489 static const SDL_GrpChkConfig_t SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_groupEntries[SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_MAX_NUM_CHECKERS] =
3490 {
3491  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_0_CHECKER_TYPE,
3492  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_0_WIDTH },
3493  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_1_CHECKER_TYPE,
3494  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_1_WIDTH },
3495  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_2_CHECKER_TYPE,
3496  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_2_WIDTH },
3497  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_3_CHECKER_TYPE,
3498  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_3_WIDTH },
3499  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_4_CHECKER_TYPE,
3500  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_4_WIDTH },
3501  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_5_CHECKER_TYPE,
3502  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_5_WIDTH },
3503  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_6_CHECKER_TYPE,
3504  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_6_WIDTH },
3505  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_7_CHECKER_TYPE,
3506  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_7_WIDTH },
3507  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_8_CHECKER_TYPE,
3508  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_8_WIDTH },
3509  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_9_CHECKER_TYPE,
3510  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_9_WIDTH },
3511  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_10_CHECKER_TYPE,
3512  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_10_WIDTH },
3513  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_11_CHECKER_TYPE,
3514  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_11_WIDTH },
3515  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_12_CHECKER_TYPE,
3516  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_12_WIDTH },
3517  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_13_CHECKER_TYPE,
3518  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_13_WIDTH },
3519  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_14_CHECKER_TYPE,
3520  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_14_WIDTH },
3521  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_15_CHECKER_TYPE,
3522  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_15_WIDTH },
3523  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_16_CHECKER_TYPE,
3524  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_16_WIDTH },
3525  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_17_CHECKER_TYPE,
3526  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_17_WIDTH },
3527  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_18_CHECKER_TYPE,
3528  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_18_WIDTH },
3529  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_19_CHECKER_TYPE,
3530  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_19_WIDTH },
3531  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_20_CHECKER_TYPE,
3532  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_20_WIDTH },
3533  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_21_CHECKER_TYPE,
3534  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_21_WIDTH },
3535  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_22_CHECKER_TYPE,
3536  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_22_WIDTH },
3537  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_23_CHECKER_TYPE,
3538  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_23_WIDTH },
3539  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_24_CHECKER_TYPE,
3540  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_24_WIDTH },
3541  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_25_CHECKER_TYPE,
3542  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_25_WIDTH },
3543  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_26_CHECKER_TYPE,
3544  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_26_WIDTH },
3545  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_27_CHECKER_TYPE,
3546  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_27_WIDTH },
3547  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_28_CHECKER_TYPE,
3548  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_28_WIDTH },
3549  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_29_CHECKER_TYPE,
3550  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_29_WIDTH },
3551  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_30_CHECKER_TYPE,
3552  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_30_WIDTH },
3553  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_31_CHECKER_TYPE,
3554  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_31_WIDTH },
3555  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_32_CHECKER_TYPE,
3556  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_32_WIDTH },
3557  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_33_CHECKER_TYPE,
3558  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_33_WIDTH },
3559  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_34_CHECKER_TYPE,
3560  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_34_WIDTH },
3561  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_35_CHECKER_TYPE,
3562  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_35_WIDTH },
3563  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_36_CHECKER_TYPE,
3564  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_36_WIDTH },
3565  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_37_CHECKER_TYPE,
3566  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_37_WIDTH },
3567  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_38_CHECKER_TYPE,
3568  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_38_WIDTH },
3569  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_39_CHECKER_TYPE,
3570  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_39_WIDTH },
3571  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_40_CHECKER_TYPE,
3572  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_40_WIDTH },
3573  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_41_CHECKER_TYPE,
3574  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_41_WIDTH },
3575  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_42_CHECKER_TYPE,
3576  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_42_WIDTH },
3577  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_43_CHECKER_TYPE,
3578  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_43_WIDTH },
3579  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_44_CHECKER_TYPE,
3580  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_44_WIDTH },
3581  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_45_CHECKER_TYPE,
3582  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_45_WIDTH },
3583  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_46_CHECKER_TYPE,
3584  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_46_WIDTH },
3585  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_47_CHECKER_TYPE,
3586  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_47_WIDTH },
3587  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_48_CHECKER_TYPE,
3588  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_48_WIDTH },
3589  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_49_CHECKER_TYPE,
3590  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_49_WIDTH },
3591  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_50_CHECKER_TYPE,
3592  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_50_WIDTH },
3593  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_51_CHECKER_TYPE,
3594  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_51_WIDTH },
3595  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_52_CHECKER_TYPE,
3596  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_52_WIDTH },
3597  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_53_CHECKER_TYPE,
3598  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_53_WIDTH },
3599  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_54_CHECKER_TYPE,
3600  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_54_WIDTH },
3601  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_55_CHECKER_TYPE,
3602  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_55_WIDTH },
3603  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_56_CHECKER_TYPE,
3604  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_56_WIDTH },
3605  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_57_CHECKER_TYPE,
3606  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_57_WIDTH },
3607  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_58_CHECKER_TYPE,
3608  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_58_WIDTH },
3609  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_59_CHECKER_TYPE,
3610  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_59_WIDTH },
3611  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_60_CHECKER_TYPE,
3612  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_60_WIDTH },
3613  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_61_CHECKER_TYPE,
3614  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_61_WIDTH },
3615  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_62_CHECKER_TYPE,
3616  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_62_WIDTH },
3617  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_63_CHECKER_TYPE,
3618  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_63_WIDTH },
3619  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_64_CHECKER_TYPE,
3620  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_64_WIDTH },
3621  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_65_CHECKER_TYPE,
3622  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_65_WIDTH },
3623  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_66_CHECKER_TYPE,
3624  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_66_WIDTH },
3625  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_67_CHECKER_TYPE,
3626  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_67_WIDTH },
3627  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_68_CHECKER_TYPE,
3628  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_68_WIDTH },
3629  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_69_CHECKER_TYPE,
3630  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_69_WIDTH },
3631  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_70_CHECKER_TYPE,
3632  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_70_WIDTH },
3633  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_71_CHECKER_TYPE,
3634  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_71_WIDTH },
3635  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_72_CHECKER_TYPE,
3636  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_72_WIDTH },
3637  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_73_CHECKER_TYPE,
3638  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_73_WIDTH },
3639  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_74_CHECKER_TYPE,
3640  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_74_WIDTH },
3641  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_75_CHECKER_TYPE,
3642  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_75_WIDTH },
3643  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_76_CHECKER_TYPE,
3644  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_76_WIDTH },
3645  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_77_CHECKER_TYPE,
3646  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_77_WIDTH },
3647  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_78_CHECKER_TYPE,
3648  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_78_WIDTH },
3649  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_79_CHECKER_TYPE,
3650  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_79_WIDTH },
3651  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_80_CHECKER_TYPE,
3652  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_80_WIDTH },
3653  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_81_CHECKER_TYPE,
3654  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_81_WIDTH },
3655  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_82_CHECKER_TYPE,
3656  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_82_WIDTH },
3657  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_83_CHECKER_TYPE,
3658  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_83_WIDTH },
3659  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_84_CHECKER_TYPE,
3660  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_84_WIDTH },
3661  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_85_CHECKER_TYPE,
3662  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_85_WIDTH },
3663  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_86_CHECKER_TYPE,
3664  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_86_WIDTH },
3665  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_87_CHECKER_TYPE,
3666  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_87_WIDTH },
3667  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_88_CHECKER_TYPE,
3668  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_88_WIDTH },
3669  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_89_CHECKER_TYPE,
3670  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_89_WIDTH },
3671  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_90_CHECKER_TYPE,
3672  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_90_WIDTH },
3673  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_91_CHECKER_TYPE,
3674  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_91_WIDTH },
3675  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_92_CHECKER_TYPE,
3676  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_92_WIDTH },
3677  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_93_CHECKER_TYPE,
3678  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_93_WIDTH },
3679  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_94_CHECKER_TYPE,
3680  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_94_WIDTH },
3681  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_95_CHECKER_TYPE,
3682  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_95_WIDTH },
3683  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_96_CHECKER_TYPE,
3684  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_96_WIDTH },
3685  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_97_CHECKER_TYPE,
3686  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_97_WIDTH },
3687  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_98_CHECKER_TYPE,
3688  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_98_WIDTH },
3689  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_99_CHECKER_TYPE,
3690  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_99_WIDTH },
3691  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_100_CHECKER_TYPE,
3692  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_100_WIDTH },
3693  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_101_CHECKER_TYPE,
3694  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_101_WIDTH },
3695  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_102_CHECKER_TYPE,
3696  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_102_WIDTH },
3697  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_103_CHECKER_TYPE,
3698  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_103_WIDTH },
3699  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_104_CHECKER_TYPE,
3700  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_104_WIDTH },
3701  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_105_CHECKER_TYPE,
3702  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_105_WIDTH },
3703  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_106_CHECKER_TYPE,
3704  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_106_WIDTH },
3705  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_107_CHECKER_TYPE,
3706  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_107_WIDTH },
3707  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_108_CHECKER_TYPE,
3708  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_108_WIDTH },
3709  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_109_CHECKER_TYPE,
3710  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_109_WIDTH },
3711  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_110_CHECKER_TYPE,
3712  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_110_WIDTH },
3713  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_111_CHECKER_TYPE,
3714  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_111_WIDTH },
3715  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_112_CHECKER_TYPE,
3716  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_112_WIDTH },
3717  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_113_CHECKER_TYPE,
3718  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_113_WIDTH },
3719  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_114_CHECKER_TYPE,
3720  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_114_WIDTH },
3721  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_115_CHECKER_TYPE,
3722  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_115_WIDTH },
3723  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_116_CHECKER_TYPE,
3724  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_116_WIDTH },
3725  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_117_CHECKER_TYPE,
3726  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_117_WIDTH },
3727  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_118_CHECKER_TYPE,
3728  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_118_WIDTH },
3729  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_119_CHECKER_TYPE,
3730  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_119_WIDTH },
3731  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_120_CHECKER_TYPE,
3732  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_120_WIDTH },
3733  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_121_CHECKER_TYPE,
3734  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_121_WIDTH },
3735  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_122_CHECKER_TYPE,
3736  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_122_WIDTH },
3737  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_123_CHECKER_TYPE,
3738  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_123_WIDTH },
3739  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_124_CHECKER_TYPE,
3740  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_124_WIDTH },
3741  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_125_CHECKER_TYPE,
3742  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_125_WIDTH },
3743  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_126_CHECKER_TYPE,
3744  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_126_WIDTH },
3745  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_127_CHECKER_TYPE,
3746  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_127_WIDTH },
3747  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_128_CHECKER_TYPE,
3748  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_128_WIDTH },
3749  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_129_CHECKER_TYPE,
3750  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_129_WIDTH },
3751  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_130_CHECKER_TYPE,
3752  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_130_WIDTH },
3753  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_131_CHECKER_TYPE,
3754  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_131_WIDTH },
3755  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_132_CHECKER_TYPE,
3756  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_132_WIDTH },
3757  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_133_CHECKER_TYPE,
3758  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_133_WIDTH },
3759  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_134_CHECKER_TYPE,
3760  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_134_WIDTH },
3761  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_135_CHECKER_TYPE,
3762  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_135_WIDTH },
3763  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_136_CHECKER_TYPE,
3764  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_136_WIDTH },
3765  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_137_CHECKER_TYPE,
3766  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_137_WIDTH },
3767  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_138_CHECKER_TYPE,
3768  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_138_WIDTH },
3769  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_139_CHECKER_TYPE,
3770  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_139_WIDTH },
3771  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_140_CHECKER_TYPE,
3772  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_140_WIDTH },
3773  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_141_CHECKER_TYPE,
3774  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_141_WIDTH },
3775  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_142_CHECKER_TYPE,
3776  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_142_WIDTH },
3777  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_143_CHECKER_TYPE,
3778  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_143_WIDTH },
3779  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_144_CHECKER_TYPE,
3780  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_144_WIDTH },
3781  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_145_CHECKER_TYPE,
3782  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_145_WIDTH },
3783  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_146_CHECKER_TYPE,
3784  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_146_WIDTH },
3785  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_147_CHECKER_TYPE,
3786  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_147_WIDTH },
3787  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_148_CHECKER_TYPE,
3788  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_148_WIDTH },
3789  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_149_CHECKER_TYPE,
3790  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_149_WIDTH },
3791  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_150_CHECKER_TYPE,
3792  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_150_WIDTH },
3793  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_151_CHECKER_TYPE,
3794  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_151_WIDTH },
3795  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_152_CHECKER_TYPE,
3796  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_152_WIDTH },
3797  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_153_CHECKER_TYPE,
3798  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_153_WIDTH },
3799 };
3800 
3806 static const SDL_GrpChkConfig_t SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_CBASS_DEFAULT_ERR_AM67_WKUP_SAFE_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_groupEntries[SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_CBASS_DEFAULT_ERR_AM67_WKUP_SAFE_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS] =
3807 {
3808  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_CBASS_DEFAULT_ERR_AM67_WKUP_SAFE_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
3809  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_CBASS_DEFAULT_ERR_AM67_WKUP_SAFE_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
3810  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_CBASS_DEFAULT_ERR_AM67_WKUP_SAFE_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
3811  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_CBASS_DEFAULT_ERR_AM67_WKUP_SAFE_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
3812  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_CBASS_DEFAULT_ERR_AM67_WKUP_SAFE_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
3813  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_CBASS_DEFAULT_ERR_AM67_WKUP_SAFE_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
3814  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_CBASS_DEFAULT_ERR_AM67_WKUP_SAFE_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
3815  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_CBASS_DEFAULT_ERR_AM67_WKUP_SAFE_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
3816  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_CBASS_DEFAULT_ERR_AM67_WKUP_SAFE_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
3817  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_CBASS_DEFAULT_ERR_AM67_WKUP_SAFE_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
3818 };
3819 
3825 static const SDL_GrpChkConfig_t SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_groupEntries[SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_MAX_NUM_CHECKERS] =
3826 {
3827  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_0_CHECKER_TYPE,
3828  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_0_WIDTH },
3829  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_1_CHECKER_TYPE,
3830  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_1_WIDTH },
3831  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_2_CHECKER_TYPE,
3832  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_2_WIDTH },
3833  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_3_CHECKER_TYPE,
3834  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_3_WIDTH },
3835  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_4_CHECKER_TYPE,
3836  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_4_WIDTH },
3837  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_5_CHECKER_TYPE,
3838  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_5_WIDTH },
3839  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_6_CHECKER_TYPE,
3840  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_6_WIDTH },
3841  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_7_CHECKER_TYPE,
3842  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_7_WIDTH },
3843  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_8_CHECKER_TYPE,
3844  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_8_WIDTH },
3845  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_9_CHECKER_TYPE,
3846  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_9_WIDTH },
3847  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_10_CHECKER_TYPE,
3848  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_10_WIDTH },
3849  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_11_CHECKER_TYPE,
3850  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_11_WIDTH },
3851  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_12_CHECKER_TYPE,
3852  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_12_WIDTH },
3853  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_13_CHECKER_TYPE,
3854  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_13_WIDTH },
3855  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_14_CHECKER_TYPE,
3856  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_14_WIDTH },
3857  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_15_CHECKER_TYPE,
3858  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_15_WIDTH },
3859  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_16_CHECKER_TYPE,
3860  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_16_WIDTH },
3861  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_17_CHECKER_TYPE,
3862  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_17_WIDTH },
3863  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_18_CHECKER_TYPE,
3864  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_18_WIDTH },
3865 };
3866 
3872 static const SDL_GrpChkConfig_t SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ERR_SCR_AM67_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_groupEntries[SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ERR_SCR_AM67_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS] =
3873 {
3874  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ERR_SCR_AM67_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
3875  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ERR_SCR_AM67_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
3876  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ERR_SCR_AM67_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
3877  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ERR_SCR_AM67_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
3878  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ERR_SCR_AM67_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
3879  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ERR_SCR_AM67_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
3880  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ERR_SCR_AM67_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
3881  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ERR_SCR_AM67_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
3882  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ERR_SCR_AM67_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
3883  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ERR_SCR_AM67_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
3884  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ERR_SCR_AM67_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_5_CHECKER_TYPE,
3885  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ERR_SCR_AM67_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_5_WIDTH },
3886  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ERR_SCR_AM67_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_6_CHECKER_TYPE,
3887  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ERR_SCR_AM67_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_6_WIDTH },
3888  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ERR_SCR_AM67_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_7_CHECKER_TYPE,
3889  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ERR_SCR_AM67_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_7_WIDTH },
3890  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ERR_SCR_AM67_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_8_CHECKER_TYPE,
3891  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ERR_SCR_AM67_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_8_WIDTH },
3892  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ERR_SCR_AM67_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_9_CHECKER_TYPE,
3893  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ERR_SCR_AM67_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_9_WIDTH },
3894  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ERR_SCR_AM67_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_10_CHECKER_TYPE,
3895  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ERR_SCR_AM67_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_10_WIDTH },
3896  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ERR_SCR_AM67_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_11_CHECKER_TYPE,
3897  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ERR_SCR_AM67_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_11_WIDTH },
3898  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ERR_SCR_AM67_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_12_CHECKER_TYPE,
3899  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ERR_SCR_AM67_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_12_WIDTH },
3900  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ERR_SCR_AM67_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_13_CHECKER_TYPE,
3901  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ERR_SCR_AM67_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_13_WIDTH },
3902  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ERR_SCR_AM67_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_14_CHECKER_TYPE,
3903  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ERR_SCR_AM67_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_14_WIDTH },
3904  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ERR_SCR_AM67_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_15_CHECKER_TYPE,
3905  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ERR_SCR_AM67_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_15_WIDTH },
3906  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ERR_SCR_AM67_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_16_CHECKER_TYPE,
3907  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ERR_SCR_AM67_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_16_WIDTH },
3908  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ERR_SCR_AM67_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_17_CHECKER_TYPE,
3909  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ERR_SCR_AM67_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_17_WIDTH },
3910  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ERR_SCR_AM67_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_18_CHECKER_TYPE,
3911  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ERR_SCR_AM67_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_18_WIDTH },
3912  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ERR_SCR_AM67_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_19_CHECKER_TYPE,
3913  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ERR_SCR_AM67_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_19_WIDTH },
3914  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ERR_SCR_AM67_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_20_CHECKER_TYPE,
3915  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ERR_SCR_AM67_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_20_WIDTH },
3916  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ERR_SCR_AM67_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_21_CHECKER_TYPE,
3917  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ERR_SCR_AM67_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_21_WIDTH },
3918  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ERR_SCR_AM67_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_22_CHECKER_TYPE,
3919  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ERR_SCR_AM67_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_22_WIDTH },
3920  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ERR_SCR_AM67_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_23_CHECKER_TYPE,
3921  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ERR_SCR_AM67_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_23_WIDTH },
3922  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ERR_SCR_AM67_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_24_CHECKER_TYPE,
3923  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ERR_SCR_AM67_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_24_WIDTH },
3924  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ERR_SCR_AM67_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_25_CHECKER_TYPE,
3925  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ERR_SCR_AM67_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_25_WIDTH },
3926  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ERR_SCR_AM67_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_26_CHECKER_TYPE,
3927  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ERR_SCR_AM67_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_26_WIDTH },
3928  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ERR_SCR_AM67_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_27_CHECKER_TYPE,
3929  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ERR_SCR_AM67_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_27_WIDTH },
3930  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ERR_SCR_AM67_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_28_CHECKER_TYPE,
3931  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ERR_SCR_AM67_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_28_WIDTH },
3932  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ERR_SCR_AM67_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_29_CHECKER_TYPE,
3933  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ERR_SCR_AM67_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_29_WIDTH },
3934  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ERR_SCR_AM67_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_30_CHECKER_TYPE,
3935  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ERR_SCR_AM67_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_30_WIDTH },
3936  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ERR_SCR_AM67_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_31_CHECKER_TYPE,
3937  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ERR_SCR_AM67_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_31_WIDTH },
3938  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ERR_SCR_AM67_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_32_CHECKER_TYPE,
3939  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ERR_SCR_AM67_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_32_WIDTH },
3940  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ERR_SCR_AM67_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_33_CHECKER_TYPE,
3941  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ERR_SCR_AM67_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_33_WIDTH },
3942  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ERR_SCR_AM67_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_34_CHECKER_TYPE,
3943  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ERR_SCR_AM67_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_34_WIDTH },
3944  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ERR_SCR_AM67_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_35_CHECKER_TYPE,
3945  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ERR_SCR_AM67_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_35_WIDTH },
3946  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ERR_SCR_AM67_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_36_CHECKER_TYPE,
3947  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ERR_SCR_AM67_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_36_WIDTH },
3948  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ERR_SCR_AM67_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_37_CHECKER_TYPE,
3949  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ERR_SCR_AM67_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_37_WIDTH },
3950  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ERR_SCR_AM67_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_38_CHECKER_TYPE,
3951  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ERR_SCR_AM67_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_38_WIDTH },
3952  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ERR_SCR_AM67_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_39_CHECKER_TYPE,
3953  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ERR_SCR_AM67_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_39_WIDTH },
3954  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ERR_SCR_AM67_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_40_CHECKER_TYPE,
3955  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ERR_SCR_AM67_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_40_WIDTH },
3956  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ERR_SCR_AM67_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_41_CHECKER_TYPE,
3957  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ERR_SCR_AM67_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_41_WIDTH },
3958 };
3959 
3965 static const SDL_GrpChkConfig_t SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_groupEntries[SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_MAX_NUM_CHECKERS] =
3966 {
3967  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_0_CHECKER_TYPE,
3968  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_0_WIDTH },
3969  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_1_CHECKER_TYPE,
3970  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_1_WIDTH },
3971  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_2_CHECKER_TYPE,
3972  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_2_WIDTH },
3973  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_3_CHECKER_TYPE,
3974  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_3_WIDTH },
3975  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_4_CHECKER_TYPE,
3976  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_4_WIDTH },
3977  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_5_CHECKER_TYPE,
3978  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_5_WIDTH },
3979  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_6_CHECKER_TYPE,
3980  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_6_WIDTH },
3981  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_7_CHECKER_TYPE,
3982  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_7_WIDTH },
3983  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_8_CHECKER_TYPE,
3984  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_8_WIDTH },
3985  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_9_CHECKER_TYPE,
3986  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_9_WIDTH },
3987  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_10_CHECKER_TYPE,
3988  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_10_WIDTH },
3989  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_11_CHECKER_TYPE,
3990  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_11_WIDTH },
3991  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_12_CHECKER_TYPE,
3992  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_12_WIDTH },
3993  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_13_CHECKER_TYPE,
3994  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_13_WIDTH },
3995  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_14_CHECKER_TYPE,
3996  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_14_WIDTH },
3997  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_15_CHECKER_TYPE,
3998  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_15_WIDTH },
3999  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_16_CHECKER_TYPE,
4000  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_16_WIDTH },
4001  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_17_CHECKER_TYPE,
4002  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_17_WIDTH },
4003  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_18_CHECKER_TYPE,
4004  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_18_WIDTH },
4005  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_19_CHECKER_TYPE,
4006  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_19_WIDTH },
4007  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_20_CHECKER_TYPE,
4008  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_20_WIDTH },
4009  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_21_CHECKER_TYPE,
4010  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_21_WIDTH },
4011  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_22_CHECKER_TYPE,
4012  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_22_WIDTH },
4013  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_23_CHECKER_TYPE,
4014  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_23_WIDTH },
4015  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_24_CHECKER_TYPE,
4016  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_24_WIDTH },
4017  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_25_CHECKER_TYPE,
4018  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_25_WIDTH },
4019  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_26_CHECKER_TYPE,
4020  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_26_WIDTH },
4021  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_27_CHECKER_TYPE,
4022  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_27_WIDTH },
4023  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_28_CHECKER_TYPE,
4024  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_28_WIDTH },
4025  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_29_CHECKER_TYPE,
4026  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_29_WIDTH },
4027  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_30_CHECKER_TYPE,
4028  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_30_WIDTH },
4029  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_31_CHECKER_TYPE,
4030  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_31_WIDTH },
4031  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_32_CHECKER_TYPE,
4032  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_32_WIDTH },
4033  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_33_CHECKER_TYPE,
4034  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_33_WIDTH },
4035  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_34_CHECKER_TYPE,
4036  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_34_WIDTH },
4037  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_35_CHECKER_TYPE,
4038  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_35_WIDTH },
4039  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_36_CHECKER_TYPE,
4040  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_36_WIDTH },
4041  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_37_CHECKER_TYPE,
4042  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_37_WIDTH },
4043  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_38_CHECKER_TYPE,
4044  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_38_WIDTH },
4045  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_39_CHECKER_TYPE,
4046  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_39_WIDTH },
4047  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_40_CHECKER_TYPE,
4048  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_40_WIDTH },
4049  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_41_CHECKER_TYPE,
4050  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_41_WIDTH },
4051  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_42_CHECKER_TYPE,
4052  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_42_WIDTH },
4053  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_43_CHECKER_TYPE,
4054  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_43_WIDTH },
4055  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_44_CHECKER_TYPE,
4056  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_44_WIDTH },
4057  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_45_CHECKER_TYPE,
4058  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_45_WIDTH },
4059  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_46_CHECKER_TYPE,
4060  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_46_WIDTH },
4061  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_47_CHECKER_TYPE,
4062  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_47_WIDTH },
4063  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_48_CHECKER_TYPE,
4064  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_48_WIDTH },
4065  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_49_CHECKER_TYPE,
4066  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_49_WIDTH },
4067  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_50_CHECKER_TYPE,
4068  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_50_WIDTH },
4069  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_51_CHECKER_TYPE,
4070  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_51_WIDTH },
4071  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_52_CHECKER_TYPE,
4072  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_52_WIDTH },
4073  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_53_CHECKER_TYPE,
4074  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_53_WIDTH },
4075  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_54_CHECKER_TYPE,
4076  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_54_WIDTH },
4077  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_55_CHECKER_TYPE,
4078  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_55_WIDTH },
4079  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_56_CHECKER_TYPE,
4080  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_56_WIDTH },
4081  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_57_CHECKER_TYPE,
4082  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_57_WIDTH },
4083  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_58_CHECKER_TYPE,
4084  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_58_WIDTH },
4085  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_59_CHECKER_TYPE,
4086  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_59_WIDTH },
4087  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_60_CHECKER_TYPE,
4088  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_60_WIDTH },
4089  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_61_CHECKER_TYPE,
4090  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_61_WIDTH },
4091  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_62_CHECKER_TYPE,
4092  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_62_WIDTH },
4093  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_63_CHECKER_TYPE,
4094  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_63_WIDTH },
4095  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_64_CHECKER_TYPE,
4096  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_64_WIDTH },
4097  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_65_CHECKER_TYPE,
4098  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_65_WIDTH },
4099  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_66_CHECKER_TYPE,
4100  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_66_WIDTH },
4101  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_67_CHECKER_TYPE,
4102  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_67_WIDTH },
4103  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_68_CHECKER_TYPE,
4104  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_68_WIDTH },
4105  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_69_CHECKER_TYPE,
4106  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_69_WIDTH },
4107  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_70_CHECKER_TYPE,
4108  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_70_WIDTH },
4109  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_71_CHECKER_TYPE,
4110  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_71_WIDTH },
4111  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_72_CHECKER_TYPE,
4112  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_72_WIDTH },
4113  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_73_CHECKER_TYPE,
4114  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_73_WIDTH },
4115  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_74_CHECKER_TYPE,
4116  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_74_WIDTH },
4117  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_75_CHECKER_TYPE,
4118  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_75_WIDTH },
4119  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_76_CHECKER_TYPE,
4120  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_76_WIDTH },
4121  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_77_CHECKER_TYPE,
4122  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_77_WIDTH },
4123  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_78_CHECKER_TYPE,
4124  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_78_WIDTH },
4125  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_79_CHECKER_TYPE,
4126  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_79_WIDTH },
4127  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_80_CHECKER_TYPE,
4128  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_80_WIDTH },
4129  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_81_CHECKER_TYPE,
4130  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_81_WIDTH },
4131  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_82_CHECKER_TYPE,
4132  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_82_WIDTH },
4133  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_83_CHECKER_TYPE,
4134  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_83_WIDTH },
4135  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_84_CHECKER_TYPE,
4136  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_84_WIDTH },
4137  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_85_CHECKER_TYPE,
4138  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_85_WIDTH },
4139  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_86_CHECKER_TYPE,
4140  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_86_WIDTH },
4141  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_87_CHECKER_TYPE,
4142  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_87_WIDTH },
4143  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_88_CHECKER_TYPE,
4144  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_88_WIDTH },
4145  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_89_CHECKER_TYPE,
4146  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_89_WIDTH },
4147  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_90_CHECKER_TYPE,
4148  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_90_WIDTH },
4149  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_91_CHECKER_TYPE,
4150  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_91_WIDTH },
4151  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_92_CHECKER_TYPE,
4152  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_92_WIDTH },
4153  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_93_CHECKER_TYPE,
4154  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_93_WIDTH },
4155  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_94_CHECKER_TYPE,
4156  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_94_WIDTH },
4157  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_95_CHECKER_TYPE,
4158  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_95_WIDTH },
4159  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_96_CHECKER_TYPE,
4160  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_96_WIDTH },
4161  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_97_CHECKER_TYPE,
4162  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_97_WIDTH },
4163  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_98_CHECKER_TYPE,
4164  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_98_WIDTH },
4165  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_99_CHECKER_TYPE,
4166  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_99_WIDTH },
4167  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_100_CHECKER_TYPE,
4168  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_100_WIDTH },
4169  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_101_CHECKER_TYPE,
4170  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_101_WIDTH },
4171  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_102_CHECKER_TYPE,
4172  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_102_WIDTH },
4173  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_103_CHECKER_TYPE,
4174  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_103_WIDTH },
4175  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_104_CHECKER_TYPE,
4176  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_104_WIDTH },
4177  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_105_CHECKER_TYPE,
4178  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_105_WIDTH },
4179  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_106_CHECKER_TYPE,
4180  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_106_WIDTH },
4181  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_107_CHECKER_TYPE,
4182  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_107_WIDTH },
4183  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_108_CHECKER_TYPE,
4184  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_108_WIDTH },
4185  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_109_CHECKER_TYPE,
4186  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_109_WIDTH },
4187  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_110_CHECKER_TYPE,
4188  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_110_WIDTH },
4189  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_111_CHECKER_TYPE,
4190  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_111_WIDTH },
4191  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_112_CHECKER_TYPE,
4192  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_112_WIDTH },
4193  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_113_CHECKER_TYPE,
4194  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_113_WIDTH },
4195  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_114_CHECKER_TYPE,
4196  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_114_WIDTH },
4197  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_115_CHECKER_TYPE,
4198  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_115_WIDTH },
4199  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_116_CHECKER_TYPE,
4200  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_116_WIDTH },
4201  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_117_CHECKER_TYPE,
4202  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_117_WIDTH },
4203  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_118_CHECKER_TYPE,
4204  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_118_WIDTH },
4205  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_119_CHECKER_TYPE,
4206  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_119_WIDTH },
4207  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_120_CHECKER_TYPE,
4208  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_120_WIDTH },
4209 };
4210 
4216 static const SDL_GrpChkConfig_t SDL_WKUP_ECC_AGGR2_SAM67_WKUP_SAFE_ECC_AGGR_EDC_CTRL_groupEntries[SDL_WKUP_ECC_AGGR2_SAM67_WKUP_SAFE_ECC_AGGR_EDC_CTRL_MAX_NUM_CHECKERS] =
4217 {
4218  { SDL_WKUP_ECC_AGGR2_SAM67_WKUP_SAFE_ECC_AGGR_EDC_CTRL_GROUP_0_CHECKER_TYPE,
4219  SDL_WKUP_ECC_AGGR2_SAM67_WKUP_SAFE_ECC_AGGR_EDC_CTRL_GROUP_0_WIDTH },
4220  { SDL_WKUP_ECC_AGGR2_SAM67_WKUP_SAFE_ECC_AGGR_EDC_CTRL_GROUP_1_CHECKER_TYPE,
4221  SDL_WKUP_ECC_AGGR2_SAM67_WKUP_SAFE_ECC_AGGR_EDC_CTRL_GROUP_1_WIDTH },
4222  { SDL_WKUP_ECC_AGGR2_SAM67_WKUP_SAFE_ECC_AGGR_EDC_CTRL_GROUP_2_CHECKER_TYPE,
4223  SDL_WKUP_ECC_AGGR2_SAM67_WKUP_SAFE_ECC_AGGR_EDC_CTRL_GROUP_2_WIDTH },
4224  { SDL_WKUP_ECC_AGGR2_SAM67_WKUP_SAFE_ECC_AGGR_EDC_CTRL_GROUP_3_CHECKER_TYPE,
4225  SDL_WKUP_ECC_AGGR2_SAM67_WKUP_SAFE_ECC_AGGR_EDC_CTRL_GROUP_3_WIDTH },
4226  { SDL_WKUP_ECC_AGGR2_SAM67_WKUP_SAFE_ECC_AGGR_EDC_CTRL_GROUP_4_CHECKER_TYPE,
4227  SDL_WKUP_ECC_AGGR2_SAM67_WKUP_SAFE_ECC_AGGR_EDC_CTRL_GROUP_4_WIDTH },
4228  { SDL_WKUP_ECC_AGGR2_SAM67_WKUP_SAFE_ECC_AGGR_EDC_CTRL_GROUP_5_CHECKER_TYPE,
4229  SDL_WKUP_ECC_AGGR2_SAM67_WKUP_SAFE_ECC_AGGR_EDC_CTRL_GROUP_5_WIDTH },
4230 };
4231 
4236 static const SDL_MemConfig_t SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_MemEntries[SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES] =
4237 {
4238  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_IMAILBOX8_MAIN_0_RAMECC_RAM_ID, 0u,
4239  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_IMAILBOX8_MAIN_0_RAMECC_RAM_SIZE, 4u,
4240  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_IMAILBOX8_MAIN_0_RAMECC_ROW_WIDTH, ((bool)false) },
4241 };
4242 
4248 static const SDL_GrpChkConfig_t SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_HSM_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_HSM_VBUSP_S_BRIDGE_BUSECC_groupEntries[SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_HSM_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_HSM_VBUSP_S_BRIDGE_BUSECC_MAX_NUM_CHECKERS] =
4249 {
4250  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_HSM_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_HSM_VBUSP_S_BRIDGE_BUSECC_GROUP_0_CHECKER_TYPE,
4251  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_HSM_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_HSM_VBUSP_S_BRIDGE_BUSECC_GROUP_0_WIDTH },
4252  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_HSM_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_HSM_VBUSP_S_BRIDGE_BUSECC_GROUP_1_CHECKER_TYPE,
4253  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_HSM_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_HSM_VBUSP_S_BRIDGE_BUSECC_GROUP_1_WIDTH },
4254  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_HSM_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_HSM_VBUSP_S_BRIDGE_BUSECC_GROUP_2_CHECKER_TYPE,
4255  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_HSM_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_HSM_VBUSP_S_BRIDGE_BUSECC_GROUP_2_WIDTH },
4256  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_HSM_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_HSM_VBUSP_S_BRIDGE_BUSECC_GROUP_3_CHECKER_TYPE,
4257  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_HSM_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_HSM_VBUSP_S_BRIDGE_BUSECC_GROUP_3_WIDTH },
4258  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_HSM_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_HSM_VBUSP_S_BRIDGE_BUSECC_GROUP_4_CHECKER_TYPE,
4259  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_HSM_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_HSM_VBUSP_S_BRIDGE_BUSECC_GROUP_4_WIDTH },
4260  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_HSM_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_HSM_VBUSP_S_BRIDGE_BUSECC_GROUP_5_CHECKER_TYPE,
4261  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_HSM_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_HSM_VBUSP_S_BRIDGE_BUSECC_GROUP_5_WIDTH },
4262  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_HSM_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_HSM_VBUSP_S_BRIDGE_BUSECC_GROUP_6_CHECKER_TYPE,
4263  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_HSM_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_HSM_VBUSP_S_BRIDGE_BUSECC_GROUP_6_WIDTH },
4264  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_HSM_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_HSM_VBUSP_S_BRIDGE_BUSECC_GROUP_7_CHECKER_TYPE,
4265  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_HSM_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_HSM_VBUSP_S_BRIDGE_BUSECC_GROUP_7_WIDTH },
4266  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_HSM_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_HSM_VBUSP_S_BRIDGE_BUSECC_GROUP_8_CHECKER_TYPE,
4267  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_HSM_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_HSM_VBUSP_S_BRIDGE_BUSECC_GROUP_8_WIDTH },
4268  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_HSM_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_HSM_VBUSP_S_BRIDGE_BUSECC_GROUP_9_CHECKER_TYPE,
4269  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_HSM_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_HSM_VBUSP_S_BRIDGE_BUSECC_GROUP_9_WIDTH },
4270  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_HSM_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_HSM_VBUSP_S_BRIDGE_BUSECC_GROUP_10_CHECKER_TYPE,
4271  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_HSM_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_HSM_VBUSP_S_BRIDGE_BUSECC_GROUP_10_WIDTH },
4272  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_HSM_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_HSM_VBUSP_S_BRIDGE_BUSECC_GROUP_11_CHECKER_TYPE,
4273  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_HSM_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_HSM_VBUSP_S_BRIDGE_BUSECC_GROUP_11_WIDTH },
4274  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_HSM_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_HSM_VBUSP_S_BRIDGE_BUSECC_GROUP_12_CHECKER_TYPE,
4275  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_HSM_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_HSM_VBUSP_S_BRIDGE_BUSECC_GROUP_12_WIDTH },
4276 };
4277 
4283 static const SDL_GrpChkConfig_t SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_TIFS_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_TIFS_VBUSP_S_BRIDGE_BUSECC_groupEntries[SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_TIFS_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_TIFS_VBUSP_S_BRIDGE_BUSECC_MAX_NUM_CHECKERS] =
4284 {
4285  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_TIFS_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_TIFS_VBUSP_S_BRIDGE_BUSECC_GROUP_0_CHECKER_TYPE,
4286  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_TIFS_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_TIFS_VBUSP_S_BRIDGE_BUSECC_GROUP_0_WIDTH },
4287  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_TIFS_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_TIFS_VBUSP_S_BRIDGE_BUSECC_GROUP_1_CHECKER_TYPE,
4288  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_TIFS_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_TIFS_VBUSP_S_BRIDGE_BUSECC_GROUP_1_WIDTH },
4289  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_TIFS_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_TIFS_VBUSP_S_BRIDGE_BUSECC_GROUP_2_CHECKER_TYPE,
4290  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_TIFS_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_TIFS_VBUSP_S_BRIDGE_BUSECC_GROUP_2_WIDTH },
4291  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_TIFS_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_TIFS_VBUSP_S_BRIDGE_BUSECC_GROUP_3_CHECKER_TYPE,
4292  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_TIFS_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_TIFS_VBUSP_S_BRIDGE_BUSECC_GROUP_3_WIDTH },
4293  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_TIFS_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_TIFS_VBUSP_S_BRIDGE_BUSECC_GROUP_4_CHECKER_TYPE,
4294  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_TIFS_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_TIFS_VBUSP_S_BRIDGE_BUSECC_GROUP_4_WIDTH },
4295  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_TIFS_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_TIFS_VBUSP_S_BRIDGE_BUSECC_GROUP_5_CHECKER_TYPE,
4296  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_TIFS_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_TIFS_VBUSP_S_BRIDGE_BUSECC_GROUP_5_WIDTH },
4297  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_TIFS_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_TIFS_VBUSP_S_BRIDGE_BUSECC_GROUP_6_CHECKER_TYPE,
4298  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_TIFS_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_TIFS_VBUSP_S_BRIDGE_BUSECC_GROUP_6_WIDTH },
4299  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_TIFS_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_TIFS_VBUSP_S_BRIDGE_BUSECC_GROUP_7_CHECKER_TYPE,
4300  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_TIFS_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_TIFS_VBUSP_S_BRIDGE_BUSECC_GROUP_7_WIDTH },
4301  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_TIFS_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_TIFS_VBUSP_S_BRIDGE_BUSECC_GROUP_8_CHECKER_TYPE,
4302  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_TIFS_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_TIFS_VBUSP_S_BRIDGE_BUSECC_GROUP_8_WIDTH },
4303  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_TIFS_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_TIFS_VBUSP_S_BRIDGE_BUSECC_GROUP_9_CHECKER_TYPE,
4304  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_TIFS_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_TIFS_VBUSP_S_BRIDGE_BUSECC_GROUP_9_WIDTH },
4305  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_TIFS_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_TIFS_VBUSP_S_BRIDGE_BUSECC_GROUP_10_CHECKER_TYPE,
4306  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_TIFS_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_TIFS_VBUSP_S_BRIDGE_BUSECC_GROUP_10_WIDTH },
4307  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_TIFS_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_TIFS_VBUSP_S_BRIDGE_BUSECC_GROUP_11_CHECKER_TYPE,
4308  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_TIFS_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_TIFS_VBUSP_S_BRIDGE_BUSECC_GROUP_11_WIDTH },
4309  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_TIFS_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_TIFS_VBUSP_S_BRIDGE_BUSECC_GROUP_12_CHECKER_TYPE,
4310  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_TIFS_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_TIFS_VBUSP_S_BRIDGE_BUSECC_GROUP_12_WIDTH },
4311 };
4312 
4318 static const SDL_GrpChkConfig_t SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_groupEntries[SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_MAX_NUM_CHECKERS] =
4319 {
4320  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_0_CHECKER_TYPE,
4321  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_0_WIDTH },
4322  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_1_CHECKER_TYPE,
4323  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_1_WIDTH },
4324  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_2_CHECKER_TYPE,
4325  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_2_WIDTH },
4326  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_3_CHECKER_TYPE,
4327  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_3_WIDTH },
4328  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_4_CHECKER_TYPE,
4329  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_4_WIDTH },
4330  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_5_CHECKER_TYPE,
4331  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_5_WIDTH },
4332  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_6_CHECKER_TYPE,
4333  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_6_WIDTH },
4334  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_7_CHECKER_TYPE,
4335  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_7_WIDTH },
4336  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_8_CHECKER_TYPE,
4337  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_8_WIDTH },
4338  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_9_CHECKER_TYPE,
4339  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_9_WIDTH },
4340  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_10_CHECKER_TYPE,
4341  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_10_WIDTH },
4342  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_11_CHECKER_TYPE,
4343  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_11_WIDTH },
4344  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_12_CHECKER_TYPE,
4345  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_12_WIDTH },
4346  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_13_CHECKER_TYPE,
4347  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_13_WIDTH },
4348  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_14_CHECKER_TYPE,
4349  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_14_WIDTH },
4350  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_15_CHECKER_TYPE,
4351  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_15_WIDTH },
4352  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_16_CHECKER_TYPE,
4353  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_16_WIDTH },
4354  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_17_CHECKER_TYPE,
4355  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_17_WIDTH },
4356  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_18_CHECKER_TYPE,
4357  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_18_WIDTH },
4358  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_19_CHECKER_TYPE,
4359  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_19_WIDTH },
4360  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_20_CHECKER_TYPE,
4361  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_20_WIDTH },
4362  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_21_CHECKER_TYPE,
4363  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_21_WIDTH },
4364  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_22_CHECKER_TYPE,
4365  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_22_WIDTH },
4366  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_23_CHECKER_TYPE,
4367  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_23_WIDTH },
4368  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_24_CHECKER_TYPE,
4369  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_24_WIDTH },
4370  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_25_CHECKER_TYPE,
4371  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_25_WIDTH },
4372  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_26_CHECKER_TYPE,
4373  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_26_WIDTH },
4374  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_27_CHECKER_TYPE,
4375  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_27_WIDTH },
4376  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_28_CHECKER_TYPE,
4377  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_28_WIDTH },
4378  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_29_CHECKER_TYPE,
4379  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_29_WIDTH },
4380  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_30_CHECKER_TYPE,
4381  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_30_WIDTH },
4382  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_31_CHECKER_TYPE,
4383  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_31_WIDTH },
4384  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_32_CHECKER_TYPE,
4385  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_32_WIDTH },
4386  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_33_CHECKER_TYPE,
4387  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_33_WIDTH },
4388  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_34_CHECKER_TYPE,
4389  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_34_WIDTH },
4390  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_35_CHECKER_TYPE,
4391  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_35_WIDTH },
4392  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_36_CHECKER_TYPE,
4393  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_36_WIDTH },
4394  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_37_CHECKER_TYPE,
4395  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_37_WIDTH },
4396  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_38_CHECKER_TYPE,
4397  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_38_WIDTH },
4398  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_39_CHECKER_TYPE,
4399  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_39_WIDTH },
4400  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_40_CHECKER_TYPE,
4401  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_40_WIDTH },
4402  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_41_CHECKER_TYPE,
4403  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_41_WIDTH },
4404  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_42_CHECKER_TYPE,
4405  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_42_WIDTH },
4406  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_43_CHECKER_TYPE,
4407  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_43_WIDTH },
4408  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_44_CHECKER_TYPE,
4409  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_44_WIDTH },
4410  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_45_CHECKER_TYPE,
4411  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_45_WIDTH },
4412  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_46_CHECKER_TYPE,
4413  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_46_WIDTH },
4414  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_47_CHECKER_TYPE,
4415  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_47_WIDTH },
4416  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_48_CHECKER_TYPE,
4417  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_48_WIDTH },
4418  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_49_CHECKER_TYPE,
4419  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_49_WIDTH },
4420  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_50_CHECKER_TYPE,
4421  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_50_WIDTH },
4422  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_51_CHECKER_TYPE,
4423  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_51_WIDTH },
4424  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_52_CHECKER_TYPE,
4425  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_52_WIDTH },
4426  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_53_CHECKER_TYPE,
4427  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_53_WIDTH },
4428  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_54_CHECKER_TYPE,
4429  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_54_WIDTH },
4430  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_55_CHECKER_TYPE,
4431  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_55_WIDTH },
4432  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_56_CHECKER_TYPE,
4433  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_56_WIDTH },
4434  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_57_CHECKER_TYPE,
4435  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_57_WIDTH },
4436  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_58_CHECKER_TYPE,
4437  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_58_WIDTH },
4438  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_59_CHECKER_TYPE,
4439  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_59_WIDTH },
4440  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_60_CHECKER_TYPE,
4441  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_60_WIDTH },
4442  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_61_CHECKER_TYPE,
4443  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_61_WIDTH },
4444 };
4445 
4451 static const SDL_GrpChkConfig_t SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_groupEntries[SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_MAX_NUM_CHECKERS] =
4452 {
4453  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_0_CHECKER_TYPE,
4454  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_0_WIDTH },
4455  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_1_CHECKER_TYPE,
4456  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_1_WIDTH },
4457  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_2_CHECKER_TYPE,
4458  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_2_WIDTH },
4459  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_3_CHECKER_TYPE,
4460  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_3_WIDTH },
4461  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_4_CHECKER_TYPE,
4462  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_4_WIDTH },
4463  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_5_CHECKER_TYPE,
4464  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_5_WIDTH },
4465  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_6_CHECKER_TYPE,
4466  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_6_WIDTH },
4467  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_7_CHECKER_TYPE,
4468  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_7_WIDTH },
4469  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_8_CHECKER_TYPE,
4470  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_8_WIDTH },
4471  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_9_CHECKER_TYPE,
4472  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_9_WIDTH },
4473  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_10_CHECKER_TYPE,
4474  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_10_WIDTH },
4475  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_11_CHECKER_TYPE,
4476  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_11_WIDTH },
4477  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_12_CHECKER_TYPE,
4478  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_12_WIDTH },
4479  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_13_CHECKER_TYPE,
4480  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_13_WIDTH },
4481  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_14_CHECKER_TYPE,
4482  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_14_WIDTH },
4483  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_15_CHECKER_TYPE,
4484  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_15_WIDTH },
4485  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_16_CHECKER_TYPE,
4486  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_16_WIDTH },
4487  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_17_CHECKER_TYPE,
4488  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_17_WIDTH },
4489  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_18_CHECKER_TYPE,
4490  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_18_WIDTH },
4491  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_19_CHECKER_TYPE,
4492  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_19_WIDTH },
4493  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_20_CHECKER_TYPE,
4494  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_20_WIDTH },
4495  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_21_CHECKER_TYPE,
4496  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_21_WIDTH },
4497  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_22_CHECKER_TYPE,
4498  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_22_WIDTH },
4499  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_23_CHECKER_TYPE,
4500  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_23_WIDTH },
4501  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_24_CHECKER_TYPE,
4502  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_24_WIDTH },
4503  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_25_CHECKER_TYPE,
4504  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_25_WIDTH },
4505 };
4506 
4512 static const SDL_GrpChkConfig_t SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_SRC_BUSECC_groupEntries[SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS] =
4513 {
4514  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_SRC_BUSECC_GROUP_0_CHECKER_TYPE,
4515  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_SRC_BUSECC_GROUP_0_WIDTH },
4516  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_SRC_BUSECC_GROUP_1_CHECKER_TYPE,
4517  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_SRC_BUSECC_GROUP_1_WIDTH },
4518  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_SRC_BUSECC_GROUP_2_CHECKER_TYPE,
4519  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_SRC_BUSECC_GROUP_2_WIDTH },
4520  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_SRC_BUSECC_GROUP_3_CHECKER_TYPE,
4521  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_SRC_BUSECC_GROUP_3_WIDTH },
4522  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_SRC_BUSECC_GROUP_4_CHECKER_TYPE,
4523  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_SRC_BUSECC_GROUP_4_WIDTH },
4524  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_SRC_BUSECC_GROUP_5_CHECKER_TYPE,
4525  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_SRC_BUSECC_GROUP_5_WIDTH },
4526  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_SRC_BUSECC_GROUP_6_CHECKER_TYPE,
4527  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_SRC_BUSECC_GROUP_6_WIDTH },
4528  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_SRC_BUSECC_GROUP_7_CHECKER_TYPE,
4529  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_SRC_BUSECC_GROUP_7_WIDTH },
4530  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_SRC_BUSECC_GROUP_8_CHECKER_TYPE,
4531  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_SRC_BUSECC_GROUP_8_WIDTH },
4532  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_SRC_BUSECC_GROUP_9_CHECKER_TYPE,
4533  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_SRC_BUSECC_GROUP_9_WIDTH },
4534  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_SRC_BUSECC_GROUP_10_CHECKER_TYPE,
4535  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_SRC_BUSECC_GROUP_10_WIDTH },
4536  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_SRC_BUSECC_GROUP_11_CHECKER_TYPE,
4537  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_SRC_BUSECC_GROUP_11_WIDTH },
4538  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_SRC_BUSECC_GROUP_12_CHECKER_TYPE,
4539  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_SRC_BUSECC_GROUP_12_WIDTH },
4540  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_SRC_BUSECC_GROUP_13_CHECKER_TYPE,
4541  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_SRC_BUSECC_GROUP_13_WIDTH },
4542  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_SRC_BUSECC_GROUP_14_CHECKER_TYPE,
4543  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_SRC_BUSECC_GROUP_14_WIDTH },
4544 };
4545 
4551 static const SDL_GrpChkConfig_t SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_DST_BUSECC_groupEntries[SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS] =
4552 {
4553  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_DST_BUSECC_GROUP_0_CHECKER_TYPE,
4554  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_DST_BUSECC_GROUP_0_WIDTH },
4555  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_DST_BUSECC_GROUP_1_CHECKER_TYPE,
4556  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_DST_BUSECC_GROUP_1_WIDTH },
4557  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_DST_BUSECC_GROUP_2_CHECKER_TYPE,
4558  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_DST_BUSECC_GROUP_2_WIDTH },
4559  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_DST_BUSECC_GROUP_3_CHECKER_TYPE,
4560  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_DST_BUSECC_GROUP_3_WIDTH },
4561 };
4562 
4568 static const SDL_GrpChkConfig_t SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_FW_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_groupEntries[SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_FW_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_MAX_NUM_CHECKERS] =
4569 {
4570  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_FW_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_0_CHECKER_TYPE,
4571  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_FW_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_0_WIDTH },
4572  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_FW_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_1_CHECKER_TYPE,
4573  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_FW_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_1_WIDTH },
4574  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_FW_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_2_CHECKER_TYPE,
4575  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_FW_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_2_WIDTH },
4576  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_FW_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_3_CHECKER_TYPE,
4577  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_FW_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_3_WIDTH },
4578  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_FW_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_4_CHECKER_TYPE,
4579  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_FW_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_4_WIDTH },
4580  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_FW_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_5_CHECKER_TYPE,
4581  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_FW_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_5_WIDTH },
4582  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_FW_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_6_CHECKER_TYPE,
4583  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_FW_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_6_WIDTH },
4584  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_FW_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_7_CHECKER_TYPE,
4585  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_FW_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_7_WIDTH },
4586  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_FW_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_8_CHECKER_TYPE,
4587  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_FW_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_8_WIDTH },
4588  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_FW_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_9_CHECKER_TYPE,
4589  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_FW_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_9_WIDTH },
4590  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_FW_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_10_CHECKER_TYPE,
4591  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_FW_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_10_WIDTH },
4592  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_FW_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_11_CHECKER_TYPE,
4593  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_FW_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_11_WIDTH },
4594 };
4595 
4601 static const SDL_GrpChkConfig_t SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_DMSS_CFG_SRC_BUSECC_groupEntries[SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_DMSS_CFG_SRC_BUSECC_MAX_NUM_CHECKERS] =
4602 {
4603  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_DMSS_CFG_SRC_BUSECC_GROUP_0_CHECKER_TYPE,
4604  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_DMSS_CFG_SRC_BUSECC_GROUP_0_WIDTH },
4605  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_DMSS_CFG_SRC_BUSECC_GROUP_1_CHECKER_TYPE,
4606  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_DMSS_CFG_SRC_BUSECC_GROUP_1_WIDTH },
4607  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_DMSS_CFG_SRC_BUSECC_GROUP_2_CHECKER_TYPE,
4608  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_DMSS_CFG_SRC_BUSECC_GROUP_2_WIDTH },
4609  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_DMSS_CFG_SRC_BUSECC_GROUP_3_CHECKER_TYPE,
4610  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_DMSS_CFG_SRC_BUSECC_GROUP_3_WIDTH },
4611  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_DMSS_CFG_SRC_BUSECC_GROUP_4_CHECKER_TYPE,
4612  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_DMSS_CFG_SRC_BUSECC_GROUP_4_WIDTH },
4613  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_DMSS_CFG_SRC_BUSECC_GROUP_5_CHECKER_TYPE,
4614  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_DMSS_CFG_SRC_BUSECC_GROUP_5_WIDTH },
4615  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_DMSS_CFG_SRC_BUSECC_GROUP_6_CHECKER_TYPE,
4616  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_DMSS_CFG_SRC_BUSECC_GROUP_6_WIDTH },
4617  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_DMSS_CFG_SRC_BUSECC_GROUP_7_CHECKER_TYPE,
4618  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_DMSS_CFG_SRC_BUSECC_GROUP_7_WIDTH },
4619  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_DMSS_CFG_SRC_BUSECC_GROUP_8_CHECKER_TYPE,
4620  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_DMSS_CFG_SRC_BUSECC_GROUP_8_WIDTH },
4621  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_DMSS_CFG_SRC_BUSECC_GROUP_9_CHECKER_TYPE,
4622  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_DMSS_CFG_SRC_BUSECC_GROUP_9_WIDTH },
4623  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_DMSS_CFG_SRC_BUSECC_GROUP_10_CHECKER_TYPE,
4624  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_DMSS_CFG_SRC_BUSECC_GROUP_10_WIDTH },
4625  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_DMSS_CFG_SRC_BUSECC_GROUP_11_CHECKER_TYPE,
4626  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_DMSS_CFG_SRC_BUSECC_GROUP_11_WIDTH },
4627  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_DMSS_CFG_SRC_BUSECC_GROUP_12_CHECKER_TYPE,
4628  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_DMSS_CFG_SRC_BUSECC_GROUP_12_WIDTH },
4629  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_DMSS_CFG_SRC_BUSECC_GROUP_13_CHECKER_TYPE,
4630  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_DMSS_CFG_SRC_BUSECC_GROUP_13_WIDTH },
4631  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_DMSS_CFG_SRC_BUSECC_GROUP_14_CHECKER_TYPE,
4632  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_DMSS_CFG_SRC_BUSECC_GROUP_14_WIDTH },
4633 };
4634 
4640 static const SDL_GrpChkConfig_t SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_DMSS_CFG_DST_BUSECC_groupEntries[SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_DMSS_CFG_DST_BUSECC_MAX_NUM_CHECKERS] =
4641 {
4642  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_DMSS_CFG_DST_BUSECC_GROUP_0_CHECKER_TYPE,
4643  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_DMSS_CFG_DST_BUSECC_GROUP_0_WIDTH },
4644  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_DMSS_CFG_DST_BUSECC_GROUP_1_CHECKER_TYPE,
4645  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_DMSS_CFG_DST_BUSECC_GROUP_1_WIDTH },
4646  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_DMSS_CFG_DST_BUSECC_GROUP_2_CHECKER_TYPE,
4647  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_DMSS_CFG_DST_BUSECC_GROUP_2_WIDTH },
4648  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_DMSS_CFG_DST_BUSECC_GROUP_3_CHECKER_TYPE,
4649  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_DMSS_CFG_DST_BUSECC_GROUP_3_WIDTH },
4650 };
4651 
4657 static const SDL_GrpChkConfig_t SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_PKTDMA_CRED_SRC_BUSECC_groupEntries[SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_PKTDMA_CRED_SRC_BUSECC_MAX_NUM_CHECKERS] =
4658 {
4659  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_PKTDMA_CRED_SRC_BUSECC_GROUP_0_CHECKER_TYPE,
4660  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_PKTDMA_CRED_SRC_BUSECC_GROUP_0_WIDTH },
4661  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_PKTDMA_CRED_SRC_BUSECC_GROUP_1_CHECKER_TYPE,
4662  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_PKTDMA_CRED_SRC_BUSECC_GROUP_1_WIDTH },
4663  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_PKTDMA_CRED_SRC_BUSECC_GROUP_2_CHECKER_TYPE,
4664  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_PKTDMA_CRED_SRC_BUSECC_GROUP_2_WIDTH },
4665  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_PKTDMA_CRED_SRC_BUSECC_GROUP_3_CHECKER_TYPE,
4666  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_PKTDMA_CRED_SRC_BUSECC_GROUP_3_WIDTH },
4667  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_PKTDMA_CRED_SRC_BUSECC_GROUP_4_CHECKER_TYPE,
4668  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_PKTDMA_CRED_SRC_BUSECC_GROUP_4_WIDTH },
4669  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_PKTDMA_CRED_SRC_BUSECC_GROUP_5_CHECKER_TYPE,
4670  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_PKTDMA_CRED_SRC_BUSECC_GROUP_5_WIDTH },
4671  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_PKTDMA_CRED_SRC_BUSECC_GROUP_6_CHECKER_TYPE,
4672  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_PKTDMA_CRED_SRC_BUSECC_GROUP_6_WIDTH },
4673  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_PKTDMA_CRED_SRC_BUSECC_GROUP_7_CHECKER_TYPE,
4674  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_PKTDMA_CRED_SRC_BUSECC_GROUP_7_WIDTH },
4675  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_PKTDMA_CRED_SRC_BUSECC_GROUP_8_CHECKER_TYPE,
4676  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_PKTDMA_CRED_SRC_BUSECC_GROUP_8_WIDTH },
4677  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_PKTDMA_CRED_SRC_BUSECC_GROUP_9_CHECKER_TYPE,
4678  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_PKTDMA_CRED_SRC_BUSECC_GROUP_9_WIDTH },
4679  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_PKTDMA_CRED_SRC_BUSECC_GROUP_10_CHECKER_TYPE,
4680  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_PKTDMA_CRED_SRC_BUSECC_GROUP_10_WIDTH },
4681  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_PKTDMA_CRED_SRC_BUSECC_GROUP_11_CHECKER_TYPE,
4682  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_PKTDMA_CRED_SRC_BUSECC_GROUP_11_WIDTH },
4683  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_PKTDMA_CRED_SRC_BUSECC_GROUP_12_CHECKER_TYPE,
4684  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_PKTDMA_CRED_SRC_BUSECC_GROUP_12_WIDTH },
4685  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_PKTDMA_CRED_SRC_BUSECC_GROUP_13_CHECKER_TYPE,
4686  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_PKTDMA_CRED_SRC_BUSECC_GROUP_13_WIDTH },
4687  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_PKTDMA_CRED_SRC_BUSECC_GROUP_14_CHECKER_TYPE,
4688  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_PKTDMA_CRED_SRC_BUSECC_GROUP_14_WIDTH },
4689 };
4690 
4696 static const SDL_GrpChkConfig_t SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_PKTDMA_CRED_DST_BUSECC_groupEntries[SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_PKTDMA_CRED_DST_BUSECC_MAX_NUM_CHECKERS] =
4697 {
4698  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_PKTDMA_CRED_DST_BUSECC_GROUP_0_CHECKER_TYPE,
4699  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_PKTDMA_CRED_DST_BUSECC_GROUP_0_WIDTH },
4700  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_PKTDMA_CRED_DST_BUSECC_GROUP_1_CHECKER_TYPE,
4701  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_PKTDMA_CRED_DST_BUSECC_GROUP_1_WIDTH },
4702  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_PKTDMA_CRED_DST_BUSECC_GROUP_2_CHECKER_TYPE,
4703  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_PKTDMA_CRED_DST_BUSECC_GROUP_2_WIDTH },
4704  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_PKTDMA_CRED_DST_BUSECC_GROUP_3_CHECKER_TYPE,
4705  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_PKTDMA_CRED_DST_BUSECC_GROUP_3_WIDTH },
4706 };
4707 
4712 static const SDL_MemConfig_t SDL_DMASS1_DMSS_CSI_AM62A_ECCAGGR_MemEntries[SDL_DMASS1_DMSS_CSI_AM62A_ECCAGGR_RAM_IDS_TOTAL_ENTRIES] =
4713 {
4714  { SDL_DMASS1_DMSS_CSI_AM62A_ECCAGGR_DMSS_CSI_AM62A_BCDMA_CFG_CONFIG_RAM_ID, 0u,
4715  SDL_DMASS1_DMSS_CSI_AM62A_ECCAGGR_DMSS_CSI_AM62A_BCDMA_CFG_CONFIG_RAM_SIZE, 4u,
4716  SDL_DMASS1_DMSS_CSI_AM62A_ECCAGGR_DMSS_CSI_AM62A_BCDMA_CFG_CONFIG_ROW_WIDTH, ((bool)false) },
4717  { SDL_DMASS1_DMSS_CSI_AM62A_ECCAGGR_DMSS_CSI_AM62A_BCDMA_CFG_STATE_RAM_ID, 0u,
4718  SDL_DMASS1_DMSS_CSI_AM62A_ECCAGGR_DMSS_CSI_AM62A_BCDMA_CFG_STATE_RAM_SIZE, 4u,
4719  SDL_DMASS1_DMSS_CSI_AM62A_ECCAGGR_DMSS_CSI_AM62A_BCDMA_CFG_STATE_ROW_WIDTH, ((bool)false) },
4720  { SDL_DMASS1_DMSS_CSI_AM62A_ECCAGGR_DMSS_CSI_AM62A_BCDMA_RPCFIFO_F0_RAM_ID, 0u,
4721  SDL_DMASS1_DMSS_CSI_AM62A_ECCAGGR_DMSS_CSI_AM62A_BCDMA_RPCFIFO_F0_RAM_SIZE, 4u,
4722  SDL_DMASS1_DMSS_CSI_AM62A_ECCAGGR_DMSS_CSI_AM62A_BCDMA_RPCFIFO_F0_ROW_WIDTH, ((bool)false) },
4723  { SDL_DMASS1_DMSS_CSI_AM62A_ECCAGGR_DMSS_CSI_AM62A_BCDMA_RPCFIFO_F1_RAM_ID, 0u,
4724  SDL_DMASS1_DMSS_CSI_AM62A_ECCAGGR_DMSS_CSI_AM62A_BCDMA_RPCFIFO_F1_RAM_SIZE, 4u,
4725  SDL_DMASS1_DMSS_CSI_AM62A_ECCAGGR_DMSS_CSI_AM62A_BCDMA_RPCFIFO_F1_ROW_WIDTH, ((bool)false) },
4726  { SDL_DMASS1_DMSS_CSI_AM62A_ECCAGGR_DMSS_CSI_AM62A_BCDMA_RPCFIFO_WC_RAM_ID, 0u,
4727  SDL_DMASS1_DMSS_CSI_AM62A_ECCAGGR_DMSS_CSI_AM62A_BCDMA_RPCFIFO_WC_RAM_SIZE, 4u,
4728  SDL_DMASS1_DMSS_CSI_AM62A_ECCAGGR_DMSS_CSI_AM62A_BCDMA_RPCFIFO_WC_ROW_WIDTH, ((bool)false) },
4729  { SDL_DMASS1_DMSS_CSI_AM62A_ECCAGGR_DMSS_CSI_AM62A_BCDMA_STATS_STSR0_RAM_ID, 0u,
4730  SDL_DMASS1_DMSS_CSI_AM62A_ECCAGGR_DMSS_CSI_AM62A_BCDMA_STATS_STSR0_RAM_SIZE, 4u,
4731  SDL_DMASS1_DMSS_CSI_AM62A_ECCAGGR_DMSS_CSI_AM62A_BCDMA_STATS_STSR0_ROW_WIDTH, ((bool)false) },
4732  { SDL_DMASS1_DMSS_CSI_AM62A_ECCAGGR_DMSS_CSI_AM62A_BCDMA_RINGOCC_CNTR_RAM_ID, 0u,
4733  SDL_DMASS1_DMSS_CSI_AM62A_ECCAGGR_DMSS_CSI_AM62A_BCDMA_RINGOCC_CNTR_RAM_SIZE, 4u,
4734  SDL_DMASS1_DMSS_CSI_AM62A_ECCAGGR_DMSS_CSI_AM62A_BCDMA_RINGOCC_CNTR_ROW_WIDTH, ((bool)false) },
4735  { SDL_DMASS1_DMSS_CSI_AM62A_ECCAGGR_DMSS_CSI_AM62A_INTAGGR_STATREG_SR_SPRAM_8X128_SWW_SR_RAM_ID, 0u,
4736  SDL_DMASS1_DMSS_CSI_AM62A_ECCAGGR_DMSS_CSI_AM62A_INTAGGR_STATREG_SR_SPRAM_8X128_SWW_SR_RAM_SIZE, 4u,
4737  SDL_DMASS1_DMSS_CSI_AM62A_ECCAGGR_DMSS_CSI_AM62A_INTAGGR_STATREG_SR_SPRAM_8X128_SWW_SR_ROW_WIDTH, ((bool)false) },
4738  { SDL_DMASS1_DMSS_CSI_AM62A_ECCAGGR_DMSS_CSI_AM62A_INTAGGR_COMMON_IM_TPRAM_153X34_SWW_SR_RAM_ID, 0u,
4739  SDL_DMASS1_DMSS_CSI_AM62A_ECCAGGR_DMSS_CSI_AM62A_INTAGGR_COMMON_IM_TPRAM_153X34_SWW_SR_RAM_SIZE, 4u,
4740  SDL_DMASS1_DMSS_CSI_AM62A_ECCAGGR_DMSS_CSI_AM62A_INTAGGR_COMMON_IM_TPRAM_153X34_SWW_SR_ROW_WIDTH, ((bool)false) },
4741 };
4742 
4747 static const SDL_MemConfig_t SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MemEntries[SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES] =
4748 {
4749  { SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_ECC0_RAM_ID, 0x79140000u,
4750  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_ECC0_RAM_SIZE, 4u,
4751  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_ECC0_ROW_WIDTH, ((bool)true) },
4752 };
4753 
4759 static const SDL_GrpChkConfig_t SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_groupEntries[SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_MAX_NUM_CHECKERS] =
4760 {
4761  { SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
4762  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_0_WIDTH },
4763  { SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
4764  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_1_WIDTH },
4765  { SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
4766  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_2_WIDTH },
4767  { SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
4768  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_3_WIDTH },
4769  { SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
4770  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_4_WIDTH },
4771  { SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
4772  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_5_WIDTH },
4773  { SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
4774  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_6_WIDTH },
4775  { SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
4776  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_7_WIDTH },
4777  { SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
4778  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_8_WIDTH },
4779  { SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
4780  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_9_WIDTH },
4781  { SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
4782  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_10_WIDTH },
4783  { SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
4784  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_11_WIDTH },
4785  { SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
4786  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_12_WIDTH },
4787  { SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
4788  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_13_WIDTH },
4789  { SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
4790  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_14_WIDTH },
4791  { SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
4792  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_15_WIDTH },
4793  { SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
4794  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_16_WIDTH },
4795  { SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
4796  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_17_WIDTH },
4797  { SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
4798  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_18_WIDTH },
4799  { SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
4800  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_19_WIDTH },
4801  { SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
4802  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_20_WIDTH },
4803  { SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
4804  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_21_WIDTH },
4805  { SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
4806  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_22_WIDTH },
4807  { SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
4808  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_23_WIDTH },
4809  { SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
4810  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_24_WIDTH },
4811  { SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
4812  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_25_WIDTH },
4813  { SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
4814  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_26_WIDTH },
4815  { SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
4816  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_27_WIDTH },
4817  { SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
4818  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_28_WIDTH },
4819  { SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
4820  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_29_WIDTH },
4821  { SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
4822  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_30_WIDTH },
4823  { SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
4824  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_31_WIDTH },
4825  { SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
4826  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_32_WIDTH },
4827  { SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_33_CHECKER_TYPE,
4828  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_33_WIDTH },
4829  { SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_34_CHECKER_TYPE,
4830  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_34_WIDTH },
4831  { SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_35_CHECKER_TYPE,
4832  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_35_WIDTH },
4833  { SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_36_CHECKER_TYPE,
4834  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_36_WIDTH },
4835  { SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_37_CHECKER_TYPE,
4836  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_37_WIDTH },
4837  { SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_38_CHECKER_TYPE,
4838  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_38_WIDTH },
4839  { SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_39_CHECKER_TYPE,
4840  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_39_WIDTH },
4841  { SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_40_CHECKER_TYPE,
4842  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_40_WIDTH },
4843  { SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_41_CHECKER_TYPE,
4844  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_41_WIDTH },
4845  { SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_42_CHECKER_TYPE,
4846  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_42_WIDTH },
4847  { SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_43_CHECKER_TYPE,
4848  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_43_WIDTH },
4849  { SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_44_CHECKER_TYPE,
4850  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_44_WIDTH },
4851  { SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_45_CHECKER_TYPE,
4852  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_45_WIDTH },
4853  { SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_46_CHECKER_TYPE,
4854  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_46_WIDTH },
4855  { SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_47_CHECKER_TYPE,
4856  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_47_WIDTH },
4857  { SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_48_CHECKER_TYPE,
4858  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_48_WIDTH },
4859  { SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_49_CHECKER_TYPE,
4860  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_49_WIDTH },
4861  { SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_50_CHECKER_TYPE,
4862  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_50_WIDTH },
4863  { SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_51_CHECKER_TYPE,
4864  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_51_WIDTH },
4865  { SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_52_CHECKER_TYPE,
4866  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_52_WIDTH },
4867  { SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_53_CHECKER_TYPE,
4868  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_53_WIDTH },
4869  { SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_54_CHECKER_TYPE,
4870  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_54_WIDTH },
4871  { SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_55_CHECKER_TYPE,
4872  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_55_WIDTH },
4873  { SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_56_CHECKER_TYPE,
4874  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_56_WIDTH },
4875  { SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_57_CHECKER_TYPE,
4876  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_57_WIDTH },
4877  { SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_58_CHECKER_TYPE,
4878  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_58_WIDTH },
4879  { SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_59_CHECKER_TYPE,
4880  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_59_WIDTH },
4881  { SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_60_CHECKER_TYPE,
4882  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_60_WIDTH },
4883  { SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_61_CHECKER_TYPE,
4884  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_61_WIDTH },
4885  { SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_62_CHECKER_TYPE,
4886  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_62_WIDTH },
4887  { SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_63_CHECKER_TYPE,
4888  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_63_WIDTH },
4889  { SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_64_CHECKER_TYPE,
4890  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_64_WIDTH },
4891 };
4892 
4898 static const SDL_GrpChkConfig_t SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_ECC_AGGR_EDC_CTRL_groupEntries[SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_ECC_AGGR_EDC_CTRL_MAX_NUM_CHECKERS] =
4899 {
4900  { SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_ECC_AGGR_EDC_CTRL_GROUP_0_CHECKER_TYPE,
4901  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_ECC_AGGR_EDC_CTRL_GROUP_0_WIDTH },
4902  { SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_ECC_AGGR_EDC_CTRL_GROUP_1_CHECKER_TYPE,
4903  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_ECC_AGGR_EDC_CTRL_GROUP_1_WIDTH },
4904  { SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_ECC_AGGR_EDC_CTRL_GROUP_2_CHECKER_TYPE,
4905  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_ECC_AGGR_EDC_CTRL_GROUP_2_WIDTH },
4906  { SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_ECC_AGGR_EDC_CTRL_GROUP_3_CHECKER_TYPE,
4907  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_ECC_AGGR_EDC_CTRL_GROUP_3_WIDTH },
4908  { SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_ECC_AGGR_EDC_CTRL_GROUP_4_CHECKER_TYPE,
4909  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_ECC_AGGR_EDC_CTRL_GROUP_4_WIDTH },
4910  { SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_ECC_AGGR_EDC_CTRL_GROUP_5_CHECKER_TYPE,
4911  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_ECC_AGGR_EDC_CTRL_GROUP_5_WIDTH },
4912 };
4913 
4919 static const SDL_GrpChkConfig_t SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_ECCAGGR_EDC_CTRL_groupEntries[SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_ECCAGGR_EDC_CTRL_MAX_NUM_CHECKERS] =
4920 {
4921  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_ECCAGGR_EDC_CTRL_GROUP_0_CHECKER_TYPE,
4922  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_ECCAGGR_EDC_CTRL_GROUP_0_WIDTH },
4923  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_ECCAGGR_EDC_CTRL_GROUP_1_CHECKER_TYPE,
4924  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_ECCAGGR_EDC_CTRL_GROUP_1_WIDTH },
4925  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_ECCAGGR_EDC_CTRL_GROUP_2_CHECKER_TYPE,
4926  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_ECCAGGR_EDC_CTRL_GROUP_2_WIDTH },
4927  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_ECCAGGR_EDC_CTRL_GROUP_3_CHECKER_TYPE,
4928  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_ECCAGGR_EDC_CTRL_GROUP_3_WIDTH },
4929  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_ECCAGGR_EDC_CTRL_GROUP_4_CHECKER_TYPE,
4930  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_ECCAGGR_EDC_CTRL_GROUP_4_WIDTH },
4931  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_ECCAGGR_EDC_CTRL_GROUP_5_CHECKER_TYPE,
4932  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_ECCAGGR_EDC_CTRL_GROUP_5_WIDTH },
4933 };
4934 
4940 static const SDL_GrpChkConfig_t SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_groupEntries[SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_MAX_NUM_CHECKERS] =
4941 {
4942  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
4943  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_0_WIDTH },
4944  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
4945  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_1_WIDTH },
4946  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
4947  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_2_WIDTH },
4948  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
4949  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_3_WIDTH },
4950  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
4951  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_4_WIDTH },
4952  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
4953  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_5_WIDTH },
4954  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
4955  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_6_WIDTH },
4956  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
4957  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_7_WIDTH },
4958  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
4959  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_8_WIDTH },
4960  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
4961  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_9_WIDTH },
4962  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
4963  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_10_WIDTH },
4964  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
4965  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_11_WIDTH },
4966  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
4967  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_12_WIDTH },
4968  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
4969  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_13_WIDTH },
4970  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
4971  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_14_WIDTH },
4972  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
4973  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_15_WIDTH },
4974  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
4975  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_16_WIDTH },
4976  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
4977  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_17_WIDTH },
4978  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
4979  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_18_WIDTH },
4980  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
4981  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_19_WIDTH },
4982  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
4983  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_20_WIDTH },
4984  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
4985  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_21_WIDTH },
4986  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
4987  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_22_WIDTH },
4988  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
4989  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_23_WIDTH },
4990  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
4991  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_24_WIDTH },
4992  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
4993  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_25_WIDTH },
4994  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
4995  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_26_WIDTH },
4996  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
4997  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_27_WIDTH },
4998  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
4999  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_28_WIDTH },
5000  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
5001  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_29_WIDTH },
5002  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
5003  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_30_WIDTH },
5004  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
5005  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_31_WIDTH },
5006  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
5007  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_32_WIDTH },
5008  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_33_CHECKER_TYPE,
5009  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_33_WIDTH },
5010  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_34_CHECKER_TYPE,
5011  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_34_WIDTH },
5012  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_35_CHECKER_TYPE,
5013  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_35_WIDTH },
5014  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_36_CHECKER_TYPE,
5015  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_36_WIDTH },
5016  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_37_CHECKER_TYPE,
5017  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_37_WIDTH },
5018  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_38_CHECKER_TYPE,
5019  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_38_WIDTH },
5020  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_39_CHECKER_TYPE,
5021  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_39_WIDTH },
5022  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_40_CHECKER_TYPE,
5023  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_40_WIDTH },
5024  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_41_CHECKER_TYPE,
5025  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_41_WIDTH },
5026  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_42_CHECKER_TYPE,
5027  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_42_WIDTH },
5028  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_43_CHECKER_TYPE,
5029  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_43_WIDTH },
5030  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_44_CHECKER_TYPE,
5031  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_44_WIDTH },
5032  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_45_CHECKER_TYPE,
5033  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_45_WIDTH },
5034  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_46_CHECKER_TYPE,
5035  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_46_WIDTH },
5036  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_47_CHECKER_TYPE,
5037  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_47_WIDTH },
5038  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_48_CHECKER_TYPE,
5039  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_48_WIDTH },
5040  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_49_CHECKER_TYPE,
5041  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_49_WIDTH },
5042  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_50_CHECKER_TYPE,
5043  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_50_WIDTH },
5044  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_51_CHECKER_TYPE,
5045  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_51_WIDTH },
5046  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_52_CHECKER_TYPE,
5047  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_52_WIDTH },
5048  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_53_CHECKER_TYPE,
5049  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_53_WIDTH },
5050  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_54_CHECKER_TYPE,
5051  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_54_WIDTH },
5052  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_55_CHECKER_TYPE,
5053  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_55_WIDTH },
5054  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_56_CHECKER_TYPE,
5055  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_56_WIDTH },
5056  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_57_CHECKER_TYPE,
5057  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_57_WIDTH },
5058  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_58_CHECKER_TYPE,
5059  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_58_WIDTH },
5060  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_59_CHECKER_TYPE,
5061  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_59_WIDTH },
5062  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_60_CHECKER_TYPE,
5063  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_60_WIDTH },
5064  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_61_CHECKER_TYPE,
5065  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_61_WIDTH },
5066  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_62_CHECKER_TYPE,
5067  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_62_WIDTH },
5068  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_63_CHECKER_TYPE,
5069  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_63_WIDTH },
5070  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_64_CHECKER_TYPE,
5071  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_64_WIDTH },
5072  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_65_CHECKER_TYPE,
5073  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_65_WIDTH },
5074  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_66_CHECKER_TYPE,
5075  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_66_WIDTH },
5076  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_67_CHECKER_TYPE,
5077  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_67_WIDTH },
5078  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_68_CHECKER_TYPE,
5079  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_68_WIDTH },
5080  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_69_CHECKER_TYPE,
5081  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_69_WIDTH },
5082  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_70_CHECKER_TYPE,
5083  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_70_WIDTH },
5084  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_71_CHECKER_TYPE,
5085  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_71_WIDTH },
5086  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_72_CHECKER_TYPE,
5087  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_72_WIDTH },
5088  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_73_CHECKER_TYPE,
5089  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_73_WIDTH },
5090  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_74_CHECKER_TYPE,
5091  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_74_WIDTH },
5092  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_75_CHECKER_TYPE,
5093  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_75_WIDTH },
5094  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_76_CHECKER_TYPE,
5095  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_76_WIDTH },
5096  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_77_CHECKER_TYPE,
5097  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_77_WIDTH },
5098  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_78_CHECKER_TYPE,
5099  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_78_WIDTH },
5100  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_79_CHECKER_TYPE,
5101  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_79_WIDTH },
5102  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_80_CHECKER_TYPE,
5103  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_80_WIDTH },
5104  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_81_CHECKER_TYPE,
5105  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_81_WIDTH },
5106  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_82_CHECKER_TYPE,
5107  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_82_WIDTH },
5108  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_83_CHECKER_TYPE,
5109  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_83_WIDTH },
5110  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_84_CHECKER_TYPE,
5111  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_84_WIDTH },
5112  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_85_CHECKER_TYPE,
5113  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_85_WIDTH },
5114  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_86_CHECKER_TYPE,
5115  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_86_WIDTH },
5116  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_87_CHECKER_TYPE,
5117  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_87_WIDTH },
5118  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_88_CHECKER_TYPE,
5119  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_88_WIDTH },
5120  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_89_CHECKER_TYPE,
5121  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_89_WIDTH },
5122  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_90_CHECKER_TYPE,
5123  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_90_WIDTH },
5124  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_91_CHECKER_TYPE,
5125  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_91_WIDTH },
5126  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_92_CHECKER_TYPE,
5127  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_92_WIDTH },
5128  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_93_CHECKER_TYPE,
5129  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_93_WIDTH },
5130  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_94_CHECKER_TYPE,
5131  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_94_WIDTH },
5132  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_95_CHECKER_TYPE,
5133  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_95_WIDTH },
5134  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_96_CHECKER_TYPE,
5135  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_96_WIDTH },
5136  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_97_CHECKER_TYPE,
5137  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_97_WIDTH },
5138  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_98_CHECKER_TYPE,
5139  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_98_WIDTH },
5140  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_99_CHECKER_TYPE,
5141  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_99_WIDTH },
5142  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_100_CHECKER_TYPE,
5143  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_100_WIDTH },
5144  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_101_CHECKER_TYPE,
5145  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_101_WIDTH },
5146  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_102_CHECKER_TYPE,
5147  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_102_WIDTH },
5148  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_103_CHECKER_TYPE,
5149  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_103_WIDTH },
5150  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_104_CHECKER_TYPE,
5151  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_104_WIDTH },
5152  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_105_CHECKER_TYPE,
5153  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_105_WIDTH },
5154  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_106_CHECKER_TYPE,
5155  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_106_WIDTH },
5156  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_107_CHECKER_TYPE,
5157  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_107_WIDTH },
5158  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_108_CHECKER_TYPE,
5159  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_108_WIDTH },
5160  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_109_CHECKER_TYPE,
5161  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_109_WIDTH },
5162  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_110_CHECKER_TYPE,
5163  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_110_WIDTH },
5164  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_111_CHECKER_TYPE,
5165  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_111_WIDTH },
5166  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_112_CHECKER_TYPE,
5167  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_112_WIDTH },
5168  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_113_CHECKER_TYPE,
5169  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_113_WIDTH },
5170  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_114_CHECKER_TYPE,
5171  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_114_WIDTH },
5172  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_115_CHECKER_TYPE,
5173  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_115_WIDTH },
5174  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_116_CHECKER_TYPE,
5175  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_116_WIDTH },
5176  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_117_CHECKER_TYPE,
5177  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_117_WIDTH },
5178  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_118_CHECKER_TYPE,
5179  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_118_WIDTH },
5180  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_119_CHECKER_TYPE,
5181  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_119_WIDTH },
5182  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_120_CHECKER_TYPE,
5183  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_120_WIDTH },
5184  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_121_CHECKER_TYPE,
5185  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_121_WIDTH },
5186  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_122_CHECKER_TYPE,
5187  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_122_WIDTH },
5188  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_123_CHECKER_TYPE,
5189  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_123_WIDTH },
5190  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_124_CHECKER_TYPE,
5191  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_124_WIDTH },
5192  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_125_CHECKER_TYPE,
5193  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_125_WIDTH },
5194  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_126_CHECKER_TYPE,
5195  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_126_WIDTH },
5196  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_127_CHECKER_TYPE,
5197  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_127_WIDTH },
5198  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_128_CHECKER_TYPE,
5199  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_128_WIDTH },
5200  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_129_CHECKER_TYPE,
5201  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_129_WIDTH },
5202  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_130_CHECKER_TYPE,
5203  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_130_WIDTH },
5204  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_131_CHECKER_TYPE,
5205  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_131_WIDTH },
5206  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_132_CHECKER_TYPE,
5207  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_132_WIDTH },
5208  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_133_CHECKER_TYPE,
5209  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_133_WIDTH },
5210  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_134_CHECKER_TYPE,
5211  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_134_WIDTH },
5212  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_135_CHECKER_TYPE,
5213  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_135_WIDTH },
5214  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_136_CHECKER_TYPE,
5215  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_136_WIDTH },
5216  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_137_CHECKER_TYPE,
5217  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_137_WIDTH },
5218  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_138_CHECKER_TYPE,
5219  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_138_WIDTH },
5220  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_139_CHECKER_TYPE,
5221  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_139_WIDTH },
5222  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_140_CHECKER_TYPE,
5223  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_140_WIDTH },
5224  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_141_CHECKER_TYPE,
5225  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_141_WIDTH },
5226  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_142_CHECKER_TYPE,
5227  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_142_WIDTH },
5228  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_143_CHECKER_TYPE,
5229  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_143_WIDTH },
5230  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_144_CHECKER_TYPE,
5231  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_144_WIDTH },
5232  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_145_CHECKER_TYPE,
5233  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_145_WIDTH },
5234  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_146_CHECKER_TYPE,
5235  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_146_WIDTH },
5236  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_147_CHECKER_TYPE,
5237  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_147_WIDTH },
5238  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_148_CHECKER_TYPE,
5239  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_148_WIDTH },
5240  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_149_CHECKER_TYPE,
5241  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_149_WIDTH },
5242  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_150_CHECKER_TYPE,
5243  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_150_WIDTH },
5244  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_151_CHECKER_TYPE,
5245  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_151_WIDTH },
5246  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_152_CHECKER_TYPE,
5247  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_152_WIDTH },
5248  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_153_CHECKER_TYPE,
5249  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_153_WIDTH },
5250  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_154_CHECKER_TYPE,
5251  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_154_WIDTH },
5252  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_155_CHECKER_TYPE,
5253  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_155_WIDTH },
5254  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_156_CHECKER_TYPE,
5255  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_156_WIDTH },
5256  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_157_CHECKER_TYPE,
5257  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_157_WIDTH },
5258  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_158_CHECKER_TYPE,
5259  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_158_WIDTH },
5260  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_159_CHECKER_TYPE,
5261  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_159_WIDTH },
5262  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_160_CHECKER_TYPE,
5263  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_160_WIDTH },
5264  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_161_CHECKER_TYPE,
5265  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_161_WIDTH },
5266  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_162_CHECKER_TYPE,
5267  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_162_WIDTH },
5268  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_163_CHECKER_TYPE,
5269  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_163_WIDTH },
5270  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_164_CHECKER_TYPE,
5271  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_164_WIDTH },
5272  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_165_CHECKER_TYPE,
5273  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_165_WIDTH },
5274  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_166_CHECKER_TYPE,
5275  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_166_WIDTH },
5276  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_167_CHECKER_TYPE,
5277  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_167_WIDTH },
5278  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_168_CHECKER_TYPE,
5279  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_168_WIDTH },
5280  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_169_CHECKER_TYPE,
5281  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_169_WIDTH },
5282  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_170_CHECKER_TYPE,
5283  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_170_WIDTH },
5284 };
5285 
5291 static const SDL_GrpChkConfig_t SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_VBUSP_P2P_BRIDGE_EDC_CTRL_0_groupEntries[SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_VBUSP_P2P_BRIDGE_EDC_CTRL_0_MAX_NUM_CHECKERS] =
5292 {
5293  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_VBUSP_P2P_BRIDGE_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
5294  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_VBUSP_P2P_BRIDGE_EDC_CTRL_0_GROUP_0_WIDTH },
5295  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_VBUSP_P2P_BRIDGE_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
5296  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_VBUSP_P2P_BRIDGE_EDC_CTRL_0_GROUP_1_WIDTH },
5297  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_VBUSP_P2P_BRIDGE_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
5298  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_VBUSP_P2P_BRIDGE_EDC_CTRL_0_GROUP_2_WIDTH },
5299 };
5300 
5306 static const SDL_GrpChkConfig_t SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_groupEntries[SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_MAX_NUM_CHECKERS] =
5307 {
5308  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
5309  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_0_WIDTH },
5310  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
5311  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_1_WIDTH },
5312  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
5313  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_2_WIDTH },
5314  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
5315  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_3_WIDTH },
5316  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
5317  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_4_WIDTH },
5318  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
5319  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_5_WIDTH },
5320  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
5321  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_6_WIDTH },
5322  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
5323  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_7_WIDTH },
5324  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
5325  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_8_WIDTH },
5326  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
5327  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_9_WIDTH },
5328  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
5329  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_10_WIDTH },
5330  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
5331  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_11_WIDTH },
5332  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
5333  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_12_WIDTH },
5334  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
5335  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_13_WIDTH },
5336  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
5337  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_14_WIDTH },
5338  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
5339  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_15_WIDTH },
5340  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
5341  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_16_WIDTH },
5342  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
5343  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_17_WIDTH },
5344  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
5345  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_18_WIDTH },
5346  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
5347  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_19_WIDTH },
5348  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
5349  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_20_WIDTH },
5350  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
5351  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_21_WIDTH },
5352  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
5353  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_22_WIDTH },
5354  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
5355  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_23_WIDTH },
5356  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
5357  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_24_WIDTH },
5358  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
5359  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_25_WIDTH },
5360  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
5361  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_26_WIDTH },
5362  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
5363  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_27_WIDTH },
5364  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
5365  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_28_WIDTH },
5366  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
5367  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_29_WIDTH },
5368  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
5369  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_30_WIDTH },
5370  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
5371  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_31_WIDTH },
5372  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
5373  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_32_WIDTH },
5374  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_33_CHECKER_TYPE,
5375  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_33_WIDTH },
5376  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_34_CHECKER_TYPE,
5377  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_34_WIDTH },
5378  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_35_CHECKER_TYPE,
5379  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_35_WIDTH },
5380  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_36_CHECKER_TYPE,
5381  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_36_WIDTH },
5382  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_37_CHECKER_TYPE,
5383  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_37_WIDTH },
5384  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_38_CHECKER_TYPE,
5385  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_38_WIDTH },
5386  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_39_CHECKER_TYPE,
5387  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_39_WIDTH },
5388  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_40_CHECKER_TYPE,
5389  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_40_WIDTH },
5390  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_41_CHECKER_TYPE,
5391  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_41_WIDTH },
5392  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_42_CHECKER_TYPE,
5393  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_42_WIDTH },
5394  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_43_CHECKER_TYPE,
5395  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_43_WIDTH },
5396  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_44_CHECKER_TYPE,
5397  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_44_WIDTH },
5398  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_45_CHECKER_TYPE,
5399  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_45_WIDTH },
5400  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_46_CHECKER_TYPE,
5401  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_46_WIDTH },
5402  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_47_CHECKER_TYPE,
5403  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_47_WIDTH },
5404  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_48_CHECKER_TYPE,
5405  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_48_WIDTH },
5406  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_49_CHECKER_TYPE,
5407  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_49_WIDTH },
5408 };
5409 
5415 static const SDL_GrpChkConfig_t SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_ISAM67_DM_MCU_ECC_AGGR_WKUP_1_CFG_P2P_BRIDGE_ISAM67_DM_MCU_ECC_AGGR_WKUP_1_CFG_BRIDGE_DST_BUSECC_groupEntries[SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_ISAM67_DM_MCU_ECC_AGGR_WKUP_1_CFG_P2P_BRIDGE_ISAM67_DM_MCU_ECC_AGGR_WKUP_1_CFG_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS] =
5416 {
5417  { SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_ISAM67_DM_MCU_ECC_AGGR_WKUP_1_CFG_P2P_BRIDGE_ISAM67_DM_MCU_ECC_AGGR_WKUP_1_CFG_BRIDGE_DST_BUSECC_GROUP_0_CHECKER_TYPE,
5418  SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_ISAM67_DM_MCU_ECC_AGGR_WKUP_1_CFG_P2P_BRIDGE_ISAM67_DM_MCU_ECC_AGGR_WKUP_1_CFG_BRIDGE_DST_BUSECC_GROUP_0_WIDTH },
5419  { SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_ISAM67_DM_MCU_ECC_AGGR_WKUP_1_CFG_P2P_BRIDGE_ISAM67_DM_MCU_ECC_AGGR_WKUP_1_CFG_BRIDGE_DST_BUSECC_GROUP_1_CHECKER_TYPE,
5420  SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_ISAM67_DM_MCU_ECC_AGGR_WKUP_1_CFG_P2P_BRIDGE_ISAM67_DM_MCU_ECC_AGGR_WKUP_1_CFG_BRIDGE_DST_BUSECC_GROUP_1_WIDTH },
5421  { SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_ISAM67_DM_MCU_ECC_AGGR_WKUP_1_CFG_P2P_BRIDGE_ISAM67_DM_MCU_ECC_AGGR_WKUP_1_CFG_BRIDGE_DST_BUSECC_GROUP_2_CHECKER_TYPE,
5422  SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_ISAM67_DM_MCU_ECC_AGGR_WKUP_1_CFG_P2P_BRIDGE_ISAM67_DM_MCU_ECC_AGGR_WKUP_1_CFG_BRIDGE_DST_BUSECC_GROUP_2_WIDTH },
5423  { SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_ISAM67_DM_MCU_ECC_AGGR_WKUP_1_CFG_P2P_BRIDGE_ISAM67_DM_MCU_ECC_AGGR_WKUP_1_CFG_BRIDGE_DST_BUSECC_GROUP_3_CHECKER_TYPE,
5424  SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_ISAM67_DM_MCU_ECC_AGGR_WKUP_1_CFG_P2P_BRIDGE_ISAM67_DM_MCU_ECC_AGGR_WKUP_1_CFG_BRIDGE_DST_BUSECC_GROUP_3_WIDTH },
5425  { SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_ISAM67_DM_MCU_ECC_AGGR_WKUP_1_CFG_P2P_BRIDGE_ISAM67_DM_MCU_ECC_AGGR_WKUP_1_CFG_BRIDGE_DST_BUSECC_GROUP_4_CHECKER_TYPE,
5426  SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_ISAM67_DM_MCU_ECC_AGGR_WKUP_1_CFG_P2P_BRIDGE_ISAM67_DM_MCU_ECC_AGGR_WKUP_1_CFG_BRIDGE_DST_BUSECC_GROUP_4_WIDTH },
5427  { SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_ISAM67_DM_MCU_ECC_AGGR_WKUP_1_CFG_P2P_BRIDGE_ISAM67_DM_MCU_ECC_AGGR_WKUP_1_CFG_BRIDGE_DST_BUSECC_GROUP_5_CHECKER_TYPE,
5428  SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_ISAM67_DM_MCU_ECC_AGGR_WKUP_1_CFG_P2P_BRIDGE_ISAM67_DM_MCU_ECC_AGGR_WKUP_1_CFG_BRIDGE_DST_BUSECC_GROUP_5_WIDTH },
5429  { SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_ISAM67_DM_MCU_ECC_AGGR_WKUP_1_CFG_P2P_BRIDGE_ISAM67_DM_MCU_ECC_AGGR_WKUP_1_CFG_BRIDGE_DST_BUSECC_GROUP_6_CHECKER_TYPE,
5430  SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_ISAM67_DM_MCU_ECC_AGGR_WKUP_1_CFG_P2P_BRIDGE_ISAM67_DM_MCU_ECC_AGGR_WKUP_1_CFG_BRIDGE_DST_BUSECC_GROUP_6_WIDTH },
5431 };
5432 
5438 static const SDL_GrpChkConfig_t SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_groupEntries[SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS] =
5439 {
5440  { SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
5441  SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
5442  { SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
5443  SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
5444  { SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
5445  SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
5446  { SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
5447  SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
5448  { SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
5449  SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
5450  { SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_5_CHECKER_TYPE,
5451  SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_5_WIDTH },
5452  { SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_6_CHECKER_TYPE,
5453  SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_6_WIDTH },
5454  { SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_7_CHECKER_TYPE,
5455  SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_7_WIDTH },
5456  { SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_8_CHECKER_TYPE,
5457  SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_8_WIDTH },
5458  { SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_9_CHECKER_TYPE,
5459  SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_9_WIDTH },
5460  { SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_10_CHECKER_TYPE,
5461  SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_10_WIDTH },
5462  { SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_11_CHECKER_TYPE,
5463  SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_11_WIDTH },
5464  { SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_12_CHECKER_TYPE,
5465  SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_12_WIDTH },
5466  { SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_13_CHECKER_TYPE,
5467  SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_13_WIDTH },
5468  { SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_14_CHECKER_TYPE,
5469  SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_14_WIDTH },
5470  { SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_15_CHECKER_TYPE,
5471  SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_15_WIDTH },
5472  { SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_16_CHECKER_TYPE,
5473  SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_16_WIDTH },
5474  { SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_17_CHECKER_TYPE,
5475  SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_17_WIDTH },
5476  { SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_18_CHECKER_TYPE,
5477  SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_18_WIDTH },
5478  { SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_19_CHECKER_TYPE,
5479  SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_19_WIDTH },
5480  { SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_20_CHECKER_TYPE,
5481  SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_20_WIDTH },
5482  { SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_21_CHECKER_TYPE,
5483  SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_21_WIDTH },
5484  { SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_22_CHECKER_TYPE,
5485  SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_22_WIDTH },
5486  { SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_23_CHECKER_TYPE,
5487  SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_23_WIDTH },
5488  { SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_24_CHECKER_TYPE,
5489  SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_24_WIDTH },
5490  { SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_25_CHECKER_TYPE,
5491  SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_25_WIDTH },
5492  { SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_26_CHECKER_TYPE,
5493  SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_26_WIDTH },
5494  { SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_27_CHECKER_TYPE,
5495  SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_27_WIDTH },
5496  { SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_28_CHECKER_TYPE,
5497  SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_28_WIDTH },
5498  { SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_29_CHECKER_TYPE,
5499  SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_29_WIDTH },
5500  { SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_30_CHECKER_TYPE,
5501  SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_30_WIDTH },
5502  { SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_31_CHECKER_TYPE,
5503  SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_31_WIDTH },
5504  { SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_32_CHECKER_TYPE,
5505  SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_32_WIDTH },
5506  { SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_33_CHECKER_TYPE,
5507  SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_33_WIDTH },
5508  { SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_34_CHECKER_TYPE,
5509  SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_34_WIDTH },
5510  { SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_35_CHECKER_TYPE,
5511  SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_35_WIDTH },
5512  { SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_36_CHECKER_TYPE,
5513  SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_36_WIDTH },
5514  { SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_37_CHECKER_TYPE,
5515  SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_37_WIDTH },
5516  { SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_38_CHECKER_TYPE,
5517  SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_38_WIDTH },
5518  { SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_39_CHECKER_TYPE,
5519  SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_39_WIDTH },
5520  { SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_40_CHECKER_TYPE,
5521  SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_40_WIDTH },
5522  { SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_41_CHECKER_TYPE,
5523  SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_41_WIDTH },
5524  { SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_42_CHECKER_TYPE,
5525  SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_42_WIDTH },
5526  { SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_43_CHECKER_TYPE,
5527  SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_43_WIDTH },
5528  { SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_44_CHECKER_TYPE,
5529  SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_44_WIDTH },
5530  { SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_45_CHECKER_TYPE,
5531  SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_45_WIDTH },
5532  { SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_46_CHECKER_TYPE,
5533  SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_46_WIDTH },
5534  { SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_47_CHECKER_TYPE,
5535  SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_47_WIDTH },
5536  { SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_48_CHECKER_TYPE,
5537  SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_48_WIDTH },
5538  { SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_49_CHECKER_TYPE,
5539  SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_49_WIDTH },
5540  { SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_50_CHECKER_TYPE,
5541  SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_50_WIDTH },
5542  { SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_51_CHECKER_TYPE,
5543  SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_51_WIDTH },
5544  { SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_52_CHECKER_TYPE,
5545  SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_52_WIDTH },
5546  { SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_53_CHECKER_TYPE,
5547  SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_53_WIDTH },
5548  { SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_54_CHECKER_TYPE,
5549  SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_54_WIDTH },
5550  { SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_55_CHECKER_TYPE,
5551  SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_55_WIDTH },
5552  { SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_56_CHECKER_TYPE,
5553  SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_56_WIDTH },
5554  { SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_57_CHECKER_TYPE,
5555  SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_57_WIDTH },
5556  { SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_58_CHECKER_TYPE,
5557  SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_58_WIDTH },
5558  { SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_59_CHECKER_TYPE,
5559  SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_59_WIDTH },
5560  { SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_60_CHECKER_TYPE,
5561  SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_60_WIDTH },
5562  { SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_61_CHECKER_TYPE,
5563  SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_61_WIDTH },
5564  { SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_62_CHECKER_TYPE,
5565  SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_62_WIDTH },
5566  { SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_63_CHECKER_TYPE,
5567  SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_63_WIDTH },
5568  { SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_64_CHECKER_TYPE,
5569  SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_64_WIDTH },
5570  { SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_65_CHECKER_TYPE,
5571  SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_65_WIDTH },
5572  { SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_66_CHECKER_TYPE,
5573  SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_66_WIDTH },
5574  { SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_67_CHECKER_TYPE,
5575  SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_67_WIDTH },
5576  { SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_68_CHECKER_TYPE,
5577  SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_68_WIDTH },
5578  { SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_69_CHECKER_TYPE,
5579  SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_69_WIDTH },
5580 };
5581 
5587 static const SDL_GrpChkConfig_t SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_groupEntries[SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS] =
5588 {
5589  { SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
5590  SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
5591  { SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
5592  SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
5593  { SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
5594  SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
5595  { SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
5596  SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
5597  { SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
5598  SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
5599  { SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_5_CHECKER_TYPE,
5600  SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_5_WIDTH },
5601  { SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_6_CHECKER_TYPE,
5602  SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_6_WIDTH },
5603  { SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_7_CHECKER_TYPE,
5604  SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_7_WIDTH },
5605  { SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_8_CHECKER_TYPE,
5606  SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_8_WIDTH },
5607  { SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_9_CHECKER_TYPE,
5608  SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_9_WIDTH },
5609  { SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_10_CHECKER_TYPE,
5610  SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_10_WIDTH },
5611  { SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_11_CHECKER_TYPE,
5612  SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_11_WIDTH },
5613  { SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_12_CHECKER_TYPE,
5614  SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_12_WIDTH },
5615  { SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_13_CHECKER_TYPE,
5616  SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_13_WIDTH },
5617  { SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_14_CHECKER_TYPE,
5618  SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_14_WIDTH },
5619  { SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_15_CHECKER_TYPE,
5620  SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_15_WIDTH },
5621  { SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_16_CHECKER_TYPE,
5622  SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_16_WIDTH },
5623  { SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_17_CHECKER_TYPE,
5624  SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_17_WIDTH },
5625  { SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_18_CHECKER_TYPE,
5626  SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_18_WIDTH },
5627  { SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_19_CHECKER_TYPE,
5628  SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_19_WIDTH },
5629  { SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_20_CHECKER_TYPE,
5630  SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_20_WIDTH },
5631  { SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_21_CHECKER_TYPE,
5632  SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_21_WIDTH },
5633  { SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_22_CHECKER_TYPE,
5634  SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_22_WIDTH },
5635  { SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_23_CHECKER_TYPE,
5636  SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_23_WIDTH },
5637  { SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_24_CHECKER_TYPE,
5638  SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_24_WIDTH },
5639  { SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_25_CHECKER_TYPE,
5640  SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_25_WIDTH },
5641  { SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_26_CHECKER_TYPE,
5642  SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_26_WIDTH },
5643  { SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_27_CHECKER_TYPE,
5644  SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_27_WIDTH },
5645  { SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_28_CHECKER_TYPE,
5646  SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_28_WIDTH },
5647  { SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_29_CHECKER_TYPE,
5648  SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_29_WIDTH },
5649  { SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_30_CHECKER_TYPE,
5650  SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_30_WIDTH },
5651  { SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_31_CHECKER_TYPE,
5652  SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_31_WIDTH },
5653  { SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_32_CHECKER_TYPE,
5654  SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_32_WIDTH },
5655  { SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_33_CHECKER_TYPE,
5656  SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_33_WIDTH },
5657  { SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_34_CHECKER_TYPE,
5658  SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_34_WIDTH },
5659  { SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_35_CHECKER_TYPE,
5660  SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_35_WIDTH },
5661  { SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_36_CHECKER_TYPE,
5662  SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_36_WIDTH },
5663  { SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_37_CHECKER_TYPE,
5664  SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_37_WIDTH },
5665  { SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_38_CHECKER_TYPE,
5666  SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_38_WIDTH },
5667  { SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_39_CHECKER_TYPE,
5668  SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_39_WIDTH },
5669  { SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_40_CHECKER_TYPE,
5670  SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_40_WIDTH },
5671  { SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_41_CHECKER_TYPE,
5672  SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_41_WIDTH },
5673  { SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_42_CHECKER_TYPE,
5674  SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_42_WIDTH },
5675  { SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_43_CHECKER_TYPE,
5676  SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_43_WIDTH },
5677  { SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_44_CHECKER_TYPE,
5678  SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_44_WIDTH },
5679  { SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_45_CHECKER_TYPE,
5680  SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_45_WIDTH },
5681  { SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_46_CHECKER_TYPE,
5682  SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_46_WIDTH },
5683  { SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_47_CHECKER_TYPE,
5684  SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_47_WIDTH },
5685  { SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_48_CHECKER_TYPE,
5686  SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_48_WIDTH },
5687  { SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_49_CHECKER_TYPE,
5688  SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_49_WIDTH },
5689  { SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_50_CHECKER_TYPE,
5690  SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_50_WIDTH },
5691  { SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_51_CHECKER_TYPE,
5692  SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_51_WIDTH },
5693  { SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_52_CHECKER_TYPE,
5694  SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_52_WIDTH },
5695  { SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_53_CHECKER_TYPE,
5696  SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_53_WIDTH },
5697  { SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_54_CHECKER_TYPE,
5698  SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_54_WIDTH },
5699  { SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_55_CHECKER_TYPE,
5700  SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_55_WIDTH },
5701  { SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_56_CHECKER_TYPE,
5702  SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_56_WIDTH },
5703  { SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_57_CHECKER_TYPE,
5704  SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_57_WIDTH },
5705  { SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_58_CHECKER_TYPE,
5706  SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_58_WIDTH },
5707  { SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_59_CHECKER_TYPE,
5708  SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_59_WIDTH },
5709  { SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_60_CHECKER_TYPE,
5710  SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_60_WIDTH },
5711  { SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_61_CHECKER_TYPE,
5712  SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_61_WIDTH },
5713  { SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_62_CHECKER_TYPE,
5714  SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_62_WIDTH },
5715  { SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_63_CHECKER_TYPE,
5716  SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_63_WIDTH },
5717  { SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_64_CHECKER_TYPE,
5718  SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_64_WIDTH },
5719  { SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_65_CHECKER_TYPE,
5720  SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_65_WIDTH },
5721  { SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_66_CHECKER_TYPE,
5722  SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_66_WIDTH },
5723  { SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_67_CHECKER_TYPE,
5724  SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_67_WIDTH },
5725  { SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_68_CHECKER_TYPE,
5726  SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_68_WIDTH },
5727 };
5728 
5734 static const SDL_GrpChkConfig_t SDL_WKUP_ECC_AGGR1_AM67_MCU_FW_CBASS_IAM67_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM67_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_groupEntries[SDL_WKUP_ECC_AGGR1_AM67_MCU_FW_CBASS_IAM67_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM67_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS] =
5735 {
5736  { SDL_WKUP_ECC_AGGR1_AM67_MCU_FW_CBASS_IAM67_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM67_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_0_CHECKER_TYPE,
5737  SDL_WKUP_ECC_AGGR1_AM67_MCU_FW_CBASS_IAM67_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM67_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_0_WIDTH },
5738  { SDL_WKUP_ECC_AGGR1_AM67_MCU_FW_CBASS_IAM67_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM67_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_1_CHECKER_TYPE,
5739  SDL_WKUP_ECC_AGGR1_AM67_MCU_FW_CBASS_IAM67_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM67_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_1_WIDTH },
5740  { SDL_WKUP_ECC_AGGR1_AM67_MCU_FW_CBASS_IAM67_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM67_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_2_CHECKER_TYPE,
5741  SDL_WKUP_ECC_AGGR1_AM67_MCU_FW_CBASS_IAM67_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM67_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_2_WIDTH },
5742  { SDL_WKUP_ECC_AGGR1_AM67_MCU_FW_CBASS_IAM67_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM67_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_3_CHECKER_TYPE,
5743  SDL_WKUP_ECC_AGGR1_AM67_MCU_FW_CBASS_IAM67_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM67_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_3_WIDTH },
5744  { SDL_WKUP_ECC_AGGR1_AM67_MCU_FW_CBASS_IAM67_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM67_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_4_CHECKER_TYPE,
5745  SDL_WKUP_ECC_AGGR1_AM67_MCU_FW_CBASS_IAM67_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM67_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_4_WIDTH },
5746  { SDL_WKUP_ECC_AGGR1_AM67_MCU_FW_CBASS_IAM67_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM67_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_5_CHECKER_TYPE,
5747  SDL_WKUP_ECC_AGGR1_AM67_MCU_FW_CBASS_IAM67_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM67_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_5_WIDTH },
5748  { SDL_WKUP_ECC_AGGR1_AM67_MCU_FW_CBASS_IAM67_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM67_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_6_CHECKER_TYPE,
5749  SDL_WKUP_ECC_AGGR1_AM67_MCU_FW_CBASS_IAM67_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM67_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_6_WIDTH },
5750  { SDL_WKUP_ECC_AGGR1_AM67_MCU_FW_CBASS_IAM67_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM67_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_7_CHECKER_TYPE,
5751  SDL_WKUP_ECC_AGGR1_AM67_MCU_FW_CBASS_IAM67_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM67_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_7_WIDTH },
5752  { SDL_WKUP_ECC_AGGR1_AM67_MCU_FW_CBASS_IAM67_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM67_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_8_CHECKER_TYPE,
5753  SDL_WKUP_ECC_AGGR1_AM67_MCU_FW_CBASS_IAM67_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM67_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_8_WIDTH },
5754  { SDL_WKUP_ECC_AGGR1_AM67_MCU_FW_CBASS_IAM67_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM67_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_9_CHECKER_TYPE,
5755  SDL_WKUP_ECC_AGGR1_AM67_MCU_FW_CBASS_IAM67_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM67_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_9_WIDTH },
5756  { SDL_WKUP_ECC_AGGR1_AM67_MCU_FW_CBASS_IAM67_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM67_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_10_CHECKER_TYPE,
5757  SDL_WKUP_ECC_AGGR1_AM67_MCU_FW_CBASS_IAM67_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM67_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_10_WIDTH },
5758  { SDL_WKUP_ECC_AGGR1_AM67_MCU_FW_CBASS_IAM67_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM67_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_11_CHECKER_TYPE,
5759  SDL_WKUP_ECC_AGGR1_AM67_MCU_FW_CBASS_IAM67_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM67_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_11_WIDTH },
5760  { SDL_WKUP_ECC_AGGR1_AM67_MCU_FW_CBASS_IAM67_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM67_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_12_CHECKER_TYPE,
5761  SDL_WKUP_ECC_AGGR1_AM67_MCU_FW_CBASS_IAM67_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM67_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_12_WIDTH },
5762  { SDL_WKUP_ECC_AGGR1_AM67_MCU_FW_CBASS_IAM67_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM67_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_13_CHECKER_TYPE,
5763  SDL_WKUP_ECC_AGGR1_AM67_MCU_FW_CBASS_IAM67_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM67_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_13_WIDTH },
5764  { SDL_WKUP_ECC_AGGR1_AM67_MCU_FW_CBASS_IAM67_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM67_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_14_CHECKER_TYPE,
5765  SDL_WKUP_ECC_AGGR1_AM67_MCU_FW_CBASS_IAM67_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM67_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_14_WIDTH },
5766  { SDL_WKUP_ECC_AGGR1_AM67_MCU_FW_CBASS_IAM67_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM67_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_15_CHECKER_TYPE,
5767  SDL_WKUP_ECC_AGGR1_AM67_MCU_FW_CBASS_IAM67_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM67_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_15_WIDTH },
5768  { SDL_WKUP_ECC_AGGR1_AM67_MCU_FW_CBASS_IAM67_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM67_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_16_CHECKER_TYPE,
5769  SDL_WKUP_ECC_AGGR1_AM67_MCU_FW_CBASS_IAM67_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM67_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_16_WIDTH },
5770 };
5771 
5777 static const SDL_GrpChkConfig_t SDL_WKUP_ECC_AGGR1_AM67_MCU_FW_CBASS_IAM67_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM67_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_groupEntries[SDL_WKUP_ECC_AGGR1_AM67_MCU_FW_CBASS_IAM67_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM67_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS] =
5778 {
5779  { SDL_WKUP_ECC_AGGR1_AM67_MCU_FW_CBASS_IAM67_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM67_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_GROUP_0_CHECKER_TYPE,
5780  SDL_WKUP_ECC_AGGR1_AM67_MCU_FW_CBASS_IAM67_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM67_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_GROUP_0_WIDTH },
5781  { SDL_WKUP_ECC_AGGR1_AM67_MCU_FW_CBASS_IAM67_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM67_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_GROUP_1_CHECKER_TYPE,
5782  SDL_WKUP_ECC_AGGR1_AM67_MCU_FW_CBASS_IAM67_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM67_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_GROUP_1_WIDTH },
5783  { SDL_WKUP_ECC_AGGR1_AM67_MCU_FW_CBASS_IAM67_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM67_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_GROUP_2_CHECKER_TYPE,
5784  SDL_WKUP_ECC_AGGR1_AM67_MCU_FW_CBASS_IAM67_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM67_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_GROUP_2_WIDTH },
5785  { SDL_WKUP_ECC_AGGR1_AM67_MCU_FW_CBASS_IAM67_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM67_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_GROUP_3_CHECKER_TYPE,
5786  SDL_WKUP_ECC_AGGR1_AM67_MCU_FW_CBASS_IAM67_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM67_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_GROUP_3_WIDTH },
5787  { SDL_WKUP_ECC_AGGR1_AM67_MCU_FW_CBASS_IAM67_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM67_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_GROUP_4_CHECKER_TYPE,
5788  SDL_WKUP_ECC_AGGR1_AM67_MCU_FW_CBASS_IAM67_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM67_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_GROUP_4_WIDTH },
5789  { SDL_WKUP_ECC_AGGR1_AM67_MCU_FW_CBASS_IAM67_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM67_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_GROUP_5_CHECKER_TYPE,
5790  SDL_WKUP_ECC_AGGR1_AM67_MCU_FW_CBASS_IAM67_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM67_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_GROUP_5_WIDTH },
5791  { SDL_WKUP_ECC_AGGR1_AM67_MCU_FW_CBASS_IAM67_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM67_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_GROUP_6_CHECKER_TYPE,
5792  SDL_WKUP_ECC_AGGR1_AM67_MCU_FW_CBASS_IAM67_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM67_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_GROUP_6_WIDTH },
5793 };
5794 
5800 static const SDL_GrpChkConfig_t SDL_WKUP_ECC_AGGR1_AM67_MCU_FW_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_groupEntries[SDL_WKUP_ECC_AGGR1_AM67_MCU_FW_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_MAX_NUM_CHECKERS] =
5801 {
5802  { SDL_WKUP_ECC_AGGR1_AM67_MCU_FW_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_0_CHECKER_TYPE,
5803  SDL_WKUP_ECC_AGGR1_AM67_MCU_FW_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_0_WIDTH },
5804  { SDL_WKUP_ECC_AGGR1_AM67_MCU_FW_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_1_CHECKER_TYPE,
5805  SDL_WKUP_ECC_AGGR1_AM67_MCU_FW_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_1_WIDTH },
5806  { SDL_WKUP_ECC_AGGR1_AM67_MCU_FW_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_2_CHECKER_TYPE,
5807  SDL_WKUP_ECC_AGGR1_AM67_MCU_FW_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_2_WIDTH },
5808  { SDL_WKUP_ECC_AGGR1_AM67_MCU_FW_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_3_CHECKER_TYPE,
5809  SDL_WKUP_ECC_AGGR1_AM67_MCU_FW_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_3_WIDTH },
5810  { SDL_WKUP_ECC_AGGR1_AM67_MCU_FW_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_4_CHECKER_TYPE,
5811  SDL_WKUP_ECC_AGGR1_AM67_MCU_FW_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_4_WIDTH },
5812  { SDL_WKUP_ECC_AGGR1_AM67_MCU_FW_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_5_CHECKER_TYPE,
5813  SDL_WKUP_ECC_AGGR1_AM67_MCU_FW_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_5_WIDTH },
5814  { SDL_WKUP_ECC_AGGR1_AM67_MCU_FW_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_6_CHECKER_TYPE,
5815  SDL_WKUP_ECC_AGGR1_AM67_MCU_FW_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_6_WIDTH },
5816  { SDL_WKUP_ECC_AGGR1_AM67_MCU_FW_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_7_CHECKER_TYPE,
5817  SDL_WKUP_ECC_AGGR1_AM67_MCU_FW_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_7_WIDTH },
5818  { SDL_WKUP_ECC_AGGR1_AM67_MCU_FW_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_8_CHECKER_TYPE,
5819  SDL_WKUP_ECC_AGGR1_AM67_MCU_FW_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_8_WIDTH },
5820  { SDL_WKUP_ECC_AGGR1_AM67_MCU_FW_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_9_CHECKER_TYPE,
5821  SDL_WKUP_ECC_AGGR1_AM67_MCU_FW_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_9_WIDTH },
5822  { SDL_WKUP_ECC_AGGR1_AM67_MCU_FW_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_10_CHECKER_TYPE,
5823  SDL_WKUP_ECC_AGGR1_AM67_MCU_FW_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_10_WIDTH },
5824 };
5825 
5831 static const SDL_GrpChkConfig_t SDL_WKUP_ECC_AGGR1_SAM67_DM_MCU_ECC_AGGR_EDC_CTRL_groupEntries[SDL_WKUP_ECC_AGGR1_SAM67_DM_MCU_ECC_AGGR_EDC_CTRL_MAX_NUM_CHECKERS] =
5832 {
5833  { SDL_WKUP_ECC_AGGR1_SAM67_DM_MCU_ECC_AGGR_EDC_CTRL_GROUP_0_CHECKER_TYPE,
5834  SDL_WKUP_ECC_AGGR1_SAM67_DM_MCU_ECC_AGGR_EDC_CTRL_GROUP_0_WIDTH },
5835  { SDL_WKUP_ECC_AGGR1_SAM67_DM_MCU_ECC_AGGR_EDC_CTRL_GROUP_1_CHECKER_TYPE,
5836  SDL_WKUP_ECC_AGGR1_SAM67_DM_MCU_ECC_AGGR_EDC_CTRL_GROUP_1_WIDTH },
5837  { SDL_WKUP_ECC_AGGR1_SAM67_DM_MCU_ECC_AGGR_EDC_CTRL_GROUP_2_CHECKER_TYPE,
5838  SDL_WKUP_ECC_AGGR1_SAM67_DM_MCU_ECC_AGGR_EDC_CTRL_GROUP_2_WIDTH },
5839  { SDL_WKUP_ECC_AGGR1_SAM67_DM_MCU_ECC_AGGR_EDC_CTRL_GROUP_3_CHECKER_TYPE,
5840  SDL_WKUP_ECC_AGGR1_SAM67_DM_MCU_ECC_AGGR_EDC_CTRL_GROUP_3_WIDTH },
5841  { SDL_WKUP_ECC_AGGR1_SAM67_DM_MCU_ECC_AGGR_EDC_CTRL_GROUP_4_CHECKER_TYPE,
5842  SDL_WKUP_ECC_AGGR1_SAM67_DM_MCU_ECC_AGGR_EDC_CTRL_GROUP_4_WIDTH },
5843  { SDL_WKUP_ECC_AGGR1_SAM67_DM_MCU_ECC_AGGR_EDC_CTRL_GROUP_5_CHECKER_TYPE,
5844  SDL_WKUP_ECC_AGGR1_SAM67_DM_MCU_ECC_AGGR_EDC_CTRL_GROUP_5_WIDTH },
5845 };
5846 
5851 static const SDL_MemConfig_t SDL_FSS0_FSS_UL_OSPI0_OSPI_WRAP_ECC_AGGR_MemEntries[SDL_FSS0_FSS_UL_OSPI0_OSPI_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES] =
5852 {
5853  { SDL_FSS0_FSS_UL_OSPI0_OSPI_WRAP_ECC_AGGR_OSPI_OSPI_WRAP_SRAM_RAM_ID, 0u,
5854  SDL_FSS0_FSS_UL_OSPI0_OSPI_WRAP_ECC_AGGR_OSPI_OSPI_WRAP_SRAM_RAM_SIZE, 4u,
5855  SDL_FSS0_FSS_UL_OSPI0_OSPI_WRAP_ECC_AGGR_OSPI_OSPI_WRAP_SRAM_ROW_WIDTH, ((bool)false) },
5856 };
5857 
5862 static const SDL_MemConfig_t SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_MemEntries[SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES] =
5863 {
5864  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_ITAG_RAM0_RAM_ID, 0u,
5865  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_ITAG_RAM0_RAM_SIZE, 4u,
5866  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_ITAG_RAM0_ROW_WIDTH, ((bool)false) },
5867  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_ITAG_RAM1_RAM_ID, 0u,
5868  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_ITAG_RAM1_RAM_SIZE, 4u,
5869  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_ITAG_RAM1_ROW_WIDTH, ((bool)false) },
5870  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_ITAG_RAM2_RAM_ID, 0u,
5871  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_ITAG_RAM2_RAM_SIZE, 4u,
5872  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_ITAG_RAM2_ROW_WIDTH, ((bool)false) },
5873  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_ITAG_RAM3_RAM_ID, 0u,
5874  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_ITAG_RAM3_RAM_SIZE, 4u,
5875  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_ITAG_RAM3_ROW_WIDTH, ((bool)false) },
5876  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_IDATA_BANK0_RAM_ID, 0u,
5877  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_IDATA_BANK0_RAM_SIZE, 4u,
5878  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_IDATA_BANK0_ROW_WIDTH, ((bool)true) },
5879  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_IDATA_BANK1_RAM_ID, 0u,
5880  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_IDATA_BANK1_RAM_SIZE, 4u,
5881  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_IDATA_BANK1_ROW_WIDTH, ((bool)true) },
5882  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_IDATA_BANK2_RAM_ID, 0u,
5883  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_IDATA_BANK2_RAM_SIZE, 4u,
5884  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_IDATA_BANK2_ROW_WIDTH, ((bool)true) },
5885  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_IDATA_BANK3_RAM_ID, 0u,
5886  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_IDATA_BANK3_RAM_SIZE, 4u,
5887  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_IDATA_BANK3_ROW_WIDTH, ((bool)true) },
5888  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_DTAG_RAM0_RAM_ID, 0u,
5889  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_DTAG_RAM0_RAM_SIZE, 4u,
5890  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_DTAG_RAM0_ROW_WIDTH, ((bool)false) },
5891  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_DTAG_RAM1_RAM_ID, 0u,
5892  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_DTAG_RAM1_RAM_SIZE, 4u,
5893  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_DTAG_RAM1_ROW_WIDTH, ((bool)false) },
5894  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_DTAG_RAM2_RAM_ID, 0u,
5895  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_DTAG_RAM2_RAM_SIZE, 4u,
5896  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_DTAG_RAM2_ROW_WIDTH, ((bool)false) },
5897  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_DTAG_RAM3_RAM_ID, 0u,
5898  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_DTAG_RAM3_RAM_SIZE, 4u,
5899  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_DTAG_RAM3_ROW_WIDTH, ((bool)false) },
5900  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_DDIRTY_RAM_RAM_ID, 0u,
5901  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_DDIRTY_RAM_RAM_SIZE, 4u,
5902  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_DDIRTY_RAM_ROW_WIDTH, ((bool)false) },
5903  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_DDATA_RAM0_RAM_ID, 0u,
5904  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_DDATA_RAM0_RAM_SIZE, 4u,
5905  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_DDATA_RAM0_ROW_WIDTH, ((bool)true) },
5906  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_DDATA_RAM1_RAM_ID, 0u,
5907  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_DDATA_RAM1_RAM_SIZE, 4u,
5908  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_DDATA_RAM1_ROW_WIDTH, ((bool)true) },
5909  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_DDATA_RAM2_RAM_ID, 0u,
5910  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_DDATA_RAM2_RAM_SIZE, 4u,
5911  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_DDATA_RAM2_ROW_WIDTH, ((bool)true) },
5912  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_DDATA_RAM3_RAM_ID, 0u,
5913  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_DDATA_RAM3_RAM_SIZE, 4u,
5914  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_DDATA_RAM3_ROW_WIDTH, ((bool)true) },
5915  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_DDATA_RAM4_RAM_ID, 0u,
5916  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_DDATA_RAM4_RAM_SIZE, 4u,
5917  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_DDATA_RAM4_ROW_WIDTH, ((bool)true) },
5918  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_DDATA_RAM5_RAM_ID, 0u,
5919  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_DDATA_RAM5_RAM_SIZE, 4u,
5920  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_DDATA_RAM5_ROW_WIDTH, ((bool)true) },
5921  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_DDATA_RAM6_RAM_ID, 0u,
5922  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_DDATA_RAM6_RAM_SIZE, 4u,
5923  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_DDATA_RAM6_ROW_WIDTH, ((bool)true) },
5924  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_DDATA_RAM7_RAM_ID, 0u,
5925  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_DDATA_RAM7_RAM_SIZE, 4u,
5926  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_DDATA_RAM7_ROW_WIDTH, ((bool)true) },
5927  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_ATCM0_BANK0_RAM_ID, 0u,
5928  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_ATCM0_BANK0_RAM_SIZE, 4u,
5929  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_ATCM0_BANK0_ROW_WIDTH, ((bool)true) },
5930  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_ATCM0_BANK1_RAM_ID, 0u,
5931  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_ATCM0_BANK1_RAM_SIZE, 4u,
5932  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_ATCM0_BANK1_ROW_WIDTH, ((bool)true) },
5933  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_B0TCM0_BANK0_RAM_ID, 0u,
5934  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_B0TCM0_BANK0_RAM_SIZE, 4u,
5935  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_B0TCM0_BANK0_ROW_WIDTH, ((bool)true) },
5936  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_B0TCM0_BANK1_RAM_ID, 0u,
5937  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_B0TCM0_BANK1_RAM_SIZE, 4u,
5938  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_B0TCM0_BANK1_ROW_WIDTH, ((bool)true) },
5939  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_B1TCM0_BANK0_RAM_ID, 0u,
5940  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_B1TCM0_BANK0_RAM_SIZE, 4u,
5941  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_B1TCM0_BANK0_ROW_WIDTH, ((bool)true) },
5942  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_B1TCM0_BANK1_RAM_ID, 0u,
5943  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_B1TCM0_BANK1_RAM_SIZE, 4u,
5944  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_B1TCM0_BANK1_ROW_WIDTH, ((bool)true) },
5945  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_KS_VIM_RAMECC_RAM_ID, 0u,
5946  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_KS_VIM_RAMECC_RAM_SIZE, 4u,
5947  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_KS_VIM_RAMECC_ROW_WIDTH, ((bool)false) },
5948  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_AXI2VBUSM_MEM_MST_RAMECC_RAM_ID, 0u,
5949  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_AXI2VBUSM_MEM_MST_RAMECC_RAM_SIZE, 4u,
5950  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_AXI2VBUSM_MEM_MST_RAMECC_ROW_WIDTH, ((bool)false) },
5951 };
5952 
5958 static const SDL_GrpChkConfig_t SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_VBUSM2AXI_EDC_groupEntries[SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_VBUSM2AXI_EDC_MAX_NUM_CHECKERS] =
5959 {
5960  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_VBUSM2AXI_EDC_GROUP_0_CHECKER_TYPE,
5961  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_VBUSM2AXI_EDC_GROUP_0_WIDTH },
5962  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_VBUSM2AXI_EDC_GROUP_1_CHECKER_TYPE,
5963  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_VBUSM2AXI_EDC_GROUP_1_WIDTH },
5964  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_VBUSM2AXI_EDC_GROUP_2_CHECKER_TYPE,
5965  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_VBUSM2AXI_EDC_GROUP_2_WIDTH },
5966  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_VBUSM2AXI_EDC_GROUP_3_CHECKER_TYPE,
5967  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_VBUSM2AXI_EDC_GROUP_3_WIDTH },
5968  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_VBUSM2AXI_EDC_GROUP_4_CHECKER_TYPE,
5969  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_VBUSM2AXI_EDC_GROUP_4_WIDTH },
5970  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_VBUSM2AXI_EDC_GROUP_5_CHECKER_TYPE,
5971  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_VBUSM2AXI_EDC_GROUP_5_WIDTH },
5972  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_VBUSM2AXI_EDC_GROUP_6_CHECKER_TYPE,
5973  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_VBUSM2AXI_EDC_GROUP_6_WIDTH },
5974  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_VBUSM2AXI_EDC_GROUP_7_CHECKER_TYPE,
5975  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_VBUSM2AXI_EDC_GROUP_7_WIDTH },
5976  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_VBUSM2AXI_EDC_GROUP_8_CHECKER_TYPE,
5977  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_VBUSM2AXI_EDC_GROUP_8_WIDTH },
5978  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_VBUSM2AXI_EDC_GROUP_9_CHECKER_TYPE,
5979  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_VBUSM2AXI_EDC_GROUP_9_WIDTH },
5980  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_VBUSM2AXI_EDC_GROUP_10_CHECKER_TYPE,
5981  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_VBUSM2AXI_EDC_GROUP_10_WIDTH },
5982  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_VBUSM2AXI_EDC_GROUP_11_CHECKER_TYPE,
5983  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_VBUSM2AXI_EDC_GROUP_11_WIDTH },
5984  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_VBUSM2AXI_EDC_GROUP_12_CHECKER_TYPE,
5985  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_VBUSM2AXI_EDC_GROUP_12_WIDTH },
5986  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_VBUSM2AXI_EDC_GROUP_13_CHECKER_TYPE,
5987  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_VBUSM2AXI_EDC_GROUP_13_WIDTH },
5988  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_VBUSM2AXI_EDC_GROUP_14_CHECKER_TYPE,
5989  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_VBUSM2AXI_EDC_GROUP_14_WIDTH },
5990  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_VBUSM2AXI_EDC_GROUP_15_CHECKER_TYPE,
5991  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_VBUSM2AXI_EDC_GROUP_15_WIDTH },
5992  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_VBUSM2AXI_EDC_GROUP_16_CHECKER_TYPE,
5993  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_VBUSM2AXI_EDC_GROUP_16_WIDTH },
5994  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_VBUSM2AXI_EDC_GROUP_17_CHECKER_TYPE,
5995  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_VBUSM2AXI_EDC_GROUP_17_WIDTH },
5996  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_VBUSM2AXI_EDC_GROUP_18_CHECKER_TYPE,
5997  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_VBUSM2AXI_EDC_GROUP_18_WIDTH },
5998  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_VBUSM2AXI_EDC_GROUP_19_CHECKER_TYPE,
5999  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_VBUSM2AXI_EDC_GROUP_19_WIDTH },
6000  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_VBUSM2AXI_EDC_GROUP_20_CHECKER_TYPE,
6001  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_VBUSM2AXI_EDC_GROUP_20_WIDTH },
6002  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_VBUSM2AXI_EDC_GROUP_21_CHECKER_TYPE,
6003  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_VBUSM2AXI_EDC_GROUP_21_WIDTH },
6004  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_VBUSM2AXI_EDC_GROUP_22_CHECKER_TYPE,
6005  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_VBUSM2AXI_EDC_GROUP_22_WIDTH },
6006  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_VBUSM2AXI_EDC_GROUP_23_CHECKER_TYPE,
6007  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_VBUSM2AXI_EDC_GROUP_23_WIDTH },
6008  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_VBUSM2AXI_EDC_GROUP_24_CHECKER_TYPE,
6009  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_VBUSM2AXI_EDC_GROUP_24_WIDTH },
6010  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_VBUSM2AXI_EDC_GROUP_25_CHECKER_TYPE,
6011  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_VBUSM2AXI_EDC_GROUP_25_WIDTH },
6012  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_VBUSM2AXI_EDC_GROUP_26_CHECKER_TYPE,
6013  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_VBUSM2AXI_EDC_GROUP_26_WIDTH },
6014  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_VBUSM2AXI_EDC_GROUP_27_CHECKER_TYPE,
6015  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_VBUSM2AXI_EDC_GROUP_27_WIDTH },
6016  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_VBUSM2AXI_EDC_GROUP_28_CHECKER_TYPE,
6017  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_VBUSM2AXI_EDC_GROUP_28_WIDTH },
6018  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_VBUSM2AXI_EDC_GROUP_29_CHECKER_TYPE,
6019  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_VBUSM2AXI_EDC_GROUP_29_WIDTH },
6020  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_VBUSM2AXI_EDC_GROUP_30_CHECKER_TYPE,
6021  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_VBUSM2AXI_EDC_GROUP_30_WIDTH },
6022  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_VBUSM2AXI_EDC_GROUP_31_CHECKER_TYPE,
6023  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_VBUSM2AXI_EDC_GROUP_31_WIDTH },
6024  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_VBUSM2AXI_EDC_GROUP_32_CHECKER_TYPE,
6025  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_VBUSM2AXI_EDC_GROUP_32_WIDTH },
6026  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_VBUSM2AXI_EDC_GROUP_33_CHECKER_TYPE,
6027  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_VBUSM2AXI_EDC_GROUP_33_WIDTH },
6028  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_VBUSM2AXI_EDC_GROUP_34_CHECKER_TYPE,
6029  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_VBUSM2AXI_EDC_GROUP_34_WIDTH },
6030  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_VBUSM2AXI_EDC_GROUP_35_CHECKER_TYPE,
6031  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_VBUSM2AXI_EDC_GROUP_35_WIDTH },
6032 };
6033 
6039 static const SDL_GrpChkConfig_t SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_groupEntries[SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_MAX_NUM_CHECKERS] =
6040 {
6041  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
6042  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_GROUP_0_WIDTH },
6043  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
6044  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_GROUP_1_WIDTH },
6045  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
6046  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_GROUP_2_WIDTH },
6047  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
6048  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_GROUP_3_WIDTH },
6049  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
6050  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_GROUP_4_WIDTH },
6051  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
6052  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_GROUP_5_WIDTH },
6053  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
6054  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_GROUP_6_WIDTH },
6055  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
6056  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_GROUP_7_WIDTH },
6057  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
6058  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_GROUP_8_WIDTH },
6059  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
6060  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_GROUP_9_WIDTH },
6061  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
6062  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_GROUP_10_WIDTH },
6063  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
6064  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_GROUP_11_WIDTH },
6065  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
6066  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_GROUP_12_WIDTH },
6067  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
6068  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_GROUP_13_WIDTH },
6069  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
6070  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_GROUP_14_WIDTH },
6071  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
6072  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_GROUP_15_WIDTH },
6073  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
6074  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_GROUP_16_WIDTH },
6075  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
6076  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_GROUP_17_WIDTH },
6077  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
6078  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_GROUP_18_WIDTH },
6079  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
6080  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_GROUP_19_WIDTH },
6081  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
6082  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_GROUP_20_WIDTH },
6083  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
6084  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_GROUP_21_WIDTH },
6085  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
6086  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_GROUP_22_WIDTH },
6087  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
6088  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_GROUP_23_WIDTH },
6089  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
6090  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_GROUP_24_WIDTH },
6091  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
6092  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_GROUP_25_WIDTH },
6093  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
6094  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_GROUP_26_WIDTH },
6095  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
6096  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_GROUP_27_WIDTH },
6097  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
6098  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_GROUP_28_WIDTH },
6099  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
6100  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_GROUP_29_WIDTH },
6101  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
6102  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_GROUP_30_WIDTH },
6103  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
6104  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_GROUP_31_WIDTH },
6105  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
6106  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_GROUP_32_WIDTH },
6107  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_GROUP_33_CHECKER_TYPE,
6108  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_GROUP_33_WIDTH },
6109  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_GROUP_34_CHECKER_TYPE,
6110  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_GROUP_34_WIDTH },
6111  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_GROUP_35_CHECKER_TYPE,
6112  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_GROUP_35_WIDTH },
6113  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_GROUP_36_CHECKER_TYPE,
6114  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_GROUP_36_WIDTH },
6115 };
6116 
6122 static const SDL_GrpChkConfig_t SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_0_groupEntries[SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_0_MAX_NUM_CHECKERS] =
6123 {
6124  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
6125  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_0_GROUP_0_WIDTH },
6126  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
6127  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_0_GROUP_1_WIDTH },
6128  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
6129  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_0_GROUP_2_WIDTH },
6130  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
6131  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_0_GROUP_3_WIDTH },
6132  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
6133  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_0_GROUP_4_WIDTH },
6134  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
6135  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_0_GROUP_5_WIDTH },
6136  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
6137  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_0_GROUP_6_WIDTH },
6138  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
6139  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_0_GROUP_7_WIDTH },
6140  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
6141  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_0_GROUP_8_WIDTH },
6142  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
6143  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_0_GROUP_9_WIDTH },
6144  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
6145  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_0_GROUP_10_WIDTH },
6146  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
6147  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_0_GROUP_11_WIDTH },
6148  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
6149  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_0_GROUP_12_WIDTH },
6150  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
6151  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_0_GROUP_13_WIDTH },
6152  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
6153  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_0_GROUP_14_WIDTH },
6154 };
6155 
6161 static const SDL_GrpChkConfig_t SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_SCRP_EDC_groupEntries[SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_SCRP_EDC_MAX_NUM_CHECKERS] =
6162 {
6163  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_SCRP_EDC_GROUP_0_CHECKER_TYPE,
6164  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_SCRP_EDC_GROUP_0_WIDTH },
6165  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_SCRP_EDC_GROUP_1_CHECKER_TYPE,
6166  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_SCRP_EDC_GROUP_1_WIDTH },
6167  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_SCRP_EDC_GROUP_2_CHECKER_TYPE,
6168  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_SCRP_EDC_GROUP_2_WIDTH },
6169  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_SCRP_EDC_GROUP_3_CHECKER_TYPE,
6170  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_SCRP_EDC_GROUP_3_WIDTH },
6171  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_SCRP_EDC_GROUP_4_CHECKER_TYPE,
6172  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_SCRP_EDC_GROUP_4_WIDTH },
6173  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_SCRP_EDC_GROUP_5_CHECKER_TYPE,
6174  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_SCRP_EDC_GROUP_5_WIDTH },
6175  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_SCRP_EDC_GROUP_6_CHECKER_TYPE,
6176  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_SCRP_EDC_GROUP_6_WIDTH },
6177  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_SCRP_EDC_GROUP_7_CHECKER_TYPE,
6178  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_SCRP_EDC_GROUP_7_WIDTH },
6179  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_SCRP_EDC_GROUP_8_CHECKER_TYPE,
6180  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_SCRP_EDC_GROUP_8_WIDTH },
6181  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_SCRP_EDC_GROUP_9_CHECKER_TYPE,
6182  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_SCRP_EDC_GROUP_9_WIDTH },
6183  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_SCRP_EDC_GROUP_10_CHECKER_TYPE,
6184  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_SCRP_EDC_GROUP_10_WIDTH },
6185 };
6186 
6192 static const SDL_GrpChkConfig_t SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_groupEntries[SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS] =
6193 {
6194  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
6195  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
6196  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
6197  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
6198  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
6199  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
6200  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
6201  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
6202  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
6203  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
6204  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_5_CHECKER_TYPE,
6205  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_5_WIDTH },
6206  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_6_CHECKER_TYPE,
6207  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_6_WIDTH },
6208  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_7_CHECKER_TYPE,
6209  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_7_WIDTH },
6210  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_8_CHECKER_TYPE,
6211  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_8_WIDTH },
6212  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_9_CHECKER_TYPE,
6213  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_9_WIDTH },
6214  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_10_CHECKER_TYPE,
6215  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_10_WIDTH },
6216  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_11_CHECKER_TYPE,
6217  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_11_WIDTH },
6218  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_12_CHECKER_TYPE,
6219  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_12_WIDTH },
6220  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_13_CHECKER_TYPE,
6221  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_13_WIDTH },
6222  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_14_CHECKER_TYPE,
6223  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_14_WIDTH },
6224  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_15_CHECKER_TYPE,
6225  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_15_WIDTH },
6226  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_16_CHECKER_TYPE,
6227  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_16_WIDTH },
6228  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_17_CHECKER_TYPE,
6229  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_17_WIDTH },
6230  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_18_CHECKER_TYPE,
6231  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_18_WIDTH },
6232  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_19_CHECKER_TYPE,
6233  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_19_WIDTH },
6234  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_20_CHECKER_TYPE,
6235  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_20_WIDTH },
6236  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_21_CHECKER_TYPE,
6237  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_21_WIDTH },
6238  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_22_CHECKER_TYPE,
6239  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_22_WIDTH },
6240  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_23_CHECKER_TYPE,
6241  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_23_WIDTH },
6242  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_24_CHECKER_TYPE,
6243  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_24_WIDTH },
6244  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_25_CHECKER_TYPE,
6245  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_25_WIDTH },
6246  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_26_CHECKER_TYPE,
6247  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_26_WIDTH },
6248  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_27_CHECKER_TYPE,
6249  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_27_WIDTH },
6250  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_28_CHECKER_TYPE,
6251  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_28_WIDTH },
6252  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_29_CHECKER_TYPE,
6253  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_29_WIDTH },
6254  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_30_CHECKER_TYPE,
6255  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_30_WIDTH },
6256  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_31_CHECKER_TYPE,
6257  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_31_WIDTH },
6258  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_32_CHECKER_TYPE,
6259  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_32_WIDTH },
6260  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_33_CHECKER_TYPE,
6261  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_33_WIDTH },
6262  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_34_CHECKER_TYPE,
6263  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_34_WIDTH },
6264  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_35_CHECKER_TYPE,
6265  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_35_WIDTH },
6266  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_36_CHECKER_TYPE,
6267  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_36_WIDTH },
6268  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_37_CHECKER_TYPE,
6269  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_37_WIDTH },
6270  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_38_CHECKER_TYPE,
6271  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_38_WIDTH },
6272  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_39_CHECKER_TYPE,
6273  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_39_WIDTH },
6274  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_40_CHECKER_TYPE,
6275  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_40_WIDTH },
6276  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_41_CHECKER_TYPE,
6277  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_41_WIDTH },
6278  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_42_CHECKER_TYPE,
6279  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_42_WIDTH },
6280  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_43_CHECKER_TYPE,
6281  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_43_WIDTH },
6282  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_44_CHECKER_TYPE,
6283  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_44_WIDTH },
6284  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_45_CHECKER_TYPE,
6285  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_45_WIDTH },
6286  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_46_CHECKER_TYPE,
6287  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_46_WIDTH },
6288  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_47_CHECKER_TYPE,
6289  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_47_WIDTH },
6290  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_48_CHECKER_TYPE,
6291  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_48_WIDTH },
6292  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_49_CHECKER_TYPE,
6293  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_49_WIDTH },
6294  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_50_CHECKER_TYPE,
6295  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_50_WIDTH },
6296  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_51_CHECKER_TYPE,
6297  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_51_WIDTH },
6298  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_52_CHECKER_TYPE,
6299  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_52_WIDTH },
6300  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_53_CHECKER_TYPE,
6301  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_53_WIDTH },
6302  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_54_CHECKER_TYPE,
6303  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_54_WIDTH },
6304  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_55_CHECKER_TYPE,
6305  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_55_WIDTH },
6306  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_56_CHECKER_TYPE,
6307  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_56_WIDTH },
6308  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_57_CHECKER_TYPE,
6309  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_57_WIDTH },
6310  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_58_CHECKER_TYPE,
6311  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_58_WIDTH },
6312  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_59_CHECKER_TYPE,
6313  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_59_WIDTH },
6314  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_60_CHECKER_TYPE,
6315  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_60_WIDTH },
6316  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_61_CHECKER_TYPE,
6317  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_61_WIDTH },
6318  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_62_CHECKER_TYPE,
6319  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_62_WIDTH },
6320  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_63_CHECKER_TYPE,
6321  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_63_WIDTH },
6322  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_64_CHECKER_TYPE,
6323  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_64_WIDTH },
6324  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_65_CHECKER_TYPE,
6325  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_65_WIDTH },
6326  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_66_CHECKER_TYPE,
6327  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_66_WIDTH },
6328  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_67_CHECKER_TYPE,
6329  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_67_WIDTH },
6330 };
6331 
6337 static const SDL_GrpChkConfig_t SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_ECC_AGGR_EDC_CTRL_groupEntries[SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_ECC_AGGR_EDC_CTRL_MAX_NUM_CHECKERS] =
6338 {
6339  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_ECC_AGGR_EDC_CTRL_GROUP_0_CHECKER_TYPE,
6340  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_ECC_AGGR_EDC_CTRL_GROUP_0_WIDTH },
6341  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_ECC_AGGR_EDC_CTRL_GROUP_1_CHECKER_TYPE,
6342  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_ECC_AGGR_EDC_CTRL_GROUP_1_WIDTH },
6343  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_ECC_AGGR_EDC_CTRL_GROUP_2_CHECKER_TYPE,
6344  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_ECC_AGGR_EDC_CTRL_GROUP_2_WIDTH },
6345  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_ECC_AGGR_EDC_CTRL_GROUP_3_CHECKER_TYPE,
6346  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_ECC_AGGR_EDC_CTRL_GROUP_3_WIDTH },
6347  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_ECC_AGGR_EDC_CTRL_GROUP_4_CHECKER_TYPE,
6348  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_ECC_AGGR_EDC_CTRL_GROUP_4_WIDTH },
6349  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_ECC_AGGR_EDC_CTRL_GROUP_5_CHECKER_TYPE,
6350  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_ECC_AGGR_EDC_CTRL_GROUP_5_WIDTH },
6351 };
6352 
6357 static const SDL_MemConfig_t SDL_GICSS0_GIC500SS_1_4_ECC_AGGR_MemEntries[SDL_GICSS0_GIC500SS_1_4_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES] =
6358 {
6359  { SDL_GICSS0_GIC500SS_1_4_ECC_AGGR_ICB_RAMECC_RAM_ID, 0u,
6360  SDL_GICSS0_GIC500SS_1_4_ECC_AGGR_ICB_RAMECC_RAM_SIZE, 4u,
6361  SDL_GICSS0_GIC500SS_1_4_ECC_AGGR_ICB_RAMECC_ROW_WIDTH, ((bool)true) },
6362  { SDL_GICSS0_GIC500SS_1_4_ECC_AGGR_ITE_RAMECC_RAM_ID, 0u,
6363  SDL_GICSS0_GIC500SS_1_4_ECC_AGGR_ITE_RAMECC_RAM_SIZE, 4u,
6364  SDL_GICSS0_GIC500SS_1_4_ECC_AGGR_ITE_RAMECC_ROW_WIDTH, ((bool)true) },
6365  { SDL_GICSS0_GIC500SS_1_4_ECC_AGGR_LPI_RAMECC_RAM_ID, 0u,
6366  SDL_GICSS0_GIC500SS_1_4_ECC_AGGR_LPI_RAMECC_RAM_SIZE, 4u,
6367  SDL_GICSS0_GIC500SS_1_4_ECC_AGGR_LPI_RAMECC_ROW_WIDTH, ((bool)true) },
6368 };
6369 
6374 static const SDL_MemConfig_t SDL_CPSW0_CPSW_3GUSS_AM67_CORE_ECC_CPSW_ECC_AGGR_MemEntries[SDL_CPSW0_CPSW_3GUSS_AM67_CORE_ECC_CPSW_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES] =
6375 {
6376  { SDL_CPSW0_CPSW_3GUSS_AM67_CORE_ECC_CPSW_ECC_AGGR_ALE_RAM_RAM_ID, 0u,
6377  SDL_CPSW0_CPSW_3GUSS_AM67_CORE_ECC_CPSW_ECC_AGGR_ALE_RAM_RAM_SIZE, 4u,
6378  SDL_CPSW0_CPSW_3GUSS_AM67_CORE_ECC_CPSW_ECC_AGGR_ALE_RAM_ROW_WIDTH, ((bool)false) },
6379  { SDL_CPSW0_CPSW_3GUSS_AM67_CORE_ECC_CPSW_ECC_AGGR_CPSW_3GU_AM67_CORE_ECC_ECC_CTRL1_RAM_ID, 0u,
6380  SDL_CPSW0_CPSW_3GUSS_AM67_CORE_ECC_CPSW_ECC_AGGR_CPSW_3GU_AM67_CORE_ECC_ECC_CTRL1_RAM_SIZE, 4u,
6381  SDL_CPSW0_CPSW_3GUSS_AM67_CORE_ECC_CPSW_ECC_AGGR_CPSW_3GU_AM67_CORE_ECC_ECC_CTRL1_ROW_WIDTH, ((bool)false) },
6382  { SDL_CPSW0_CPSW_3GUSS_AM67_CORE_ECC_CPSW_ECC_AGGR_CPSW_3GU_AM67_CORE_ECC_ECC_CTRL2_RAM_ID, 0u,
6383  SDL_CPSW0_CPSW_3GUSS_AM67_CORE_ECC_CPSW_ECC_AGGR_CPSW_3GU_AM67_CORE_ECC_ECC_CTRL2_RAM_SIZE, 4u,
6384  SDL_CPSW0_CPSW_3GUSS_AM67_CORE_ECC_CPSW_ECC_AGGR_CPSW_3GU_AM67_CORE_ECC_ECC_CTRL2_ROW_WIDTH, ((bool)false) },
6385  { SDL_CPSW0_CPSW_3GUSS_AM67_CORE_ECC_CPSW_ECC_AGGR_CPSW_3GU_AM67_CORE_ECC_ECC_CTRL3_RAM_ID, 0u,
6386  SDL_CPSW0_CPSW_3GUSS_AM67_CORE_ECC_CPSW_ECC_AGGR_CPSW_3GU_AM67_CORE_ECC_ECC_CTRL3_RAM_SIZE, 4u,
6387  SDL_CPSW0_CPSW_3GUSS_AM67_CORE_ECC_CPSW_ECC_AGGR_CPSW_3GU_AM67_CORE_ECC_ECC_CTRL3_ROW_WIDTH, ((bool)false) },
6388  { SDL_CPSW0_CPSW_3GUSS_AM67_CORE_ECC_CPSW_ECC_AGGR_CPSW_3GU_AM67_CORE_ECC_ECC_CTRL4_RAM_ID, 0u,
6389  SDL_CPSW0_CPSW_3GUSS_AM67_CORE_ECC_CPSW_ECC_AGGR_CPSW_3GU_AM67_CORE_ECC_ECC_CTRL4_RAM_SIZE, 4u,
6390  SDL_CPSW0_CPSW_3GUSS_AM67_CORE_ECC_CPSW_ECC_AGGR_CPSW_3GU_AM67_CORE_ECC_ECC_CTRL4_ROW_WIDTH, ((bool)false) },
6391  { SDL_CPSW0_CPSW_3GUSS_AM67_CORE_ECC_CPSW_ECC_AGGR_CPSW_3GU_AM67_CORE_ECC_ECC_CTRL5_RAM_ID, 0u,
6392  SDL_CPSW0_CPSW_3GUSS_AM67_CORE_ECC_CPSW_ECC_AGGR_CPSW_3GU_AM67_CORE_ECC_ECC_CTRL5_RAM_SIZE, 4u,
6393  SDL_CPSW0_CPSW_3GUSS_AM67_CORE_ECC_CPSW_ECC_AGGR_CPSW_3GU_AM67_CORE_ECC_ECC_CTRL5_ROW_WIDTH, ((bool)false) },
6394  { SDL_CPSW0_CPSW_3GUSS_AM67_CORE_ECC_CPSW_ECC_AGGR_CPSW_3GU_AM67_CORE_ECC_ECC_CTRL6_RAM_ID, 0u,
6395  SDL_CPSW0_CPSW_3GUSS_AM67_CORE_ECC_CPSW_ECC_AGGR_CPSW_3GU_AM67_CORE_ECC_ECC_CTRL6_RAM_SIZE, 4u,
6396  SDL_CPSW0_CPSW_3GUSS_AM67_CORE_ECC_CPSW_ECC_AGGR_CPSW_3GU_AM67_CORE_ECC_ECC_CTRL6_ROW_WIDTH, ((bool)false) },
6397  { SDL_CPSW0_CPSW_3GUSS_AM67_CORE_ECC_CPSW_ECC_AGGR_EST_RAM_RAM_ID, 0u,
6398  SDL_CPSW0_CPSW_3GUSS_AM67_CORE_ECC_CPSW_ECC_AGGR_EST_RAM_RAM_SIZE, 4u,
6399  SDL_CPSW0_CPSW_3GUSS_AM67_CORE_ECC_CPSW_ECC_AGGR_EST_RAM_ROW_WIDTH, ((bool)false) },
6400 };
6401 
6406 static const SDL_MemConfig_t SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_MemEntries[SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES] =
6407 {
6408  { SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_RX_SHIM_DMA_PSIL_FIFO_RAM_ID, 0u,
6409  SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_RX_SHIM_DMA_PSIL_FIFO_RAM_SIZE, 4u,
6410  SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_RX_SHIM_DMA_PSIL_FIFO_ROW_WIDTH, ((bool)false) },
6411  { SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_RAM_WRAPPER0_FIFO_RAM_ID, 0u,
6412  SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_RAM_WRAPPER0_FIFO_RAM_SIZE, 4u,
6413  SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_RAM_WRAPPER0_FIFO_ROW_WIDTH, ((bool)false) },
6414  { SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_RAM_WRAPPER1_FIFO_RAM_ID, 0u,
6415  SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_RAM_WRAPPER1_FIFO_RAM_SIZE, 4u,
6416  SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_RAM_WRAPPER1_FIFO_ROW_WIDTH, ((bool)false) },
6417  { SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_RAM_WRAPPER2_FIFO_RAM_ID, 0u,
6418  SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_RAM_WRAPPER2_FIFO_RAM_SIZE, 4u,
6419  SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_RAM_WRAPPER2_FIFO_ROW_WIDTH, ((bool)false) },
6420  { SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_RAM_WRAPPER3_FIFO_RAM_ID, 0u,
6421  SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_RAM_WRAPPER3_FIFO_RAM_SIZE, 4u,
6422  SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_RAM_WRAPPER3_FIFO_ROW_WIDTH, ((bool)false) },
6423  { SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_VP0_VP_FIFO_RAM_ID, 0u,
6424  SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_VP0_VP_FIFO_RAM_SIZE, 4u,
6425  SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_VP0_VP_FIFO_ROW_WIDTH, ((bool)false) },
6426  { SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_VP1_VP_FIFO_RAM_ID, 0u,
6427  SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_VP1_VP_FIFO_RAM_SIZE, 4u,
6428  SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_VP1_VP_FIFO_ROW_WIDTH, ((bool)false) },
6429 };
6430 
6436 static const SDL_GrpChkConfig_t SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_EDC_CTRL_0_groupEntries[SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_EDC_CTRL_0_MAX_NUM_CHECKERS] =
6437 {
6438  { SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
6439  SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_EDC_CTRL_0_GROUP_0_WIDTH },
6440  { SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
6441  SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_EDC_CTRL_0_GROUP_1_WIDTH },
6442 };
6443 
6448 static const SDL_MemConfig_t SDL_PSCSS0_SAM67_MAIN_PSC_WRAP_ECC_AGGR_MemEntries[SDL_PSCSS0_SAM67_MAIN_PSC_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES] =
6449 {
6450  { SDL_PSCSS0_SAM67_MAIN_PSC_WRAP_ECC_AGGR_AM62A_PSC_CHFW_CBASS_DST_FW_CH_VBUSP_TABLE_RAM_ID, 0u,
6451  SDL_PSCSS0_SAM67_MAIN_PSC_WRAP_ECC_AGGR_AM62A_PSC_CHFW_CBASS_DST_FW_CH_VBUSP_TABLE_RAM_SIZE, 4u,
6452  SDL_PSCSS0_SAM67_MAIN_PSC_WRAP_ECC_AGGR_AM62A_PSC_CHFW_CBASS_DST_FW_CH_VBUSP_TABLE_ROW_WIDTH, ((bool)false) },
6453 };
6454 
6459 static const SDL_MemConfig_t SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_RXMEM_MemEntries[SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_RXMEM_RAM_IDS_TOTAL_ENTRIES] =
6460 {
6461  { SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_RXMEM_EMMCSD4SS_SDHC_WRAP_RXMEM_RAM_ID, 0u,
6462  SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_RXMEM_EMMCSD4SS_SDHC_WRAP_RXMEM_RAM_SIZE, 4u,
6463  SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_RXMEM_EMMCSD4SS_SDHC_WRAP_RXMEM_ROW_WIDTH, ((bool)false) },
6464 };
6465 
6470 static const SDL_MemConfig_t SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_TXMEM_MemEntries[SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_TXMEM_RAM_IDS_TOTAL_ENTRIES] =
6471 {
6472  { SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_TXMEM_EMMCSD4SS_SDHC_WRAP_TXMEM_RAM_ID, 0u,
6473  SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_TXMEM_EMMCSD4SS_SDHC_WRAP_TXMEM_RAM_SIZE, 4u,
6474  SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_TXMEM_EMMCSD4SS_SDHC_WRAP_TXMEM_ROW_WIDTH, ((bool)false) },
6475 };
6476 
6481 static const SDL_MemConfig_t SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_MemEntries[SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_RAM_IDS_TOTAL_ENTRIES] =
6482 {
6483  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_CFG_CONFIG_RAM_ID, 0u,
6484  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_CFG_CONFIG_RAM_SIZE, 4u,
6485  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_CFG_CONFIG_ROW_WIDTH, ((bool)false) },
6486  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_CFG_STATE_RAM_ID, 0u,
6487  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_CFG_STATE_RAM_SIZE, 4u,
6488  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_CFG_STATE_ROW_WIDTH, ((bool)false) },
6489  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_TPCFIFO_F0_RAM_ID, 0u,
6490  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_TPCFIFO_F0_RAM_SIZE, 4u,
6491  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_TPCFIFO_F0_ROW_WIDTH, ((bool)false) },
6492  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_TPCFIFO_F1_RAM_ID, 0u,
6493  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_TPCFIFO_F1_RAM_SIZE, 4u,
6494  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_TPCFIFO_F1_ROW_WIDTH, ((bool)false) },
6495  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_RPCFIFO_F0_RAM_ID, 0u,
6496  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_RPCFIFO_F0_RAM_SIZE, 4u,
6497  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_RPCFIFO_F0_ROW_WIDTH, ((bool)false) },
6498  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_RPCFIFO_F1_RAM_ID, 0u,
6499  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_RPCFIFO_F1_RAM_SIZE, 4u,
6500  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_RPCFIFO_F1_ROW_WIDTH, ((bool)false) },
6501  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_RPCFIFO_WC_RAM_ID, 0u,
6502  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_RPCFIFO_WC_RAM_SIZE, 4u,
6503  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_RPCFIFO_WC_ROW_WIDTH, ((bool)false) },
6504  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_STATS_STST0_RAM_ID, 0u,
6505  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_STATS_STST0_RAM_SIZE, 4u,
6506  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_STATS_STST0_ROW_WIDTH, ((bool)false) },
6507  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_STATS_STSR0_RAM_ID, 0u,
6508  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_STATS_STSR0_RAM_SIZE, 4u,
6509  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_STATS_STSR0_ROW_WIDTH, ((bool)false) },
6510  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_RINGOCC_CNTR_RAM_ID, 0u,
6511  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_RINGOCC_CNTR_RAM_SIZE, 4u,
6512  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_RINGOCC_CNTR_ROW_WIDTH, ((bool)false) },
6513  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_STATREG_SR_SPRAM_8X128_SWW_SR_RAM_ID, 0u,
6514  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_STATREG_SR_SPRAM_8X128_SWW_SR_RAM_SIZE, 4u,
6515  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_STATREG_SR_SPRAM_8X128_SWW_SR_ROW_WIDTH, ((bool)false) },
6516  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_COMMON_IM_TPRAM_158X34_SWW_SR_RAM_ID, 0u,
6517  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_COMMON_IM_TPRAM_158X34_SWW_SR_RAM_SIZE, 4u,
6518  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_COMMON_IM_TPRAM_158X34_SWW_SR_ROW_WIDTH, ((bool)false) },
6519  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_STRAM_RAM_ID, 0u,
6520  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_STRAM_RAM_SIZE, 4u,
6521  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_STRAM_ROW_WIDTH, ((bool)false) },
6522  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_BUF_STRAM_RAM_ID, 0u,
6523  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_BUF_STRAM_RAM_SIZE, 4u,
6524  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_BUF_STRAM_ROW_WIDTH, ((bool)false) },
6525  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_BUF_BUFRAM_RAM_ID, 0u,
6526  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_BUF_BUFRAM_RAM_SIZE, 4u,
6527  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_BUF_BUFRAM_ROW_WIDTH, ((bool)false) },
6528  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_ECC0_RAM_ID, 0u,
6529  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_ECC0_RAM_SIZE, 4u,
6530  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_ECC0_ROW_WIDTH, ((bool)false) },
6531 };
6532 
6538 static const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_ECCAGGR_EDC_CTRL_groupEntries[SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_ECCAGGR_EDC_CTRL_MAX_NUM_CHECKERS] =
6539 {
6540  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_ECCAGGR_EDC_CTRL_GROUP_0_CHECKER_TYPE,
6541  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_ECCAGGR_EDC_CTRL_GROUP_0_WIDTH },
6542  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_ECCAGGR_EDC_CTRL_GROUP_1_CHECKER_TYPE,
6543  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_ECCAGGR_EDC_CTRL_GROUP_1_WIDTH },
6544  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_ECCAGGR_EDC_CTRL_GROUP_2_CHECKER_TYPE,
6545  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_ECCAGGR_EDC_CTRL_GROUP_2_WIDTH },
6546  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_ECCAGGR_EDC_CTRL_GROUP_3_CHECKER_TYPE,
6547  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_ECCAGGR_EDC_CTRL_GROUP_3_WIDTH },
6548  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_ECCAGGR_EDC_CTRL_GROUP_4_CHECKER_TYPE,
6549  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_ECCAGGR_EDC_CTRL_GROUP_4_WIDTH },
6550  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_ECCAGGR_EDC_CTRL_GROUP_5_CHECKER_TYPE,
6551  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_ECCAGGR_EDC_CTRL_GROUP_5_WIDTH },
6552 };
6553 
6559 static const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_groupEntries[SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_MAX_NUM_CHECKERS] =
6560 {
6561  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
6562  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_0_WIDTH },
6563  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
6564  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_1_WIDTH },
6565  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
6566  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_2_WIDTH },
6567  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
6568  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_3_WIDTH },
6569  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
6570  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_4_WIDTH },
6571  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
6572  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_5_WIDTH },
6573  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
6574  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_6_WIDTH },
6575  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
6576  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_7_WIDTH },
6577  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
6578  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_8_WIDTH },
6579  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
6580  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_9_WIDTH },
6581  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
6582  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_10_WIDTH },
6583  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
6584  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_11_WIDTH },
6585  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
6586  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_12_WIDTH },
6587  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
6588  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_13_WIDTH },
6589  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
6590  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_14_WIDTH },
6591  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
6592  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_15_WIDTH },
6593  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
6594  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_16_WIDTH },
6595  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
6596  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_17_WIDTH },
6597  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
6598  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_18_WIDTH },
6599  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
6600  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_19_WIDTH },
6601  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
6602  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_20_WIDTH },
6603  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
6604  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_21_WIDTH },
6605  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
6606  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_22_WIDTH },
6607  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
6608  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_23_WIDTH },
6609  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
6610  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_24_WIDTH },
6611  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
6612  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_25_WIDTH },
6613  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
6614  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_26_WIDTH },
6615  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
6616  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_27_WIDTH },
6617  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
6618  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_28_WIDTH },
6619  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
6620  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_29_WIDTH },
6621  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
6622  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_30_WIDTH },
6623  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
6624  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_31_WIDTH },
6625  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
6626  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_32_WIDTH },
6627  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_33_CHECKER_TYPE,
6628  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_33_WIDTH },
6629  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_34_CHECKER_TYPE,
6630  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_34_WIDTH },
6631  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_35_CHECKER_TYPE,
6632  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_35_WIDTH },
6633  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_36_CHECKER_TYPE,
6634  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_36_WIDTH },
6635  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_37_CHECKER_TYPE,
6636  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_37_WIDTH },
6637  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_38_CHECKER_TYPE,
6638  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_38_WIDTH },
6639  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_39_CHECKER_TYPE,
6640  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_39_WIDTH },
6641  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_40_CHECKER_TYPE,
6642  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_40_WIDTH },
6643  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_41_CHECKER_TYPE,
6644  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_41_WIDTH },
6645  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_42_CHECKER_TYPE,
6646  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_42_WIDTH },
6647  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_43_CHECKER_TYPE,
6648  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_43_WIDTH },
6649  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_44_CHECKER_TYPE,
6650  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_44_WIDTH },
6651  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_45_CHECKER_TYPE,
6652  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_45_WIDTH },
6653  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_46_CHECKER_TYPE,
6654  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_46_WIDTH },
6655  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_47_CHECKER_TYPE,
6656  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_47_WIDTH },
6657  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_48_CHECKER_TYPE,
6658  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_48_WIDTH },
6659  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_49_CHECKER_TYPE,
6660  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_49_WIDTH },
6661  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_50_CHECKER_TYPE,
6662  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_50_WIDTH },
6663  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_51_CHECKER_TYPE,
6664  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_51_WIDTH },
6665  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_52_CHECKER_TYPE,
6666  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_52_WIDTH },
6667  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_53_CHECKER_TYPE,
6668  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_53_WIDTH },
6669  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_54_CHECKER_TYPE,
6670  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_54_WIDTH },
6671  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_55_CHECKER_TYPE,
6672  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_55_WIDTH },
6673  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_56_CHECKER_TYPE,
6674  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_56_WIDTH },
6675  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_57_CHECKER_TYPE,
6676  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_57_WIDTH },
6677  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_58_CHECKER_TYPE,
6678  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_58_WIDTH },
6679  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_59_CHECKER_TYPE,
6680  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_59_WIDTH },
6681  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_60_CHECKER_TYPE,
6682  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_60_WIDTH },
6683  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_61_CHECKER_TYPE,
6684  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_61_WIDTH },
6685  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_62_CHECKER_TYPE,
6686  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_62_WIDTH },
6687  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_63_CHECKER_TYPE,
6688  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_63_WIDTH },
6689  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_64_CHECKER_TYPE,
6690  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_64_WIDTH },
6691  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_65_CHECKER_TYPE,
6692  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_65_WIDTH },
6693  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_66_CHECKER_TYPE,
6694  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_66_WIDTH },
6695  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_67_CHECKER_TYPE,
6696  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_67_WIDTH },
6697  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_68_CHECKER_TYPE,
6698  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_68_WIDTH },
6699  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_69_CHECKER_TYPE,
6700  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_69_WIDTH },
6701  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_70_CHECKER_TYPE,
6702  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_70_WIDTH },
6703  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_71_CHECKER_TYPE,
6704  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_71_WIDTH },
6705 };
6706 
6712 static const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_EDC_CTRL_0_groupEntries[SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_EDC_CTRL_0_MAX_NUM_CHECKERS] =
6713 {
6714  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
6715  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_EDC_CTRL_0_GROUP_0_WIDTH },
6716  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
6717  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_EDC_CTRL_0_GROUP_1_WIDTH },
6718  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
6719  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_EDC_CTRL_0_GROUP_2_WIDTH },
6720  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
6721  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_EDC_CTRL_0_GROUP_3_WIDTH },
6722  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
6723  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_EDC_CTRL_0_GROUP_4_WIDTH },
6724  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
6725  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_EDC_CTRL_0_GROUP_5_WIDTH },
6726  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
6727  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_EDC_CTRL_0_GROUP_6_WIDTH },
6728  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
6729  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_EDC_CTRL_0_GROUP_7_WIDTH },
6730  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
6731  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_EDC_CTRL_0_GROUP_8_WIDTH },
6732  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
6733  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_EDC_CTRL_0_GROUP_9_WIDTH },
6734  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
6735  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_EDC_CTRL_0_GROUP_10_WIDTH },
6736  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
6737  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_EDC_CTRL_0_GROUP_11_WIDTH },
6738  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
6739  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_EDC_CTRL_0_GROUP_12_WIDTH },
6740  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
6741  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_EDC_CTRL_0_GROUP_13_WIDTH },
6742  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
6743  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_EDC_CTRL_0_GROUP_14_WIDTH },
6744  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
6745  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_EDC_CTRL_0_GROUP_15_WIDTH },
6746  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
6747  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_EDC_CTRL_0_GROUP_16_WIDTH },
6748  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
6749  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_EDC_CTRL_0_GROUP_17_WIDTH },
6750 };
6751 
6757 static const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_groupEntries[SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_MAX_NUM_CHECKERS] =
6758 {
6759  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
6760  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_0_WIDTH },
6761  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
6762  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_1_WIDTH },
6763  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
6764  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_2_WIDTH },
6765  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
6766  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_3_WIDTH },
6767  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
6768  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_4_WIDTH },
6769  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
6770  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_5_WIDTH },
6771  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
6772  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_6_WIDTH },
6773  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
6774  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_7_WIDTH },
6775  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
6776  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_8_WIDTH },
6777  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
6778  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_9_WIDTH },
6779  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
6780  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_10_WIDTH },
6781  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
6782  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_11_WIDTH },
6783  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
6784  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_12_WIDTH },
6785  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
6786  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_13_WIDTH },
6787  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
6788  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_14_WIDTH },
6789  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
6790  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_15_WIDTH },
6791  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
6792  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_16_WIDTH },
6793  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
6794  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_17_WIDTH },
6795  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
6796  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_18_WIDTH },
6797  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
6798  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_19_WIDTH },
6799  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
6800  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_20_WIDTH },
6801  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
6802  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_21_WIDTH },
6803  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
6804  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_22_WIDTH },
6805  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
6806  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_23_WIDTH },
6807  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
6808  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_24_WIDTH },
6809  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
6810  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_25_WIDTH },
6811  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
6812  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_26_WIDTH },
6813  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
6814  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_27_WIDTH },
6815  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
6816  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_28_WIDTH },
6817  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
6818  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_29_WIDTH },
6819  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
6820  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_30_WIDTH },
6821  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
6822  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_31_WIDTH },
6823  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
6824  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_32_WIDTH },
6825  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_33_CHECKER_TYPE,
6826  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_33_WIDTH },
6827  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_34_CHECKER_TYPE,
6828  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_34_WIDTH },
6829  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_35_CHECKER_TYPE,
6830  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_35_WIDTH },
6831  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_36_CHECKER_TYPE,
6832  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_36_WIDTH },
6833  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_37_CHECKER_TYPE,
6834  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_37_WIDTH },
6835  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_38_CHECKER_TYPE,
6836  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_38_WIDTH },
6837  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_39_CHECKER_TYPE,
6838  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_39_WIDTH },
6839  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_40_CHECKER_TYPE,
6840  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_40_WIDTH },
6841  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_41_CHECKER_TYPE,
6842  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_41_WIDTH },
6843  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_42_CHECKER_TYPE,
6844  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_42_WIDTH },
6845  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_43_CHECKER_TYPE,
6846  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_43_WIDTH },
6847  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_44_CHECKER_TYPE,
6848  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_44_WIDTH },
6849  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_45_CHECKER_TYPE,
6850  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_45_WIDTH },
6851  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_46_CHECKER_TYPE,
6852  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_46_WIDTH },
6853  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_47_CHECKER_TYPE,
6854  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_47_WIDTH },
6855  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_48_CHECKER_TYPE,
6856  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_48_WIDTH },
6857  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_49_CHECKER_TYPE,
6858  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_49_WIDTH },
6859  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_50_CHECKER_TYPE,
6860  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_50_WIDTH },
6861  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_51_CHECKER_TYPE,
6862  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_51_WIDTH },
6863  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_52_CHECKER_TYPE,
6864  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_52_WIDTH },
6865  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_53_CHECKER_TYPE,
6866  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_53_WIDTH },
6867  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_54_CHECKER_TYPE,
6868  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_54_WIDTH },
6869  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_55_CHECKER_TYPE,
6870  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_55_WIDTH },
6871  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_56_CHECKER_TYPE,
6872  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_56_WIDTH },
6873  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_57_CHECKER_TYPE,
6874  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_57_WIDTH },
6875  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_58_CHECKER_TYPE,
6876  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_58_WIDTH },
6877  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_59_CHECKER_TYPE,
6878  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_59_WIDTH },
6879  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_60_CHECKER_TYPE,
6880  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_60_WIDTH },
6881  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_61_CHECKER_TYPE,
6882  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_61_WIDTH },
6883  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_62_CHECKER_TYPE,
6884  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_62_WIDTH },
6885  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_63_CHECKER_TYPE,
6886  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_63_WIDTH },
6887  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_64_CHECKER_TYPE,
6888  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_64_WIDTH },
6889  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_65_CHECKER_TYPE,
6890  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_65_WIDTH },
6891  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_66_CHECKER_TYPE,
6892  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_66_WIDTH },
6893  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_67_CHECKER_TYPE,
6894  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_67_WIDTH },
6895  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_68_CHECKER_TYPE,
6896  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_68_WIDTH },
6897  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_69_CHECKER_TYPE,
6898  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_69_WIDTH },
6899  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_70_CHECKER_TYPE,
6900  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_70_WIDTH },
6901  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_71_CHECKER_TYPE,
6902  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_71_WIDTH },
6903  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_72_CHECKER_TYPE,
6904  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_72_WIDTH },
6905  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_73_CHECKER_TYPE,
6906  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_73_WIDTH },
6907  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_74_CHECKER_TYPE,
6908  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_74_WIDTH },
6909  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_75_CHECKER_TYPE,
6910  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_75_WIDTH },
6911  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_76_CHECKER_TYPE,
6912  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_76_WIDTH },
6913  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_77_CHECKER_TYPE,
6914  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_77_WIDTH },
6915  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_78_CHECKER_TYPE,
6916  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_78_WIDTH },
6917  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_79_CHECKER_TYPE,
6918  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_79_WIDTH },
6919  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_80_CHECKER_TYPE,
6920  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_80_WIDTH },
6921  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_81_CHECKER_TYPE,
6922  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_81_WIDTH },
6923  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_82_CHECKER_TYPE,
6924  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_82_WIDTH },
6925  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_83_CHECKER_TYPE,
6926  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_83_WIDTH },
6927  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_84_CHECKER_TYPE,
6928  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_84_WIDTH },
6929  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_85_CHECKER_TYPE,
6930  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_85_WIDTH },
6931  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_86_CHECKER_TYPE,
6932  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_86_WIDTH },
6933  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_87_CHECKER_TYPE,
6934  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_87_WIDTH },
6935  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_88_CHECKER_TYPE,
6936  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_88_WIDTH },
6937  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_89_CHECKER_TYPE,
6938  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_89_WIDTH },
6939  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_90_CHECKER_TYPE,
6940  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_90_WIDTH },
6941  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_91_CHECKER_TYPE,
6942  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_91_WIDTH },
6943  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_92_CHECKER_TYPE,
6944  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_92_WIDTH },
6945  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_93_CHECKER_TYPE,
6946  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_93_WIDTH },
6947  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_94_CHECKER_TYPE,
6948  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_94_WIDTH },
6949  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_95_CHECKER_TYPE,
6950  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_95_WIDTH },
6951  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_96_CHECKER_TYPE,
6952  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_96_WIDTH },
6953  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_97_CHECKER_TYPE,
6954  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_97_WIDTH },
6955  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_98_CHECKER_TYPE,
6956  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_98_WIDTH },
6957  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_99_CHECKER_TYPE,
6958  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_99_WIDTH },
6959  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_100_CHECKER_TYPE,
6960  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_100_WIDTH },
6961  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_101_CHECKER_TYPE,
6962  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_101_WIDTH },
6963  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_102_CHECKER_TYPE,
6964  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_102_WIDTH },
6965  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_103_CHECKER_TYPE,
6966  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_103_WIDTH },
6967  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_104_CHECKER_TYPE,
6968  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_104_WIDTH },
6969  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_105_CHECKER_TYPE,
6970  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_105_WIDTH },
6971  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_106_CHECKER_TYPE,
6972  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_106_WIDTH },
6973  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_107_CHECKER_TYPE,
6974  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_107_WIDTH },
6975  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_108_CHECKER_TYPE,
6976  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_108_WIDTH },
6977  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_109_CHECKER_TYPE,
6978  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_109_WIDTH },
6979  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_110_CHECKER_TYPE,
6980  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_110_WIDTH },
6981  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_111_CHECKER_TYPE,
6982  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_111_WIDTH },
6983  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_112_CHECKER_TYPE,
6984  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_112_WIDTH },
6985  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_113_CHECKER_TYPE,
6986  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_113_WIDTH },
6987  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_114_CHECKER_TYPE,
6988  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_114_WIDTH },
6989  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_115_CHECKER_TYPE,
6990  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_115_WIDTH },
6991  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_116_CHECKER_TYPE,
6992  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_116_WIDTH },
6993  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_117_CHECKER_TYPE,
6994  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_117_WIDTH },
6995  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_118_CHECKER_TYPE,
6996  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_118_WIDTH },
6997  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_119_CHECKER_TYPE,
6998  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_119_WIDTH },
6999  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_120_CHECKER_TYPE,
7000  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_120_WIDTH },
7001  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_121_CHECKER_TYPE,
7002  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_121_WIDTH },
7003  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_122_CHECKER_TYPE,
7004  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_122_WIDTH },
7005  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_123_CHECKER_TYPE,
7006  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_123_WIDTH },
7007  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_124_CHECKER_TYPE,
7008  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_124_WIDTH },
7009  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_125_CHECKER_TYPE,
7010  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_125_WIDTH },
7011  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_126_CHECKER_TYPE,
7012  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_126_WIDTH },
7013  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_127_CHECKER_TYPE,
7014  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_127_WIDTH },
7015  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_128_CHECKER_TYPE,
7016  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_128_WIDTH },
7017  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_129_CHECKER_TYPE,
7018  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_129_WIDTH },
7019  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_130_CHECKER_TYPE,
7020  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_130_WIDTH },
7021  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_131_CHECKER_TYPE,
7022  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_131_WIDTH },
7023  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_132_CHECKER_TYPE,
7024  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_132_WIDTH },
7025  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_133_CHECKER_TYPE,
7026  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_133_WIDTH },
7027  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_134_CHECKER_TYPE,
7028  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_134_WIDTH },
7029  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_135_CHECKER_TYPE,
7030  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_135_WIDTH },
7031  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_136_CHECKER_TYPE,
7032  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_136_WIDTH },
7033  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_137_CHECKER_TYPE,
7034  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_137_WIDTH },
7035  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_138_CHECKER_TYPE,
7036  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_138_WIDTH },
7037  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_139_CHECKER_TYPE,
7038  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_139_WIDTH },
7039  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_140_CHECKER_TYPE,
7040  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_140_WIDTH },
7041  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_141_CHECKER_TYPE,
7042  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_141_WIDTH },
7043  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_142_CHECKER_TYPE,
7044  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_142_WIDTH },
7045  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_143_CHECKER_TYPE,
7046  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_143_WIDTH },
7047  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_144_CHECKER_TYPE,
7048  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_144_WIDTH },
7049  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_145_CHECKER_TYPE,
7050  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_145_WIDTH },
7051  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_146_CHECKER_TYPE,
7052  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_146_WIDTH },
7053  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_147_CHECKER_TYPE,
7054  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_147_WIDTH },
7055  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_148_CHECKER_TYPE,
7056  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_148_WIDTH },
7057  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_149_CHECKER_TYPE,
7058  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_149_WIDTH },
7059  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_150_CHECKER_TYPE,
7060  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_150_WIDTH },
7061  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_151_CHECKER_TYPE,
7062  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_151_WIDTH },
7063  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_152_CHECKER_TYPE,
7064  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_152_WIDTH },
7065  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_153_CHECKER_TYPE,
7066  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_153_WIDTH },
7067  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_154_CHECKER_TYPE,
7068  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_154_WIDTH },
7069  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_155_CHECKER_TYPE,
7070  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_155_WIDTH },
7071  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_156_CHECKER_TYPE,
7072  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_156_WIDTH },
7073  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_157_CHECKER_TYPE,
7074  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_157_WIDTH },
7075  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_158_CHECKER_TYPE,
7076  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_158_WIDTH },
7077  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_159_CHECKER_TYPE,
7078  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_159_WIDTH },
7079  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_160_CHECKER_TYPE,
7080  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_160_WIDTH },
7081  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_161_CHECKER_TYPE,
7082  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_161_WIDTH },
7083  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_162_CHECKER_TYPE,
7084  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_162_WIDTH },
7085  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_163_CHECKER_TYPE,
7086  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_163_WIDTH },
7087  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_164_CHECKER_TYPE,
7088  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_164_WIDTH },
7089  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_165_CHECKER_TYPE,
7090  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_165_WIDTH },
7091  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_166_CHECKER_TYPE,
7092  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_166_WIDTH },
7093  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_167_CHECKER_TYPE,
7094  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_167_WIDTH },
7095  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_168_CHECKER_TYPE,
7096  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_168_WIDTH },
7097  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_169_CHECKER_TYPE,
7098  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_169_WIDTH },
7099  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_170_CHECKER_TYPE,
7100  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_170_WIDTH },
7101  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_171_CHECKER_TYPE,
7102  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_171_WIDTH },
7103  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_172_CHECKER_TYPE,
7104  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_172_WIDTH },
7105  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_173_CHECKER_TYPE,
7106  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_173_WIDTH },
7107  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_174_CHECKER_TYPE,
7108  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_174_WIDTH },
7109  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_175_CHECKER_TYPE,
7110  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_175_WIDTH },
7111  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_176_CHECKER_TYPE,
7112  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_176_WIDTH },
7113  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_177_CHECKER_TYPE,
7114  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_177_WIDTH },
7115  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_178_CHECKER_TYPE,
7116  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_178_WIDTH },
7117  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_179_CHECKER_TYPE,
7118  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_179_WIDTH },
7119  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_180_CHECKER_TYPE,
7120  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_180_WIDTH },
7121  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_181_CHECKER_TYPE,
7122  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_181_WIDTH },
7123  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_182_CHECKER_TYPE,
7124  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_182_WIDTH },
7125  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_183_CHECKER_TYPE,
7126  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_183_WIDTH },
7127  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_184_CHECKER_TYPE,
7128  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_184_WIDTH },
7129  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_185_CHECKER_TYPE,
7130  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_185_WIDTH },
7131  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_186_CHECKER_TYPE,
7132  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_186_WIDTH },
7133  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_187_CHECKER_TYPE,
7134  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_187_WIDTH },
7135  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_188_CHECKER_TYPE,
7136  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_188_WIDTH },
7137  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_189_CHECKER_TYPE,
7138  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_189_WIDTH },
7139  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_190_CHECKER_TYPE,
7140  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_190_WIDTH },
7141  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_191_CHECKER_TYPE,
7142  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_191_WIDTH },
7143  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_192_CHECKER_TYPE,
7144  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_192_WIDTH },
7145  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_193_CHECKER_TYPE,
7146  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_193_WIDTH },
7147  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_194_CHECKER_TYPE,
7148  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_194_WIDTH },
7149  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_195_CHECKER_TYPE,
7150  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_195_WIDTH },
7151  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_196_CHECKER_TYPE,
7152  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_196_WIDTH },
7153  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_197_CHECKER_TYPE,
7154  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_197_WIDTH },
7155  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_198_CHECKER_TYPE,
7156  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_198_WIDTH },
7157  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_199_CHECKER_TYPE,
7158  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_199_WIDTH },
7159  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_200_CHECKER_TYPE,
7160  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_200_WIDTH },
7161  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_201_CHECKER_TYPE,
7162  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_201_WIDTH },
7163  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_202_CHECKER_TYPE,
7164  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_202_WIDTH },
7165  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_203_CHECKER_TYPE,
7166  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_203_WIDTH },
7167  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_204_CHECKER_TYPE,
7168  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_204_WIDTH },
7169  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_205_CHECKER_TYPE,
7170  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_205_WIDTH },
7171  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_206_CHECKER_TYPE,
7172  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_206_WIDTH },
7173  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_207_CHECKER_TYPE,
7174  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_207_WIDTH },
7175  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_208_CHECKER_TYPE,
7176  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_208_WIDTH },
7177  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_209_CHECKER_TYPE,
7178  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_209_WIDTH },
7179  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_210_CHECKER_TYPE,
7180  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_210_WIDTH },
7181  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_211_CHECKER_TYPE,
7182  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_211_WIDTH },
7183  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_212_CHECKER_TYPE,
7184  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_212_WIDTH },
7185  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_213_CHECKER_TYPE,
7186  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_213_WIDTH },
7187  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_214_CHECKER_TYPE,
7188  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_214_WIDTH },
7189  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_215_CHECKER_TYPE,
7190  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_215_WIDTH },
7191  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_216_CHECKER_TYPE,
7192  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_216_WIDTH },
7193  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_217_CHECKER_TYPE,
7194  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_217_WIDTH },
7195  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_218_CHECKER_TYPE,
7196  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_218_WIDTH },
7197  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_219_CHECKER_TYPE,
7198  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_219_WIDTH },
7199  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_220_CHECKER_TYPE,
7200  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_220_WIDTH },
7201  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_221_CHECKER_TYPE,
7202  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_221_WIDTH },
7203  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_222_CHECKER_TYPE,
7204  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_222_WIDTH },
7205  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_223_CHECKER_TYPE,
7206  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_223_WIDTH },
7207  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_224_CHECKER_TYPE,
7208  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_224_WIDTH },
7209  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_225_CHECKER_TYPE,
7210  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_225_WIDTH },
7211  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_226_CHECKER_TYPE,
7212  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_226_WIDTH },
7213  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_227_CHECKER_TYPE,
7214  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_227_WIDTH },
7215  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_228_CHECKER_TYPE,
7216  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_228_WIDTH },
7217  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_229_CHECKER_TYPE,
7218  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_229_WIDTH },
7219  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_230_CHECKER_TYPE,
7220  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_230_WIDTH },
7221  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_231_CHECKER_TYPE,
7222  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_231_WIDTH },
7223  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_232_CHECKER_TYPE,
7224  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_232_WIDTH },
7225  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_233_CHECKER_TYPE,
7226  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_233_WIDTH },
7227  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_234_CHECKER_TYPE,
7228  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_234_WIDTH },
7229  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_235_CHECKER_TYPE,
7230  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_235_WIDTH },
7231  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_236_CHECKER_TYPE,
7232  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_236_WIDTH },
7233  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_237_CHECKER_TYPE,
7234  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_237_WIDTH },
7235  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_238_CHECKER_TYPE,
7236  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_238_WIDTH },
7237  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_239_CHECKER_TYPE,
7238  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_239_WIDTH },
7239  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_240_CHECKER_TYPE,
7240  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_240_WIDTH },
7241  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_241_CHECKER_TYPE,
7242  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_241_WIDTH },
7243  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_242_CHECKER_TYPE,
7244  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_242_WIDTH },
7245  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_243_CHECKER_TYPE,
7246  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_243_WIDTH },
7247  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_244_CHECKER_TYPE,
7248  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_244_WIDTH },
7249  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_245_CHECKER_TYPE,
7250  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_245_WIDTH },
7251  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_246_CHECKER_TYPE,
7252  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_246_WIDTH },
7253  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_247_CHECKER_TYPE,
7254  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_247_WIDTH },
7255  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_248_CHECKER_TYPE,
7256  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_248_WIDTH },
7257  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_249_CHECKER_TYPE,
7258  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_249_WIDTH },
7259  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_250_CHECKER_TYPE,
7260  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_250_WIDTH },
7261  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_251_CHECKER_TYPE,
7262  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_251_WIDTH },
7263  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_252_CHECKER_TYPE,
7264  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_252_WIDTH },
7265  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_253_CHECKER_TYPE,
7266  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_253_WIDTH },
7267  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_254_CHECKER_TYPE,
7268  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_254_WIDTH },
7269  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_255_CHECKER_TYPE,
7270  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_255_WIDTH },
7271 };
7272 
7278 static const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_groupEntries[SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_MAX_NUM_CHECKERS] =
7279 {
7280  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_0_CHECKER_TYPE,
7281  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_0_WIDTH },
7282  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_1_CHECKER_TYPE,
7283  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_1_WIDTH },
7284  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_2_CHECKER_TYPE,
7285  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_2_WIDTH },
7286  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_3_CHECKER_TYPE,
7287  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_3_WIDTH },
7288  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_4_CHECKER_TYPE,
7289  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_4_WIDTH },
7290  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_5_CHECKER_TYPE,
7291  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_5_WIDTH },
7292  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_6_CHECKER_TYPE,
7293  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_6_WIDTH },
7294  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_7_CHECKER_TYPE,
7295  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_7_WIDTH },
7296  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_8_CHECKER_TYPE,
7297  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_8_WIDTH },
7298  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_9_CHECKER_TYPE,
7299  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_9_WIDTH },
7300  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_10_CHECKER_TYPE,
7301  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_10_WIDTH },
7302  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_11_CHECKER_TYPE,
7303  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_11_WIDTH },
7304  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_12_CHECKER_TYPE,
7305  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_12_WIDTH },
7306  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_13_CHECKER_TYPE,
7307  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_13_WIDTH },
7308  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_14_CHECKER_TYPE,
7309  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_14_WIDTH },
7310  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_15_CHECKER_TYPE,
7311  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_15_WIDTH },
7312  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_16_CHECKER_TYPE,
7313  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_16_WIDTH },
7314  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_17_CHECKER_TYPE,
7315  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_17_WIDTH },
7316  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_18_CHECKER_TYPE,
7317  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_18_WIDTH },
7318  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_19_CHECKER_TYPE,
7319  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_19_WIDTH },
7320  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_20_CHECKER_TYPE,
7321  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_20_WIDTH },
7322  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_21_CHECKER_TYPE,
7323  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_21_WIDTH },
7324  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_22_CHECKER_TYPE,
7325  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_22_WIDTH },
7326  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_23_CHECKER_TYPE,
7327  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_23_WIDTH },
7328  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_24_CHECKER_TYPE,
7329  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_24_WIDTH },
7330  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_25_CHECKER_TYPE,
7331  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_25_WIDTH },
7332  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_26_CHECKER_TYPE,
7333  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_26_WIDTH },
7334  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_27_CHECKER_TYPE,
7335  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_27_WIDTH },
7336  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_28_CHECKER_TYPE,
7337  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_28_WIDTH },
7338  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_29_CHECKER_TYPE,
7339  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_29_WIDTH },
7340  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_30_CHECKER_TYPE,
7341  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_30_WIDTH },
7342  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_31_CHECKER_TYPE,
7343  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_31_WIDTH },
7344  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_32_CHECKER_TYPE,
7345  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_32_WIDTH },
7346  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_33_CHECKER_TYPE,
7347  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_33_WIDTH },
7348  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_34_CHECKER_TYPE,
7349  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_34_WIDTH },
7350  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_35_CHECKER_TYPE,
7351  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_35_WIDTH },
7352  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_36_CHECKER_TYPE,
7353  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_36_WIDTH },
7354  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_37_CHECKER_TYPE,
7355  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_37_WIDTH },
7356  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_38_CHECKER_TYPE,
7357  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_38_WIDTH },
7358  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_39_CHECKER_TYPE,
7359  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_39_WIDTH },
7360  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_40_CHECKER_TYPE,
7361  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_40_WIDTH },
7362  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_41_CHECKER_TYPE,
7363  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_41_WIDTH },
7364  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_42_CHECKER_TYPE,
7365  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_42_WIDTH },
7366  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_43_CHECKER_TYPE,
7367  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_43_WIDTH },
7368  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_44_CHECKER_TYPE,
7369  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_44_WIDTH },
7370  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_45_CHECKER_TYPE,
7371  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_45_WIDTH },
7372  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_46_CHECKER_TYPE,
7373  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_46_WIDTH },
7374  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_47_CHECKER_TYPE,
7375  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_47_WIDTH },
7376  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_48_CHECKER_TYPE,
7377  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_48_WIDTH },
7378  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_49_CHECKER_TYPE,
7379  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_49_WIDTH },
7380  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_50_CHECKER_TYPE,
7381  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_50_WIDTH },
7382  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_51_CHECKER_TYPE,
7383  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_51_WIDTH },
7384  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_52_CHECKER_TYPE,
7385  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_52_WIDTH },
7386  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_53_CHECKER_TYPE,
7387  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_53_WIDTH },
7388  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_54_CHECKER_TYPE,
7389  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_54_WIDTH },
7390  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_55_CHECKER_TYPE,
7391  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_55_WIDTH },
7392  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_56_CHECKER_TYPE,
7393  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_56_WIDTH },
7394 };
7395 
7401 static const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_groupEntries[SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_MAX_NUM_CHECKERS] =
7402 {
7403  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
7404  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_0_WIDTH },
7405  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
7406  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_1_WIDTH },
7407  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
7408  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_2_WIDTH },
7409  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
7410  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_3_WIDTH },
7411  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
7412  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_4_WIDTH },
7413  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
7414  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_5_WIDTH },
7415  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
7416  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_6_WIDTH },
7417  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
7418  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_7_WIDTH },
7419  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
7420  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_8_WIDTH },
7421  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
7422  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_9_WIDTH },
7423  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
7424  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_10_WIDTH },
7425  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
7426  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_11_WIDTH },
7427  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
7428  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_12_WIDTH },
7429  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
7430  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_13_WIDTH },
7431  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
7432  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_14_WIDTH },
7433  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
7434  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_15_WIDTH },
7435  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
7436  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_16_WIDTH },
7437  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
7438  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_17_WIDTH },
7439  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
7440  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_18_WIDTH },
7441  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
7442  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_19_WIDTH },
7443  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
7444  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_20_WIDTH },
7445  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
7446  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_21_WIDTH },
7447  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
7448  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_22_WIDTH },
7449  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
7450  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_23_WIDTH },
7451  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
7452  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_24_WIDTH },
7453  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
7454  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_25_WIDTH },
7455  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
7456  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_26_WIDTH },
7457  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
7458  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_27_WIDTH },
7459  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
7460  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_28_WIDTH },
7461  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
7462  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_29_WIDTH },
7463  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
7464  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_30_WIDTH },
7465  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
7466  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_31_WIDTH },
7467  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
7468  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_32_WIDTH },
7469  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_33_CHECKER_TYPE,
7470  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_33_WIDTH },
7471  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_34_CHECKER_TYPE,
7472  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_34_WIDTH },
7473  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_35_CHECKER_TYPE,
7474  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_35_WIDTH },
7475  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_36_CHECKER_TYPE,
7476  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_36_WIDTH },
7477  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_37_CHECKER_TYPE,
7478  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_37_WIDTH },
7479  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_38_CHECKER_TYPE,
7480  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_38_WIDTH },
7481  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_39_CHECKER_TYPE,
7482  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_39_WIDTH },
7483  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_40_CHECKER_TYPE,
7484  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_40_WIDTH },
7485  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_41_CHECKER_TYPE,
7486  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_41_WIDTH },
7487  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_42_CHECKER_TYPE,
7488  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_42_WIDTH },
7489  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_43_CHECKER_TYPE,
7490  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_43_WIDTH },
7491  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_44_CHECKER_TYPE,
7492  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_44_WIDTH },
7493  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_45_CHECKER_TYPE,
7494  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_45_WIDTH },
7495  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_46_CHECKER_TYPE,
7496  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_46_WIDTH },
7497  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_47_CHECKER_TYPE,
7498  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_47_WIDTH },
7499  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_48_CHECKER_TYPE,
7500  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_48_WIDTH },
7501  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_49_CHECKER_TYPE,
7502  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_49_WIDTH },
7503  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_50_CHECKER_TYPE,
7504  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_50_WIDTH },
7505  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_51_CHECKER_TYPE,
7506  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_51_WIDTH },
7507  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_52_CHECKER_TYPE,
7508  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_52_WIDTH },
7509  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_53_CHECKER_TYPE,
7510  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_53_WIDTH },
7511  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_54_CHECKER_TYPE,
7512  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_54_WIDTH },
7513  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_55_CHECKER_TYPE,
7514  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_55_WIDTH },
7515  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_56_CHECKER_TYPE,
7516  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_56_WIDTH },
7517  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_57_CHECKER_TYPE,
7518  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_57_WIDTH },
7519  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_58_CHECKER_TYPE,
7520  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_58_WIDTH },
7521  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_59_CHECKER_TYPE,
7522  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_59_WIDTH },
7523  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_60_CHECKER_TYPE,
7524  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_60_WIDTH },
7525  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_61_CHECKER_TYPE,
7526  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_61_WIDTH },
7527  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_62_CHECKER_TYPE,
7528  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_62_WIDTH },
7529  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_63_CHECKER_TYPE,
7530  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_63_WIDTH },
7531  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_64_CHECKER_TYPE,
7532  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_64_WIDTH },
7533  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_65_CHECKER_TYPE,
7534  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_65_WIDTH },
7535  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_66_CHECKER_TYPE,
7536  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_66_WIDTH },
7537 };
7538 
7544 static const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries[SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS] =
7545 {
7546  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
7547  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_0_WIDTH },
7548  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
7549  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_1_WIDTH },
7550  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
7551  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_2_WIDTH },
7552  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
7553  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_3_WIDTH },
7554  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
7555  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_4_WIDTH },
7556  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
7557  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_5_WIDTH },
7558  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
7559  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_6_WIDTH },
7560  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
7561  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_7_WIDTH },
7562  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
7563  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_8_WIDTH },
7564  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
7565  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_9_WIDTH },
7566  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
7567  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_10_WIDTH },
7568  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
7569  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_11_WIDTH },
7570  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
7571  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_12_WIDTH },
7572  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
7573  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_13_WIDTH },
7574  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
7575  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_14_WIDTH },
7576  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
7577  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_15_WIDTH },
7578  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
7579  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_16_WIDTH },
7580  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
7581  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_17_WIDTH },
7582  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
7583  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_18_WIDTH },
7584  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
7585  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_19_WIDTH },
7586  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
7587  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_20_WIDTH },
7588  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
7589  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_21_WIDTH },
7590  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
7591  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_22_WIDTH },
7592  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
7593  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_23_WIDTH },
7594  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
7595  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_24_WIDTH },
7596  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
7597  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_25_WIDTH },
7598  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
7599  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_26_WIDTH },
7600  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
7601  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_27_WIDTH },
7602  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
7603  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_28_WIDTH },
7604  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
7605  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_29_WIDTH },
7606  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
7607  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_30_WIDTH },
7608  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
7609  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_31_WIDTH },
7610  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
7611  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_32_WIDTH },
7612  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_33_CHECKER_TYPE,
7613  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_33_WIDTH },
7614  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_34_CHECKER_TYPE,
7615  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_34_WIDTH },
7616  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_35_CHECKER_TYPE,
7617  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_35_WIDTH },
7618  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_36_CHECKER_TYPE,
7619  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_36_WIDTH },
7620  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_37_CHECKER_TYPE,
7621  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_37_WIDTH },
7622  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_38_CHECKER_TYPE,
7623  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_38_WIDTH },
7624  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_39_CHECKER_TYPE,
7625  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_39_WIDTH },
7626  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_40_CHECKER_TYPE,
7627  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_40_WIDTH },
7628  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_41_CHECKER_TYPE,
7629  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_41_WIDTH },
7630  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_42_CHECKER_TYPE,
7631  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_42_WIDTH },
7632  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_43_CHECKER_TYPE,
7633  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_43_WIDTH },
7634  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_44_CHECKER_TYPE,
7635  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_44_WIDTH },
7636  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_45_CHECKER_TYPE,
7637  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_45_WIDTH },
7638  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_46_CHECKER_TYPE,
7639  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_46_WIDTH },
7640  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_47_CHECKER_TYPE,
7641  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_47_WIDTH },
7642  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_48_CHECKER_TYPE,
7643  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_48_WIDTH },
7644  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_49_CHECKER_TYPE,
7645  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_49_WIDTH },
7646  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_50_CHECKER_TYPE,
7647  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_50_WIDTH },
7648  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_51_CHECKER_TYPE,
7649  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_51_WIDTH },
7650  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_52_CHECKER_TYPE,
7651  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_52_WIDTH },
7652  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_53_CHECKER_TYPE,
7653  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_53_WIDTH },
7654  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_54_CHECKER_TYPE,
7655  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_54_WIDTH },
7656  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_55_CHECKER_TYPE,
7657  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_55_WIDTH },
7658  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_56_CHECKER_TYPE,
7659  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_56_WIDTH },
7660  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_57_CHECKER_TYPE,
7661  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_57_WIDTH },
7662  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_58_CHECKER_TYPE,
7663  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_58_WIDTH },
7664  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_59_CHECKER_TYPE,
7665  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_59_WIDTH },
7666  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_60_CHECKER_TYPE,
7667  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_60_WIDTH },
7668  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_61_CHECKER_TYPE,
7669  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_61_WIDTH },
7670  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_62_CHECKER_TYPE,
7671  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_62_WIDTH },
7672  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_63_CHECKER_TYPE,
7673  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_63_WIDTH },
7674  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_64_CHECKER_TYPE,
7675  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_64_WIDTH },
7676  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_65_CHECKER_TYPE,
7677  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_65_WIDTH },
7678  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_66_CHECKER_TYPE,
7679  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_66_WIDTH },
7680  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_67_CHECKER_TYPE,
7681  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_67_WIDTH },
7682  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_68_CHECKER_TYPE,
7683  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_68_WIDTH },
7684  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_69_CHECKER_TYPE,
7685  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_69_WIDTH },
7686  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_70_CHECKER_TYPE,
7687  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_70_WIDTH },
7688  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_71_CHECKER_TYPE,
7689  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_71_WIDTH },
7690 };
7691 
7697 static const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_groupEntries[SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_MAX_NUM_CHECKERS] =
7698 {
7699  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
7700  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_0_WIDTH },
7701  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
7702  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_1_WIDTH },
7703  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
7704  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_2_WIDTH },
7705  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
7706  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_3_WIDTH },
7707  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
7708  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_4_WIDTH },
7709  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
7710  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_5_WIDTH },
7711  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
7712  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_6_WIDTH },
7713  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
7714  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_7_WIDTH },
7715  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
7716  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_8_WIDTH },
7717  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
7718  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_9_WIDTH },
7719  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
7720  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_10_WIDTH },
7721  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
7722  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_11_WIDTH },
7723  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
7724  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_12_WIDTH },
7725  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
7726  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_13_WIDTH },
7727  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
7728  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_14_WIDTH },
7729  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
7730  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_15_WIDTH },
7731  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
7732  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_16_WIDTH },
7733  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
7734  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_17_WIDTH },
7735  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
7736  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_18_WIDTH },
7737  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
7738  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_19_WIDTH },
7739  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
7740  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_20_WIDTH },
7741  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
7742  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_21_WIDTH },
7743  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
7744  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_22_WIDTH },
7745  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
7746  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_23_WIDTH },
7747  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
7748  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_24_WIDTH },
7749  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
7750  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_25_WIDTH },
7751  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
7752  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_26_WIDTH },
7753  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
7754  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_27_WIDTH },
7755  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
7756  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_28_WIDTH },
7757  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
7758  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_29_WIDTH },
7759  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
7760  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_30_WIDTH },
7761  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
7762  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_31_WIDTH },
7763  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
7764  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_32_WIDTH },
7765  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_33_CHECKER_TYPE,
7766  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_33_WIDTH },
7767  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_34_CHECKER_TYPE,
7768  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_34_WIDTH },
7769  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_35_CHECKER_TYPE,
7770  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_35_WIDTH },
7771  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_36_CHECKER_TYPE,
7772  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_36_WIDTH },
7773  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_37_CHECKER_TYPE,
7774  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_37_WIDTH },
7775  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_38_CHECKER_TYPE,
7776  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_38_WIDTH },
7777  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_39_CHECKER_TYPE,
7778  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_39_WIDTH },
7779  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_40_CHECKER_TYPE,
7780  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_40_WIDTH },
7781  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_41_CHECKER_TYPE,
7782  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_41_WIDTH },
7783  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_42_CHECKER_TYPE,
7784  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_42_WIDTH },
7785  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_43_CHECKER_TYPE,
7786  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_43_WIDTH },
7787  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_44_CHECKER_TYPE,
7788  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_44_WIDTH },
7789  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_45_CHECKER_TYPE,
7790  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_45_WIDTH },
7791  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_46_CHECKER_TYPE,
7792  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_46_WIDTH },
7793  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_47_CHECKER_TYPE,
7794  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_47_WIDTH },
7795  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_48_CHECKER_TYPE,
7796  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_48_WIDTH },
7797  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_49_CHECKER_TYPE,
7798  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_49_WIDTH },
7799  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_50_CHECKER_TYPE,
7800  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_50_WIDTH },
7801  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_51_CHECKER_TYPE,
7802  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_51_WIDTH },
7803  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_52_CHECKER_TYPE,
7804  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_52_WIDTH },
7805  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_53_CHECKER_TYPE,
7806  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_53_WIDTH },
7807  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_54_CHECKER_TYPE,
7808  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_54_WIDTH },
7809  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_55_CHECKER_TYPE,
7810  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_55_WIDTH },
7811  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_56_CHECKER_TYPE,
7812  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_56_WIDTH },
7813  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_57_CHECKER_TYPE,
7814  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_57_WIDTH },
7815  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_58_CHECKER_TYPE,
7816  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_58_WIDTH },
7817  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_59_CHECKER_TYPE,
7818  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_59_WIDTH },
7819  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_60_CHECKER_TYPE,
7820  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_60_WIDTH },
7821  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_61_CHECKER_TYPE,
7822  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_61_WIDTH },
7823  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_62_CHECKER_TYPE,
7824  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_62_WIDTH },
7825  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_63_CHECKER_TYPE,
7826  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_63_WIDTH },
7827  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_64_CHECKER_TYPE,
7828  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_64_WIDTH },
7829  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_65_CHECKER_TYPE,
7830  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_65_WIDTH },
7831  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_66_CHECKER_TYPE,
7832  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_66_WIDTH },
7833  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_67_CHECKER_TYPE,
7834  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_67_WIDTH },
7835  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_68_CHECKER_TYPE,
7836  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_68_WIDTH },
7837  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_69_CHECKER_TYPE,
7838  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_69_WIDTH },
7839  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_70_CHECKER_TYPE,
7840  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_70_WIDTH },
7841  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_71_CHECKER_TYPE,
7842  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_71_WIDTH },
7843  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_72_CHECKER_TYPE,
7844  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_72_WIDTH },
7845  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_73_CHECKER_TYPE,
7846  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_73_WIDTH },
7847  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_74_CHECKER_TYPE,
7848  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_74_WIDTH },
7849  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_75_CHECKER_TYPE,
7850  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_75_WIDTH },
7851  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_76_CHECKER_TYPE,
7852  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_76_WIDTH },
7853  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_77_CHECKER_TYPE,
7854  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_77_WIDTH },
7855  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_78_CHECKER_TYPE,
7856  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_78_WIDTH },
7857  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_79_CHECKER_TYPE,
7858  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_79_WIDTH },
7859  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_80_CHECKER_TYPE,
7860  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_80_WIDTH },
7861  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_81_CHECKER_TYPE,
7862  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_81_WIDTH },
7863  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_82_CHECKER_TYPE,
7864  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_82_WIDTH },
7865  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_83_CHECKER_TYPE,
7866  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_83_WIDTH },
7867  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_84_CHECKER_TYPE,
7868  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_84_WIDTH },
7869  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_85_CHECKER_TYPE,
7870  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_85_WIDTH },
7871  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_86_CHECKER_TYPE,
7872  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_86_WIDTH },
7873  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_87_CHECKER_TYPE,
7874  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_87_WIDTH },
7875  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_88_CHECKER_TYPE,
7876  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_88_WIDTH },
7877  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_89_CHECKER_TYPE,
7878  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_89_WIDTH },
7879  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_90_CHECKER_TYPE,
7880  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_90_WIDTH },
7881  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_91_CHECKER_TYPE,
7882  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_91_WIDTH },
7883  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_92_CHECKER_TYPE,
7884  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_92_WIDTH },
7885  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_93_CHECKER_TYPE,
7886  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_93_WIDTH },
7887  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_94_CHECKER_TYPE,
7888  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_94_WIDTH },
7889  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_95_CHECKER_TYPE,
7890  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_95_WIDTH },
7891  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_96_CHECKER_TYPE,
7892  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_96_WIDTH },
7893  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_97_CHECKER_TYPE,
7894  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_97_WIDTH },
7895  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_98_CHECKER_TYPE,
7896  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_98_WIDTH },
7897  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_99_CHECKER_TYPE,
7898  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_99_WIDTH },
7899  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_100_CHECKER_TYPE,
7900  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_100_WIDTH },
7901  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_101_CHECKER_TYPE,
7902  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_101_WIDTH },
7903  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_102_CHECKER_TYPE,
7904  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_102_WIDTH },
7905  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_103_CHECKER_TYPE,
7906  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_103_WIDTH },
7907  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_104_CHECKER_TYPE,
7908  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_104_WIDTH },
7909  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_105_CHECKER_TYPE,
7910  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_105_WIDTH },
7911  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_106_CHECKER_TYPE,
7912  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_106_WIDTH },
7913  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_107_CHECKER_TYPE,
7914  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_107_WIDTH },
7915  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_108_CHECKER_TYPE,
7916  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_108_WIDTH },
7917  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_109_CHECKER_TYPE,
7918  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_109_WIDTH },
7919  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_110_CHECKER_TYPE,
7920  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_110_WIDTH },
7921  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_111_CHECKER_TYPE,
7922  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_111_WIDTH },
7923  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_112_CHECKER_TYPE,
7924  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_112_WIDTH },
7925  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_113_CHECKER_TYPE,
7926  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_113_WIDTH },
7927  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_114_CHECKER_TYPE,
7928  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_114_WIDTH },
7929  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_115_CHECKER_TYPE,
7930  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_115_WIDTH },
7931  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_116_CHECKER_TYPE,
7932  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_116_WIDTH },
7933  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_117_CHECKER_TYPE,
7934  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_117_WIDTH },
7935  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_118_CHECKER_TYPE,
7936  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_118_WIDTH },
7937  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_119_CHECKER_TYPE,
7938  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_119_WIDTH },
7939  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_120_CHECKER_TYPE,
7940  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_120_WIDTH },
7941  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_121_CHECKER_TYPE,
7942  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_121_WIDTH },
7943  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_122_CHECKER_TYPE,
7944  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_122_WIDTH },
7945  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_123_CHECKER_TYPE,
7946  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_123_WIDTH },
7947  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_124_CHECKER_TYPE,
7948  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_124_WIDTH },
7949  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_125_CHECKER_TYPE,
7950  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_125_WIDTH },
7951  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_126_CHECKER_TYPE,
7952  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_126_WIDTH },
7953  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_127_CHECKER_TYPE,
7954  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_127_WIDTH },
7955  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_128_CHECKER_TYPE,
7956  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_128_WIDTH },
7957  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_129_CHECKER_TYPE,
7958  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_129_WIDTH },
7959  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_130_CHECKER_TYPE,
7960  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_130_WIDTH },
7961  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_131_CHECKER_TYPE,
7962  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_131_WIDTH },
7963 };
7964 
7970 static const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_VD2GCLK_EDC_CTRL_0_groupEntries[SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_VD2GCLK_EDC_CTRL_0_MAX_NUM_CHECKERS] =
7971 {
7972  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
7973  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_0_WIDTH },
7974  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
7975  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_1_WIDTH },
7976  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
7977  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_2_WIDTH },
7978 };
7979 
7985 static const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_groupEntries[SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_MAX_NUM_CHECKERS] =
7986 {
7987  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
7988  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_0_WIDTH },
7989  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
7990  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_1_WIDTH },
7991  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
7992  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_2_WIDTH },
7993  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
7994  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_3_WIDTH },
7995  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
7996  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_4_WIDTH },
7997  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
7998  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_5_WIDTH },
7999  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
8000  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_6_WIDTH },
8001  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
8002  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_7_WIDTH },
8003  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
8004  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_8_WIDTH },
8005  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
8006  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_9_WIDTH },
8007  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
8008  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_10_WIDTH },
8009  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
8010  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_11_WIDTH },
8011  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
8012  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_12_WIDTH },
8013  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
8014  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_13_WIDTH },
8015  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
8016  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_14_WIDTH },
8017  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
8018  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_15_WIDTH },
8019  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
8020  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_16_WIDTH },
8021  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
8022  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_17_WIDTH },
8023  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
8024  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_18_WIDTH },
8025  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
8026  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_19_WIDTH },
8027  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
8028  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_20_WIDTH },
8029  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
8030  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_21_WIDTH },
8031  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
8032  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_22_WIDTH },
8033  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
8034  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_23_WIDTH },
8035  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
8036  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_24_WIDTH },
8037  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
8038  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_25_WIDTH },
8039  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
8040  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_26_WIDTH },
8041  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
8042  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_27_WIDTH },
8043  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
8044  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_28_WIDTH },
8045  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
8046  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_29_WIDTH },
8047  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
8048  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_30_WIDTH },
8049  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
8050  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_31_WIDTH },
8051  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
8052  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_32_WIDTH },
8053  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_33_CHECKER_TYPE,
8054  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_33_WIDTH },
8055  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_34_CHECKER_TYPE,
8056  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_34_WIDTH },
8057  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_35_CHECKER_TYPE,
8058  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_35_WIDTH },
8059  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_36_CHECKER_TYPE,
8060  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_36_WIDTH },
8061  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_37_CHECKER_TYPE,
8062  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_37_WIDTH },
8063  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_38_CHECKER_TYPE,
8064  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_38_WIDTH },
8065  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_39_CHECKER_TYPE,
8066  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_39_WIDTH },
8067  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_40_CHECKER_TYPE,
8068  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_40_WIDTH },
8069  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_41_CHECKER_TYPE,
8070  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_41_WIDTH },
8071  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_42_CHECKER_TYPE,
8072  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_42_WIDTH },
8073  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_43_CHECKER_TYPE,
8074  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_43_WIDTH },
8075  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_44_CHECKER_TYPE,
8076  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_44_WIDTH },
8077  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_45_CHECKER_TYPE,
8078  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_45_WIDTH },
8079  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_46_CHECKER_TYPE,
8080  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_46_WIDTH },
8081  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_47_CHECKER_TYPE,
8082  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_47_WIDTH },
8083  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_48_CHECKER_TYPE,
8084  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_48_WIDTH },
8085  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_49_CHECKER_TYPE,
8086  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_49_WIDTH },
8087  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_50_CHECKER_TYPE,
8088  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_50_WIDTH },
8089  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_51_CHECKER_TYPE,
8090  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_51_WIDTH },
8091  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_52_CHECKER_TYPE,
8092  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_52_WIDTH },
8093  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_53_CHECKER_TYPE,
8094  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_53_WIDTH },
8095  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_54_CHECKER_TYPE,
8096  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_54_WIDTH },
8097  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_55_CHECKER_TYPE,
8098  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_55_WIDTH },
8099  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_56_CHECKER_TYPE,
8100  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_56_WIDTH },
8101  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_57_CHECKER_TYPE,
8102  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_57_WIDTH },
8103  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_58_CHECKER_TYPE,
8104  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_58_WIDTH },
8105  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_59_CHECKER_TYPE,
8106  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_59_WIDTH },
8107  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_60_CHECKER_TYPE,
8108  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_60_WIDTH },
8109  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_61_CHECKER_TYPE,
8110  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_61_WIDTH },
8111  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_62_CHECKER_TYPE,
8112  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_62_WIDTH },
8113 };
8114 
8120 static const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_groupEntries[SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_MAX_NUM_CHECKERS] =
8121 {
8122  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
8123  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_0_WIDTH },
8124  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
8125  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_1_WIDTH },
8126  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
8127  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_2_WIDTH },
8128  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
8129  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_3_WIDTH },
8130  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
8131  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_4_WIDTH },
8132  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
8133  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_5_WIDTH },
8134  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
8135  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_6_WIDTH },
8136  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
8137  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_7_WIDTH },
8138  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
8139  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_8_WIDTH },
8140  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
8141  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_9_WIDTH },
8142  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
8143  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_10_WIDTH },
8144  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
8145  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_11_WIDTH },
8146  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
8147  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_12_WIDTH },
8148  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
8149  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_13_WIDTH },
8150  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
8151  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_14_WIDTH },
8152  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
8153  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_15_WIDTH },
8154  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
8155  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_16_WIDTH },
8156  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
8157  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_17_WIDTH },
8158  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
8159  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_18_WIDTH },
8160  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
8161  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_19_WIDTH },
8162  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
8163  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_20_WIDTH },
8164  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
8165  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_21_WIDTH },
8166  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
8167  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_22_WIDTH },
8168  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
8169  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_23_WIDTH },
8170  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
8171  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_24_WIDTH },
8172  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
8173  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_25_WIDTH },
8174  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
8175  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_26_WIDTH },
8176  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
8177  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_27_WIDTH },
8178  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
8179  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_28_WIDTH },
8180  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
8181  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_29_WIDTH },
8182  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
8183  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_30_WIDTH },
8184  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
8185  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_31_WIDTH },
8186  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
8187  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_32_WIDTH },
8188 };
8189 
8195 static const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_groupEntries[SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_MAX_NUM_CHECKERS] =
8196 {
8197  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
8198  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_0_WIDTH },
8199  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
8200  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_1_WIDTH },
8201  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
8202  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_2_WIDTH },
8203  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
8204  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_3_WIDTH },
8205  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
8206  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_4_WIDTH },
8207  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
8208  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_5_WIDTH },
8209  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
8210  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_6_WIDTH },
8211  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
8212  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_7_WIDTH },
8213  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
8214  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_8_WIDTH },
8215  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
8216  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_9_WIDTH },
8217  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
8218  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_10_WIDTH },
8219  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
8220  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_11_WIDTH },
8221  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
8222  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_12_WIDTH },
8223  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
8224  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_13_WIDTH },
8225  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
8226  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_14_WIDTH },
8227  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
8228  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_15_WIDTH },
8229  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
8230  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_16_WIDTH },
8231  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
8232  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_17_WIDTH },
8233  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
8234  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_18_WIDTH },
8235  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
8236  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_19_WIDTH },
8237  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
8238  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_20_WIDTH },
8239  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
8240  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_21_WIDTH },
8241  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
8242  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_22_WIDTH },
8243  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
8244  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_23_WIDTH },
8245  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
8246  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_24_WIDTH },
8247  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
8248  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_25_WIDTH },
8249  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
8250  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_26_WIDTH },
8251  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
8252  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_27_WIDTH },
8253  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
8254  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_28_WIDTH },
8255  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
8256  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_29_WIDTH },
8257  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
8258  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_30_WIDTH },
8259  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
8260  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_31_WIDTH },
8261  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
8262  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_32_WIDTH },
8263 };
8264 
8270 static const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_groupEntries[SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_MAX_NUM_CHECKERS] =
8271 {
8272  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
8273  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_0_WIDTH },
8274  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
8275  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_1_WIDTH },
8276  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
8277  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_2_WIDTH },
8278  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
8279  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_3_WIDTH },
8280  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
8281  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_4_WIDTH },
8282  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
8283  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_5_WIDTH },
8284  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
8285  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_6_WIDTH },
8286  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
8287  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_7_WIDTH },
8288  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
8289  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_8_WIDTH },
8290  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
8291  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_9_WIDTH },
8292  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
8293  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_10_WIDTH },
8294  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
8295  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_11_WIDTH },
8296  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
8297  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_12_WIDTH },
8298  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
8299  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_13_WIDTH },
8300  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
8301  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_14_WIDTH },
8302  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
8303  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_15_WIDTH },
8304  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
8305  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_16_WIDTH },
8306  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
8307  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_17_WIDTH },
8308  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
8309  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_18_WIDTH },
8310  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
8311  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_19_WIDTH },
8312  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
8313  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_20_WIDTH },
8314  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
8315  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_21_WIDTH },
8316  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
8317  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_22_WIDTH },
8318  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
8319  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_23_WIDTH },
8320  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
8321  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_24_WIDTH },
8322  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
8323  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_25_WIDTH },
8324  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
8325  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_26_WIDTH },
8326  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
8327  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_27_WIDTH },
8328  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
8329  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_28_WIDTH },
8330  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
8331  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_29_WIDTH },
8332 };
8333 
8339 static const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_groupEntries[SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_MAX_NUM_CHECKERS] =
8340 {
8341  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
8342  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_0_WIDTH },
8343  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
8344  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_1_WIDTH },
8345  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
8346  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_2_WIDTH },
8347  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
8348  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_3_WIDTH },
8349  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
8350  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_4_WIDTH },
8351  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
8352  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_5_WIDTH },
8353  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
8354  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_6_WIDTH },
8355  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
8356  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_7_WIDTH },
8357  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
8358  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_8_WIDTH },
8359  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
8360  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_9_WIDTH },
8361  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
8362  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_10_WIDTH },
8363  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
8364  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_11_WIDTH },
8365  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
8366  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_12_WIDTH },
8367  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
8368  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_13_WIDTH },
8369  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
8370  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_14_WIDTH },
8371  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
8372  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_15_WIDTH },
8373  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
8374  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_16_WIDTH },
8375  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
8376  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_17_WIDTH },
8377  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
8378  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_18_WIDTH },
8379  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
8380  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_19_WIDTH },
8381  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
8382  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_20_WIDTH },
8383  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
8384  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_21_WIDTH },
8385  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
8386  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_22_WIDTH },
8387  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
8388  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_23_WIDTH },
8389  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
8390  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_24_WIDTH },
8391  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
8392  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_25_WIDTH },
8393  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
8394  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_26_WIDTH },
8395  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
8396  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_27_WIDTH },
8397  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
8398  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_28_WIDTH },
8399  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
8400  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_29_WIDTH },
8401 };
8402 
8408 static const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_groupEntries[SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_MAX_NUM_CHECKERS] =
8409 {
8410  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
8411  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_0_WIDTH },
8412  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
8413  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_1_WIDTH },
8414  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
8415  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_2_WIDTH },
8416  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
8417  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_3_WIDTH },
8418  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
8419  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_4_WIDTH },
8420  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
8421  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_5_WIDTH },
8422  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
8423  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_6_WIDTH },
8424  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
8425  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_7_WIDTH },
8426  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
8427  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_8_WIDTH },
8428  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
8429  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_9_WIDTH },
8430  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
8431  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_10_WIDTH },
8432  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
8433  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_11_WIDTH },
8434  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
8435  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_12_WIDTH },
8436  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
8437  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_13_WIDTH },
8438  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
8439  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_14_WIDTH },
8440  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
8441  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_15_WIDTH },
8442  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
8443  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_16_WIDTH },
8444  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
8445  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_17_WIDTH },
8446  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
8447  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_18_WIDTH },
8448  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
8449  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_19_WIDTH },
8450  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
8451  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_20_WIDTH },
8452  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
8453  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_21_WIDTH },
8454  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
8455  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_22_WIDTH },
8456  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
8457  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_23_WIDTH },
8458  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
8459  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_24_WIDTH },
8460  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
8461  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_25_WIDTH },
8462  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
8463  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_26_WIDTH },
8464  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
8465  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_27_WIDTH },
8466  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
8467  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_28_WIDTH },
8468  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
8469  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_29_WIDTH },
8470  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
8471  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_30_WIDTH },
8472  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
8473  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_31_WIDTH },
8474  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
8475  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_32_WIDTH },
8476  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_33_CHECKER_TYPE,
8477  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_33_WIDTH },
8478  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_34_CHECKER_TYPE,
8479  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_34_WIDTH },
8480  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_35_CHECKER_TYPE,
8481  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_35_WIDTH },
8482  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_36_CHECKER_TYPE,
8483  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_36_WIDTH },
8484  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_37_CHECKER_TYPE,
8485  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_37_WIDTH },
8486  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_38_CHECKER_TYPE,
8487  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_38_WIDTH },
8488  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_39_CHECKER_TYPE,
8489  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_39_WIDTH },
8490  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_40_CHECKER_TYPE,
8491  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_40_WIDTH },
8492  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_41_CHECKER_TYPE,
8493  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_41_WIDTH },
8494  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_42_CHECKER_TYPE,
8495  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_42_WIDTH },
8496  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_43_CHECKER_TYPE,
8497  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_43_WIDTH },
8498  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_44_CHECKER_TYPE,
8499  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_44_WIDTH },
8500  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_45_CHECKER_TYPE,
8501  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_45_WIDTH },
8502  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_46_CHECKER_TYPE,
8503  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_46_WIDTH },
8504  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_47_CHECKER_TYPE,
8505  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_47_WIDTH },
8506  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_48_CHECKER_TYPE,
8507  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_48_WIDTH },
8508  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_49_CHECKER_TYPE,
8509  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_49_WIDTH },
8510  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_50_CHECKER_TYPE,
8511  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_50_WIDTH },
8512  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_51_CHECKER_TYPE,
8513  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_51_WIDTH },
8514  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_52_CHECKER_TYPE,
8515  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_52_WIDTH },
8516  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_53_CHECKER_TYPE,
8517  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_53_WIDTH },
8518  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_54_CHECKER_TYPE,
8519  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_54_WIDTH },
8520  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_55_CHECKER_TYPE,
8521  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_55_WIDTH },
8522  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_56_CHECKER_TYPE,
8523  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_56_WIDTH },
8524  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_57_CHECKER_TYPE,
8525  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_57_WIDTH },
8526  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_58_CHECKER_TYPE,
8527  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_58_WIDTH },
8528  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_59_CHECKER_TYPE,
8529  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_59_WIDTH },
8530  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_60_CHECKER_TYPE,
8531  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_60_WIDTH },
8532  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_61_CHECKER_TYPE,
8533  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_61_WIDTH },
8534  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_62_CHECKER_TYPE,
8535  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_62_WIDTH },
8536  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_63_CHECKER_TYPE,
8537  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_63_WIDTH },
8538  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_64_CHECKER_TYPE,
8539  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_64_WIDTH },
8540  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_65_CHECKER_TYPE,
8541  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_65_WIDTH },
8542  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_66_CHECKER_TYPE,
8543  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_66_WIDTH },
8544  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_67_CHECKER_TYPE,
8545  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_67_WIDTH },
8546  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_68_CHECKER_TYPE,
8547  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_68_WIDTH },
8548  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_69_CHECKER_TYPE,
8549  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_69_WIDTH },
8550  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_70_CHECKER_TYPE,
8551  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_70_WIDTH },
8552  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_71_CHECKER_TYPE,
8553  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_71_WIDTH },
8554  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_72_CHECKER_TYPE,
8555  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_72_WIDTH },
8556  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_73_CHECKER_TYPE,
8557  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_73_WIDTH },
8558  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_74_CHECKER_TYPE,
8559  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_74_WIDTH },
8560  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_75_CHECKER_TYPE,
8561  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_75_WIDTH },
8562  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_76_CHECKER_TYPE,
8563  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_76_WIDTH },
8564  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_77_CHECKER_TYPE,
8565  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_77_WIDTH },
8566  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_78_CHECKER_TYPE,
8567  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_78_WIDTH },
8568  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_79_CHECKER_TYPE,
8569  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_79_WIDTH },
8570  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_80_CHECKER_TYPE,
8571  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_80_WIDTH },
8572  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_81_CHECKER_TYPE,
8573  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_81_WIDTH },
8574  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_82_CHECKER_TYPE,
8575  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_82_WIDTH },
8576  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_83_CHECKER_TYPE,
8577  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_83_WIDTH },
8578  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_84_CHECKER_TYPE,
8579  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_84_WIDTH },
8580  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_85_CHECKER_TYPE,
8581  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_85_WIDTH },
8582  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_86_CHECKER_TYPE,
8583  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_86_WIDTH },
8584  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_87_CHECKER_TYPE,
8585  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_87_WIDTH },
8586  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_88_CHECKER_TYPE,
8587  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_88_WIDTH },
8588  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_89_CHECKER_TYPE,
8589  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_89_WIDTH },
8590  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_90_CHECKER_TYPE,
8591  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_90_WIDTH },
8592  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_91_CHECKER_TYPE,
8593  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_91_WIDTH },
8594  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_92_CHECKER_TYPE,
8595  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_92_WIDTH },
8596  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_93_CHECKER_TYPE,
8597  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_93_WIDTH },
8598  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_94_CHECKER_TYPE,
8599  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_94_WIDTH },
8600  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_95_CHECKER_TYPE,
8601  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_95_WIDTH },
8602  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_96_CHECKER_TYPE,
8603  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_96_WIDTH },
8604  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_97_CHECKER_TYPE,
8605  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_97_WIDTH },
8606  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_98_CHECKER_TYPE,
8607  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_98_WIDTH },
8608  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_99_CHECKER_TYPE,
8609  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_99_WIDTH },
8610  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_100_CHECKER_TYPE,
8611  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_100_WIDTH },
8612 };
8613 
8619 static const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_groupEntries[SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_MAX_NUM_CHECKERS] =
8620 {
8621  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
8622  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_0_WIDTH },
8623  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
8624  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_1_WIDTH },
8625  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
8626  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_2_WIDTH },
8627  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
8628  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_3_WIDTH },
8629  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
8630  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_4_WIDTH },
8631  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
8632  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_5_WIDTH },
8633  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
8634  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_6_WIDTH },
8635  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
8636  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_7_WIDTH },
8637  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
8638  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_8_WIDTH },
8639  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
8640  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_9_WIDTH },
8641  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
8642  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_10_WIDTH },
8643  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
8644  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_11_WIDTH },
8645  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
8646  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_12_WIDTH },
8647  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
8648  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_13_WIDTH },
8649  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
8650  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_14_WIDTH },
8651  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
8652  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_15_WIDTH },
8653  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
8654  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_16_WIDTH },
8655  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
8656  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_17_WIDTH },
8657  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
8658  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_18_WIDTH },
8659  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
8660  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_19_WIDTH },
8661  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
8662  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_20_WIDTH },
8663  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
8664  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_21_WIDTH },
8665  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
8666  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_22_WIDTH },
8667  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
8668  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_23_WIDTH },
8669  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
8670  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_24_WIDTH },
8671  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
8672  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_25_WIDTH },
8673  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
8674  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_26_WIDTH },
8675  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
8676  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_27_WIDTH },
8677  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
8678  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_28_WIDTH },
8679  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
8680  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_29_WIDTH },
8681  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
8682  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_30_WIDTH },
8683  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
8684  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_31_WIDTH },
8685  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
8686  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_32_WIDTH },
8687  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_33_CHECKER_TYPE,
8688  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_33_WIDTH },
8689  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_34_CHECKER_TYPE,
8690  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_34_WIDTH },
8691  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_35_CHECKER_TYPE,
8692  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_35_WIDTH },
8693  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_36_CHECKER_TYPE,
8694  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_36_WIDTH },
8695  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_37_CHECKER_TYPE,
8696  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_37_WIDTH },
8697  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_38_CHECKER_TYPE,
8698  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_38_WIDTH },
8699  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_39_CHECKER_TYPE,
8700  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_39_WIDTH },
8701  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_40_CHECKER_TYPE,
8702  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_40_WIDTH },
8703  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_41_CHECKER_TYPE,
8704  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_41_WIDTH },
8705  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_42_CHECKER_TYPE,
8706  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_42_WIDTH },
8707  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_43_CHECKER_TYPE,
8708  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_43_WIDTH },
8709  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_44_CHECKER_TYPE,
8710  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_44_WIDTH },
8711  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_45_CHECKER_TYPE,
8712  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_45_WIDTH },
8713  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_46_CHECKER_TYPE,
8714  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_46_WIDTH },
8715  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_47_CHECKER_TYPE,
8716  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_47_WIDTH },
8717  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_48_CHECKER_TYPE,
8718  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_48_WIDTH },
8719  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_49_CHECKER_TYPE,
8720  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_49_WIDTH },
8721  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_50_CHECKER_TYPE,
8722  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_50_WIDTH },
8723  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_51_CHECKER_TYPE,
8724  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_51_WIDTH },
8725  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_52_CHECKER_TYPE,
8726  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_52_WIDTH },
8727  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_53_CHECKER_TYPE,
8728  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_53_WIDTH },
8729  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_54_CHECKER_TYPE,
8730  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_54_WIDTH },
8731  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_55_CHECKER_TYPE,
8732  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_55_WIDTH },
8733  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_56_CHECKER_TYPE,
8734  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_56_WIDTH },
8735  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_57_CHECKER_TYPE,
8736  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_57_WIDTH },
8737  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_58_CHECKER_TYPE,
8738  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_58_WIDTH },
8739  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_59_CHECKER_TYPE,
8740  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_59_WIDTH },
8741  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_60_CHECKER_TYPE,
8742  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_60_WIDTH },
8743  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_61_CHECKER_TYPE,
8744  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_61_WIDTH },
8745  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_62_CHECKER_TYPE,
8746  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_62_WIDTH },
8747  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_63_CHECKER_TYPE,
8748  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_63_WIDTH },
8749  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_64_CHECKER_TYPE,
8750  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_64_WIDTH },
8751  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_65_CHECKER_TYPE,
8752  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_65_WIDTH },
8753  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_66_CHECKER_TYPE,
8754  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_66_WIDTH },
8755  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_67_CHECKER_TYPE,
8756  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_67_WIDTH },
8757  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_68_CHECKER_TYPE,
8758  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_68_WIDTH },
8759  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_69_CHECKER_TYPE,
8760  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_69_WIDTH },
8761  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_70_CHECKER_TYPE,
8762  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_70_WIDTH },
8763  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_71_CHECKER_TYPE,
8764  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_71_WIDTH },
8765  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_72_CHECKER_TYPE,
8766  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_72_WIDTH },
8767  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_73_CHECKER_TYPE,
8768  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_73_WIDTH },
8769  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_74_CHECKER_TYPE,
8770  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_74_WIDTH },
8771  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_75_CHECKER_TYPE,
8772  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_75_WIDTH },
8773  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_76_CHECKER_TYPE,
8774  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_76_WIDTH },
8775  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_77_CHECKER_TYPE,
8776  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_77_WIDTH },
8777  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_78_CHECKER_TYPE,
8778  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_78_WIDTH },
8779  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_79_CHECKER_TYPE,
8780  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_79_WIDTH },
8781  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_80_CHECKER_TYPE,
8782  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_80_WIDTH },
8783  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_81_CHECKER_TYPE,
8784  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_81_WIDTH },
8785  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_82_CHECKER_TYPE,
8786  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_82_WIDTH },
8787  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_83_CHECKER_TYPE,
8788  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_83_WIDTH },
8789  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_84_CHECKER_TYPE,
8790  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_84_WIDTH },
8791  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_85_CHECKER_TYPE,
8792  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_85_WIDTH },
8793  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_86_CHECKER_TYPE,
8794  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_86_WIDTH },
8795  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_87_CHECKER_TYPE,
8796  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_87_WIDTH },
8797  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_88_CHECKER_TYPE,
8798  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_88_WIDTH },
8799  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_89_CHECKER_TYPE,
8800  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_89_WIDTH },
8801  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_90_CHECKER_TYPE,
8802  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_90_WIDTH },
8803  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_91_CHECKER_TYPE,
8804  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_91_WIDTH },
8805  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_92_CHECKER_TYPE,
8806  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_92_WIDTH },
8807  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_93_CHECKER_TYPE,
8808  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_93_WIDTH },
8809  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_94_CHECKER_TYPE,
8810  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_94_WIDTH },
8811  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_95_CHECKER_TYPE,
8812  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_95_WIDTH },
8813  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_96_CHECKER_TYPE,
8814  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_96_WIDTH },
8815  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_97_CHECKER_TYPE,
8816  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_97_WIDTH },
8817  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_98_CHECKER_TYPE,
8818  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_98_WIDTH },
8819  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_99_CHECKER_TYPE,
8820  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_99_WIDTH },
8821  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_100_CHECKER_TYPE,
8822  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_100_WIDTH },
8823 };
8824 
8830 static const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_groupEntries[SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_MAX_NUM_CHECKERS] =
8831 {
8832  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
8833  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_0_WIDTH },
8834  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
8835  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_1_WIDTH },
8836  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
8837  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_2_WIDTH },
8838  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
8839  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_3_WIDTH },
8840  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
8841  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_4_WIDTH },
8842  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
8843  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_5_WIDTH },
8844  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
8845  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_6_WIDTH },
8846  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
8847  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_7_WIDTH },
8848  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
8849  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_8_WIDTH },
8850  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
8851  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_9_WIDTH },
8852  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
8853  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_10_WIDTH },
8854  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
8855  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_11_WIDTH },
8856  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
8857  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_12_WIDTH },
8858  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
8859  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_13_WIDTH },
8860  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
8861  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_14_WIDTH },
8862  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
8863  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_15_WIDTH },
8864  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
8865  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_16_WIDTH },
8866  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
8867  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_17_WIDTH },
8868  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
8869  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_18_WIDTH },
8870  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
8871  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_19_WIDTH },
8872  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
8873  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_20_WIDTH },
8874  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
8875  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_21_WIDTH },
8876  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
8877  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_22_WIDTH },
8878  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
8879  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_23_WIDTH },
8880  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
8881  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_24_WIDTH },
8882  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
8883  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_25_WIDTH },
8884  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
8885  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_26_WIDTH },
8886  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
8887  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_27_WIDTH },
8888  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
8889  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_28_WIDTH },
8890  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
8891  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_29_WIDTH },
8892  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
8893  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_30_WIDTH },
8894  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
8895  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_31_WIDTH },
8896  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
8897  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_32_WIDTH },
8898  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_33_CHECKER_TYPE,
8899  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_33_WIDTH },
8900  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_34_CHECKER_TYPE,
8901  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_34_WIDTH },
8902 };
8903 
8909 static const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_groupEntries[SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_MAX_NUM_CHECKERS] =
8910 {
8911  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
8912  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_0_WIDTH },
8913  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
8914  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_1_WIDTH },
8915  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
8916  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_2_WIDTH },
8917  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
8918  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_3_WIDTH },
8919  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
8920  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_4_WIDTH },
8921  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
8922  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_5_WIDTH },
8923  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
8924  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_6_WIDTH },
8925  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
8926  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_7_WIDTH },
8927  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
8928  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_8_WIDTH },
8929  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
8930  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_9_WIDTH },
8931  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
8932  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_10_WIDTH },
8933  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
8934  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_11_WIDTH },
8935  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
8936  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_12_WIDTH },
8937  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
8938  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_13_WIDTH },
8939  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
8940  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_14_WIDTH },
8941  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
8942  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_15_WIDTH },
8943  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
8944  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_16_WIDTH },
8945  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
8946  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_17_WIDTH },
8947  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
8948  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_18_WIDTH },
8949  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
8950  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_19_WIDTH },
8951  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
8952  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_20_WIDTH },
8953  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
8954  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_21_WIDTH },
8955  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
8956  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_22_WIDTH },
8957  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
8958  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_23_WIDTH },
8959  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
8960  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_24_WIDTH },
8961  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
8962  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_25_WIDTH },
8963  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
8964  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_26_WIDTH },
8965  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
8966  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_27_WIDTH },
8967  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
8968  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_28_WIDTH },
8969  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
8970  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_29_WIDTH },
8971  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
8972  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_30_WIDTH },
8973  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
8974  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_31_WIDTH },
8975  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
8976  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_32_WIDTH },
8977  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_33_CHECKER_TYPE,
8978  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_33_WIDTH },
8979  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_34_CHECKER_TYPE,
8980  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_34_WIDTH },
8981 };
8982 
8988 static const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_groupEntries[SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_MAX_NUM_CHECKERS] =
8989 {
8990  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
8991  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_0_WIDTH },
8992  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
8993  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_1_WIDTH },
8994  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
8995  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_2_WIDTH },
8996  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
8997  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_3_WIDTH },
8998  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
8999  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_4_WIDTH },
9000  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
9001  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_5_WIDTH },
9002  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
9003  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_6_WIDTH },
9004  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
9005  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_7_WIDTH },
9006  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
9007  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_8_WIDTH },
9008  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
9009  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_9_WIDTH },
9010  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
9011  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_10_WIDTH },
9012  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
9013  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_11_WIDTH },
9014  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
9015  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_12_WIDTH },
9016  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
9017  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_13_WIDTH },
9018  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
9019  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_14_WIDTH },
9020  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
9021  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_15_WIDTH },
9022  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
9023  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_16_WIDTH },
9024  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
9025  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_17_WIDTH },
9026  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
9027  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_18_WIDTH },
9028  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
9029  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_19_WIDTH },
9030  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
9031  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_20_WIDTH },
9032  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
9033  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_21_WIDTH },
9034  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
9035  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_22_WIDTH },
9036  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
9037  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_23_WIDTH },
9038  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
9039  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_24_WIDTH },
9040  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
9041  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_25_WIDTH },
9042  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
9043  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_26_WIDTH },
9044  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
9045  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_27_WIDTH },
9046  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
9047  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_28_WIDTH },
9048  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
9049  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_29_WIDTH },
9050  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
9051  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_30_WIDTH },
9052  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
9053  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_31_WIDTH },
9054  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
9055  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_32_WIDTH },
9056  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_33_CHECKER_TYPE,
9057  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_33_WIDTH },
9058  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_34_CHECKER_TYPE,
9059  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_34_WIDTH },
9060 };
9061 
9067 static const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_INTAGGR_EVT_EDC_CTRL_0_groupEntries[SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_INTAGGR_EVT_EDC_CTRL_0_MAX_NUM_CHECKERS] =
9068 {
9069  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_INTAGGR_EVT_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
9070  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_INTAGGR_EVT_EDC_CTRL_0_GROUP_0_WIDTH },
9071  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_INTAGGR_EVT_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
9072  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_INTAGGR_EVT_EDC_CTRL_0_GROUP_1_WIDTH },
9073 };
9074 
9080 static const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_INTAGGR_CEVT_EDC_CTRL_0_groupEntries[SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_INTAGGR_CEVT_EDC_CTRL_0_MAX_NUM_CHECKERS] =
9081 {
9082  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_INTAGGR_CEVT_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
9083  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_INTAGGR_CEVT_EDC_CTRL_0_GROUP_0_WIDTH },
9084  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_INTAGGR_CEVT_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
9085  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_INTAGGR_CEVT_EDC_CTRL_0_GROUP_1_WIDTH },
9086 };
9087 
9093 static const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_INTAGGR_MEVT_IN_EDC_CTRL_0_groupEntries[SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_INTAGGR_MEVT_IN_EDC_CTRL_0_MAX_NUM_CHECKERS] =
9094 {
9095  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_INTAGGR_MEVT_IN_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
9096  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_INTAGGR_MEVT_IN_EDC_CTRL_0_GROUP_0_WIDTH },
9097  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_INTAGGR_MEVT_IN_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
9098  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_INTAGGR_MEVT_IN_EDC_CTRL_0_GROUP_1_WIDTH },
9099 };
9100 
9106 static const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_groupEntries[SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_MAX_NUM_CHECKERS] =
9107 {
9108  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
9109  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_0_WIDTH },
9110  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
9111  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_1_WIDTH },
9112  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
9113  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_2_WIDTH },
9114  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
9115  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_3_WIDTH },
9116  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
9117  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_4_WIDTH },
9118  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
9119  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_5_WIDTH },
9120  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
9121  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_6_WIDTH },
9122  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
9123  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_7_WIDTH },
9124  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
9125  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_8_WIDTH },
9126  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
9127  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_9_WIDTH },
9128  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
9129  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_10_WIDTH },
9130  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
9131  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_11_WIDTH },
9132  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
9133  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_12_WIDTH },
9134  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
9135  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_13_WIDTH },
9136  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
9137  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_14_WIDTH },
9138  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
9139  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_15_WIDTH },
9140  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
9141  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_16_WIDTH },
9142  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
9143  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_17_WIDTH },
9144  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
9145  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_18_WIDTH },
9146  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
9147  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_19_WIDTH },
9148  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
9149  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_20_WIDTH },
9150  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
9151  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_21_WIDTH },
9152  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
9153  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_22_WIDTH },
9154  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
9155  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_23_WIDTH },
9156  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
9157  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_24_WIDTH },
9158  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
9159  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_25_WIDTH },
9160  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
9161  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_26_WIDTH },
9162  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
9163  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_27_WIDTH },
9164  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
9165  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_28_WIDTH },
9166  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
9167  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_29_WIDTH },
9168  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
9169  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_30_WIDTH },
9170  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
9171  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_31_WIDTH },
9172  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
9173  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_32_WIDTH },
9174  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_33_CHECKER_TYPE,
9175  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_33_WIDTH },
9176  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_34_CHECKER_TYPE,
9177  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_34_WIDTH },
9178 };
9179 
9185 static const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CFG_EDC_CTRL_0_groupEntries[SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CFG_EDC_CTRL_0_MAX_NUM_CHECKERS] =
9186 {
9187  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CFG_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
9188  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CFG_EDC_CTRL_0_GROUP_0_WIDTH },
9189  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CFG_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
9190  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CFG_EDC_CTRL_0_GROUP_1_WIDTH },
9191  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CFG_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
9192  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CFG_EDC_CTRL_0_GROUP_2_WIDTH },
9193 };
9194 
9200 static const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_groupEntries[SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_MAX_NUM_CHECKERS] =
9201 {
9202  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
9203  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_0_WIDTH },
9204  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
9205  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_1_WIDTH },
9206  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
9207  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_2_WIDTH },
9208  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
9209  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_3_WIDTH },
9210  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
9211  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_4_WIDTH },
9212  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
9213  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_5_WIDTH },
9214  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
9215  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_6_WIDTH },
9216  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
9217  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_7_WIDTH },
9218  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
9219  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_8_WIDTH },
9220  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
9221  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_9_WIDTH },
9222  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
9223  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_10_WIDTH },
9224  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
9225  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_11_WIDTH },
9226  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
9227  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_12_WIDTH },
9228  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
9229  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_13_WIDTH },
9230  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
9231  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_14_WIDTH },
9232  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
9233  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_15_WIDTH },
9234  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
9235  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_16_WIDTH },
9236  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
9237  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_17_WIDTH },
9238  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
9239  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_18_WIDTH },
9240  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
9241  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_19_WIDTH },
9242  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
9243  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_20_WIDTH },
9244  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
9245  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_21_WIDTH },
9246  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
9247  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_22_WIDTH },
9248  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
9249  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_23_WIDTH },
9250  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
9251  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_24_WIDTH },
9252  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
9253  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_25_WIDTH },
9254  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
9255  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_26_WIDTH },
9256  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
9257  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_27_WIDTH },
9258  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
9259  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_28_WIDTH },
9260  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
9261  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_29_WIDTH },
9262  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
9263  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_30_WIDTH },
9264  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
9265  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_31_WIDTH },
9266  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
9267  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_32_WIDTH },
9268  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_33_CHECKER_TYPE,
9269  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_33_WIDTH },
9270  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_34_CHECKER_TYPE,
9271  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_34_WIDTH },
9272  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_35_CHECKER_TYPE,
9273  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_35_WIDTH },
9274  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_36_CHECKER_TYPE,
9275  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_36_WIDTH },
9276  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_37_CHECKER_TYPE,
9277  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_37_WIDTH },
9278  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_38_CHECKER_TYPE,
9279  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_38_WIDTH },
9280  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_39_CHECKER_TYPE,
9281  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_39_WIDTH },
9282  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_40_CHECKER_TYPE,
9283  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_40_WIDTH },
9284  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_41_CHECKER_TYPE,
9285  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_41_WIDTH },
9286  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_42_CHECKER_TYPE,
9287  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_42_WIDTH },
9288  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_43_CHECKER_TYPE,
9289  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_43_WIDTH },
9290  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_44_CHECKER_TYPE,
9291  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_44_WIDTH },
9292  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_45_CHECKER_TYPE,
9293  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_45_WIDTH },
9294  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_46_CHECKER_TYPE,
9295  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_46_WIDTH },
9296  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_47_CHECKER_TYPE,
9297  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_47_WIDTH },
9298  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_48_CHECKER_TYPE,
9299  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_48_WIDTH },
9300  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_49_CHECKER_TYPE,
9301  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_49_WIDTH },
9302  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_50_CHECKER_TYPE,
9303  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_50_WIDTH },
9304  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_51_CHECKER_TYPE,
9305  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_51_WIDTH },
9306  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_52_CHECKER_TYPE,
9307  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_52_WIDTH },
9308  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_53_CHECKER_TYPE,
9309  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_53_WIDTH },
9310  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_54_CHECKER_TYPE,
9311  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_54_WIDTH },
9312  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_55_CHECKER_TYPE,
9313  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_55_WIDTH },
9314  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_56_CHECKER_TYPE,
9315  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_56_WIDTH },
9316  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_57_CHECKER_TYPE,
9317  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_57_WIDTH },
9318  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_58_CHECKER_TYPE,
9319  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_58_WIDTH },
9320  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_59_CHECKER_TYPE,
9321  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_59_WIDTH },
9322  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_60_CHECKER_TYPE,
9323  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_60_WIDTH },
9324  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_61_CHECKER_TYPE,
9325  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_61_WIDTH },
9326  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_62_CHECKER_TYPE,
9327  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_62_WIDTH },
9328  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_63_CHECKER_TYPE,
9329  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_63_WIDTH },
9330  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_64_CHECKER_TYPE,
9331  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_64_WIDTH },
9332  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_65_CHECKER_TYPE,
9333  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_65_WIDTH },
9334  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_66_CHECKER_TYPE,
9335  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_66_WIDTH },
9336  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_67_CHECKER_TYPE,
9337  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_67_WIDTH },
9338  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_68_CHECKER_TYPE,
9339  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_68_WIDTH },
9340  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_69_CHECKER_TYPE,
9341  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_69_WIDTH },
9342  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_70_CHECKER_TYPE,
9343  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_70_WIDTH },
9344  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_71_CHECKER_TYPE,
9345  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_71_WIDTH },
9346  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_72_CHECKER_TYPE,
9347  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_72_WIDTH },
9348  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_73_CHECKER_TYPE,
9349  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_73_WIDTH },
9350  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_74_CHECKER_TYPE,
9351  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_74_WIDTH },
9352  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_75_CHECKER_TYPE,
9353  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_75_WIDTH },
9354  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_76_CHECKER_TYPE,
9355  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_76_WIDTH },
9356  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_77_CHECKER_TYPE,
9357  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_77_WIDTH },
9358  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_78_CHECKER_TYPE,
9359  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_78_WIDTH },
9360  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_79_CHECKER_TYPE,
9361  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_79_WIDTH },
9362  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_80_CHECKER_TYPE,
9363  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_80_WIDTH },
9364  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_81_CHECKER_TYPE,
9365  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_81_WIDTH },
9366  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_82_CHECKER_TYPE,
9367  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_82_WIDTH },
9368  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_83_CHECKER_TYPE,
9369  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_83_WIDTH },
9370  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_84_CHECKER_TYPE,
9371  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_84_WIDTH },
9372  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_85_CHECKER_TYPE,
9373  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_85_WIDTH },
9374  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_86_CHECKER_TYPE,
9375  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_86_WIDTH },
9376  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_87_CHECKER_TYPE,
9377  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_87_WIDTH },
9378  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_88_CHECKER_TYPE,
9379  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_88_WIDTH },
9380  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_89_CHECKER_TYPE,
9381  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_89_WIDTH },
9382  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_90_CHECKER_TYPE,
9383  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_90_WIDTH },
9384  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_91_CHECKER_TYPE,
9385  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_91_WIDTH },
9386  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_92_CHECKER_TYPE,
9387  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_92_WIDTH },
9388  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_93_CHECKER_TYPE,
9389  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_93_WIDTH },
9390  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_94_CHECKER_TYPE,
9391  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_94_WIDTH },
9392  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_95_CHECKER_TYPE,
9393  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_95_WIDTH },
9394  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_96_CHECKER_TYPE,
9395  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_96_WIDTH },
9396  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_97_CHECKER_TYPE,
9397  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_97_WIDTH },
9398  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_98_CHECKER_TYPE,
9399  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_98_WIDTH },
9400  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_99_CHECKER_TYPE,
9401  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_99_WIDTH },
9402  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_100_CHECKER_TYPE,
9403  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_100_WIDTH },
9404  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_101_CHECKER_TYPE,
9405  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_101_WIDTH },
9406  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_102_CHECKER_TYPE,
9407  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_102_WIDTH },
9408  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_103_CHECKER_TYPE,
9409  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_103_WIDTH },
9410  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_104_CHECKER_TYPE,
9411  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_104_WIDTH },
9412  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_105_CHECKER_TYPE,
9413  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_105_WIDTH },
9414 };
9415 
9421 static const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_groupEntries[SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_MAX_NUM_CHECKERS] =
9422 {
9423  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
9424  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_0_WIDTH },
9425  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
9426  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_1_WIDTH },
9427  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
9428  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_2_WIDTH },
9429  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
9430  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_3_WIDTH },
9431  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
9432  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_4_WIDTH },
9433  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
9434  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_5_WIDTH },
9435  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
9436  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_6_WIDTH },
9437  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
9438  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_7_WIDTH },
9439  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
9440  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_8_WIDTH },
9441  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
9442  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_9_WIDTH },
9443  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
9444  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_10_WIDTH },
9445  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
9446  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_11_WIDTH },
9447  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
9448  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_12_WIDTH },
9449  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
9450  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_13_WIDTH },
9451  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
9452  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_14_WIDTH },
9453  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
9454  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_15_WIDTH },
9455  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
9456  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_16_WIDTH },
9457  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
9458  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_17_WIDTH },
9459  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
9460  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_18_WIDTH },
9461  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
9462  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_19_WIDTH },
9463  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
9464  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_20_WIDTH },
9465  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
9466  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_21_WIDTH },
9467  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
9468  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_22_WIDTH },
9469  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
9470  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_23_WIDTH },
9471  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
9472  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_24_WIDTH },
9473  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
9474  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_25_WIDTH },
9475  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
9476  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_26_WIDTH },
9477  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
9478  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_27_WIDTH },
9479  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
9480  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_28_WIDTH },
9481  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
9482  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_29_WIDTH },
9483  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
9484  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_30_WIDTH },
9485  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
9486  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_31_WIDTH },
9487  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
9488  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_32_WIDTH },
9489  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_33_CHECKER_TYPE,
9490  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_33_WIDTH },
9491  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_34_CHECKER_TYPE,
9492  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_34_WIDTH },
9493  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_35_CHECKER_TYPE,
9494  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_35_WIDTH },
9495  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_36_CHECKER_TYPE,
9496  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_36_WIDTH },
9497  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_37_CHECKER_TYPE,
9498  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_37_WIDTH },
9499  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_38_CHECKER_TYPE,
9500  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_38_WIDTH },
9501  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_39_CHECKER_TYPE,
9502  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_39_WIDTH },
9503  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_40_CHECKER_TYPE,
9504  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_40_WIDTH },
9505  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_41_CHECKER_TYPE,
9506  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_41_WIDTH },
9507  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_42_CHECKER_TYPE,
9508  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_42_WIDTH },
9509  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_43_CHECKER_TYPE,
9510  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_43_WIDTH },
9511  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_44_CHECKER_TYPE,
9512  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_44_WIDTH },
9513  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_45_CHECKER_TYPE,
9514  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_45_WIDTH },
9515  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_46_CHECKER_TYPE,
9516  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_46_WIDTH },
9517  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_47_CHECKER_TYPE,
9518  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_47_WIDTH },
9519  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_48_CHECKER_TYPE,
9520  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_48_WIDTH },
9521  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_49_CHECKER_TYPE,
9522  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_49_WIDTH },
9523  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_50_CHECKER_TYPE,
9524  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_50_WIDTH },
9525  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_51_CHECKER_TYPE,
9526  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_51_WIDTH },
9527  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_52_CHECKER_TYPE,
9528  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_52_WIDTH },
9529  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_53_CHECKER_TYPE,
9530  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_53_WIDTH },
9531  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_54_CHECKER_TYPE,
9532  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_54_WIDTH },
9533  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_55_CHECKER_TYPE,
9534  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_55_WIDTH },
9535  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_56_CHECKER_TYPE,
9536  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_56_WIDTH },
9537  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_57_CHECKER_TYPE,
9538  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_57_WIDTH },
9539  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_58_CHECKER_TYPE,
9540  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_58_WIDTH },
9541  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_59_CHECKER_TYPE,
9542  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_59_WIDTH },
9543  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_60_CHECKER_TYPE,
9544  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_60_WIDTH },
9545  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_61_CHECKER_TYPE,
9546  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_61_WIDTH },
9547  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_62_CHECKER_TYPE,
9548  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_62_WIDTH },
9549  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_63_CHECKER_TYPE,
9550  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_63_WIDTH },
9551  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_64_CHECKER_TYPE,
9552  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_64_WIDTH },
9553  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_65_CHECKER_TYPE,
9554  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_65_WIDTH },
9555  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_66_CHECKER_TYPE,
9556  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_66_WIDTH },
9557  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_67_CHECKER_TYPE,
9558  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_67_WIDTH },
9559  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_68_CHECKER_TYPE,
9560  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_68_WIDTH },
9561  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_69_CHECKER_TYPE,
9562  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_69_WIDTH },
9563  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_70_CHECKER_TYPE,
9564  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_70_WIDTH },
9565  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_71_CHECKER_TYPE,
9566  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_71_WIDTH },
9567  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_72_CHECKER_TYPE,
9568  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_72_WIDTH },
9569  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_73_CHECKER_TYPE,
9570  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_73_WIDTH },
9571  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_74_CHECKER_TYPE,
9572  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_74_WIDTH },
9573  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_75_CHECKER_TYPE,
9574  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_75_WIDTH },
9575  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_76_CHECKER_TYPE,
9576  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_76_WIDTH },
9577  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_77_CHECKER_TYPE,
9578  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_77_WIDTH },
9579  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_78_CHECKER_TYPE,
9580  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_78_WIDTH },
9581  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_79_CHECKER_TYPE,
9582  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_79_WIDTH },
9583  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_80_CHECKER_TYPE,
9584  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_80_WIDTH },
9585  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_81_CHECKER_TYPE,
9586  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_81_WIDTH },
9587  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_82_CHECKER_TYPE,
9588  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_82_WIDTH },
9589  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_83_CHECKER_TYPE,
9590  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_83_WIDTH },
9591  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_84_CHECKER_TYPE,
9592  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_84_WIDTH },
9593  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_85_CHECKER_TYPE,
9594  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_85_WIDTH },
9595  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_86_CHECKER_TYPE,
9596  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_86_WIDTH },
9597  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_87_CHECKER_TYPE,
9598  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_87_WIDTH },
9599  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_88_CHECKER_TYPE,
9600  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_88_WIDTH },
9601  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_89_CHECKER_TYPE,
9602  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_89_WIDTH },
9603  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_90_CHECKER_TYPE,
9604  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_90_WIDTH },
9605  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_91_CHECKER_TYPE,
9606  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_91_WIDTH },
9607  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_92_CHECKER_TYPE,
9608  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_92_WIDTH },
9609  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_93_CHECKER_TYPE,
9610  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_93_WIDTH },
9611  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_94_CHECKER_TYPE,
9612  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_94_WIDTH },
9613  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_95_CHECKER_TYPE,
9614  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_95_WIDTH },
9615  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_96_CHECKER_TYPE,
9616  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_96_WIDTH },
9617  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_97_CHECKER_TYPE,
9618  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_97_WIDTH },
9619  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_98_CHECKER_TYPE,
9620  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_98_WIDTH },
9621  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_99_CHECKER_TYPE,
9622  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_99_WIDTH },
9623  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_100_CHECKER_TYPE,
9624  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_100_WIDTH },
9625  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_101_CHECKER_TYPE,
9626  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_101_WIDTH },
9627  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_102_CHECKER_TYPE,
9628  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_102_WIDTH },
9629 };
9630 
9636 static const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_groupEntries[SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_MAX_NUM_CHECKERS] =
9637 {
9638  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
9639  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_0_WIDTH },
9640  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
9641  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_1_WIDTH },
9642  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
9643  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_2_WIDTH },
9644  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
9645  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_3_WIDTH },
9646  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
9647  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_4_WIDTH },
9648  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
9649  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_5_WIDTH },
9650  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
9651  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_6_WIDTH },
9652  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
9653  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_7_WIDTH },
9654  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
9655  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_8_WIDTH },
9656  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
9657  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_9_WIDTH },
9658  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
9659  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_10_WIDTH },
9660  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
9661  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_11_WIDTH },
9662  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
9663  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_12_WIDTH },
9664  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
9665  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_13_WIDTH },
9666  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
9667  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_14_WIDTH },
9668  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
9669  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_15_WIDTH },
9670  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
9671  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_16_WIDTH },
9672  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
9673  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_17_WIDTH },
9674  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
9675  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_18_WIDTH },
9676  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
9677  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_19_WIDTH },
9678  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
9679  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_20_WIDTH },
9680  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
9681  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_21_WIDTH },
9682  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
9683  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_22_WIDTH },
9684  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
9685  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_23_WIDTH },
9686  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
9687  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_24_WIDTH },
9688  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
9689  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_25_WIDTH },
9690  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
9691  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_26_WIDTH },
9692  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
9693  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_27_WIDTH },
9694  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
9695  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_28_WIDTH },
9696  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
9697  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_29_WIDTH },
9698  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
9699  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_30_WIDTH },
9700  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
9701  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_31_WIDTH },
9702  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
9703  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_32_WIDTH },
9704  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_33_CHECKER_TYPE,
9705  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_33_WIDTH },
9706  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_34_CHECKER_TYPE,
9707  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_34_WIDTH },
9708  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_35_CHECKER_TYPE,
9709  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_35_WIDTH },
9710  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_36_CHECKER_TYPE,
9711  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_36_WIDTH },
9712  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_37_CHECKER_TYPE,
9713  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_37_WIDTH },
9714  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_38_CHECKER_TYPE,
9715  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_38_WIDTH },
9716  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_39_CHECKER_TYPE,
9717  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_39_WIDTH },
9718  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_40_CHECKER_TYPE,
9719  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_40_WIDTH },
9720  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_41_CHECKER_TYPE,
9721  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_41_WIDTH },
9722  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_42_CHECKER_TYPE,
9723  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_42_WIDTH },
9724  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_43_CHECKER_TYPE,
9725  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_43_WIDTH },
9726  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_44_CHECKER_TYPE,
9727  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_44_WIDTH },
9728  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_45_CHECKER_TYPE,
9729  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_45_WIDTH },
9730  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_46_CHECKER_TYPE,
9731  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_46_WIDTH },
9732  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_47_CHECKER_TYPE,
9733  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_47_WIDTH },
9734  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_48_CHECKER_TYPE,
9735  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_48_WIDTH },
9736  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_49_CHECKER_TYPE,
9737  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_49_WIDTH },
9738  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_50_CHECKER_TYPE,
9739  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_50_WIDTH },
9740  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_51_CHECKER_TYPE,
9741  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_51_WIDTH },
9742  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_52_CHECKER_TYPE,
9743  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_52_WIDTH },
9744  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_53_CHECKER_TYPE,
9745  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_53_WIDTH },
9746  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_54_CHECKER_TYPE,
9747  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_54_WIDTH },
9748  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_55_CHECKER_TYPE,
9749  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_55_WIDTH },
9750  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_56_CHECKER_TYPE,
9751  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_56_WIDTH },
9752  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_57_CHECKER_TYPE,
9753  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_57_WIDTH },
9754  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_58_CHECKER_TYPE,
9755  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_58_WIDTH },
9756  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_59_CHECKER_TYPE,
9757  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_59_WIDTH },
9758  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_60_CHECKER_TYPE,
9759  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_60_WIDTH },
9760  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_61_CHECKER_TYPE,
9761  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_61_WIDTH },
9762  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_62_CHECKER_TYPE,
9763  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_62_WIDTH },
9764  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_63_CHECKER_TYPE,
9765  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_63_WIDTH },
9766  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_64_CHECKER_TYPE,
9767  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_64_WIDTH },
9768  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_65_CHECKER_TYPE,
9769  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_65_WIDTH },
9770  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_66_CHECKER_TYPE,
9771  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_66_WIDTH },
9772  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_67_CHECKER_TYPE,
9773  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_67_WIDTH },
9774  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_68_CHECKER_TYPE,
9775  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_68_WIDTH },
9776  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_69_CHECKER_TYPE,
9777  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_69_WIDTH },
9778  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_70_CHECKER_TYPE,
9779  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_70_WIDTH },
9780  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_71_CHECKER_TYPE,
9781  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_71_WIDTH },
9782  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_72_CHECKER_TYPE,
9783  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_72_WIDTH },
9784  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_73_CHECKER_TYPE,
9785  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_73_WIDTH },
9786  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_74_CHECKER_TYPE,
9787  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_74_WIDTH },
9788  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_75_CHECKER_TYPE,
9789  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_75_WIDTH },
9790  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_76_CHECKER_TYPE,
9791  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_76_WIDTH },
9792  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_77_CHECKER_TYPE,
9793  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_77_WIDTH },
9794  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_78_CHECKER_TYPE,
9795  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_78_WIDTH },
9796  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_79_CHECKER_TYPE,
9797  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_79_WIDTH },
9798  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_80_CHECKER_TYPE,
9799  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_80_WIDTH },
9800  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_81_CHECKER_TYPE,
9801  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_81_WIDTH },
9802  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_82_CHECKER_TYPE,
9803  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_82_WIDTH },
9804  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_83_CHECKER_TYPE,
9805  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_83_WIDTH },
9806  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_84_CHECKER_TYPE,
9807  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_84_WIDTH },
9808  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_85_CHECKER_TYPE,
9809  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_85_WIDTH },
9810  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_86_CHECKER_TYPE,
9811  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_86_WIDTH },
9812  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_87_CHECKER_TYPE,
9813  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_87_WIDTH },
9814  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_88_CHECKER_TYPE,
9815  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_88_WIDTH },
9816  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_89_CHECKER_TYPE,
9817  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_89_WIDTH },
9818  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_90_CHECKER_TYPE,
9819  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_90_WIDTH },
9820  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_91_CHECKER_TYPE,
9821  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_91_WIDTH },
9822  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_92_CHECKER_TYPE,
9823  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_92_WIDTH },
9824  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_93_CHECKER_TYPE,
9825  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_93_WIDTH },
9826  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_94_CHECKER_TYPE,
9827  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_94_WIDTH },
9828  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_95_CHECKER_TYPE,
9829  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_95_WIDTH },
9830  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_96_CHECKER_TYPE,
9831  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_96_WIDTH },
9832  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_97_CHECKER_TYPE,
9833  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_97_WIDTH },
9834  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_98_CHECKER_TYPE,
9835  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_98_WIDTH },
9836  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_99_CHECKER_TYPE,
9837  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_99_WIDTH },
9838  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_100_CHECKER_TYPE,
9839  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_100_WIDTH },
9840  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_101_CHECKER_TYPE,
9841  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_101_WIDTH },
9842  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_102_CHECKER_TYPE,
9843  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_102_WIDTH },
9844  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_103_CHECKER_TYPE,
9845  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_103_WIDTH },
9846  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_104_CHECKER_TYPE,
9847  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_104_WIDTH },
9848  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_105_CHECKER_TYPE,
9849  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_105_WIDTH },
9850  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_106_CHECKER_TYPE,
9851  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_106_WIDTH },
9852  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_107_CHECKER_TYPE,
9853  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_107_WIDTH },
9854  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_108_CHECKER_TYPE,
9855  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_108_WIDTH },
9856  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_109_CHECKER_TYPE,
9857  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_109_WIDTH },
9858  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_110_CHECKER_TYPE,
9859  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_110_WIDTH },
9860  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_111_CHECKER_TYPE,
9861  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_111_WIDTH },
9862  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_112_CHECKER_TYPE,
9863  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_112_WIDTH },
9864  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_113_CHECKER_TYPE,
9865  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_113_WIDTH },
9866  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_114_CHECKER_TYPE,
9867  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_114_WIDTH },
9868  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_115_CHECKER_TYPE,
9869  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_115_WIDTH },
9870  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_116_CHECKER_TYPE,
9871  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_116_WIDTH },
9872  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_117_CHECKER_TYPE,
9873  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_117_WIDTH },
9874  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_118_CHECKER_TYPE,
9875  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_118_WIDTH },
9876  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_119_CHECKER_TYPE,
9877  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_119_WIDTH },
9878  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_120_CHECKER_TYPE,
9879  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_120_WIDTH },
9880  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_121_CHECKER_TYPE,
9881  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_121_WIDTH },
9882  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_122_CHECKER_TYPE,
9883  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_122_WIDTH },
9884  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_123_CHECKER_TYPE,
9885  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_123_WIDTH },
9886  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_124_CHECKER_TYPE,
9887  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_124_WIDTH },
9888  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_125_CHECKER_TYPE,
9889  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_125_WIDTH },
9890  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_126_CHECKER_TYPE,
9891  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_126_WIDTH },
9892  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_127_CHECKER_TYPE,
9893  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_127_WIDTH },
9894  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_128_CHECKER_TYPE,
9895  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_128_WIDTH },
9896  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_129_CHECKER_TYPE,
9897  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_129_WIDTH },
9898  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_130_CHECKER_TYPE,
9899  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_130_WIDTH },
9900 };
9901 
9907 static const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_VD2GCLK_EDC_CTRL_0_groupEntries[SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_VD2GCLK_EDC_CTRL_0_MAX_NUM_CHECKERS] =
9908 {
9909  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_VD2GCLK_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
9910  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_VD2GCLK_EDC_CTRL_0_GROUP_0_WIDTH },
9911  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_VD2GCLK_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
9912  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_VD2GCLK_EDC_CTRL_0_GROUP_1_WIDTH },
9913  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_VD2GCLK_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
9914  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_VD2GCLK_EDC_CTRL_0_GROUP_2_WIDTH },
9915  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_VD2GCLK_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
9916  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_VD2GCLK_EDC_CTRL_0_GROUP_3_WIDTH },
9917  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_VD2GCLK_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
9918  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_VD2GCLK_EDC_CTRL_0_GROUP_4_WIDTH },
9919  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_VD2GCLK_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
9920  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_VD2GCLK_EDC_CTRL_0_GROUP_5_WIDTH },
9921  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_VD2GCLK_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
9922  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_VD2GCLK_EDC_CTRL_0_GROUP_6_WIDTH },
9923  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_VD2GCLK_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
9924  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_VD2GCLK_EDC_CTRL_0_GROUP_7_WIDTH },
9925  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_VD2GCLK_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
9926  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_VD2GCLK_EDC_CTRL_0_GROUP_8_WIDTH },
9927  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_VD2GCLK_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
9928  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_VD2GCLK_EDC_CTRL_0_GROUP_9_WIDTH },
9929 };
9930 
9936 static const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_DMSS_CFG_P2P_BRIDGE_EDC_CTRL_0_groupEntries[SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_DMSS_CFG_P2P_BRIDGE_EDC_CTRL_0_MAX_NUM_CHECKERS] =
9937 {
9938  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_DMSS_CFG_P2P_BRIDGE_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
9939  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_DMSS_CFG_P2P_BRIDGE_EDC_CTRL_0_GROUP_0_WIDTH },
9940  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_DMSS_CFG_P2P_BRIDGE_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
9941  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_DMSS_CFG_P2P_BRIDGE_EDC_CTRL_0_GROUP_1_WIDTH },
9942  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_DMSS_CFG_P2P_BRIDGE_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
9943  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_DMSS_CFG_P2P_BRIDGE_EDC_CTRL_0_GROUP_2_WIDTH },
9944  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_DMSS_CFG_P2P_BRIDGE_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
9945  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_DMSS_CFG_P2P_BRIDGE_EDC_CTRL_0_GROUP_3_WIDTH },
9946  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_DMSS_CFG_P2P_BRIDGE_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
9947  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_DMSS_CFG_P2P_BRIDGE_EDC_CTRL_0_GROUP_4_WIDTH },
9948  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_DMSS_CFG_P2P_BRIDGE_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
9949  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_DMSS_CFG_P2P_BRIDGE_EDC_CTRL_0_GROUP_5_WIDTH },
9950  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_DMSS_CFG_P2P_BRIDGE_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
9951  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_DMSS_CFG_P2P_BRIDGE_EDC_CTRL_0_GROUP_6_WIDTH },
9952 };
9953 
9959 static const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_groupEntries[SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_MAX_NUM_CHECKERS] =
9960 {
9961  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
9962  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_0_WIDTH },
9963  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
9964  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_1_WIDTH },
9965  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
9966  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_2_WIDTH },
9967  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
9968  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_3_WIDTH },
9969  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
9970  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_4_WIDTH },
9971  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
9972  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_5_WIDTH },
9973  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
9974  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_6_WIDTH },
9975  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
9976  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_7_WIDTH },
9977  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
9978  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_8_WIDTH },
9979  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
9980  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_9_WIDTH },
9981  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
9982  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_10_WIDTH },
9983  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
9984  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_11_WIDTH },
9985  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
9986  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_12_WIDTH },
9987  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
9988  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_13_WIDTH },
9989  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
9990  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_14_WIDTH },
9991  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
9992  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_15_WIDTH },
9993  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
9994  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_16_WIDTH },
9995  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
9996  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_17_WIDTH },
9997  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
9998  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_18_WIDTH },
9999  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
10000  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_19_WIDTH },
10001  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
10002  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_20_WIDTH },
10003  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
10004  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_21_WIDTH },
10005  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
10006  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_22_WIDTH },
10007  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
10008  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_23_WIDTH },
10009  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
10010  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_24_WIDTH },
10011  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
10012  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_25_WIDTH },
10013  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
10014  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_26_WIDTH },
10015  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
10016  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_27_WIDTH },
10017  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
10018  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_28_WIDTH },
10019  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
10020  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_29_WIDTH },
10021  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
10022  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_30_WIDTH },
10023  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
10024  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_31_WIDTH },
10025  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
10026  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_32_WIDTH },
10027  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_33_CHECKER_TYPE,
10028  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_33_WIDTH },
10029  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_34_CHECKER_TYPE,
10030  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_34_WIDTH },
10031  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_35_CHECKER_TYPE,
10032  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_35_WIDTH },
10033  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_36_CHECKER_TYPE,
10034  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_36_WIDTH },
10035  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_37_CHECKER_TYPE,
10036  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_37_WIDTH },
10037  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_38_CHECKER_TYPE,
10038  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_38_WIDTH },
10039  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_39_CHECKER_TYPE,
10040  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_39_WIDTH },
10041  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_40_CHECKER_TYPE,
10042  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_40_WIDTH },
10043  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_41_CHECKER_TYPE,
10044  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_41_WIDTH },
10045  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_42_CHECKER_TYPE,
10046  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_42_WIDTH },
10047  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_43_CHECKER_TYPE,
10048  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_43_WIDTH },
10049  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_44_CHECKER_TYPE,
10050  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_44_WIDTH },
10051  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_45_CHECKER_TYPE,
10052  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_45_WIDTH },
10053  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_46_CHECKER_TYPE,
10054  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_46_WIDTH },
10055  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_47_CHECKER_TYPE,
10056  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_47_WIDTH },
10057  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_48_CHECKER_TYPE,
10058  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_48_WIDTH },
10059  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_49_CHECKER_TYPE,
10060  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_49_WIDTH },
10061  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_50_CHECKER_TYPE,
10062  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_50_WIDTH },
10063  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_51_CHECKER_TYPE,
10064  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_51_WIDTH },
10065  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_52_CHECKER_TYPE,
10066  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_52_WIDTH },
10067  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_53_CHECKER_TYPE,
10068  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_53_WIDTH },
10069  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_54_CHECKER_TYPE,
10070  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_54_WIDTH },
10071  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_55_CHECKER_TYPE,
10072  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_55_WIDTH },
10073  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_56_CHECKER_TYPE,
10074  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_56_WIDTH },
10075  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_57_CHECKER_TYPE,
10076  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_57_WIDTH },
10077  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_58_CHECKER_TYPE,
10078  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_58_WIDTH },
10079  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_59_CHECKER_TYPE,
10080  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_59_WIDTH },
10081  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_60_CHECKER_TYPE,
10082  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_60_WIDTH },
10083  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_61_CHECKER_TYPE,
10084  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_61_WIDTH },
10085  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_62_CHECKER_TYPE,
10086  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_62_WIDTH },
10087  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_63_CHECKER_TYPE,
10088  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_63_WIDTH },
10089  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_64_CHECKER_TYPE,
10090  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_64_WIDTH },
10091  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_65_CHECKER_TYPE,
10092  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_65_WIDTH },
10093  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_66_CHECKER_TYPE,
10094  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_66_WIDTH },
10095  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_67_CHECKER_TYPE,
10096  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_67_WIDTH },
10097  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_68_CHECKER_TYPE,
10098  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_68_WIDTH },
10099  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_69_CHECKER_TYPE,
10100  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_69_WIDTH },
10101  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_70_CHECKER_TYPE,
10102  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_70_WIDTH },
10103  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_71_CHECKER_TYPE,
10104  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_71_WIDTH },
10105  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_72_CHECKER_TYPE,
10106  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_72_WIDTH },
10107  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_73_CHECKER_TYPE,
10108  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_73_WIDTH },
10109  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_74_CHECKER_TYPE,
10110  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_74_WIDTH },
10111  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_75_CHECKER_TYPE,
10112  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_75_WIDTH },
10113  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_76_CHECKER_TYPE,
10114  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_76_WIDTH },
10115  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_77_CHECKER_TYPE,
10116  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_77_WIDTH },
10117  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_78_CHECKER_TYPE,
10118  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_78_WIDTH },
10119  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_79_CHECKER_TYPE,
10120  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_79_WIDTH },
10121  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_80_CHECKER_TYPE,
10122  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_80_WIDTH },
10123  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_81_CHECKER_TYPE,
10124  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_81_WIDTH },
10125  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_82_CHECKER_TYPE,
10126  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_82_WIDTH },
10127  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_83_CHECKER_TYPE,
10128  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_83_WIDTH },
10129  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_84_CHECKER_TYPE,
10130  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_84_WIDTH },
10131  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_85_CHECKER_TYPE,
10132  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_85_WIDTH },
10133  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_86_CHECKER_TYPE,
10134  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_86_WIDTH },
10135  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_87_CHECKER_TYPE,
10136  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_87_WIDTH },
10137  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_88_CHECKER_TYPE,
10138  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_88_WIDTH },
10139  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_89_CHECKER_TYPE,
10140  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_89_WIDTH },
10141  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_90_CHECKER_TYPE,
10142  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_90_WIDTH },
10143 };
10144 
10150 static const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_groupEntries[SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_MAX_NUM_CHECKERS] =
10151 {
10152  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
10153  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_0_WIDTH },
10154  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
10155  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_1_WIDTH },
10156  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
10157  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_2_WIDTH },
10158  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
10159  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_3_WIDTH },
10160  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
10161  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_4_WIDTH },
10162  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
10163  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_5_WIDTH },
10164  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
10165  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_6_WIDTH },
10166  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
10167  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_7_WIDTH },
10168  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
10169  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_8_WIDTH },
10170  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
10171  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_9_WIDTH },
10172  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
10173  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_10_WIDTH },
10174  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
10175  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_11_WIDTH },
10176  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
10177  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_12_WIDTH },
10178  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
10179  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_13_WIDTH },
10180  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
10181  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_14_WIDTH },
10182  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
10183  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_15_WIDTH },
10184  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
10185  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_16_WIDTH },
10186  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
10187  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_17_WIDTH },
10188  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
10189  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_18_WIDTH },
10190  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
10191  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_19_WIDTH },
10192  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
10193  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_20_WIDTH },
10194  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
10195  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_21_WIDTH },
10196  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
10197  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_22_WIDTH },
10198  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
10199  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_23_WIDTH },
10200  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
10201  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_24_WIDTH },
10202  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
10203  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_25_WIDTH },
10204  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
10205  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_26_WIDTH },
10206  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
10207  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_27_WIDTH },
10208  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
10209  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_28_WIDTH },
10210  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
10211  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_29_WIDTH },
10212  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
10213  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_30_WIDTH },
10214  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
10215  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_31_WIDTH },
10216  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
10217  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_32_WIDTH },
10218  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_33_CHECKER_TYPE,
10219  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_33_WIDTH },
10220  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_34_CHECKER_TYPE,
10221  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_34_WIDTH },
10222  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_35_CHECKER_TYPE,
10223  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_35_WIDTH },
10224  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_36_CHECKER_TYPE,
10225  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_36_WIDTH },
10226  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_37_CHECKER_TYPE,
10227  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_37_WIDTH },
10228  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_38_CHECKER_TYPE,
10229  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_38_WIDTH },
10230  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_39_CHECKER_TYPE,
10231  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_39_WIDTH },
10232  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_40_CHECKER_TYPE,
10233  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_40_WIDTH },
10234  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_41_CHECKER_TYPE,
10235  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_41_WIDTH },
10236  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_42_CHECKER_TYPE,
10237  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_42_WIDTH },
10238  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_43_CHECKER_TYPE,
10239  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_43_WIDTH },
10240  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_44_CHECKER_TYPE,
10241  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_44_WIDTH },
10242  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_45_CHECKER_TYPE,
10243  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_45_WIDTH },
10244  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_46_CHECKER_TYPE,
10245  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_46_WIDTH },
10246  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_47_CHECKER_TYPE,
10247  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_47_WIDTH },
10248  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_48_CHECKER_TYPE,
10249  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_48_WIDTH },
10250  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_49_CHECKER_TYPE,
10251  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_49_WIDTH },
10252  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_50_CHECKER_TYPE,
10253  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_50_WIDTH },
10254  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_51_CHECKER_TYPE,
10255  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_51_WIDTH },
10256  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_52_CHECKER_TYPE,
10257  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_52_WIDTH },
10258  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_53_CHECKER_TYPE,
10259  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_53_WIDTH },
10260  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_54_CHECKER_TYPE,
10261  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_54_WIDTH },
10262  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_55_CHECKER_TYPE,
10263  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_55_WIDTH },
10264  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_56_CHECKER_TYPE,
10265  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_56_WIDTH },
10266  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_57_CHECKER_TYPE,
10267  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_57_WIDTH },
10268  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_58_CHECKER_TYPE,
10269  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_58_WIDTH },
10270  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_59_CHECKER_TYPE,
10271  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_59_WIDTH },
10272  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_60_CHECKER_TYPE,
10273  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_60_WIDTH },
10274  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_61_CHECKER_TYPE,
10275  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_61_WIDTH },
10276 };
10277 
10282 static const SDL_MemConfig_t SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_MemEntries[SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES] =
10283 {
10284  { SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_PKTRAM0_ECC_RAM_ID, 0u,
10285  SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_PKTRAM0_ECC_RAM_SIZE, 4u,
10286  SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_PKTRAM0_ECC_ROW_WIDTH, ((bool)false) },
10287  { SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_PKTRAM1_ECC_RAM_ID, 0u,
10288  SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_PKTRAM1_ECC_RAM_SIZE, 4u,
10289  SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_PKTRAM1_ECC_ROW_WIDTH, ((bool)false) },
10290  { SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_PKA_PROG_RAM_ECC_RAM_ID, 0u,
10291  SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_PKA_PROG_RAM_ECC_RAM_SIZE, 4u,
10292  SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_PKA_PROG_RAM_ECC_ROW_WIDTH, ((bool)false) },
10293  { SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_ENCR_CTXRAM_BANK01_ECC_RAM_ID, 0u,
10294  SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_ENCR_CTXRAM_BANK01_ECC_RAM_SIZE, 4u,
10295  SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_ENCR_CTXRAM_BANK01_ECC_ROW_WIDTH, ((bool)false) },
10296  { SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_ENCR_CTXRAM_BANK23_ECC_RAM_ID, 0u,
10297  SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_ENCR_CTXRAM_BANK23_ECC_RAM_SIZE, 4u,
10298  SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_ENCR_CTXRAM_BANK23_ECC_ROW_WIDTH, ((bool)false) },
10299  { SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_ENCR_CTXRAM_BANK4_ECC_RAM_ID, 0u,
10300  SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_ENCR_CTXRAM_BANK4_ECC_RAM_SIZE, 4u,
10301  SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_ENCR_CTXRAM_BANK4_ECC_ROW_WIDTH, ((bool)false) },
10302  { SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_AUTH_CTXRAM_BANK01_ECC_RAM_ID, 0u,
10303  SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_AUTH_CTXRAM_BANK01_ECC_RAM_SIZE, 4u,
10304  SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_AUTH_CTXRAM_BANK01_ECC_ROW_WIDTH, ((bool)false) },
10305  { SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_AUTH_CTXRAM_BANK23_ECC_RAM_ID, 0u,
10306  SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_AUTH_CTXRAM_BANK23_ECC_RAM_SIZE, 4u,
10307  SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_AUTH_CTXRAM_BANK23_ECC_ROW_WIDTH, ((bool)false) },
10308  { SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_AUTH_CTXRAM_BANK45_ECC_RAM_ID, 0u,
10309  SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_AUTH_CTXRAM_BANK45_ECC_RAM_SIZE, 4u,
10310  SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_AUTH_CTXRAM_BANK45_ECC_ROW_WIDTH, ((bool)false) },
10311  { SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_AUTH_CTXRAM_BANK67_ECC_RAM_ID, 0u,
10312  SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_AUTH_CTXRAM_BANK67_ECC_RAM_SIZE, 4u,
10313  SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_AUTH_CTXRAM_BANK67_ECC_ROW_WIDTH, ((bool)false) },
10314  { SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_AUTH_CTXRAM_BANK89_ECC_RAM_ID, 0u,
10315  SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_AUTH_CTXRAM_BANK89_ECC_RAM_SIZE, 4u,
10316  SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_AUTH_CTXRAM_BANK89_ECC_ROW_WIDTH, ((bool)false) },
10317  { SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_AUTH_CTXRAM_BANK10_ECC_RAM_ID, 0u,
10318  SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_AUTH_CTXRAM_BANK10_ECC_RAM_SIZE, 4u,
10319  SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_AUTH_CTXRAM_BANK10_ECC_ROW_WIDTH, ((bool)false) },
10320 };
10321 
10326 static const SDL_MemConfig_t SDL_MCU_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_MemEntries[SDL_MCU_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES] =
10327 {
10328  { SDL_MCU_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_ID, 0x0004E10000u,
10329  SDL_MCU_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_SIZE, 4u,
10330  SDL_MCU_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_ROW_WIDTH, ((bool)true) },
10331 };
10332 
10338 static const SDL_GrpChkConfig_t SDL_MCU_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_groupEntries[SDL_MCU_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_MAX_NUM_CHECKERS] =
10339 {
10340  { SDL_MCU_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_GROUP_0_CHECKER_TYPE,
10341  SDL_MCU_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_GROUP_0_WIDTH },
10342 };
10343 
10349 static const SDL_GrpChkConfig_t SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS] =
10350 {
10351  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
10352  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
10353  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
10354  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
10355  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
10356  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
10357  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
10358  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
10359  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
10360  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
10361  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_5_CHECKER_TYPE,
10362  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_5_WIDTH },
10363  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_6_CHECKER_TYPE,
10364  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_6_WIDTH },
10365  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_7_CHECKER_TYPE,
10366  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_7_WIDTH },
10367  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_8_CHECKER_TYPE,
10368  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_8_WIDTH },
10369  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_9_CHECKER_TYPE,
10370  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_9_WIDTH },
10371  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_10_CHECKER_TYPE,
10372  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_10_WIDTH },
10373  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_11_CHECKER_TYPE,
10374  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_11_WIDTH },
10375  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_12_CHECKER_TYPE,
10376  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_12_WIDTH },
10377  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_13_CHECKER_TYPE,
10378  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_13_WIDTH },
10379  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_14_CHECKER_TYPE,
10380  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_14_WIDTH },
10381  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_15_CHECKER_TYPE,
10382  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_15_WIDTH },
10383  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_16_CHECKER_TYPE,
10384  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_16_WIDTH },
10385  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_17_CHECKER_TYPE,
10386  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_17_WIDTH },
10387  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_18_CHECKER_TYPE,
10388  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_18_WIDTH },
10389  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_19_CHECKER_TYPE,
10390  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_19_WIDTH },
10391  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_20_CHECKER_TYPE,
10392  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_20_WIDTH },
10393  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_21_CHECKER_TYPE,
10394  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_21_WIDTH },
10395  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_22_CHECKER_TYPE,
10396  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_22_WIDTH },
10397  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_23_CHECKER_TYPE,
10398  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_23_WIDTH },
10399  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_24_CHECKER_TYPE,
10400  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_24_WIDTH },
10401  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_25_CHECKER_TYPE,
10402  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_25_WIDTH },
10403  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_26_CHECKER_TYPE,
10404  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_26_WIDTH },
10405  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_27_CHECKER_TYPE,
10406  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_27_WIDTH },
10407  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_28_CHECKER_TYPE,
10408  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_28_WIDTH },
10409  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_29_CHECKER_TYPE,
10410  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_29_WIDTH },
10411  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_30_CHECKER_TYPE,
10412  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_30_WIDTH },
10413  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_31_CHECKER_TYPE,
10414  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_31_WIDTH },
10415  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_32_CHECKER_TYPE,
10416  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_32_WIDTH },
10417  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_33_CHECKER_TYPE,
10418  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_33_WIDTH },
10419  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_34_CHECKER_TYPE,
10420  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_34_WIDTH },
10421  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_35_CHECKER_TYPE,
10422  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_35_WIDTH },
10423  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_36_CHECKER_TYPE,
10424  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_36_WIDTH },
10425  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_37_CHECKER_TYPE,
10426  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_37_WIDTH },
10427  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_38_CHECKER_TYPE,
10428  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_38_WIDTH },
10429  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_39_CHECKER_TYPE,
10430  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_39_WIDTH },
10431  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_40_CHECKER_TYPE,
10432  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_40_WIDTH },
10433  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_41_CHECKER_TYPE,
10434  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_41_WIDTH },
10435  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_42_CHECKER_TYPE,
10436  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_42_WIDTH },
10437  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_43_CHECKER_TYPE,
10438  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_43_WIDTH },
10439  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_44_CHECKER_TYPE,
10440  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_44_WIDTH },
10441  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_45_CHECKER_TYPE,
10442  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_45_WIDTH },
10443  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_46_CHECKER_TYPE,
10444  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_46_WIDTH },
10445  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_47_CHECKER_TYPE,
10446  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_47_WIDTH },
10447  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_48_CHECKER_TYPE,
10448  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_48_WIDTH },
10449  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_49_CHECKER_TYPE,
10450  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_49_WIDTH },
10451  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_50_CHECKER_TYPE,
10452  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_50_WIDTH },
10453  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_51_CHECKER_TYPE,
10454  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_51_WIDTH },
10455  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_52_CHECKER_TYPE,
10456  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_52_WIDTH },
10457  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_53_CHECKER_TYPE,
10458  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_53_WIDTH },
10459  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_54_CHECKER_TYPE,
10460  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_54_WIDTH },
10461  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_55_CHECKER_TYPE,
10462  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_55_WIDTH },
10463  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_56_CHECKER_TYPE,
10464  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_56_WIDTH },
10465  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_57_CHECKER_TYPE,
10466  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_57_WIDTH },
10467  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_58_CHECKER_TYPE,
10468  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_58_WIDTH },
10469  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_59_CHECKER_TYPE,
10470  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_59_WIDTH },
10471  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_60_CHECKER_TYPE,
10472  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_60_WIDTH },
10473  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_61_CHECKER_TYPE,
10474  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_61_WIDTH },
10475  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_62_CHECKER_TYPE,
10476  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_62_WIDTH },
10477  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_63_CHECKER_TYPE,
10478  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_63_WIDTH },
10479  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_64_CHECKER_TYPE,
10480  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_64_WIDTH },
10481  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_65_CHECKER_TYPE,
10482  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_65_WIDTH },
10483  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_66_CHECKER_TYPE,
10484  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_66_WIDTH },
10485  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_67_CHECKER_TYPE,
10486  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_67_WIDTH },
10487  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_68_CHECKER_TYPE,
10488  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_68_WIDTH },
10489  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_69_CHECKER_TYPE,
10490  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_69_WIDTH },
10491  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_70_CHECKER_TYPE,
10492  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_70_WIDTH },
10493  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_71_CHECKER_TYPE,
10494  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_71_WIDTH },
10495  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_72_CHECKER_TYPE,
10496  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_72_WIDTH },
10497  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_73_CHECKER_TYPE,
10498  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_73_WIDTH },
10499  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_74_CHECKER_TYPE,
10500  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_74_WIDTH },
10501  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_75_CHECKER_TYPE,
10502  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_75_WIDTH },
10503  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_76_CHECKER_TYPE,
10504  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_76_WIDTH },
10505  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_77_CHECKER_TYPE,
10506  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_77_WIDTH },
10507 };
10508 
10514 static const SDL_GrpChkConfig_t SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_groupEntries[SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS] =
10515 {
10516  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
10517  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
10518  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
10519  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
10520  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
10521  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
10522  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
10523  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
10524  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
10525  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
10526  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_5_CHECKER_TYPE,
10527  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_5_WIDTH },
10528  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_6_CHECKER_TYPE,
10529  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_6_WIDTH },
10530  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_7_CHECKER_TYPE,
10531  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_7_WIDTH },
10532  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_8_CHECKER_TYPE,
10533  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_8_WIDTH },
10534  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_9_CHECKER_TYPE,
10535  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_9_WIDTH },
10536  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_10_CHECKER_TYPE,
10537  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_10_WIDTH },
10538  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_11_CHECKER_TYPE,
10539  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_11_WIDTH },
10540  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_12_CHECKER_TYPE,
10541  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_12_WIDTH },
10542  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_13_CHECKER_TYPE,
10543  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_13_WIDTH },
10544  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_14_CHECKER_TYPE,
10545  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_14_WIDTH },
10546  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_15_CHECKER_TYPE,
10547  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_15_WIDTH },
10548  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_16_CHECKER_TYPE,
10549  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_16_WIDTH },
10550  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_17_CHECKER_TYPE,
10551  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_17_WIDTH },
10552  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_18_CHECKER_TYPE,
10553  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_18_WIDTH },
10554  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_19_CHECKER_TYPE,
10555  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_19_WIDTH },
10556  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_20_CHECKER_TYPE,
10557  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_20_WIDTH },
10558  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_21_CHECKER_TYPE,
10559  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_21_WIDTH },
10560  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_22_CHECKER_TYPE,
10561  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_22_WIDTH },
10562  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_23_CHECKER_TYPE,
10563  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_23_WIDTH },
10564  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_24_CHECKER_TYPE,
10565  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_24_WIDTH },
10566  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_25_CHECKER_TYPE,
10567  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_25_WIDTH },
10568  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_26_CHECKER_TYPE,
10569  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_26_WIDTH },
10570  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_27_CHECKER_TYPE,
10571  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_27_WIDTH },
10572  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_28_CHECKER_TYPE,
10573  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_28_WIDTH },
10574  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_29_CHECKER_TYPE,
10575  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_29_WIDTH },
10576  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_30_CHECKER_TYPE,
10577  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_30_WIDTH },
10578  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_31_CHECKER_TYPE,
10579  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_31_WIDTH },
10580  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_32_CHECKER_TYPE,
10581  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_32_WIDTH },
10582  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_33_CHECKER_TYPE,
10583  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_33_WIDTH },
10584  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_34_CHECKER_TYPE,
10585  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_34_WIDTH },
10586  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_35_CHECKER_TYPE,
10587  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_35_WIDTH },
10588  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_36_CHECKER_TYPE,
10589  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_36_WIDTH },
10590  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_37_CHECKER_TYPE,
10591  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_37_WIDTH },
10592  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_38_CHECKER_TYPE,
10593  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_38_WIDTH },
10594  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_39_CHECKER_TYPE,
10595  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_39_WIDTH },
10596  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_40_CHECKER_TYPE,
10597  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_40_WIDTH },
10598  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_41_CHECKER_TYPE,
10599  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_41_WIDTH },
10600  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_42_CHECKER_TYPE,
10601  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_42_WIDTH },
10602  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_43_CHECKER_TYPE,
10603  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_43_WIDTH },
10604  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_44_CHECKER_TYPE,
10605  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_44_WIDTH },
10606  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_45_CHECKER_TYPE,
10607  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_45_WIDTH },
10608  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_46_CHECKER_TYPE,
10609  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_46_WIDTH },
10610  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_47_CHECKER_TYPE,
10611  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_47_WIDTH },
10612  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_48_CHECKER_TYPE,
10613  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_48_WIDTH },
10614  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_49_CHECKER_TYPE,
10615  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_49_WIDTH },
10616  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_50_CHECKER_TYPE,
10617  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_50_WIDTH },
10618  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_51_CHECKER_TYPE,
10619  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_51_WIDTH },
10620  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_52_CHECKER_TYPE,
10621  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_52_WIDTH },
10622  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_53_CHECKER_TYPE,
10623  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_53_WIDTH },
10624  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_54_CHECKER_TYPE,
10625  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_54_WIDTH },
10626  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_55_CHECKER_TYPE,
10627  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_55_WIDTH },
10628  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_56_CHECKER_TYPE,
10629  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_56_WIDTH },
10630  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_57_CHECKER_TYPE,
10631  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_57_WIDTH },
10632  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_58_CHECKER_TYPE,
10633  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_58_WIDTH },
10634  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_59_CHECKER_TYPE,
10635  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_59_WIDTH },
10636  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_60_CHECKER_TYPE,
10637  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_60_WIDTH },
10638  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_61_CHECKER_TYPE,
10639  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_61_WIDTH },
10640  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_62_CHECKER_TYPE,
10641  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_62_WIDTH },
10642  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_63_CHECKER_TYPE,
10643  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_63_WIDTH },
10644  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_64_CHECKER_TYPE,
10645  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_64_WIDTH },
10646  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_65_CHECKER_TYPE,
10647  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_65_WIDTH },
10648  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_66_CHECKER_TYPE,
10649  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_66_WIDTH },
10650  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_67_CHECKER_TYPE,
10651  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_67_WIDTH },
10652  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_68_CHECKER_TYPE,
10653  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_68_WIDTH },
10654  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_69_CHECKER_TYPE,
10655  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_69_WIDTH },
10656  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_70_CHECKER_TYPE,
10657  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_70_WIDTH },
10658  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_71_CHECKER_TYPE,
10659  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_71_WIDTH },
10660  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_72_CHECKER_TYPE,
10661  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_72_WIDTH },
10662  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_73_CHECKER_TYPE,
10663  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_73_WIDTH },
10664  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_74_CHECKER_TYPE,
10665  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_74_WIDTH },
10666  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_75_CHECKER_TYPE,
10667  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_75_WIDTH },
10668  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_76_CHECKER_TYPE,
10669  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_76_WIDTH },
10670  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_77_CHECKER_TYPE,
10671  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_77_WIDTH },
10672  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_78_CHECKER_TYPE,
10673  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_78_WIDTH },
10674  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_79_CHECKER_TYPE,
10675  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_79_WIDTH },
10676  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_80_CHECKER_TYPE,
10677  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_80_WIDTH },
10678 };
10679 
10685 static const SDL_GrpChkConfig_t SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISAM67_DM_MCU_ECC_AGGR_WKUP_1_CFG_P2P_BRIDGE_ISAM67_DM_MCU_ECC_AGGR_WKUP_1_CFG_BRIDGE_SRC_BUSECC_groupEntries[SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISAM67_DM_MCU_ECC_AGGR_WKUP_1_CFG_P2P_BRIDGE_ISAM67_DM_MCU_ECC_AGGR_WKUP_1_CFG_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS] =
10686 {
10687  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISAM67_DM_MCU_ECC_AGGR_WKUP_1_CFG_P2P_BRIDGE_ISAM67_DM_MCU_ECC_AGGR_WKUP_1_CFG_BRIDGE_SRC_BUSECC_GROUP_0_CHECKER_TYPE,
10688  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISAM67_DM_MCU_ECC_AGGR_WKUP_1_CFG_P2P_BRIDGE_ISAM67_DM_MCU_ECC_AGGR_WKUP_1_CFG_BRIDGE_SRC_BUSECC_GROUP_0_WIDTH },
10689  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISAM67_DM_MCU_ECC_AGGR_WKUP_1_CFG_P2P_BRIDGE_ISAM67_DM_MCU_ECC_AGGR_WKUP_1_CFG_BRIDGE_SRC_BUSECC_GROUP_1_CHECKER_TYPE,
10690  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISAM67_DM_MCU_ECC_AGGR_WKUP_1_CFG_P2P_BRIDGE_ISAM67_DM_MCU_ECC_AGGR_WKUP_1_CFG_BRIDGE_SRC_BUSECC_GROUP_1_WIDTH },
10691  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISAM67_DM_MCU_ECC_AGGR_WKUP_1_CFG_P2P_BRIDGE_ISAM67_DM_MCU_ECC_AGGR_WKUP_1_CFG_BRIDGE_SRC_BUSECC_GROUP_2_CHECKER_TYPE,
10692  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISAM67_DM_MCU_ECC_AGGR_WKUP_1_CFG_P2P_BRIDGE_ISAM67_DM_MCU_ECC_AGGR_WKUP_1_CFG_BRIDGE_SRC_BUSECC_GROUP_2_WIDTH },
10693  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISAM67_DM_MCU_ECC_AGGR_WKUP_1_CFG_P2P_BRIDGE_ISAM67_DM_MCU_ECC_AGGR_WKUP_1_CFG_BRIDGE_SRC_BUSECC_GROUP_3_CHECKER_TYPE,
10694  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISAM67_DM_MCU_ECC_AGGR_WKUP_1_CFG_P2P_BRIDGE_ISAM67_DM_MCU_ECC_AGGR_WKUP_1_CFG_BRIDGE_SRC_BUSECC_GROUP_3_WIDTH },
10695  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISAM67_DM_MCU_ECC_AGGR_WKUP_1_CFG_P2P_BRIDGE_ISAM67_DM_MCU_ECC_AGGR_WKUP_1_CFG_BRIDGE_SRC_BUSECC_GROUP_4_CHECKER_TYPE,
10696  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISAM67_DM_MCU_ECC_AGGR_WKUP_1_CFG_P2P_BRIDGE_ISAM67_DM_MCU_ECC_AGGR_WKUP_1_CFG_BRIDGE_SRC_BUSECC_GROUP_4_WIDTH },
10697  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISAM67_DM_MCU_ECC_AGGR_WKUP_1_CFG_P2P_BRIDGE_ISAM67_DM_MCU_ECC_AGGR_WKUP_1_CFG_BRIDGE_SRC_BUSECC_GROUP_5_CHECKER_TYPE,
10698  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISAM67_DM_MCU_ECC_AGGR_WKUP_1_CFG_P2P_BRIDGE_ISAM67_DM_MCU_ECC_AGGR_WKUP_1_CFG_BRIDGE_SRC_BUSECC_GROUP_5_WIDTH },
10699  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISAM67_DM_MCU_ECC_AGGR_WKUP_1_CFG_P2P_BRIDGE_ISAM67_DM_MCU_ECC_AGGR_WKUP_1_CFG_BRIDGE_SRC_BUSECC_GROUP_6_CHECKER_TYPE,
10700  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISAM67_DM_MCU_ECC_AGGR_WKUP_1_CFG_P2P_BRIDGE_ISAM67_DM_MCU_ECC_AGGR_WKUP_1_CFG_BRIDGE_SRC_BUSECC_GROUP_6_WIDTH },
10701  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISAM67_DM_MCU_ECC_AGGR_WKUP_1_CFG_P2P_BRIDGE_ISAM67_DM_MCU_ECC_AGGR_WKUP_1_CFG_BRIDGE_SRC_BUSECC_GROUP_7_CHECKER_TYPE,
10702  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISAM67_DM_MCU_ECC_AGGR_WKUP_1_CFG_P2P_BRIDGE_ISAM67_DM_MCU_ECC_AGGR_WKUP_1_CFG_BRIDGE_SRC_BUSECC_GROUP_7_WIDTH },
10703  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISAM67_DM_MCU_ECC_AGGR_WKUP_1_CFG_P2P_BRIDGE_ISAM67_DM_MCU_ECC_AGGR_WKUP_1_CFG_BRIDGE_SRC_BUSECC_GROUP_8_CHECKER_TYPE,
10704  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISAM67_DM_MCU_ECC_AGGR_WKUP_1_CFG_P2P_BRIDGE_ISAM67_DM_MCU_ECC_AGGR_WKUP_1_CFG_BRIDGE_SRC_BUSECC_GROUP_8_WIDTH },
10705  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISAM67_DM_MCU_ECC_AGGR_WKUP_1_CFG_P2P_BRIDGE_ISAM67_DM_MCU_ECC_AGGR_WKUP_1_CFG_BRIDGE_SRC_BUSECC_GROUP_9_CHECKER_TYPE,
10706  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISAM67_DM_MCU_ECC_AGGR_WKUP_1_CFG_P2P_BRIDGE_ISAM67_DM_MCU_ECC_AGGR_WKUP_1_CFG_BRIDGE_SRC_BUSECC_GROUP_9_WIDTH },
10707  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISAM67_DM_MCU_ECC_AGGR_WKUP_1_CFG_P2P_BRIDGE_ISAM67_DM_MCU_ECC_AGGR_WKUP_1_CFG_BRIDGE_SRC_BUSECC_GROUP_10_CHECKER_TYPE,
10708  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISAM67_DM_MCU_ECC_AGGR_WKUP_1_CFG_P2P_BRIDGE_ISAM67_DM_MCU_ECC_AGGR_WKUP_1_CFG_BRIDGE_SRC_BUSECC_GROUP_10_WIDTH },
10709  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISAM67_DM_MCU_ECC_AGGR_WKUP_1_CFG_P2P_BRIDGE_ISAM67_DM_MCU_ECC_AGGR_WKUP_1_CFG_BRIDGE_SRC_BUSECC_GROUP_11_CHECKER_TYPE,
10710  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISAM67_DM_MCU_ECC_AGGR_WKUP_1_CFG_P2P_BRIDGE_ISAM67_DM_MCU_ECC_AGGR_WKUP_1_CFG_BRIDGE_SRC_BUSECC_GROUP_11_WIDTH },
10711  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISAM67_DM_MCU_ECC_AGGR_WKUP_1_CFG_P2P_BRIDGE_ISAM67_DM_MCU_ECC_AGGR_WKUP_1_CFG_BRIDGE_SRC_BUSECC_GROUP_12_CHECKER_TYPE,
10712  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISAM67_DM_MCU_ECC_AGGR_WKUP_1_CFG_P2P_BRIDGE_ISAM67_DM_MCU_ECC_AGGR_WKUP_1_CFG_BRIDGE_SRC_BUSECC_GROUP_12_WIDTH },
10713  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISAM67_DM_MCU_ECC_AGGR_WKUP_1_CFG_P2P_BRIDGE_ISAM67_DM_MCU_ECC_AGGR_WKUP_1_CFG_BRIDGE_SRC_BUSECC_GROUP_13_CHECKER_TYPE,
10714  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISAM67_DM_MCU_ECC_AGGR_WKUP_1_CFG_P2P_BRIDGE_ISAM67_DM_MCU_ECC_AGGR_WKUP_1_CFG_BRIDGE_SRC_BUSECC_GROUP_13_WIDTH },
10715  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISAM67_DM_MCU_ECC_AGGR_WKUP_1_CFG_P2P_BRIDGE_ISAM67_DM_MCU_ECC_AGGR_WKUP_1_CFG_BRIDGE_SRC_BUSECC_GROUP_14_CHECKER_TYPE,
10716  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISAM67_DM_MCU_ECC_AGGR_WKUP_1_CFG_P2P_BRIDGE_ISAM67_DM_MCU_ECC_AGGR_WKUP_1_CFG_BRIDGE_SRC_BUSECC_GROUP_14_WIDTH },
10717  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISAM67_DM_MCU_ECC_AGGR_WKUP_1_CFG_P2P_BRIDGE_ISAM67_DM_MCU_ECC_AGGR_WKUP_1_CFG_BRIDGE_SRC_BUSECC_GROUP_15_CHECKER_TYPE,
10718  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISAM67_DM_MCU_ECC_AGGR_WKUP_1_CFG_P2P_BRIDGE_ISAM67_DM_MCU_ECC_AGGR_WKUP_1_CFG_BRIDGE_SRC_BUSECC_GROUP_15_WIDTH },
10719  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISAM67_DM_MCU_ECC_AGGR_WKUP_1_CFG_P2P_BRIDGE_ISAM67_DM_MCU_ECC_AGGR_WKUP_1_CFG_BRIDGE_SRC_BUSECC_GROUP_16_CHECKER_TYPE,
10720  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISAM67_DM_MCU_ECC_AGGR_WKUP_1_CFG_P2P_BRIDGE_ISAM67_DM_MCU_ECC_AGGR_WKUP_1_CFG_BRIDGE_SRC_BUSECC_GROUP_16_WIDTH },
10721 };
10722 
10728 static const SDL_GrpChkConfig_t SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_IK3VTM_N16FFC_WKUP_0_VBUSP_P2P_BRIDGE_IK3VTM_N16FFC_WKUP_0_VBUSP_BRIDGE_BUSECC_groupEntries[SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_IK3VTM_N16FFC_WKUP_0_VBUSP_P2P_BRIDGE_IK3VTM_N16FFC_WKUP_0_VBUSP_BRIDGE_BUSECC_MAX_NUM_CHECKERS] =
10729 {
10730  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_IK3VTM_N16FFC_WKUP_0_VBUSP_P2P_BRIDGE_IK3VTM_N16FFC_WKUP_0_VBUSP_BRIDGE_BUSECC_GROUP_0_CHECKER_TYPE,
10731  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_IK3VTM_N16FFC_WKUP_0_VBUSP_P2P_BRIDGE_IK3VTM_N16FFC_WKUP_0_VBUSP_BRIDGE_BUSECC_GROUP_0_WIDTH },
10732  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_IK3VTM_N16FFC_WKUP_0_VBUSP_P2P_BRIDGE_IK3VTM_N16FFC_WKUP_0_VBUSP_BRIDGE_BUSECC_GROUP_1_CHECKER_TYPE,
10733  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_IK3VTM_N16FFC_WKUP_0_VBUSP_P2P_BRIDGE_IK3VTM_N16FFC_WKUP_0_VBUSP_BRIDGE_BUSECC_GROUP_1_WIDTH },
10734  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_IK3VTM_N16FFC_WKUP_0_VBUSP_P2P_BRIDGE_IK3VTM_N16FFC_WKUP_0_VBUSP_BRIDGE_BUSECC_GROUP_2_CHECKER_TYPE,
10735  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_IK3VTM_N16FFC_WKUP_0_VBUSP_P2P_BRIDGE_IK3VTM_N16FFC_WKUP_0_VBUSP_BRIDGE_BUSECC_GROUP_2_WIDTH },
10736  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_IK3VTM_N16FFC_WKUP_0_VBUSP_P2P_BRIDGE_IK3VTM_N16FFC_WKUP_0_VBUSP_BRIDGE_BUSECC_GROUP_3_CHECKER_TYPE,
10737  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_IK3VTM_N16FFC_WKUP_0_VBUSP_P2P_BRIDGE_IK3VTM_N16FFC_WKUP_0_VBUSP_BRIDGE_BUSECC_GROUP_3_WIDTH },
10738  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_IK3VTM_N16FFC_WKUP_0_VBUSP_P2P_BRIDGE_IK3VTM_N16FFC_WKUP_0_VBUSP_BRIDGE_BUSECC_GROUP_4_CHECKER_TYPE,
10739  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_IK3VTM_N16FFC_WKUP_0_VBUSP_P2P_BRIDGE_IK3VTM_N16FFC_WKUP_0_VBUSP_BRIDGE_BUSECC_GROUP_4_WIDTH },
10740  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_IK3VTM_N16FFC_WKUP_0_VBUSP_P2P_BRIDGE_IK3VTM_N16FFC_WKUP_0_VBUSP_BRIDGE_BUSECC_GROUP_5_CHECKER_TYPE,
10741  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_IK3VTM_N16FFC_WKUP_0_VBUSP_P2P_BRIDGE_IK3VTM_N16FFC_WKUP_0_VBUSP_BRIDGE_BUSECC_GROUP_5_WIDTH },
10742  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_IK3VTM_N16FFC_WKUP_0_VBUSP_P2P_BRIDGE_IK3VTM_N16FFC_WKUP_0_VBUSP_BRIDGE_BUSECC_GROUP_6_CHECKER_TYPE,
10743  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_IK3VTM_N16FFC_WKUP_0_VBUSP_P2P_BRIDGE_IK3VTM_N16FFC_WKUP_0_VBUSP_BRIDGE_BUSECC_GROUP_6_WIDTH },
10744  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_IK3VTM_N16FFC_WKUP_0_VBUSP_P2P_BRIDGE_IK3VTM_N16FFC_WKUP_0_VBUSP_BRIDGE_BUSECC_GROUP_7_CHECKER_TYPE,
10745  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_IK3VTM_N16FFC_WKUP_0_VBUSP_P2P_BRIDGE_IK3VTM_N16FFC_WKUP_0_VBUSP_BRIDGE_BUSECC_GROUP_7_WIDTH },
10746  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_IK3VTM_N16FFC_WKUP_0_VBUSP_P2P_BRIDGE_IK3VTM_N16FFC_WKUP_0_VBUSP_BRIDGE_BUSECC_GROUP_8_CHECKER_TYPE,
10747  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_IK3VTM_N16FFC_WKUP_0_VBUSP_P2P_BRIDGE_IK3VTM_N16FFC_WKUP_0_VBUSP_BRIDGE_BUSECC_GROUP_8_WIDTH },
10748  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_IK3VTM_N16FFC_WKUP_0_VBUSP_P2P_BRIDGE_IK3VTM_N16FFC_WKUP_0_VBUSP_BRIDGE_BUSECC_GROUP_9_CHECKER_TYPE,
10749  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_IK3VTM_N16FFC_WKUP_0_VBUSP_P2P_BRIDGE_IK3VTM_N16FFC_WKUP_0_VBUSP_BRIDGE_BUSECC_GROUP_9_WIDTH },
10750  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_IK3VTM_N16FFC_WKUP_0_VBUSP_P2P_BRIDGE_IK3VTM_N16FFC_WKUP_0_VBUSP_BRIDGE_BUSECC_GROUP_10_CHECKER_TYPE,
10751  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_IK3VTM_N16FFC_WKUP_0_VBUSP_P2P_BRIDGE_IK3VTM_N16FFC_WKUP_0_VBUSP_BRIDGE_BUSECC_GROUP_10_WIDTH },
10752  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_IK3VTM_N16FFC_WKUP_0_VBUSP_P2P_BRIDGE_IK3VTM_N16FFC_WKUP_0_VBUSP_BRIDGE_BUSECC_GROUP_11_CHECKER_TYPE,
10753  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_IK3VTM_N16FFC_WKUP_0_VBUSP_P2P_BRIDGE_IK3VTM_N16FFC_WKUP_0_VBUSP_BRIDGE_BUSECC_GROUP_11_WIDTH },
10754  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_IK3VTM_N16FFC_WKUP_0_VBUSP_P2P_BRIDGE_IK3VTM_N16FFC_WKUP_0_VBUSP_BRIDGE_BUSECC_GROUP_12_CHECKER_TYPE,
10755  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_IK3VTM_N16FFC_WKUP_0_VBUSP_P2P_BRIDGE_IK3VTM_N16FFC_WKUP_0_VBUSP_BRIDGE_BUSECC_GROUP_12_WIDTH },
10756 };
10757 
10763 static const SDL_GrpChkConfig_t SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISAM67_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM67_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_SRC_BUSECC_groupEntries[SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISAM67_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM67_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS] =
10764 {
10765  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISAM67_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM67_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_SRC_BUSECC_GROUP_0_CHECKER_TYPE,
10766  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISAM67_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM67_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_SRC_BUSECC_GROUP_0_WIDTH },
10767  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISAM67_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM67_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_SRC_BUSECC_GROUP_1_CHECKER_TYPE,
10768  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISAM67_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM67_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_SRC_BUSECC_GROUP_1_WIDTH },
10769  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISAM67_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM67_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_SRC_BUSECC_GROUP_2_CHECKER_TYPE,
10770  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISAM67_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM67_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_SRC_BUSECC_GROUP_2_WIDTH },
10771  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISAM67_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM67_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_SRC_BUSECC_GROUP_3_CHECKER_TYPE,
10772  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISAM67_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM67_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_SRC_BUSECC_GROUP_3_WIDTH },
10773  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISAM67_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM67_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_SRC_BUSECC_GROUP_4_CHECKER_TYPE,
10774  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISAM67_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM67_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_SRC_BUSECC_GROUP_4_WIDTH },
10775  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISAM67_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM67_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_SRC_BUSECC_GROUP_5_CHECKER_TYPE,
10776  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISAM67_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM67_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_SRC_BUSECC_GROUP_5_WIDTH },
10777  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISAM67_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM67_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_SRC_BUSECC_GROUP_6_CHECKER_TYPE,
10778  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISAM67_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM67_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_SRC_BUSECC_GROUP_6_WIDTH },
10779  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISAM67_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM67_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_SRC_BUSECC_GROUP_7_CHECKER_TYPE,
10780  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISAM67_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM67_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_SRC_BUSECC_GROUP_7_WIDTH },
10781  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISAM67_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM67_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_SRC_BUSECC_GROUP_8_CHECKER_TYPE,
10782  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISAM67_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM67_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_SRC_BUSECC_GROUP_8_WIDTH },
10783  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISAM67_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM67_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_SRC_BUSECC_GROUP_9_CHECKER_TYPE,
10784  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISAM67_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM67_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_SRC_BUSECC_GROUP_9_WIDTH },
10785  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISAM67_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM67_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_SRC_BUSECC_GROUP_10_CHECKER_TYPE,
10786  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISAM67_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM67_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_SRC_BUSECC_GROUP_10_WIDTH },
10787  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISAM67_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM67_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_SRC_BUSECC_GROUP_11_CHECKER_TYPE,
10788  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISAM67_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM67_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_SRC_BUSECC_GROUP_11_WIDTH },
10789  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISAM67_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM67_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_SRC_BUSECC_GROUP_12_CHECKER_TYPE,
10790  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISAM67_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM67_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_SRC_BUSECC_GROUP_12_WIDTH },
10791  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISAM67_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM67_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_SRC_BUSECC_GROUP_13_CHECKER_TYPE,
10792  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISAM67_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM67_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_SRC_BUSECC_GROUP_13_WIDTH },
10793  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISAM67_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM67_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_SRC_BUSECC_GROUP_14_CHECKER_TYPE,
10794  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISAM67_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM67_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_SRC_BUSECC_GROUP_14_WIDTH },
10795  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISAM67_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM67_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_SRC_BUSECC_GROUP_15_CHECKER_TYPE,
10796  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISAM67_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM67_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_SRC_BUSECC_GROUP_15_WIDTH },
10797  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISAM67_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM67_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_SRC_BUSECC_GROUP_16_CHECKER_TYPE,
10798  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISAM67_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM67_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_SRC_BUSECC_GROUP_16_WIDTH },
10799 };
10800 
10806 static const SDL_GrpChkConfig_t SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISAM67_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM67_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_DST_BUSECC_groupEntries[SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISAM67_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM67_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS] =
10807 {
10808  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISAM67_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM67_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_DST_BUSECC_GROUP_0_CHECKER_TYPE,
10809  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISAM67_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM67_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_DST_BUSECC_GROUP_0_WIDTH },
10810  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISAM67_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM67_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_DST_BUSECC_GROUP_1_CHECKER_TYPE,
10811  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISAM67_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM67_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_DST_BUSECC_GROUP_1_WIDTH },
10812  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISAM67_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM67_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_DST_BUSECC_GROUP_2_CHECKER_TYPE,
10813  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISAM67_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM67_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_DST_BUSECC_GROUP_2_WIDTH },
10814  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISAM67_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM67_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_DST_BUSECC_GROUP_3_CHECKER_TYPE,
10815  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISAM67_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM67_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_DST_BUSECC_GROUP_3_WIDTH },
10816  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISAM67_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM67_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_DST_BUSECC_GROUP_4_CHECKER_TYPE,
10817  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISAM67_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM67_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_DST_BUSECC_GROUP_4_WIDTH },
10818  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISAM67_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM67_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_DST_BUSECC_GROUP_5_CHECKER_TYPE,
10819  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISAM67_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM67_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_DST_BUSECC_GROUP_5_WIDTH },
10820  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISAM67_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM67_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_DST_BUSECC_GROUP_6_CHECKER_TYPE,
10821  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISAM67_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM67_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_DST_BUSECC_GROUP_6_WIDTH },
10822 };
10823 
10829 static const SDL_GrpChkConfig_t SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS] =
10830 {
10831  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
10832  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
10833  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
10834  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
10835  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
10836  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
10837  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
10838  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
10839  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
10840  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
10841  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_5_CHECKER_TYPE,
10842  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_5_WIDTH },
10843  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_6_CHECKER_TYPE,
10844  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_6_WIDTH },
10845  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_7_CHECKER_TYPE,
10846  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_7_WIDTH },
10847  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_8_CHECKER_TYPE,
10848  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_8_WIDTH },
10849  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_9_CHECKER_TYPE,
10850  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_9_WIDTH },
10851  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_10_CHECKER_TYPE,
10852  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_10_WIDTH },
10853  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_11_CHECKER_TYPE,
10854  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_11_WIDTH },
10855  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_12_CHECKER_TYPE,
10856  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_12_WIDTH },
10857  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_13_CHECKER_TYPE,
10858  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_13_WIDTH },
10859  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_14_CHECKER_TYPE,
10860  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_14_WIDTH },
10861  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_15_CHECKER_TYPE,
10862  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_15_WIDTH },
10863  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_16_CHECKER_TYPE,
10864  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_16_WIDTH },
10865  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_17_CHECKER_TYPE,
10866  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_17_WIDTH },
10867  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_18_CHECKER_TYPE,
10868  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_18_WIDTH },
10869  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_19_CHECKER_TYPE,
10870  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_19_WIDTH },
10871  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_20_CHECKER_TYPE,
10872  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_20_WIDTH },
10873  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_21_CHECKER_TYPE,
10874  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_21_WIDTH },
10875  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_22_CHECKER_TYPE,
10876  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_22_WIDTH },
10877  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_23_CHECKER_TYPE,
10878  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_23_WIDTH },
10879  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_24_CHECKER_TYPE,
10880  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_24_WIDTH },
10881  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_25_CHECKER_TYPE,
10882  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_25_WIDTH },
10883  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_26_CHECKER_TYPE,
10884  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_26_WIDTH },
10885  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_27_CHECKER_TYPE,
10886  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_27_WIDTH },
10887  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_28_CHECKER_TYPE,
10888  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_28_WIDTH },
10889  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_29_CHECKER_TYPE,
10890  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_29_WIDTH },
10891  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_30_CHECKER_TYPE,
10892  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_30_WIDTH },
10893  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_31_CHECKER_TYPE,
10894  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_31_WIDTH },
10895  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_32_CHECKER_TYPE,
10896  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_32_WIDTH },
10897  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_33_CHECKER_TYPE,
10898  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_33_WIDTH },
10899  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_34_CHECKER_TYPE,
10900  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_34_WIDTH },
10901  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_35_CHECKER_TYPE,
10902  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_35_WIDTH },
10903  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_36_CHECKER_TYPE,
10904  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_36_WIDTH },
10905  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_37_CHECKER_TYPE,
10906  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_37_WIDTH },
10907  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_38_CHECKER_TYPE,
10908  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_38_WIDTH },
10909  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_39_CHECKER_TYPE,
10910  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_39_WIDTH },
10911  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_40_CHECKER_TYPE,
10912  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_40_WIDTH },
10913  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_41_CHECKER_TYPE,
10914  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_41_WIDTH },
10915  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_42_CHECKER_TYPE,
10916  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_42_WIDTH },
10917  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_43_CHECKER_TYPE,
10918  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_43_WIDTH },
10919  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_44_CHECKER_TYPE,
10920  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_44_WIDTH },
10921  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_45_CHECKER_TYPE,
10922  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_45_WIDTH },
10923  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_46_CHECKER_TYPE,
10924  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_46_WIDTH },
10925  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_47_CHECKER_TYPE,
10926  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_47_WIDTH },
10927  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_48_CHECKER_TYPE,
10928  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_48_WIDTH },
10929  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_49_CHECKER_TYPE,
10930  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_49_WIDTH },
10931  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_50_CHECKER_TYPE,
10932  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_50_WIDTH },
10933  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_51_CHECKER_TYPE,
10934  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_51_WIDTH },
10935  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_52_CHECKER_TYPE,
10936  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_52_WIDTH },
10937  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_53_CHECKER_TYPE,
10938  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_53_WIDTH },
10939  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_54_CHECKER_TYPE,
10940  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_54_WIDTH },
10941  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_55_CHECKER_TYPE,
10942  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_55_WIDTH },
10943  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_56_CHECKER_TYPE,
10944  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_56_WIDTH },
10945  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_57_CHECKER_TYPE,
10946  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_57_WIDTH },
10947  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_58_CHECKER_TYPE,
10948  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_58_WIDTH },
10949  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_59_CHECKER_TYPE,
10950  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_59_WIDTH },
10951  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_60_CHECKER_TYPE,
10952  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_60_WIDTH },
10953  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_61_CHECKER_TYPE,
10954  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_61_WIDTH },
10955  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_62_CHECKER_TYPE,
10956  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_62_WIDTH },
10957  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_63_CHECKER_TYPE,
10958  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_63_WIDTH },
10959  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_64_CHECKER_TYPE,
10960  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_64_WIDTH },
10961  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_65_CHECKER_TYPE,
10962  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_65_WIDTH },
10963  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_66_CHECKER_TYPE,
10964  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_66_WIDTH },
10965  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_67_CHECKER_TYPE,
10966  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_67_WIDTH },
10967  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_68_CHECKER_TYPE,
10968  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_68_WIDTH },
10969  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_69_CHECKER_TYPE,
10970  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_69_WIDTH },
10971 };
10972 
10978 static const SDL_GrpChkConfig_t SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS] =
10979 {
10980  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
10981  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
10982  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
10983  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
10984  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
10985  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
10986  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
10987  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
10988  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
10989  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
10990  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_5_CHECKER_TYPE,
10991  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_5_WIDTH },
10992  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_6_CHECKER_TYPE,
10993  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_6_WIDTH },
10994  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_7_CHECKER_TYPE,
10995  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_7_WIDTH },
10996  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_8_CHECKER_TYPE,
10997  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_8_WIDTH },
10998  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_9_CHECKER_TYPE,
10999  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_9_WIDTH },
11000  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_10_CHECKER_TYPE,
11001  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_10_WIDTH },
11002  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_11_CHECKER_TYPE,
11003  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_11_WIDTH },
11004  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_12_CHECKER_TYPE,
11005  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_12_WIDTH },
11006  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_13_CHECKER_TYPE,
11007  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_13_WIDTH },
11008  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_14_CHECKER_TYPE,
11009  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_14_WIDTH },
11010  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_15_CHECKER_TYPE,
11011  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_15_WIDTH },
11012  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_16_CHECKER_TYPE,
11013  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_16_WIDTH },
11014  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_17_CHECKER_TYPE,
11015  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_17_WIDTH },
11016  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_18_CHECKER_TYPE,
11017  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_18_WIDTH },
11018  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_19_CHECKER_TYPE,
11019  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_19_WIDTH },
11020  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_20_CHECKER_TYPE,
11021  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_20_WIDTH },
11022  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_21_CHECKER_TYPE,
11023  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_21_WIDTH },
11024  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_22_CHECKER_TYPE,
11025  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_22_WIDTH },
11026  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_23_CHECKER_TYPE,
11027  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_23_WIDTH },
11028  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_24_CHECKER_TYPE,
11029  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_24_WIDTH },
11030  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_25_CHECKER_TYPE,
11031  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_25_WIDTH },
11032  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_26_CHECKER_TYPE,
11033  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_26_WIDTH },
11034  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_27_CHECKER_TYPE,
11035  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_27_WIDTH },
11036  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_28_CHECKER_TYPE,
11037  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_28_WIDTH },
11038  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_29_CHECKER_TYPE,
11039  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_29_WIDTH },
11040  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_30_CHECKER_TYPE,
11041  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_30_WIDTH },
11042  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_31_CHECKER_TYPE,
11043  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_31_WIDTH },
11044  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_32_CHECKER_TYPE,
11045  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_32_WIDTH },
11046  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_33_CHECKER_TYPE,
11047  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_33_WIDTH },
11048  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_34_CHECKER_TYPE,
11049  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_34_WIDTH },
11050  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_35_CHECKER_TYPE,
11051  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_35_WIDTH },
11052  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_36_CHECKER_TYPE,
11053  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_36_WIDTH },
11054  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_37_CHECKER_TYPE,
11055  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_37_WIDTH },
11056  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_38_CHECKER_TYPE,
11057  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_38_WIDTH },
11058  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_39_CHECKER_TYPE,
11059  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_39_WIDTH },
11060  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_40_CHECKER_TYPE,
11061  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_40_WIDTH },
11062  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_41_CHECKER_TYPE,
11063  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_41_WIDTH },
11064  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_42_CHECKER_TYPE,
11065  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_42_WIDTH },
11066  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_43_CHECKER_TYPE,
11067  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_43_WIDTH },
11068  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_44_CHECKER_TYPE,
11069  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_44_WIDTH },
11070  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_45_CHECKER_TYPE,
11071  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_45_WIDTH },
11072  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_46_CHECKER_TYPE,
11073  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_46_WIDTH },
11074  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_47_CHECKER_TYPE,
11075  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_47_WIDTH },
11076  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_48_CHECKER_TYPE,
11077  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_48_WIDTH },
11078  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_49_CHECKER_TYPE,
11079  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_49_WIDTH },
11080  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_50_CHECKER_TYPE,
11081  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_50_WIDTH },
11082  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_51_CHECKER_TYPE,
11083  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_51_WIDTH },
11084  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_52_CHECKER_TYPE,
11085  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_52_WIDTH },
11086  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_53_CHECKER_TYPE,
11087  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_53_WIDTH },
11088  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_54_CHECKER_TYPE,
11089  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_54_WIDTH },
11090  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_55_CHECKER_TYPE,
11091  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_55_WIDTH },
11092  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_56_CHECKER_TYPE,
11093  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_56_WIDTH },
11094  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_57_CHECKER_TYPE,
11095  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_57_WIDTH },
11096  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_58_CHECKER_TYPE,
11097  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_58_WIDTH },
11098  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_59_CHECKER_TYPE,
11099  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_59_WIDTH },
11100  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_60_CHECKER_TYPE,
11101  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_60_WIDTH },
11102  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_61_CHECKER_TYPE,
11103  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_61_WIDTH },
11104  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_62_CHECKER_TYPE,
11105  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_62_WIDTH },
11106  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_63_CHECKER_TYPE,
11107  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_63_WIDTH },
11108  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_64_CHECKER_TYPE,
11109  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_64_WIDTH },
11110  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_65_CHECKER_TYPE,
11111  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_65_WIDTH },
11112  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_66_CHECKER_TYPE,
11113  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_66_WIDTH },
11114  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_67_CHECKER_TYPE,
11115  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_67_WIDTH },
11116 };
11117 
11123 static const SDL_GrpChkConfig_t SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_groupEntries[SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_MAX_NUM_CHECKERS] =
11124 {
11125  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_0_CHECKER_TYPE,
11126  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_0_WIDTH },
11127  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_1_CHECKER_TYPE,
11128  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_1_WIDTH },
11129  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_2_CHECKER_TYPE,
11130  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_2_WIDTH },
11131  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_3_CHECKER_TYPE,
11132  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_3_WIDTH },
11133  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_4_CHECKER_TYPE,
11134  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_4_WIDTH },
11135  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_5_CHECKER_TYPE,
11136  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_5_WIDTH },
11137  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_6_CHECKER_TYPE,
11138  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_6_WIDTH },
11139  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_7_CHECKER_TYPE,
11140  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_7_WIDTH },
11141  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_8_CHECKER_TYPE,
11142  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_8_WIDTH },
11143  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_9_CHECKER_TYPE,
11144  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_9_WIDTH },
11145  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_10_CHECKER_TYPE,
11146  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_10_WIDTH },
11147  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_11_CHECKER_TYPE,
11148  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_11_WIDTH },
11149  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_12_CHECKER_TYPE,
11150  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_12_WIDTH },
11151  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_13_CHECKER_TYPE,
11152  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_13_WIDTH },
11153  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_14_CHECKER_TYPE,
11154  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_14_WIDTH },
11155  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_15_CHECKER_TYPE,
11156  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_15_WIDTH },
11157  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_16_CHECKER_TYPE,
11158  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_16_WIDTH },
11159  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_17_CHECKER_TYPE,
11160  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_17_WIDTH },
11161  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_18_CHECKER_TYPE,
11162  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_18_WIDTH },
11163  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_19_CHECKER_TYPE,
11164  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_19_WIDTH },
11165  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_20_CHECKER_TYPE,
11166  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_20_WIDTH },
11167  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_21_CHECKER_TYPE,
11168  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_21_WIDTH },
11169  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_22_CHECKER_TYPE,
11170  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_22_WIDTH },
11171  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_23_CHECKER_TYPE,
11172  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_23_WIDTH },
11173  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_24_CHECKER_TYPE,
11174  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_24_WIDTH },
11175  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_25_CHECKER_TYPE,
11176  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_25_WIDTH },
11177  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_26_CHECKER_TYPE,
11178  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_26_WIDTH },
11179  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_27_CHECKER_TYPE,
11180  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_27_WIDTH },
11181  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_28_CHECKER_TYPE,
11182  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_28_WIDTH },
11183  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_29_CHECKER_TYPE,
11184  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_29_WIDTH },
11185  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_30_CHECKER_TYPE,
11186  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_30_WIDTH },
11187  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_31_CHECKER_TYPE,
11188  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_31_WIDTH },
11189  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_32_CHECKER_TYPE,
11190  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_32_WIDTH },
11191  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_33_CHECKER_TYPE,
11192  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_33_WIDTH },
11193  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_34_CHECKER_TYPE,
11194  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_34_WIDTH },
11195  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_35_CHECKER_TYPE,
11196  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_35_WIDTH },
11197  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_36_CHECKER_TYPE,
11198  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_36_WIDTH },
11199  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_37_CHECKER_TYPE,
11200  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_37_WIDTH },
11201  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_38_CHECKER_TYPE,
11202  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_38_WIDTH },
11203  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_39_CHECKER_TYPE,
11204  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_39_WIDTH },
11205  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_40_CHECKER_TYPE,
11206  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_40_WIDTH },
11207  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_41_CHECKER_TYPE,
11208  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_41_WIDTH },
11209  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_42_CHECKER_TYPE,
11210  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_42_WIDTH },
11211  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_43_CHECKER_TYPE,
11212  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_43_WIDTH },
11213  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_44_CHECKER_TYPE,
11214  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_44_WIDTH },
11215  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_45_CHECKER_TYPE,
11216  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_45_WIDTH },
11217  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_46_CHECKER_TYPE,
11218  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_46_WIDTH },
11219  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_47_CHECKER_TYPE,
11220  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_47_WIDTH },
11221  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_48_CHECKER_TYPE,
11222  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_48_WIDTH },
11223  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_49_CHECKER_TYPE,
11224  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_49_WIDTH },
11225  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_50_CHECKER_TYPE,
11226  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_50_WIDTH },
11227  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_51_CHECKER_TYPE,
11228  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_51_WIDTH },
11229  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_52_CHECKER_TYPE,
11230  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_52_WIDTH },
11231  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_53_CHECKER_TYPE,
11232  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_53_WIDTH },
11233  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_54_CHECKER_TYPE,
11234  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_54_WIDTH },
11235  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_55_CHECKER_TYPE,
11236  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_55_WIDTH },
11237  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_56_CHECKER_TYPE,
11238  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_56_WIDTH },
11239  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_57_CHECKER_TYPE,
11240  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_57_WIDTH },
11241  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_58_CHECKER_TYPE,
11242  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_58_WIDTH },
11243  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_59_CHECKER_TYPE,
11244  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_59_WIDTH },
11245  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_60_CHECKER_TYPE,
11246  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_60_WIDTH },
11247  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_61_CHECKER_TYPE,
11248  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_61_WIDTH },
11249  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_62_CHECKER_TYPE,
11250  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_62_WIDTH },
11251  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_63_CHECKER_TYPE,
11252  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_63_WIDTH },
11253  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_64_CHECKER_TYPE,
11254  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_64_WIDTH },
11255  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_65_CHECKER_TYPE,
11256  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_65_WIDTH },
11257  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_66_CHECKER_TYPE,
11258  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_66_WIDTH },
11259  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_67_CHECKER_TYPE,
11260  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_67_WIDTH },
11261  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_68_CHECKER_TYPE,
11262  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_68_WIDTH },
11263  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_69_CHECKER_TYPE,
11264  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_69_WIDTH },
11265  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_70_CHECKER_TYPE,
11266  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_70_WIDTH },
11267  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_71_CHECKER_TYPE,
11268  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_71_WIDTH },
11269  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_72_CHECKER_TYPE,
11270  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_72_WIDTH },
11271  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_73_CHECKER_TYPE,
11272  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_73_WIDTH },
11273  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_74_CHECKER_TYPE,
11274  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_74_WIDTH },
11275  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_75_CHECKER_TYPE,
11276  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_75_WIDTH },
11277  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_76_CHECKER_TYPE,
11278  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_76_WIDTH },
11279  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_77_CHECKER_TYPE,
11280  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_77_WIDTH },
11281 };
11282 
11288 static const SDL_GrpChkConfig_t SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_groupEntries[SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_MAX_NUM_CHECKERS] =
11289 {
11290  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_0_CHECKER_TYPE,
11291  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_0_WIDTH },
11292  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_1_CHECKER_TYPE,
11293  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_1_WIDTH },
11294  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_2_CHECKER_TYPE,
11295  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_2_WIDTH },
11296  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_3_CHECKER_TYPE,
11297  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_3_WIDTH },
11298  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_4_CHECKER_TYPE,
11299  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_4_WIDTH },
11300  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_5_CHECKER_TYPE,
11301  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_5_WIDTH },
11302  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_6_CHECKER_TYPE,
11303  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_6_WIDTH },
11304  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_7_CHECKER_TYPE,
11305  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_7_WIDTH },
11306  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_8_CHECKER_TYPE,
11307  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_8_WIDTH },
11308  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_9_CHECKER_TYPE,
11309  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_9_WIDTH },
11310  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_10_CHECKER_TYPE,
11311  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_10_WIDTH },
11312  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_11_CHECKER_TYPE,
11313  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_11_WIDTH },
11314  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_12_CHECKER_TYPE,
11315  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_12_WIDTH },
11316  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_13_CHECKER_TYPE,
11317  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_13_WIDTH },
11318  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_14_CHECKER_TYPE,
11319  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_14_WIDTH },
11320  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_15_CHECKER_TYPE,
11321  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_15_WIDTH },
11322  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_16_CHECKER_TYPE,
11323  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_16_WIDTH },
11324  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_17_CHECKER_TYPE,
11325  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_17_WIDTH },
11326  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_18_CHECKER_TYPE,
11327  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_18_WIDTH },
11328  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_19_CHECKER_TYPE,
11329  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_19_WIDTH },
11330  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_20_CHECKER_TYPE,
11331  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_20_WIDTH },
11332  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_21_CHECKER_TYPE,
11333  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_21_WIDTH },
11334  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_22_CHECKER_TYPE,
11335  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_22_WIDTH },
11336  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_23_CHECKER_TYPE,
11337  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_23_WIDTH },
11338  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_24_CHECKER_TYPE,
11339  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_24_WIDTH },
11340  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_25_CHECKER_TYPE,
11341  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_25_WIDTH },
11342  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_26_CHECKER_TYPE,
11343  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_26_WIDTH },
11344  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_27_CHECKER_TYPE,
11345  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_27_WIDTH },
11346  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_28_CHECKER_TYPE,
11347  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_28_WIDTH },
11348  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_29_CHECKER_TYPE,
11349  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_29_WIDTH },
11350  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_30_CHECKER_TYPE,
11351  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_30_WIDTH },
11352  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_31_CHECKER_TYPE,
11353  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_31_WIDTH },
11354  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_32_CHECKER_TYPE,
11355  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_32_WIDTH },
11356 };
11357 
11363 static const SDL_GrpChkConfig_t SDL_WKUP_ECC_AGGR0_SAM67_DM_DM_ECC_AGGR_EDC_CTRL_groupEntries[SDL_WKUP_ECC_AGGR0_SAM67_DM_DM_ECC_AGGR_EDC_CTRL_MAX_NUM_CHECKERS] =
11364 {
11365  { SDL_WKUP_ECC_AGGR0_SAM67_DM_DM_ECC_AGGR_EDC_CTRL_GROUP_0_CHECKER_TYPE,
11366  SDL_WKUP_ECC_AGGR0_SAM67_DM_DM_ECC_AGGR_EDC_CTRL_GROUP_0_WIDTH },
11367  { SDL_WKUP_ECC_AGGR0_SAM67_DM_DM_ECC_AGGR_EDC_CTRL_GROUP_1_CHECKER_TYPE,
11368  SDL_WKUP_ECC_AGGR0_SAM67_DM_DM_ECC_AGGR_EDC_CTRL_GROUP_1_WIDTH },
11369  { SDL_WKUP_ECC_AGGR0_SAM67_DM_DM_ECC_AGGR_EDC_CTRL_GROUP_2_CHECKER_TYPE,
11370  SDL_WKUP_ECC_AGGR0_SAM67_DM_DM_ECC_AGGR_EDC_CTRL_GROUP_2_WIDTH },
11371  { SDL_WKUP_ECC_AGGR0_SAM67_DM_DM_ECC_AGGR_EDC_CTRL_GROUP_3_CHECKER_TYPE,
11372  SDL_WKUP_ECC_AGGR0_SAM67_DM_DM_ECC_AGGR_EDC_CTRL_GROUP_3_WIDTH },
11373  { SDL_WKUP_ECC_AGGR0_SAM67_DM_DM_ECC_AGGR_EDC_CTRL_GROUP_4_CHECKER_TYPE,
11374  SDL_WKUP_ECC_AGGR0_SAM67_DM_DM_ECC_AGGR_EDC_CTRL_GROUP_4_WIDTH },
11375  { SDL_WKUP_ECC_AGGR0_SAM67_DM_DM_ECC_AGGR_EDC_CTRL_GROUP_5_CHECKER_TYPE,
11376  SDL_WKUP_ECC_AGGR0_SAM67_DM_DM_ECC_AGGR_EDC_CTRL_GROUP_5_WIDTH },
11377 };
11378 
11383 static const SDL_MemConfig_t SDL_DMASS0_ECC_AGGR_0_MemEntries[SDL_DMASS0_ECC_AGGR_0_RAM_IDS_TOTAL_ENTRIES] =
11384 {
11385  { SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_PKTDMA_CFG_CONFIG_RAM_ID, 0u,
11386  SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_PKTDMA_CFG_CONFIG_RAM_SIZE, 4u,
11387  SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_PKTDMA_CFG_CONFIG_ROW_WIDTH, ((bool)false) },
11388  { SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_PKTDMA_CFG_STATE_RAM_ID, 0u,
11389  SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_PKTDMA_CFG_STATE_RAM_SIZE, 4u,
11390  SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_PKTDMA_CFG_STATE_ROW_WIDTH, ((bool)false) },
11391  { SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_PKTDMA_TPCFIFO_F0_RAM_ID, 0u,
11392  SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_PKTDMA_TPCFIFO_F0_RAM_SIZE, 4u,
11393  SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_PKTDMA_TPCFIFO_F0_ROW_WIDTH, ((bool)false) },
11394  { SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_PKTDMA_TPCFIFO_F1_RAM_ID, 0u,
11395  SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_PKTDMA_TPCFIFO_F1_RAM_SIZE, 4u,
11396  SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_PKTDMA_TPCFIFO_F1_ROW_WIDTH, ((bool)false) },
11397  { SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_PKTDMA_RPCFIFO_F0_RAM_ID, 0u,
11398  SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_PKTDMA_RPCFIFO_F0_RAM_SIZE, 4u,
11399  SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_PKTDMA_RPCFIFO_F0_ROW_WIDTH, ((bool)false) },
11400  { SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_PKTDMA_RPCFIFO_F1_RAM_ID, 0u,
11401  SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_PKTDMA_RPCFIFO_F1_RAM_SIZE, 4u,
11402  SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_PKTDMA_RPCFIFO_F1_ROW_WIDTH, ((bool)false) },
11403  { SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_PKTDMA_RPCFIFO_WC_RAM_ID, 0u,
11404  SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_PKTDMA_RPCFIFO_WC_RAM_SIZE, 4u,
11405  SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_PKTDMA_RPCFIFO_WC_ROW_WIDTH, ((bool)false) },
11406  { SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_PKTDMA_STATS_STST0_RAM_ID, 0u,
11407  SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_PKTDMA_STATS_STST0_RAM_SIZE, 4u,
11408  SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_PKTDMA_STATS_STST0_ROW_WIDTH, ((bool)false) },
11409  { SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_PKTDMA_STATS_STSR0_RAM_ID, 0u,
11410  SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_PKTDMA_STATS_STSR0_RAM_SIZE, 4u,
11411  SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_PKTDMA_STATS_STSR0_ROW_WIDTH, ((bool)false) },
11412  { SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_PKTDMA_RINGOCC_CNTR_RAM_ID, 0u,
11413  SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_PKTDMA_RINGOCC_CNTR_RAM_SIZE, 4u,
11414  SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_PKTDMA_RINGOCC_CNTR_ROW_WIDTH, ((bool)false) },
11415  { SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_BCDMA_CFG_CONFIG_RAM_ID, 0u,
11416  SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_BCDMA_CFG_CONFIG_RAM_SIZE, 4u,
11417  SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_BCDMA_CFG_CONFIG_ROW_WIDTH, ((bool)false) },
11418  { SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_BCDMA_CFG_STATE_RAM_ID, 0u,
11419  SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_BCDMA_CFG_STATE_RAM_SIZE, 4u,
11420  SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_BCDMA_CFG_STATE_ROW_WIDTH, ((bool)false) },
11421  { SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_BCDMA_PCFIFO_DFIFO_F0_RAM_ID, 0u,
11422  SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_BCDMA_PCFIFO_DFIFO_F0_RAM_SIZE, 4u,
11423  SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_BCDMA_PCFIFO_DFIFO_F0_ROW_WIDTH, ((bool)false) },
11424  { SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_BCDMA_PCFIFO_DFIFO_F1_RAM_ID, 0u,
11425  SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_BCDMA_PCFIFO_DFIFO_F1_RAM_SIZE, 4u,
11426  SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_BCDMA_PCFIFO_DFIFO_F1_ROW_WIDTH, ((bool)false) },
11427  { SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_BCDMA_TPCFIFO_F0_RAM_ID, 0u,
11428  SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_BCDMA_TPCFIFO_F0_RAM_SIZE, 4u,
11429  SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_BCDMA_TPCFIFO_F0_ROW_WIDTH, ((bool)false) },
11430  { SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_BCDMA_TPCFIFO_F1_RAM_ID, 0u,
11431  SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_BCDMA_TPCFIFO_F1_RAM_SIZE, 4u,
11432  SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_BCDMA_TPCFIFO_F1_ROW_WIDTH, ((bool)false) },
11433  { SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_BCDMA_RPCFIFO_F0_RAM_ID, 0u,
11434  SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_BCDMA_RPCFIFO_F0_RAM_SIZE, 4u,
11435  SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_BCDMA_RPCFIFO_F0_ROW_WIDTH, ((bool)false) },
11436  { SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_BCDMA_RPCFIFO_F1_RAM_ID, 0u,
11437  SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_BCDMA_RPCFIFO_F1_RAM_SIZE, 4u,
11438  SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_BCDMA_RPCFIFO_F1_ROW_WIDTH, ((bool)false) },
11439  { SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_BCDMA_RPCFIFO_WC_RAM_ID, 0u,
11440  SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_BCDMA_RPCFIFO_WC_RAM_SIZE, 4u,
11441  SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_BCDMA_RPCFIFO_WC_ROW_WIDTH, ((bool)false) },
11442  { SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_BCDMA_STATS_STST0_RAM_ID, 0u,
11443  SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_BCDMA_STATS_STST0_RAM_SIZE, 4u,
11444  SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_BCDMA_STATS_STST0_ROW_WIDTH, ((bool)false) },
11445  { SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_BCDMA_STATS_STSR0_RAM_ID, 0u,
11446  SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_BCDMA_STATS_STSR0_RAM_SIZE, 4u,
11447  SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_BCDMA_STATS_STSR0_ROW_WIDTH, ((bool)false) },
11448  { SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_BCDMA_RINGOCC_CNTR_RAM_ID, 0u,
11449  SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_BCDMA_RINGOCC_CNTR_RAM_SIZE, 4u,
11450  SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_BCDMA_RINGOCC_CNTR_ROW_WIDTH, ((bool)false) },
11451  { SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_INTAGGR_STATREG_SR_SPRAM_184X128_SWW_SR_RAM_ID, 0u,
11452  SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_INTAGGR_STATREG_SR_SPRAM_184X128_SWW_SR_RAM_SIZE, 4u,
11453  SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_INTAGGR_STATREG_SR_SPRAM_184X128_SWW_SR_ROW_WIDTH, ((bool)false) },
11454  { SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_INTAGGR_COMMON_IM_TPRAM_1531X34_SWW_SR_RAM_ID, 0u,
11455  SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_INTAGGR_COMMON_IM_TPRAM_1531X34_SWW_SR_RAM_SIZE, 4u,
11456  SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_INTAGGR_COMMON_IM_TPRAM_1531X34_SWW_SR_ROW_WIDTH, ((bool)false) },
11457  { SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_IPCSS_RINGACC_STRAM_RAM_ID, 0u,
11458  SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_IPCSS_RINGACC_STRAM_RAM_SIZE, 4u,
11459  SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_IPCSS_RINGACC_STRAM_ROW_WIDTH, ((bool)false) },
11460  { SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_IPCSS_SEC_PROXY_BUF_STRAM_RAM_ID, 0u,
11461  SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_IPCSS_SEC_PROXY_BUF_STRAM_RAM_SIZE, 4u,
11462  SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_IPCSS_SEC_PROXY_BUF_STRAM_ROW_WIDTH, ((bool)false) },
11463  { SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_IPCSS_SEC_PROXY_BUF_BUFRAM_RAM_ID, 0u,
11464  SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_IPCSS_SEC_PROXY_BUF_BUFRAM_RAM_SIZE, 4u,
11465  SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_IPCSS_SEC_PROXY_BUF_BUFRAM_ROW_WIDTH, ((bool)false) },
11466  { SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_IPCSS_MSRAM_ECC0_RAM_ID, 0u,
11467  SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_IPCSS_MSRAM_ECC0_RAM_SIZE, 4u,
11468  SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_IPCSS_MSRAM_ECC0_ROW_WIDTH, ((bool)false) },
11469 };
11470 
11475 static const SDL_MemConfig_t SDL_PDMA0_SAM67_PDMA_SPI_ECCAGGR_MemEntries[SDL_PDMA0_SAM67_PDMA_SPI_ECCAGGR_RAM_IDS_TOTAL_ENTRIES] =
11476 {
11477  { SDL_PDMA0_SAM67_PDMA_SPI_ECCAGGR_SAM67_PDMA_SPI_PDMA_CORE_TF0_F0_TPRAM_72X128_SBW_SR_RAM_ID, 0u,
11478  SDL_PDMA0_SAM67_PDMA_SPI_ECCAGGR_SAM67_PDMA_SPI_PDMA_CORE_TF0_F0_TPRAM_72X128_SBW_SR_RAM_SIZE, 4u,
11479  SDL_PDMA0_SAM67_PDMA_SPI_ECCAGGR_SAM67_PDMA_SPI_PDMA_CORE_TF0_F0_TPRAM_72X128_SBW_SR_ROW_WIDTH, ((bool)false) },
11480  { SDL_PDMA0_SAM67_PDMA_SPI_ECCAGGR_SAM67_PDMA_SPI_PDMA_CORE_TF0_F1_TPRAM_72X128_SBW_SR_RAM_ID, 0u,
11481  SDL_PDMA0_SAM67_PDMA_SPI_ECCAGGR_SAM67_PDMA_SPI_PDMA_CORE_TF0_F1_TPRAM_72X128_SBW_SR_RAM_SIZE, 4u,
11482  SDL_PDMA0_SAM67_PDMA_SPI_ECCAGGR_SAM67_PDMA_SPI_PDMA_CORE_TF0_F1_TPRAM_72X128_SBW_SR_ROW_WIDTH, ((bool)false) },
11483  { SDL_PDMA0_SAM67_PDMA_SPI_ECCAGGR_SAM67_PDMA_SPI_PDMA_CORE_RF0_F0_TPRAM_72X144_SBW_SR_RAM_ID, 0u,
11484  SDL_PDMA0_SAM67_PDMA_SPI_ECCAGGR_SAM67_PDMA_SPI_PDMA_CORE_RF0_F0_TPRAM_72X144_SBW_SR_RAM_SIZE, 4u,
11485  SDL_PDMA0_SAM67_PDMA_SPI_ECCAGGR_SAM67_PDMA_SPI_PDMA_CORE_RF0_F0_TPRAM_72X144_SBW_SR_ROW_WIDTH, ((bool)false) },
11486  { SDL_PDMA0_SAM67_PDMA_SPI_ECCAGGR_SAM67_PDMA_SPI_PDMA_CORE_RF0_F1_TPRAM_72X144_SBW_SR_RAM_ID, 0u,
11487  SDL_PDMA0_SAM67_PDMA_SPI_ECCAGGR_SAM67_PDMA_SPI_PDMA_CORE_RF0_F1_TPRAM_72X144_SBW_SR_RAM_SIZE, 4u,
11488  SDL_PDMA0_SAM67_PDMA_SPI_ECCAGGR_SAM67_PDMA_SPI_PDMA_CORE_RF0_F1_TPRAM_72X144_SBW_SR_ROW_WIDTH, ((bool)false) },
11489 };
11490 
11496 static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_groupEntries[SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_MAX_NUM_CHECKERS] =
11497 {
11498  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_0_CHECKER_TYPE,
11499  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_0_WIDTH },
11500  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_1_CHECKER_TYPE,
11501  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_1_WIDTH },
11502  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_2_CHECKER_TYPE,
11503  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_2_WIDTH },
11504  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_3_CHECKER_TYPE,
11505  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_3_WIDTH },
11506  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_4_CHECKER_TYPE,
11507  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_4_WIDTH },
11508  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_5_CHECKER_TYPE,
11509  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_5_WIDTH },
11510  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_6_CHECKER_TYPE,
11511  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_6_WIDTH },
11512  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_7_CHECKER_TYPE,
11513  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_7_WIDTH },
11514  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_8_CHECKER_TYPE,
11515  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_8_WIDTH },
11516  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_9_CHECKER_TYPE,
11517  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_9_WIDTH },
11518  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_10_CHECKER_TYPE,
11519  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_10_WIDTH },
11520  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_11_CHECKER_TYPE,
11521  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_11_WIDTH },
11522  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_12_CHECKER_TYPE,
11523  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_12_WIDTH },
11524  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_13_CHECKER_TYPE,
11525  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_13_WIDTH },
11526  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_14_CHECKER_TYPE,
11527  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_14_WIDTH },
11528  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_15_CHECKER_TYPE,
11529  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_15_WIDTH },
11530  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_16_CHECKER_TYPE,
11531  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_16_WIDTH },
11532  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_17_CHECKER_TYPE,
11533  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_17_WIDTH },
11534  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_18_CHECKER_TYPE,
11535  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_18_WIDTH },
11536  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_19_CHECKER_TYPE,
11537  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_19_WIDTH },
11538  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_20_CHECKER_TYPE,
11539  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_20_WIDTH },
11540  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_21_CHECKER_TYPE,
11541  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_21_WIDTH },
11542  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_22_CHECKER_TYPE,
11543  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_22_WIDTH },
11544  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_23_CHECKER_TYPE,
11545  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_23_WIDTH },
11546  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_24_CHECKER_TYPE,
11547  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_24_WIDTH },
11548  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_25_CHECKER_TYPE,
11549  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_25_WIDTH },
11550  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_26_CHECKER_TYPE,
11551  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_26_WIDTH },
11552  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_27_CHECKER_TYPE,
11553  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_27_WIDTH },
11554  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_28_CHECKER_TYPE,
11555  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_28_WIDTH },
11556  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_29_CHECKER_TYPE,
11557  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_29_WIDTH },
11558  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_30_CHECKER_TYPE,
11559  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_30_WIDTH },
11560  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_31_CHECKER_TYPE,
11561  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_31_WIDTH },
11562  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_32_CHECKER_TYPE,
11563  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_32_WIDTH },
11564  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_33_CHECKER_TYPE,
11565  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_33_WIDTH },
11566  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_34_CHECKER_TYPE,
11567  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_34_WIDTH },
11568  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_35_CHECKER_TYPE,
11569  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_35_WIDTH },
11570  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_36_CHECKER_TYPE,
11571  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_36_WIDTH },
11572  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_37_CHECKER_TYPE,
11573  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_37_WIDTH },
11574  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_38_CHECKER_TYPE,
11575  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_38_WIDTH },
11576  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_39_CHECKER_TYPE,
11577  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_39_WIDTH },
11578  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_40_CHECKER_TYPE,
11579  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_40_WIDTH },
11580  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_41_CHECKER_TYPE,
11581  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_41_WIDTH },
11582  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_42_CHECKER_TYPE,
11583  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_42_WIDTH },
11584  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_43_CHECKER_TYPE,
11585  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_43_WIDTH },
11586  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_44_CHECKER_TYPE,
11587  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_44_WIDTH },
11588  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_45_CHECKER_TYPE,
11589  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_45_WIDTH },
11590  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_46_CHECKER_TYPE,
11591  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_46_WIDTH },
11592  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_47_CHECKER_TYPE,
11593  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_47_WIDTH },
11594  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_48_CHECKER_TYPE,
11595  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_48_WIDTH },
11596  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_49_CHECKER_TYPE,
11597  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_49_WIDTH },
11598  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_50_CHECKER_TYPE,
11599  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_50_WIDTH },
11600  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_51_CHECKER_TYPE,
11601  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_51_WIDTH },
11602  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_52_CHECKER_TYPE,
11603  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_52_WIDTH },
11604  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_53_CHECKER_TYPE,
11605  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_53_WIDTH },
11606  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_54_CHECKER_TYPE,
11607  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_54_WIDTH },
11608  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_55_CHECKER_TYPE,
11609  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_55_WIDTH },
11610  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_56_CHECKER_TYPE,
11611  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_56_WIDTH },
11612  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_57_CHECKER_TYPE,
11613  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_57_WIDTH },
11614  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_58_CHECKER_TYPE,
11615  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_58_WIDTH },
11616  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_59_CHECKER_TYPE,
11617  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_59_WIDTH },
11618  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_60_CHECKER_TYPE,
11619  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_60_WIDTH },
11620  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_61_CHECKER_TYPE,
11621  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_61_WIDTH },
11622  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_62_CHECKER_TYPE,
11623  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_62_WIDTH },
11624  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_63_CHECKER_TYPE,
11625  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_63_WIDTH },
11626  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_64_CHECKER_TYPE,
11627  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_64_WIDTH },
11628  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_65_CHECKER_TYPE,
11629  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_65_WIDTH },
11630  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_66_CHECKER_TYPE,
11631  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_66_WIDTH },
11632  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_67_CHECKER_TYPE,
11633  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_67_WIDTH },
11634  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_68_CHECKER_TYPE,
11635  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_68_WIDTH },
11636 };
11637 
11643 static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_groupEntries[SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_MAX_NUM_CHECKERS] =
11644 {
11645  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_0_CHECKER_TYPE,
11646  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_0_WIDTH },
11647  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_1_CHECKER_TYPE,
11648  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_1_WIDTH },
11649  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_2_CHECKER_TYPE,
11650  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_2_WIDTH },
11651  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_3_CHECKER_TYPE,
11652  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_3_WIDTH },
11653  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_4_CHECKER_TYPE,
11654  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_4_WIDTH },
11655  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_5_CHECKER_TYPE,
11656  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_5_WIDTH },
11657  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_6_CHECKER_TYPE,
11658  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_6_WIDTH },
11659  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_7_CHECKER_TYPE,
11660  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_7_WIDTH },
11661  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_8_CHECKER_TYPE,
11662  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_8_WIDTH },
11663  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_9_CHECKER_TYPE,
11664  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_9_WIDTH },
11665  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_10_CHECKER_TYPE,
11666  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_10_WIDTH },
11667  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_11_CHECKER_TYPE,
11668  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_11_WIDTH },
11669  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_12_CHECKER_TYPE,
11670  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_12_WIDTH },
11671  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_13_CHECKER_TYPE,
11672  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_13_WIDTH },
11673  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_14_CHECKER_TYPE,
11674  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_14_WIDTH },
11675  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_15_CHECKER_TYPE,
11676  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_15_WIDTH },
11677  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_16_CHECKER_TYPE,
11678  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_16_WIDTH },
11679  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_17_CHECKER_TYPE,
11680  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_17_WIDTH },
11681  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_18_CHECKER_TYPE,
11682  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_18_WIDTH },
11683  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_19_CHECKER_TYPE,
11684  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_19_WIDTH },
11685  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_20_CHECKER_TYPE,
11686  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_20_WIDTH },
11687  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_21_CHECKER_TYPE,
11688  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_21_WIDTH },
11689  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_22_CHECKER_TYPE,
11690  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_22_WIDTH },
11691  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_23_CHECKER_TYPE,
11692  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_23_WIDTH },
11693  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_24_CHECKER_TYPE,
11694  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_24_WIDTH },
11695  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_25_CHECKER_TYPE,
11696  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_25_WIDTH },
11697  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_26_CHECKER_TYPE,
11698  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_26_WIDTH },
11699  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_27_CHECKER_TYPE,
11700  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_27_WIDTH },
11701  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_28_CHECKER_TYPE,
11702  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_28_WIDTH },
11703  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_29_CHECKER_TYPE,
11704  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_29_WIDTH },
11705  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_30_CHECKER_TYPE,
11706  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_30_WIDTH },
11707  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_31_CHECKER_TYPE,
11708  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_31_WIDTH },
11709  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_32_CHECKER_TYPE,
11710  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_32_WIDTH },
11711  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_33_CHECKER_TYPE,
11712  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_33_WIDTH },
11713  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_34_CHECKER_TYPE,
11714  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_34_WIDTH },
11715  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_35_CHECKER_TYPE,
11716  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_35_WIDTH },
11717  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_36_CHECKER_TYPE,
11718  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_36_WIDTH },
11719  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_37_CHECKER_TYPE,
11720  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_37_WIDTH },
11721  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_38_CHECKER_TYPE,
11722  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_38_WIDTH },
11723  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_39_CHECKER_TYPE,
11724  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_39_WIDTH },
11725  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_40_CHECKER_TYPE,
11726  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_40_WIDTH },
11727  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_41_CHECKER_TYPE,
11728  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_41_WIDTH },
11729  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_42_CHECKER_TYPE,
11730  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_42_WIDTH },
11731  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_43_CHECKER_TYPE,
11732  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_43_WIDTH },
11733  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_44_CHECKER_TYPE,
11734  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_44_WIDTH },
11735  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_45_CHECKER_TYPE,
11736  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_45_WIDTH },
11737  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_46_CHECKER_TYPE,
11738  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_46_WIDTH },
11739  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_47_CHECKER_TYPE,
11740  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_47_WIDTH },
11741  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_48_CHECKER_TYPE,
11742  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_48_WIDTH },
11743  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_49_CHECKER_TYPE,
11744  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_49_WIDTH },
11745  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_50_CHECKER_TYPE,
11746  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_50_WIDTH },
11747  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_51_CHECKER_TYPE,
11748  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_51_WIDTH },
11749  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_52_CHECKER_TYPE,
11750  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_52_WIDTH },
11751  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_53_CHECKER_TYPE,
11752  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_53_WIDTH },
11753  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_54_CHECKER_TYPE,
11754  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_54_WIDTH },
11755  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_55_CHECKER_TYPE,
11756  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_55_WIDTH },
11757  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_56_CHECKER_TYPE,
11758  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_56_WIDTH },
11759  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_57_CHECKER_TYPE,
11760  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_57_WIDTH },
11761  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_58_CHECKER_TYPE,
11762  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_58_WIDTH },
11763  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_59_CHECKER_TYPE,
11764  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_59_WIDTH },
11765  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_60_CHECKER_TYPE,
11766  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_60_WIDTH },
11767  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_61_CHECKER_TYPE,
11768  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_61_WIDTH },
11769  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_62_CHECKER_TYPE,
11770  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_62_WIDTH },
11771  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_63_CHECKER_TYPE,
11772  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_63_WIDTH },
11773  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_64_CHECKER_TYPE,
11774  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_64_WIDTH },
11775 };
11776 
11782 static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_groupEntries[SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_MAX_NUM_CHECKERS] =
11783 {
11784  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_0_CHECKER_TYPE,
11785  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_0_WIDTH },
11786  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_1_CHECKER_TYPE,
11787  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_1_WIDTH },
11788  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_2_CHECKER_TYPE,
11789  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_2_WIDTH },
11790  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_3_CHECKER_TYPE,
11791  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_3_WIDTH },
11792  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_4_CHECKER_TYPE,
11793  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_4_WIDTH },
11794  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_5_CHECKER_TYPE,
11795  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_5_WIDTH },
11796  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_6_CHECKER_TYPE,
11797  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_6_WIDTH },
11798  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_7_CHECKER_TYPE,
11799  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_7_WIDTH },
11800  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_8_CHECKER_TYPE,
11801  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_8_WIDTH },
11802  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_9_CHECKER_TYPE,
11803  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_9_WIDTH },
11804  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_10_CHECKER_TYPE,
11805  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_10_WIDTH },
11806  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_11_CHECKER_TYPE,
11807  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_11_WIDTH },
11808  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_12_CHECKER_TYPE,
11809  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_12_WIDTH },
11810  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_13_CHECKER_TYPE,
11811  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_13_WIDTH },
11812  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_14_CHECKER_TYPE,
11813  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_14_WIDTH },
11814  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_15_CHECKER_TYPE,
11815  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_15_WIDTH },
11816  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_16_CHECKER_TYPE,
11817  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_16_WIDTH },
11818  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_17_CHECKER_TYPE,
11819  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_17_WIDTH },
11820  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_18_CHECKER_TYPE,
11821  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_18_WIDTH },
11822  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_19_CHECKER_TYPE,
11823  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_19_WIDTH },
11824  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_20_CHECKER_TYPE,
11825  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_20_WIDTH },
11826  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_21_CHECKER_TYPE,
11827  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_21_WIDTH },
11828  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_22_CHECKER_TYPE,
11829  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_22_WIDTH },
11830  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_23_CHECKER_TYPE,
11831  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_23_WIDTH },
11832  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_24_CHECKER_TYPE,
11833  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_24_WIDTH },
11834  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_25_CHECKER_TYPE,
11835  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_25_WIDTH },
11836  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_26_CHECKER_TYPE,
11837  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_26_WIDTH },
11838  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_27_CHECKER_TYPE,
11839  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_27_WIDTH },
11840  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_28_CHECKER_TYPE,
11841  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_28_WIDTH },
11842  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_29_CHECKER_TYPE,
11843  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_29_WIDTH },
11844  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_30_CHECKER_TYPE,
11845  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_30_WIDTH },
11846  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_31_CHECKER_TYPE,
11847  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_31_WIDTH },
11848  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_32_CHECKER_TYPE,
11849  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_32_WIDTH },
11850  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_33_CHECKER_TYPE,
11851  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_33_WIDTH },
11852  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_34_CHECKER_TYPE,
11853  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_34_WIDTH },
11854  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_35_CHECKER_TYPE,
11855  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_35_WIDTH },
11856  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_36_CHECKER_TYPE,
11857  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_36_WIDTH },
11858  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_37_CHECKER_TYPE,
11859  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_37_WIDTH },
11860  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_38_CHECKER_TYPE,
11861  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_38_WIDTH },
11862  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_39_CHECKER_TYPE,
11863  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_39_WIDTH },
11864  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_40_CHECKER_TYPE,
11865  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_40_WIDTH },
11866  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_41_CHECKER_TYPE,
11867  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_41_WIDTH },
11868  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_42_CHECKER_TYPE,
11869  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_42_WIDTH },
11870  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_43_CHECKER_TYPE,
11871  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_43_WIDTH },
11872  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_44_CHECKER_TYPE,
11873  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_44_WIDTH },
11874  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_45_CHECKER_TYPE,
11875  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_45_WIDTH },
11876  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_46_CHECKER_TYPE,
11877  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_46_WIDTH },
11878  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_47_CHECKER_TYPE,
11879  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_47_WIDTH },
11880  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_48_CHECKER_TYPE,
11881  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_48_WIDTH },
11882  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_49_CHECKER_TYPE,
11883  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_49_WIDTH },
11884  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_50_CHECKER_TYPE,
11885  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_50_WIDTH },
11886  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_51_CHECKER_TYPE,
11887  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_51_WIDTH },
11888  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_52_CHECKER_TYPE,
11889  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_52_WIDTH },
11890  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_53_CHECKER_TYPE,
11891  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_53_WIDTH },
11892  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_54_CHECKER_TYPE,
11893  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_54_WIDTH },
11894  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_55_CHECKER_TYPE,
11895  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_55_WIDTH },
11896  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_56_CHECKER_TYPE,
11897  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_56_WIDTH },
11898  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_57_CHECKER_TYPE,
11899  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_57_WIDTH },
11900  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_58_CHECKER_TYPE,
11901  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_58_WIDTH },
11902  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_59_CHECKER_TYPE,
11903  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_59_WIDTH },
11904  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_60_CHECKER_TYPE,
11905  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_60_WIDTH },
11906  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_61_CHECKER_TYPE,
11907  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_61_WIDTH },
11908  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_62_CHECKER_TYPE,
11909  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_62_WIDTH },
11910  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_63_CHECKER_TYPE,
11911  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_63_WIDTH },
11912  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_64_CHECKER_TYPE,
11913  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_64_WIDTH },
11914  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_65_CHECKER_TYPE,
11915  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_65_WIDTH },
11916  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_66_CHECKER_TYPE,
11917  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_66_WIDTH },
11918  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_67_CHECKER_TYPE,
11919  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_67_WIDTH },
11920  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_68_CHECKER_TYPE,
11921  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_68_WIDTH },
11922 };
11923 
11929 static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_CFG_SLV_DST_BUSECC_groupEntries[SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_CFG_SLV_DST_BUSECC_MAX_NUM_CHECKERS] =
11930 {
11931  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_CFG_SLV_DST_BUSECC_GROUP_0_CHECKER_TYPE,
11932  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_CFG_SLV_DST_BUSECC_GROUP_0_WIDTH },
11933  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_CFG_SLV_DST_BUSECC_GROUP_1_CHECKER_TYPE,
11934  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_CFG_SLV_DST_BUSECC_GROUP_1_WIDTH },
11935  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_CFG_SLV_DST_BUSECC_GROUP_2_CHECKER_TYPE,
11936  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_CFG_SLV_DST_BUSECC_GROUP_2_WIDTH },
11937  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_CFG_SLV_DST_BUSECC_GROUP_3_CHECKER_TYPE,
11938  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_CFG_SLV_DST_BUSECC_GROUP_3_WIDTH },
11939 };
11940 
11946 static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_PMST_SRC_BUSECC_groupEntries[SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_PMST_SRC_BUSECC_MAX_NUM_CHECKERS] =
11947 {
11948  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_PMST_SRC_BUSECC_GROUP_0_CHECKER_TYPE,
11949  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_PMST_SRC_BUSECC_GROUP_0_WIDTH },
11950  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_PMST_SRC_BUSECC_GROUP_1_CHECKER_TYPE,
11951  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_PMST_SRC_BUSECC_GROUP_1_WIDTH },
11952  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_PMST_SRC_BUSECC_GROUP_2_CHECKER_TYPE,
11953  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_PMST_SRC_BUSECC_GROUP_2_WIDTH },
11954  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_PMST_SRC_BUSECC_GROUP_3_CHECKER_TYPE,
11955  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_PMST_SRC_BUSECC_GROUP_3_WIDTH },
11956  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_PMST_SRC_BUSECC_GROUP_4_CHECKER_TYPE,
11957  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_PMST_SRC_BUSECC_GROUP_4_WIDTH },
11958  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_PMST_SRC_BUSECC_GROUP_5_CHECKER_TYPE,
11959  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_PMST_SRC_BUSECC_GROUP_5_WIDTH },
11960  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_PMST_SRC_BUSECC_GROUP_6_CHECKER_TYPE,
11961  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_PMST_SRC_BUSECC_GROUP_6_WIDTH },
11962  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_PMST_SRC_BUSECC_GROUP_7_CHECKER_TYPE,
11963  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_PMST_SRC_BUSECC_GROUP_7_WIDTH },
11964  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_PMST_SRC_BUSECC_GROUP_8_CHECKER_TYPE,
11965  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_PMST_SRC_BUSECC_GROUP_8_WIDTH },
11966  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_PMST_SRC_BUSECC_GROUP_9_CHECKER_TYPE,
11967  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_PMST_SRC_BUSECC_GROUP_9_WIDTH },
11968  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_PMST_SRC_BUSECC_GROUP_10_CHECKER_TYPE,
11969  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_PMST_SRC_BUSECC_GROUP_10_WIDTH },
11970  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_PMST_SRC_BUSECC_GROUP_11_CHECKER_TYPE,
11971  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_PMST_SRC_BUSECC_GROUP_11_WIDTH },
11972  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_PMST_SRC_BUSECC_GROUP_12_CHECKER_TYPE,
11973  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_PMST_SRC_BUSECC_GROUP_12_WIDTH },
11974  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_PMST_SRC_BUSECC_GROUP_13_CHECKER_TYPE,
11975  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_PMST_SRC_BUSECC_GROUP_13_WIDTH },
11976  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_PMST_SRC_BUSECC_GROUP_14_CHECKER_TYPE,
11977  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_PMST_SRC_BUSECC_GROUP_14_WIDTH },
11978 };
11979 
11985 static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__IECC_AGGR_CFG_DST_BUSECC_groupEntries[SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__IECC_AGGR_CFG_DST_BUSECC_MAX_NUM_CHECKERS] =
11986 {
11987  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__IECC_AGGR_CFG_DST_BUSECC_GROUP_0_CHECKER_TYPE,
11988  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__IECC_AGGR_CFG_DST_BUSECC_GROUP_0_WIDTH },
11989  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__IECC_AGGR_CFG_DST_BUSECC_GROUP_1_CHECKER_TYPE,
11990  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__IECC_AGGR_CFG_DST_BUSECC_GROUP_1_WIDTH },
11991  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__IECC_AGGR_CFG_DST_BUSECC_GROUP_2_CHECKER_TYPE,
11992  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__IECC_AGGR_CFG_DST_BUSECC_GROUP_2_WIDTH },
11993  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__IECC_AGGR_CFG_DST_BUSECC_GROUP_3_CHECKER_TYPE,
11994  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__IECC_AGGR_CFG_DST_BUSECC_GROUP_3_WIDTH },
11995 };
11996 
12002 static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_SAM62A_MCU_PULSAR_UL_ECC_AGGR_EDC_CTRL_groupEntries[SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_SAM62A_MCU_PULSAR_UL_ECC_AGGR_EDC_CTRL_MAX_NUM_CHECKERS] =
12003 {
12004  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_SAM62A_MCU_PULSAR_UL_ECC_AGGR_EDC_CTRL_GROUP_0_CHECKER_TYPE,
12005  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_SAM62A_MCU_PULSAR_UL_ECC_AGGR_EDC_CTRL_GROUP_0_WIDTH },
12006  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_SAM62A_MCU_PULSAR_UL_ECC_AGGR_EDC_CTRL_GROUP_1_CHECKER_TYPE,
12007  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_SAM62A_MCU_PULSAR_UL_ECC_AGGR_EDC_CTRL_GROUP_1_WIDTH },
12008  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_SAM62A_MCU_PULSAR_UL_ECC_AGGR_EDC_CTRL_GROUP_2_CHECKER_TYPE,
12009  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_SAM62A_MCU_PULSAR_UL_ECC_AGGR_EDC_CTRL_GROUP_2_WIDTH },
12010  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_SAM62A_MCU_PULSAR_UL_ECC_AGGR_EDC_CTRL_GROUP_3_CHECKER_TYPE,
12011  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_SAM62A_MCU_PULSAR_UL_ECC_AGGR_EDC_CTRL_GROUP_3_WIDTH },
12012  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_SAM62A_MCU_PULSAR_UL_ECC_AGGR_EDC_CTRL_GROUP_4_CHECKER_TYPE,
12013  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_SAM62A_MCU_PULSAR_UL_ECC_AGGR_EDC_CTRL_GROUP_4_WIDTH },
12014  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_SAM62A_MCU_PULSAR_UL_ECC_AGGR_EDC_CTRL_GROUP_5_CHECKER_TYPE,
12015  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_SAM62A_MCU_PULSAR_UL_ECC_AGGR_EDC_CTRL_GROUP_5_WIDTH },
12016 };
12017 
12022 static const SDL_MemConfig_t SDL_USB1_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_MemEntries[SDL_USB1_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES] =
12023 {
12024  { SDL_USB1_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_USB2SS_16FFC_USB2SS_CORE_AXI2VBUSM_MST_KSBUS_AXI2VBUSM_R_RDATA_BUFFER_RAM_ID, 0u,
12025  SDL_USB1_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_USB2SS_16FFC_USB2SS_CORE_AXI2VBUSM_MST_KSBUS_AXI2VBUSM_R_RDATA_BUFFER_RAM_SIZE, 4u,
12026  SDL_USB1_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_USB2SS_16FFC_USB2SS_CORE_AXI2VBUSM_MST_KSBUS_AXI2VBUSM_R_RDATA_BUFFER_ROW_WIDTH, ((bool)false) },
12027  { SDL_USB1_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_USB2SS_16FFC_USB2SS_CORE_RAMS_MEM_CTRL_RAM0_RAM_ID, 0u,
12028  SDL_USB1_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_USB2SS_16FFC_USB2SS_CORE_RAMS_MEM_CTRL_RAM0_RAM_SIZE, 4u,
12029  SDL_USB1_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_USB2SS_16FFC_USB2SS_CORE_RAMS_MEM_CTRL_RAM0_ROW_WIDTH, ((bool)false) },
12030 };
12031 
12036 static const SDL_MemConfig_t SDL_USB0_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_MemEntries[SDL_USB0_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES] =
12037 {
12038  { SDL_USB0_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_USB2SS_16FFC_USB2SS_CORE_AXI2VBUSM_MST_KSBUS_AXI2VBUSM_R_RDATA_BUFFER_RAM_ID, 0u,
12039  SDL_USB0_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_USB2SS_16FFC_USB2SS_CORE_AXI2VBUSM_MST_KSBUS_AXI2VBUSM_R_RDATA_BUFFER_RAM_SIZE, 4u,
12040  SDL_USB0_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_USB2SS_16FFC_USB2SS_CORE_AXI2VBUSM_MST_KSBUS_AXI2VBUSM_R_RDATA_BUFFER_ROW_WIDTH, ((bool)false) },
12041  { SDL_USB0_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_USB2SS_16FFC_USB2SS_CORE_RAMS_MEM_CTRL_RAM0_RAM_ID, 0u,
12042  SDL_USB0_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_USB2SS_16FFC_USB2SS_CORE_RAMS_MEM_CTRL_RAM0_RAM_SIZE, 4u,
12043  SDL_USB0_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_USB2SS_16FFC_USB2SS_CORE_RAMS_MEM_CTRL_RAM0_ROW_WIDTH, ((bool)false) },
12044 };
12045 
12050 static const SDL_MemConfig_t SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MemEntries[SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES] =
12051 {
12052  { SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_ECC0_RAM_ID, 0x79100000u,
12053  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_ECC0_RAM_SIZE, 4u,
12054  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_ECC0_ROW_WIDTH, ((bool)true) },
12055 };
12056 
12062 static const SDL_GrpChkConfig_t SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_groupEntries[SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_MAX_NUM_CHECKERS] =
12063 {
12064  { SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
12065  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_0_WIDTH },
12066  { SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
12067  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_1_WIDTH },
12068  { SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
12069  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_2_WIDTH },
12070  { SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
12071  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_3_WIDTH },
12072  { SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
12073  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_4_WIDTH },
12074  { SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
12075  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_5_WIDTH },
12076  { SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
12077  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_6_WIDTH },
12078  { SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
12079  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_7_WIDTH },
12080  { SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
12081  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_8_WIDTH },
12082  { SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
12083  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_9_WIDTH },
12084  { SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
12085  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_10_WIDTH },
12086  { SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
12087  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_11_WIDTH },
12088  { SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
12089  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_12_WIDTH },
12090  { SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
12091  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_13_WIDTH },
12092  { SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
12093  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_14_WIDTH },
12094  { SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
12095  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_15_WIDTH },
12096  { SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
12097  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_16_WIDTH },
12098  { SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
12099  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_17_WIDTH },
12100  { SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
12101  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_18_WIDTH },
12102  { SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
12103  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_19_WIDTH },
12104  { SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
12105  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_20_WIDTH },
12106  { SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
12107  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_21_WIDTH },
12108  { SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
12109  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_22_WIDTH },
12110  { SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
12111  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_23_WIDTH },
12112  { SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
12113  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_24_WIDTH },
12114  { SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
12115  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_25_WIDTH },
12116  { SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
12117  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_26_WIDTH },
12118  { SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
12119  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_27_WIDTH },
12120  { SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
12121  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_28_WIDTH },
12122  { SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
12123  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_29_WIDTH },
12124  { SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
12125  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_30_WIDTH },
12126  { SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
12127  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_31_WIDTH },
12128  { SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
12129  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_32_WIDTH },
12130  { SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_33_CHECKER_TYPE,
12131  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_33_WIDTH },
12132  { SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_34_CHECKER_TYPE,
12133  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_34_WIDTH },
12134  { SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_35_CHECKER_TYPE,
12135  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_35_WIDTH },
12136  { SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_36_CHECKER_TYPE,
12137  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_36_WIDTH },
12138  { SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_37_CHECKER_TYPE,
12139  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_37_WIDTH },
12140  { SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_38_CHECKER_TYPE,
12141  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_38_WIDTH },
12142  { SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_39_CHECKER_TYPE,
12143  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_39_WIDTH },
12144  { SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_40_CHECKER_TYPE,
12145  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_40_WIDTH },
12146  { SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_41_CHECKER_TYPE,
12147  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_41_WIDTH },
12148  { SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_42_CHECKER_TYPE,
12149  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_42_WIDTH },
12150  { SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_43_CHECKER_TYPE,
12151  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_43_WIDTH },
12152  { SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_44_CHECKER_TYPE,
12153  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_44_WIDTH },
12154  { SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_45_CHECKER_TYPE,
12155  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_45_WIDTH },
12156  { SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_46_CHECKER_TYPE,
12157  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_46_WIDTH },
12158  { SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_47_CHECKER_TYPE,
12159  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_47_WIDTH },
12160  { SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_48_CHECKER_TYPE,
12161  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_48_WIDTH },
12162  { SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_49_CHECKER_TYPE,
12163  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_49_WIDTH },
12164  { SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_50_CHECKER_TYPE,
12165  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_50_WIDTH },
12166  { SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_51_CHECKER_TYPE,
12167  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_51_WIDTH },
12168  { SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_52_CHECKER_TYPE,
12169  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_52_WIDTH },
12170  { SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_53_CHECKER_TYPE,
12171  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_53_WIDTH },
12172  { SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_54_CHECKER_TYPE,
12173  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_54_WIDTH },
12174  { SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_55_CHECKER_TYPE,
12175  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_55_WIDTH },
12176  { SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_56_CHECKER_TYPE,
12177  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_56_WIDTH },
12178  { SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_57_CHECKER_TYPE,
12179  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_57_WIDTH },
12180  { SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_58_CHECKER_TYPE,
12181  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_58_WIDTH },
12182  { SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_59_CHECKER_TYPE,
12183  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_59_WIDTH },
12184  { SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_60_CHECKER_TYPE,
12185  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_60_WIDTH },
12186  { SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_61_CHECKER_TYPE,
12187  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_61_WIDTH },
12188  { SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_62_CHECKER_TYPE,
12189  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_62_WIDTH },
12190  { SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_63_CHECKER_TYPE,
12191  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_63_WIDTH },
12192  { SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_64_CHECKER_TYPE,
12193  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_64_WIDTH },
12194 };
12195 
12201 static const SDL_GrpChkConfig_t SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_ECC_AGGR_EDC_CTRL_groupEntries[SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_ECC_AGGR_EDC_CTRL_MAX_NUM_CHECKERS] =
12202 {
12203  { SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_ECC_AGGR_EDC_CTRL_GROUP_0_CHECKER_TYPE,
12204  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_ECC_AGGR_EDC_CTRL_GROUP_0_WIDTH },
12205  { SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_ECC_AGGR_EDC_CTRL_GROUP_1_CHECKER_TYPE,
12206  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_ECC_AGGR_EDC_CTRL_GROUP_1_WIDTH },
12207  { SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_ECC_AGGR_EDC_CTRL_GROUP_2_CHECKER_TYPE,
12208  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_ECC_AGGR_EDC_CTRL_GROUP_2_WIDTH },
12209  { SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_ECC_AGGR_EDC_CTRL_GROUP_3_CHECKER_TYPE,
12210  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_ECC_AGGR_EDC_CTRL_GROUP_3_WIDTH },
12211  { SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_ECC_AGGR_EDC_CTRL_GROUP_4_CHECKER_TYPE,
12212  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_ECC_AGGR_EDC_CTRL_GROUP_4_WIDTH },
12213  { SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_ECC_AGGR_EDC_CTRL_GROUP_5_CHECKER_TYPE,
12214  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_ECC_AGGR_EDC_CTRL_GROUP_5_WIDTH },
12215 };
12216 
12221 static const SDL_MemConfig_t SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_RXMEM_MemEntries[SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_RXMEM_RAM_IDS_TOTAL_ENTRIES] =
12222 {
12223  { SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_RXMEM_EMMCSD4SS_SDHC_WRAP_RXMEM_RAM_ID, 0u,
12224  SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_RXMEM_EMMCSD4SS_SDHC_WRAP_RXMEM_RAM_SIZE, 4u,
12225  SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_RXMEM_EMMCSD4SS_SDHC_WRAP_RXMEM_ROW_WIDTH, ((bool)false) },
12226 };
12227 
12232 static const SDL_MemConfig_t SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_TXMEM_MemEntries[SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_TXMEM_RAM_IDS_TOTAL_ENTRIES] =
12233 {
12234  { SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_TXMEM_EMMCSD4SS_SDHC_WRAP_TXMEM_RAM_ID, 0u,
12235  SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_TXMEM_EMMCSD4SS_SDHC_WRAP_TXMEM_RAM_SIZE, 4u,
12236  SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_TXMEM_EMMCSD4SS_SDHC_WRAP_TXMEM_ROW_WIDTH, ((bool)false) },
12237 };
12238 
12243 static const SDL_MemConfig_t SDL_WKUP_PSRAMECC_8K0_PSRAM8KX32E_ECC_AGGR_MemEntries[SDL_WKUP_PSRAMECC_8K0_PSRAM8KX32E_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES] =
12244 {
12245  { SDL_WKUP_PSRAMECC_8K0_PSRAM8KX32E_ECC_AGGR_PSRAM8KX32E_PSRAM0_ECC_RAM_ID, 0x41880000u,
12246  SDL_WKUP_PSRAMECC_8K0_PSRAM8KX32E_ECC_AGGR_PSRAM8KX32E_PSRAM0_ECC_RAM_SIZE, 4u,
12247  SDL_WKUP_PSRAMECC_8K0_PSRAM8KX32E_ECC_AGGR_PSRAM8KX32E_PSRAM0_ECC_ROW_WIDTH, ((bool)true) },
12248 };
12249 
12254 static const SDL_MemConfig_t SDL_PDMA1_SAM62_PDMA_UART_ECCAGGR_MemEntries[SDL_PDMA1_SAM62_PDMA_UART_ECCAGGR_RAM_IDS_TOTAL_ENTRIES] =
12255 {
12256  { SDL_PDMA1_SAM62_PDMA_UART_ECCAGGR_SAM62_PDMA_UART_PDMA_CORE_TF0_F0_TPRAM_28X128_SBW_SR_RAM_ID, 0u,
12257  SDL_PDMA1_SAM62_PDMA_UART_ECCAGGR_SAM62_PDMA_UART_PDMA_CORE_TF0_F0_TPRAM_28X128_SBW_SR_RAM_SIZE, 4u,
12258  SDL_PDMA1_SAM62_PDMA_UART_ECCAGGR_SAM62_PDMA_UART_PDMA_CORE_TF0_F0_TPRAM_28X128_SBW_SR_ROW_WIDTH, ((bool)false) },
12259  { SDL_PDMA1_SAM62_PDMA_UART_ECCAGGR_SAM62_PDMA_UART_PDMA_CORE_TF0_F1_TPRAM_28X128_SBW_SR_RAM_ID, 0u,
12260  SDL_PDMA1_SAM62_PDMA_UART_ECCAGGR_SAM62_PDMA_UART_PDMA_CORE_TF0_F1_TPRAM_28X128_SBW_SR_RAM_SIZE, 4u,
12261  SDL_PDMA1_SAM62_PDMA_UART_ECCAGGR_SAM62_PDMA_UART_PDMA_CORE_TF0_F1_TPRAM_28X128_SBW_SR_ROW_WIDTH, ((bool)false) },
12262  { SDL_PDMA1_SAM62_PDMA_UART_ECCAGGR_SAM62_PDMA_UART_PDMA_CORE_RF0_F0_TPRAM_28X144_SBW_SR_RAM_ID, 0u,
12263  SDL_PDMA1_SAM62_PDMA_UART_ECCAGGR_SAM62_PDMA_UART_PDMA_CORE_RF0_F0_TPRAM_28X144_SBW_SR_RAM_SIZE, 4u,
12264  SDL_PDMA1_SAM62_PDMA_UART_ECCAGGR_SAM62_PDMA_UART_PDMA_CORE_RF0_F0_TPRAM_28X144_SBW_SR_ROW_WIDTH, ((bool)false) },
12265  { SDL_PDMA1_SAM62_PDMA_UART_ECCAGGR_SAM62_PDMA_UART_PDMA_CORE_RF0_F1_TPRAM_28X144_SBW_SR_RAM_ID, 0u,
12266  SDL_PDMA1_SAM62_PDMA_UART_ECCAGGR_SAM62_PDMA_UART_PDMA_CORE_RF0_F1_TPRAM_28X144_SBW_SR_RAM_SIZE, 4u,
12267  SDL_PDMA1_SAM62_PDMA_UART_ECCAGGR_SAM62_PDMA_UART_PDMA_CORE_RF0_F1_TPRAM_28X144_SBW_SR_ROW_WIDTH, ((bool)false) },
12268 };
12269 
12274 static const SDL_MemConfig_t SDL_MCU_ECC_AGGR0_MemEntries[SDL_MCU_ECC_AGGR0_RAM_IDS_TOTAL_ENTRIES] =
12275 {
12276  { SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_WR_RAMECC_RAM_ID, 0u,
12277  SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_WR_RAMECC_RAM_SIZE, 4u,
12278  SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_WR_RAMECC_ROW_WIDTH, ((bool)false) },
12279  { SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_RD_RAMECC_RAM_ID, 0u,
12280  SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_RD_RAMECC_RAM_SIZE, 4u,
12281  SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_RD_RAMECC_ROW_WIDTH, ((bool)false) },
12282 };
12283 
12289 static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_groupEntries[SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_MAX_NUM_CHECKERS] =
12290 {
12291  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_0_CHECKER_TYPE,
12292  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_0_WIDTH },
12293  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_1_CHECKER_TYPE,
12294  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_1_WIDTH },
12295  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_2_CHECKER_TYPE,
12296  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_2_WIDTH },
12297  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_3_CHECKER_TYPE,
12298  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_3_WIDTH },
12299  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_4_CHECKER_TYPE,
12300  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_4_WIDTH },
12301  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_5_CHECKER_TYPE,
12302  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_5_WIDTH },
12303  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_6_CHECKER_TYPE,
12304  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_6_WIDTH },
12305  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_7_CHECKER_TYPE,
12306  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_7_WIDTH },
12307  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_8_CHECKER_TYPE,
12308  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_8_WIDTH },
12309  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_9_CHECKER_TYPE,
12310  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_9_WIDTH },
12311  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_10_CHECKER_TYPE,
12312  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_10_WIDTH },
12313  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_11_CHECKER_TYPE,
12314  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_11_WIDTH },
12315  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_12_CHECKER_TYPE,
12316  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_12_WIDTH },
12317  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_13_CHECKER_TYPE,
12318  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_13_WIDTH },
12319  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_14_CHECKER_TYPE,
12320  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_14_WIDTH },
12321  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_15_CHECKER_TYPE,
12322  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_15_WIDTH },
12323  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_16_CHECKER_TYPE,
12324  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_16_WIDTH },
12325  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_17_CHECKER_TYPE,
12326  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_17_WIDTH },
12327  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_18_CHECKER_TYPE,
12328  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_18_WIDTH },
12329  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_19_CHECKER_TYPE,
12330  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_19_WIDTH },
12331  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_20_CHECKER_TYPE,
12332  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_20_WIDTH },
12333  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_21_CHECKER_TYPE,
12334  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_21_WIDTH },
12335  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_22_CHECKER_TYPE,
12336  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_22_WIDTH },
12337  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_23_CHECKER_TYPE,
12338  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_23_WIDTH },
12339  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_24_CHECKER_TYPE,
12340  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_24_WIDTH },
12341  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_25_CHECKER_TYPE,
12342  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_25_WIDTH },
12343  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_26_CHECKER_TYPE,
12344  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_26_WIDTH },
12345  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_27_CHECKER_TYPE,
12346  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_27_WIDTH },
12347  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_28_CHECKER_TYPE,
12348  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_28_WIDTH },
12349  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_29_CHECKER_TYPE,
12350  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_29_WIDTH },
12351  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_30_CHECKER_TYPE,
12352  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_30_WIDTH },
12353  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_31_CHECKER_TYPE,
12354  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_31_WIDTH },
12355  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_32_CHECKER_TYPE,
12356  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_32_WIDTH },
12357  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_33_CHECKER_TYPE,
12358  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_33_WIDTH },
12359  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_34_CHECKER_TYPE,
12360  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_34_WIDTH },
12361  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_35_CHECKER_TYPE,
12362  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_35_WIDTH },
12363  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_36_CHECKER_TYPE,
12364  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_36_WIDTH },
12365  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_37_CHECKER_TYPE,
12366  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_37_WIDTH },
12367  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_38_CHECKER_TYPE,
12368  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_38_WIDTH },
12369  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_39_CHECKER_TYPE,
12370  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_39_WIDTH },
12371  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_40_CHECKER_TYPE,
12372  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_40_WIDTH },
12373  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_41_CHECKER_TYPE,
12374  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_41_WIDTH },
12375  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_42_CHECKER_TYPE,
12376  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_42_WIDTH },
12377  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_43_CHECKER_TYPE,
12378  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_43_WIDTH },
12379  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_44_CHECKER_TYPE,
12380  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_44_WIDTH },
12381  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_45_CHECKER_TYPE,
12382  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_45_WIDTH },
12383  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_46_CHECKER_TYPE,
12384  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_46_WIDTH },
12385  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_47_CHECKER_TYPE,
12386  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_47_WIDTH },
12387  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_48_CHECKER_TYPE,
12388  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_48_WIDTH },
12389  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_49_CHECKER_TYPE,
12390  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_49_WIDTH },
12391  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_50_CHECKER_TYPE,
12392  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_50_WIDTH },
12393  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_51_CHECKER_TYPE,
12394  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_51_WIDTH },
12395  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_52_CHECKER_TYPE,
12396  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_52_WIDTH },
12397  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_53_CHECKER_TYPE,
12398  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_53_WIDTH },
12399  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_54_CHECKER_TYPE,
12400  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_54_WIDTH },
12401  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_55_CHECKER_TYPE,
12402  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_55_WIDTH },
12403  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_56_CHECKER_TYPE,
12404  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_56_WIDTH },
12405  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_57_CHECKER_TYPE,
12406  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_57_WIDTH },
12407  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_58_CHECKER_TYPE,
12408  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_58_WIDTH },
12409  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_59_CHECKER_TYPE,
12410  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_59_WIDTH },
12411  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_60_CHECKER_TYPE,
12412  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_60_WIDTH },
12413  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_61_CHECKER_TYPE,
12414  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_61_WIDTH },
12415  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_62_CHECKER_TYPE,
12416  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_62_WIDTH },
12417  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_63_CHECKER_TYPE,
12418  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_63_WIDTH },
12419  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_64_CHECKER_TYPE,
12420  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_64_WIDTH },
12421 };
12422 
12428 static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_CFG_SLV_SRC_BUSECC_groupEntries[SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_CFG_SLV_SRC_BUSECC_MAX_NUM_CHECKERS] =
12429 {
12430  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_CFG_SLV_SRC_BUSECC_GROUP_0_CHECKER_TYPE,
12431  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_CFG_SLV_SRC_BUSECC_GROUP_0_WIDTH },
12432  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_CFG_SLV_SRC_BUSECC_GROUP_1_CHECKER_TYPE,
12433  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_CFG_SLV_SRC_BUSECC_GROUP_1_WIDTH },
12434  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_CFG_SLV_SRC_BUSECC_GROUP_2_CHECKER_TYPE,
12435  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_CFG_SLV_SRC_BUSECC_GROUP_2_WIDTH },
12436  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_CFG_SLV_SRC_BUSECC_GROUP_3_CHECKER_TYPE,
12437  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_CFG_SLV_SRC_BUSECC_GROUP_3_WIDTH },
12438  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_CFG_SLV_SRC_BUSECC_GROUP_4_CHECKER_TYPE,
12439  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_CFG_SLV_SRC_BUSECC_GROUP_4_WIDTH },
12440  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_CFG_SLV_SRC_BUSECC_GROUP_5_CHECKER_TYPE,
12441  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_CFG_SLV_SRC_BUSECC_GROUP_5_WIDTH },
12442  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_CFG_SLV_SRC_BUSECC_GROUP_6_CHECKER_TYPE,
12443  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_CFG_SLV_SRC_BUSECC_GROUP_6_WIDTH },
12444  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_CFG_SLV_SRC_BUSECC_GROUP_7_CHECKER_TYPE,
12445  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_CFG_SLV_SRC_BUSECC_GROUP_7_WIDTH },
12446  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_CFG_SLV_SRC_BUSECC_GROUP_8_CHECKER_TYPE,
12447  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_CFG_SLV_SRC_BUSECC_GROUP_8_WIDTH },
12448  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_CFG_SLV_SRC_BUSECC_GROUP_9_CHECKER_TYPE,
12449  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_CFG_SLV_SRC_BUSECC_GROUP_9_WIDTH },
12450  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_CFG_SLV_SRC_BUSECC_GROUP_10_CHECKER_TYPE,
12451  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_CFG_SLV_SRC_BUSECC_GROUP_10_WIDTH },
12452  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_CFG_SLV_SRC_BUSECC_GROUP_11_CHECKER_TYPE,
12453  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_CFG_SLV_SRC_BUSECC_GROUP_11_WIDTH },
12454  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_CFG_SLV_SRC_BUSECC_GROUP_12_CHECKER_TYPE,
12455  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_CFG_SLV_SRC_BUSECC_GROUP_12_WIDTH },
12456  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_CFG_SLV_SRC_BUSECC_GROUP_13_CHECKER_TYPE,
12457  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_CFG_SLV_SRC_BUSECC_GROUP_13_WIDTH },
12458  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_CFG_SLV_SRC_BUSECC_GROUP_14_CHECKER_TYPE,
12459  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_CFG_SLV_SRC_BUSECC_GROUP_14_WIDTH },
12460 };
12461 
12467 static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_PMST_DST_BUSECC_groupEntries[SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_PMST_DST_BUSECC_MAX_NUM_CHECKERS] =
12468 {
12469  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_PMST_DST_BUSECC_GROUP_0_CHECKER_TYPE,
12470  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_PMST_DST_BUSECC_GROUP_0_WIDTH },
12471  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_PMST_DST_BUSECC_GROUP_1_CHECKER_TYPE,
12472  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_PMST_DST_BUSECC_GROUP_1_WIDTH },
12473  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_PMST_DST_BUSECC_GROUP_2_CHECKER_TYPE,
12474  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_PMST_DST_BUSECC_GROUP_2_WIDTH },
12475  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_PMST_DST_BUSECC_GROUP_3_CHECKER_TYPE,
12476  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_PMST_DST_BUSECC_GROUP_3_WIDTH },
12477 };
12478 
12484 static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_groupEntries[SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_MAX_NUM_CHECKERS] =
12485 {
12486  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_0_CHECKER_TYPE,
12487  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_0_WIDTH },
12488  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_1_CHECKER_TYPE,
12489  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_1_WIDTH },
12490  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_2_CHECKER_TYPE,
12491  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_2_WIDTH },
12492  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_3_CHECKER_TYPE,
12493  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_3_WIDTH },
12494  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_4_CHECKER_TYPE,
12495  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_4_WIDTH },
12496  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_5_CHECKER_TYPE,
12497  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_5_WIDTH },
12498  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_6_CHECKER_TYPE,
12499  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_6_WIDTH },
12500  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_7_CHECKER_TYPE,
12501  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_7_WIDTH },
12502  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_8_CHECKER_TYPE,
12503  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_8_WIDTH },
12504  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_9_CHECKER_TYPE,
12505  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_9_WIDTH },
12506  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_10_CHECKER_TYPE,
12507  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_10_WIDTH },
12508  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_11_CHECKER_TYPE,
12509  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_11_WIDTH },
12510  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_12_CHECKER_TYPE,
12511  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_12_WIDTH },
12512  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_13_CHECKER_TYPE,
12513  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_13_WIDTH },
12514  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_14_CHECKER_TYPE,
12515  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_14_WIDTH },
12516  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_15_CHECKER_TYPE,
12517  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_15_WIDTH },
12518  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_16_CHECKER_TYPE,
12519  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_16_WIDTH },
12520  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_17_CHECKER_TYPE,
12521  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_17_WIDTH },
12522  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_18_CHECKER_TYPE,
12523  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_18_WIDTH },
12524  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_19_CHECKER_TYPE,
12525  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_19_WIDTH },
12526  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_20_CHECKER_TYPE,
12527  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_20_WIDTH },
12528  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_21_CHECKER_TYPE,
12529  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_21_WIDTH },
12530  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_22_CHECKER_TYPE,
12531  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_22_WIDTH },
12532  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_23_CHECKER_TYPE,
12533  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_23_WIDTH },
12534  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_24_CHECKER_TYPE,
12535  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_24_WIDTH },
12536  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_25_CHECKER_TYPE,
12537  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_25_WIDTH },
12538  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_26_CHECKER_TYPE,
12539  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_26_WIDTH },
12540  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_27_CHECKER_TYPE,
12541  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_27_WIDTH },
12542  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_28_CHECKER_TYPE,
12543  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_28_WIDTH },
12544  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_29_CHECKER_TYPE,
12545  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_29_WIDTH },
12546  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_30_CHECKER_TYPE,
12547  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_30_WIDTH },
12548  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_31_CHECKER_TYPE,
12549  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_31_WIDTH },
12550  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_32_CHECKER_TYPE,
12551  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_32_WIDTH },
12552  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_33_CHECKER_TYPE,
12553  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_33_WIDTH },
12554  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_34_CHECKER_TYPE,
12555  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_34_WIDTH },
12556  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_35_CHECKER_TYPE,
12557  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_35_WIDTH },
12558  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_36_CHECKER_TYPE,
12559  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_36_WIDTH },
12560  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_37_CHECKER_TYPE,
12561  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_37_WIDTH },
12562  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_38_CHECKER_TYPE,
12563  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_38_WIDTH },
12564  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_39_CHECKER_TYPE,
12565  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_39_WIDTH },
12566  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_40_CHECKER_TYPE,
12567  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_40_WIDTH },
12568  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_41_CHECKER_TYPE,
12569  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_41_WIDTH },
12570  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_42_CHECKER_TYPE,
12571  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_42_WIDTH },
12572  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_43_CHECKER_TYPE,
12573  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_43_WIDTH },
12574  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_44_CHECKER_TYPE,
12575  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_44_WIDTH },
12576  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_45_CHECKER_TYPE,
12577  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_45_WIDTH },
12578  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_46_CHECKER_TYPE,
12579  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_46_WIDTH },
12580  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_47_CHECKER_TYPE,
12581  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_47_WIDTH },
12582  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_48_CHECKER_TYPE,
12583  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_48_WIDTH },
12584  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_49_CHECKER_TYPE,
12585  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_49_WIDTH },
12586  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_50_CHECKER_TYPE,
12587  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_50_WIDTH },
12588  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_51_CHECKER_TYPE,
12589  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_51_WIDTH },
12590  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_52_CHECKER_TYPE,
12591  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_52_WIDTH },
12592  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_53_CHECKER_TYPE,
12593  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_53_WIDTH },
12594  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_54_CHECKER_TYPE,
12595  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_54_WIDTH },
12596  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_55_CHECKER_TYPE,
12597  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_55_WIDTH },
12598  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_56_CHECKER_TYPE,
12599  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_56_WIDTH },
12600  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_57_CHECKER_TYPE,
12601  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_57_WIDTH },
12602  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_58_CHECKER_TYPE,
12603  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_58_WIDTH },
12604  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_59_CHECKER_TYPE,
12605  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_59_WIDTH },
12606  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_60_CHECKER_TYPE,
12607  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_60_WIDTH },
12608  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_61_CHECKER_TYPE,
12609  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_61_WIDTH },
12610  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_62_CHECKER_TYPE,
12611  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_62_WIDTH },
12612  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_63_CHECKER_TYPE,
12613  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_63_WIDTH },
12614  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_64_CHECKER_TYPE,
12615  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_64_WIDTH },
12616  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_65_CHECKER_TYPE,
12617  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_65_WIDTH },
12618  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_66_CHECKER_TYPE,
12619  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_66_WIDTH },
12620  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_67_CHECKER_TYPE,
12621  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_67_WIDTH },
12622  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_68_CHECKER_TYPE,
12623  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_68_WIDTH },
12624 };
12625 
12631 static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_groupEntries[SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_MAX_NUM_CHECKERS] =
12632 {
12633  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_0_CHECKER_TYPE,
12634  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_0_WIDTH },
12635  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_1_CHECKER_TYPE,
12636  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_1_WIDTH },
12637  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_2_CHECKER_TYPE,
12638  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_2_WIDTH },
12639  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_3_CHECKER_TYPE,
12640  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_3_WIDTH },
12641  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_4_CHECKER_TYPE,
12642  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_4_WIDTH },
12643  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_5_CHECKER_TYPE,
12644  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_5_WIDTH },
12645  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_6_CHECKER_TYPE,
12646  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_6_WIDTH },
12647  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_7_CHECKER_TYPE,
12648  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_7_WIDTH },
12649  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_8_CHECKER_TYPE,
12650  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_8_WIDTH },
12651  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_9_CHECKER_TYPE,
12652  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_9_WIDTH },
12653  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_10_CHECKER_TYPE,
12654  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_10_WIDTH },
12655  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_11_CHECKER_TYPE,
12656  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_11_WIDTH },
12657  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_12_CHECKER_TYPE,
12658  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_12_WIDTH },
12659  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_13_CHECKER_TYPE,
12660  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_13_WIDTH },
12661  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_14_CHECKER_TYPE,
12662  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_14_WIDTH },
12663  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_15_CHECKER_TYPE,
12664  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_15_WIDTH },
12665  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_16_CHECKER_TYPE,
12666  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_16_WIDTH },
12667  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_17_CHECKER_TYPE,
12668  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_17_WIDTH },
12669  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_18_CHECKER_TYPE,
12670  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_18_WIDTH },
12671  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_19_CHECKER_TYPE,
12672  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_19_WIDTH },
12673  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_20_CHECKER_TYPE,
12674  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_20_WIDTH },
12675  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_21_CHECKER_TYPE,
12676  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_21_WIDTH },
12677  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_22_CHECKER_TYPE,
12678  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_22_WIDTH },
12679  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_23_CHECKER_TYPE,
12680  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_23_WIDTH },
12681  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_24_CHECKER_TYPE,
12682  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_24_WIDTH },
12683  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_25_CHECKER_TYPE,
12684  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_25_WIDTH },
12685  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_26_CHECKER_TYPE,
12686  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_26_WIDTH },
12687  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_27_CHECKER_TYPE,
12688  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_27_WIDTH },
12689  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_28_CHECKER_TYPE,
12690  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_28_WIDTH },
12691  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_29_CHECKER_TYPE,
12692  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_29_WIDTH },
12693  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_30_CHECKER_TYPE,
12694  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_30_WIDTH },
12695  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_31_CHECKER_TYPE,
12696  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_31_WIDTH },
12697  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_32_CHECKER_TYPE,
12698  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_32_WIDTH },
12699  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_33_CHECKER_TYPE,
12700  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_33_WIDTH },
12701  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_34_CHECKER_TYPE,
12702  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_34_WIDTH },
12703  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_35_CHECKER_TYPE,
12704  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_35_WIDTH },
12705  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_36_CHECKER_TYPE,
12706  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_36_WIDTH },
12707  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_37_CHECKER_TYPE,
12708  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_37_WIDTH },
12709  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_38_CHECKER_TYPE,
12710  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_38_WIDTH },
12711  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_39_CHECKER_TYPE,
12712  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_39_WIDTH },
12713  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_40_CHECKER_TYPE,
12714  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_40_WIDTH },
12715  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_41_CHECKER_TYPE,
12716  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_41_WIDTH },
12717  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_42_CHECKER_TYPE,
12718  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_42_WIDTH },
12719  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_43_CHECKER_TYPE,
12720  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_43_WIDTH },
12721  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_44_CHECKER_TYPE,
12722  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_44_WIDTH },
12723  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_45_CHECKER_TYPE,
12724  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_45_WIDTH },
12725  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_46_CHECKER_TYPE,
12726  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_46_WIDTH },
12727  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_47_CHECKER_TYPE,
12728  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_47_WIDTH },
12729  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_48_CHECKER_TYPE,
12730  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_48_WIDTH },
12731  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_49_CHECKER_TYPE,
12732  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_49_WIDTH },
12733  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_50_CHECKER_TYPE,
12734  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_50_WIDTH },
12735  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_51_CHECKER_TYPE,
12736  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_51_WIDTH },
12737  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_52_CHECKER_TYPE,
12738  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_52_WIDTH },
12739  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_53_CHECKER_TYPE,
12740  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_53_WIDTH },
12741  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_54_CHECKER_TYPE,
12742  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_54_WIDTH },
12743  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_55_CHECKER_TYPE,
12744  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_55_WIDTH },
12745  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_56_CHECKER_TYPE,
12746  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_56_WIDTH },
12747  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_57_CHECKER_TYPE,
12748  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_57_WIDTH },
12749  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_58_CHECKER_TYPE,
12750  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_58_WIDTH },
12751  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_59_CHECKER_TYPE,
12752  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_59_WIDTH },
12753  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_60_CHECKER_TYPE,
12754  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_60_WIDTH },
12755  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_61_CHECKER_TYPE,
12756  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_61_WIDTH },
12757  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_62_CHECKER_TYPE,
12758  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_62_WIDTH },
12759  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_63_CHECKER_TYPE,
12760  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_63_WIDTH },
12761  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_64_CHECKER_TYPE,
12762  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_64_WIDTH },
12763  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_65_CHECKER_TYPE,
12764  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_65_WIDTH },
12765  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_66_CHECKER_TYPE,
12766  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_66_WIDTH },
12767  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_67_CHECKER_TYPE,
12768  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_67_WIDTH },
12769  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_68_CHECKER_TYPE,
12770  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_68_WIDTH },
12771 };
12772 
12778 static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__IECC_AGGR_CFG_SRC_BUSECC_groupEntries[SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__IECC_AGGR_CFG_SRC_BUSECC_MAX_NUM_CHECKERS] =
12779 {
12780  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__IECC_AGGR_CFG_SRC_BUSECC_GROUP_0_CHECKER_TYPE,
12781  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__IECC_AGGR_CFG_SRC_BUSECC_GROUP_0_WIDTH },
12782  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__IECC_AGGR_CFG_SRC_BUSECC_GROUP_1_CHECKER_TYPE,
12783  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__IECC_AGGR_CFG_SRC_BUSECC_GROUP_1_WIDTH },
12784  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__IECC_AGGR_CFG_SRC_BUSECC_GROUP_2_CHECKER_TYPE,
12785  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__IECC_AGGR_CFG_SRC_BUSECC_GROUP_2_WIDTH },
12786  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__IECC_AGGR_CFG_SRC_BUSECC_GROUP_3_CHECKER_TYPE,
12787  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__IECC_AGGR_CFG_SRC_BUSECC_GROUP_3_WIDTH },
12788  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__IECC_AGGR_CFG_SRC_BUSECC_GROUP_4_CHECKER_TYPE,
12789  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__IECC_AGGR_CFG_SRC_BUSECC_GROUP_4_WIDTH },
12790  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__IECC_AGGR_CFG_SRC_BUSECC_GROUP_5_CHECKER_TYPE,
12791  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__IECC_AGGR_CFG_SRC_BUSECC_GROUP_5_WIDTH },
12792  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__IECC_AGGR_CFG_SRC_BUSECC_GROUP_6_CHECKER_TYPE,
12793  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__IECC_AGGR_CFG_SRC_BUSECC_GROUP_6_WIDTH },
12794  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__IECC_AGGR_CFG_SRC_BUSECC_GROUP_7_CHECKER_TYPE,
12795  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__IECC_AGGR_CFG_SRC_BUSECC_GROUP_7_WIDTH },
12796  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__IECC_AGGR_CFG_SRC_BUSECC_GROUP_8_CHECKER_TYPE,
12797  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__IECC_AGGR_CFG_SRC_BUSECC_GROUP_8_WIDTH },
12798  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__IECC_AGGR_CFG_SRC_BUSECC_GROUP_9_CHECKER_TYPE,
12799  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__IECC_AGGR_CFG_SRC_BUSECC_GROUP_9_WIDTH },
12800  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__IECC_AGGR_CFG_SRC_BUSECC_GROUP_10_CHECKER_TYPE,
12801  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__IECC_AGGR_CFG_SRC_BUSECC_GROUP_10_WIDTH },
12802  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__IECC_AGGR_CFG_SRC_BUSECC_GROUP_11_CHECKER_TYPE,
12803  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__IECC_AGGR_CFG_SRC_BUSECC_GROUP_11_WIDTH },
12804  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__IECC_AGGR_CFG_SRC_BUSECC_GROUP_12_CHECKER_TYPE,
12805  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__IECC_AGGR_CFG_SRC_BUSECC_GROUP_12_WIDTH },
12806  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__IECC_AGGR_CFG_SRC_BUSECC_GROUP_13_CHECKER_TYPE,
12807  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__IECC_AGGR_CFG_SRC_BUSECC_GROUP_13_WIDTH },
12808  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__IECC_AGGR_CFG_SRC_BUSECC_GROUP_14_CHECKER_TYPE,
12809  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__IECC_AGGR_CFG_SRC_BUSECC_GROUP_14_WIDTH },
12810 };
12811 
12817 static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_ISAM67_DM2MCU_VBUSM_GASKET_MCU_0_EDC_CTRL_groupEntries[SDL_MCU_ECC_AGGR0_ISAM67_DM2MCU_VBUSM_GASKET_MCU_0_EDC_CTRL_MAX_NUM_CHECKERS] =
12818 {
12819  { SDL_MCU_ECC_AGGR0_ISAM67_DM2MCU_VBUSM_GASKET_MCU_0_EDC_CTRL_GROUP_0_CHECKER_TYPE,
12820  SDL_MCU_ECC_AGGR0_ISAM67_DM2MCU_VBUSM_GASKET_MCU_0_EDC_CTRL_GROUP_0_WIDTH },
12821 };
12822 
12828 static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_groupEntries[SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_MAX_NUM_CHECKERS] =
12829 {
12830  { SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_0_CHECKER_TYPE,
12831  SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_0_WIDTH },
12832  { SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_1_CHECKER_TYPE,
12833  SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_1_WIDTH },
12834  { SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_2_CHECKER_TYPE,
12835  SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_2_WIDTH },
12836  { SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_3_CHECKER_TYPE,
12837  SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_3_WIDTH },
12838  { SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_4_CHECKER_TYPE,
12839  SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_4_WIDTH },
12840  { SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_5_CHECKER_TYPE,
12841  SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_5_WIDTH },
12842  { SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_6_CHECKER_TYPE,
12843  SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_6_WIDTH },
12844  { SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_7_CHECKER_TYPE,
12845  SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_7_WIDTH },
12846  { SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_8_CHECKER_TYPE,
12847  SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_8_WIDTH },
12848  { SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_9_CHECKER_TYPE,
12849  SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_9_WIDTH },
12850  { SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_10_CHECKER_TYPE,
12851  SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_10_WIDTH },
12852  { SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_11_CHECKER_TYPE,
12853  SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_11_WIDTH },
12854  { SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_12_CHECKER_TYPE,
12855  SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_12_WIDTH },
12856  { SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_13_CHECKER_TYPE,
12857  SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_13_WIDTH },
12858  { SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_14_CHECKER_TYPE,
12859  SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_14_WIDTH },
12860  { SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_15_CHECKER_TYPE,
12861  SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_15_WIDTH },
12862  { SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_16_CHECKER_TYPE,
12863  SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_16_WIDTH },
12864  { SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_17_CHECKER_TYPE,
12865  SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_17_WIDTH },
12866  { SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_18_CHECKER_TYPE,
12867  SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_18_WIDTH },
12868  { SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_19_CHECKER_TYPE,
12869  SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_19_WIDTH },
12870  { SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_20_CHECKER_TYPE,
12871  SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_20_WIDTH },
12872  { SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_21_CHECKER_TYPE,
12873  SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_21_WIDTH },
12874  { SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_22_CHECKER_TYPE,
12875  SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_22_WIDTH },
12876  { SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_23_CHECKER_TYPE,
12877  SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_23_WIDTH },
12878  { SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_24_CHECKER_TYPE,
12879  SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_24_WIDTH },
12880  { SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_25_CHECKER_TYPE,
12881  SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_25_WIDTH },
12882  { SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_26_CHECKER_TYPE,
12883  SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_26_WIDTH },
12884  { SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_27_CHECKER_TYPE,
12885  SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_27_WIDTH },
12886  { SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_28_CHECKER_TYPE,
12887  SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_28_WIDTH },
12888  { SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_29_CHECKER_TYPE,
12889  SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_29_WIDTH },
12890  { SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_30_CHECKER_TYPE,
12891  SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_30_WIDTH },
12892  { SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_31_CHECKER_TYPE,
12893  SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_31_WIDTH },
12894  { SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_32_CHECKER_TYPE,
12895  SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_32_WIDTH },
12896  { SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_33_CHECKER_TYPE,
12897  SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_33_WIDTH },
12898  { SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_34_CHECKER_TYPE,
12899  SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_34_WIDTH },
12900  { SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_35_CHECKER_TYPE,
12901  SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_35_WIDTH },
12902  { SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_36_CHECKER_TYPE,
12903  SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_36_WIDTH },
12904  { SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_37_CHECKER_TYPE,
12905  SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_37_WIDTH },
12906  { SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_38_CHECKER_TYPE,
12907  SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_38_WIDTH },
12908  { SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_39_CHECKER_TYPE,
12909  SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_39_WIDTH },
12910  { SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_40_CHECKER_TYPE,
12911  SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_40_WIDTH },
12912  { SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_41_CHECKER_TYPE,
12913  SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_41_WIDTH },
12914  { SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_42_CHECKER_TYPE,
12915  SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_42_WIDTH },
12916  { SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_43_CHECKER_TYPE,
12917  SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_43_WIDTH },
12918  { SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_44_CHECKER_TYPE,
12919  SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_44_WIDTH },
12920  { SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_45_CHECKER_TYPE,
12921  SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_45_WIDTH },
12922  { SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_46_CHECKER_TYPE,
12923  SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_46_WIDTH },
12924  { SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_47_CHECKER_TYPE,
12925  SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_47_WIDTH },
12926  { SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_48_CHECKER_TYPE,
12927  SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_48_WIDTH },
12928  { SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_49_CHECKER_TYPE,
12929  SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_49_WIDTH },
12930  { SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_50_CHECKER_TYPE,
12931  SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_50_WIDTH },
12932  { SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_51_CHECKER_TYPE,
12933  SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_51_WIDTH },
12934  { SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_52_CHECKER_TYPE,
12935  SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_52_WIDTH },
12936  { SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_53_CHECKER_TYPE,
12937  SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_53_WIDTH },
12938  { SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_54_CHECKER_TYPE,
12939  SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_54_WIDTH },
12940  { SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_55_CHECKER_TYPE,
12941  SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_55_WIDTH },
12942  { SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_56_CHECKER_TYPE,
12943  SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_56_WIDTH },
12944  { SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_57_CHECKER_TYPE,
12945  SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_57_WIDTH },
12946  { SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_58_CHECKER_TYPE,
12947  SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_58_WIDTH },
12948  { SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_59_CHECKER_TYPE,
12949  SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_59_WIDTH },
12950  { SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_60_CHECKER_TYPE,
12951  SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_60_WIDTH },
12952  { SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_61_CHECKER_TYPE,
12953  SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_61_WIDTH },
12954  { SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_62_CHECKER_TYPE,
12955  SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_62_WIDTH },
12956  { SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_63_CHECKER_TYPE,
12957  SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_63_WIDTH },
12958  { SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_64_CHECKER_TYPE,
12959  SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_64_WIDTH },
12960  { SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_65_CHECKER_TYPE,
12961  SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_65_WIDTH },
12962  { SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_66_CHECKER_TYPE,
12963  SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_66_WIDTH },
12964  { SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_67_CHECKER_TYPE,
12965  SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_67_WIDTH },
12966  { SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_68_CHECKER_TYPE,
12967  SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_68_WIDTH },
12968  { SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_69_CHECKER_TYPE,
12969  SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_69_WIDTH },
12970  { SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_70_CHECKER_TYPE,
12971  SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_70_WIDTH },
12972  { SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_71_CHECKER_TYPE,
12973  SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_71_WIDTH },
12974  { SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_72_CHECKER_TYPE,
12975  SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_72_WIDTH },
12976  { SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_73_CHECKER_TYPE,
12977  SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_73_WIDTH },
12978  { SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_74_CHECKER_TYPE,
12979  SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_74_WIDTH },
12980  { SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_75_CHECKER_TYPE,
12981  SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_75_WIDTH },
12982  { SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_76_CHECKER_TYPE,
12983  SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_76_WIDTH },
12984  { SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_77_CHECKER_TYPE,
12985  SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_77_WIDTH },
12986  { SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_78_CHECKER_TYPE,
12987  SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_78_WIDTH },
12988  { SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_79_CHECKER_TYPE,
12989  SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_79_WIDTH },
12990  { SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_80_CHECKER_TYPE,
12991  SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_80_WIDTH },
12992 };
12993 
12999 static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_P2P_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_BRIDGE_SRC_BUSECC_groupEntries[SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_P2P_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS] =
13000 {
13001  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_P2P_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_BRIDGE_SRC_BUSECC_GROUP_0_CHECKER_TYPE,
13002  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_P2P_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_BRIDGE_SRC_BUSECC_GROUP_0_WIDTH },
13003  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_P2P_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_BRIDGE_SRC_BUSECC_GROUP_1_CHECKER_TYPE,
13004  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_P2P_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_BRIDGE_SRC_BUSECC_GROUP_1_WIDTH },
13005  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_P2P_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_BRIDGE_SRC_BUSECC_GROUP_2_CHECKER_TYPE,
13006  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_P2P_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_BRIDGE_SRC_BUSECC_GROUP_2_WIDTH },
13007  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_P2P_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_BRIDGE_SRC_BUSECC_GROUP_3_CHECKER_TYPE,
13008  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_P2P_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_BRIDGE_SRC_BUSECC_GROUP_3_WIDTH },
13009  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_P2P_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_BRIDGE_SRC_BUSECC_GROUP_4_CHECKER_TYPE,
13010  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_P2P_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_BRIDGE_SRC_BUSECC_GROUP_4_WIDTH },
13011  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_P2P_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_BRIDGE_SRC_BUSECC_GROUP_5_CHECKER_TYPE,
13012  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_P2P_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_BRIDGE_SRC_BUSECC_GROUP_5_WIDTH },
13013  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_P2P_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_BRIDGE_SRC_BUSECC_GROUP_6_CHECKER_TYPE,
13014  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_P2P_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_BRIDGE_SRC_BUSECC_GROUP_6_WIDTH },
13015  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_P2P_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_BRIDGE_SRC_BUSECC_GROUP_7_CHECKER_TYPE,
13016  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_P2P_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_BRIDGE_SRC_BUSECC_GROUP_7_WIDTH },
13017  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_P2P_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_BRIDGE_SRC_BUSECC_GROUP_8_CHECKER_TYPE,
13018  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_P2P_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_BRIDGE_SRC_BUSECC_GROUP_8_WIDTH },
13019  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_P2P_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_BRIDGE_SRC_BUSECC_GROUP_9_CHECKER_TYPE,
13020  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_P2P_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_BRIDGE_SRC_BUSECC_GROUP_9_WIDTH },
13021  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_P2P_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_BRIDGE_SRC_BUSECC_GROUP_10_CHECKER_TYPE,
13022  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_P2P_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_BRIDGE_SRC_BUSECC_GROUP_10_WIDTH },
13023  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_P2P_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_BRIDGE_SRC_BUSECC_GROUP_11_CHECKER_TYPE,
13024  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_P2P_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_BRIDGE_SRC_BUSECC_GROUP_11_WIDTH },
13025  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_P2P_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_BRIDGE_SRC_BUSECC_GROUP_12_CHECKER_TYPE,
13026  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_P2P_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_BRIDGE_SRC_BUSECC_GROUP_12_WIDTH },
13027  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_P2P_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_BRIDGE_SRC_BUSECC_GROUP_13_CHECKER_TYPE,
13028  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_P2P_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_BRIDGE_SRC_BUSECC_GROUP_13_WIDTH },
13029  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_P2P_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_BRIDGE_SRC_BUSECC_GROUP_14_CHECKER_TYPE,
13030  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_P2P_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_BRIDGE_SRC_BUSECC_GROUP_14_WIDTH },
13031  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_P2P_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_BRIDGE_SRC_BUSECC_GROUP_15_CHECKER_TYPE,
13032  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_P2P_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_BRIDGE_SRC_BUSECC_GROUP_15_WIDTH },
13033  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_P2P_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_BRIDGE_SRC_BUSECC_GROUP_16_CHECKER_TYPE,
13034  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_P2P_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_BRIDGE_SRC_BUSECC_GROUP_16_WIDTH },
13035 };
13036 
13042 static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_P2P_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_BRIDGE_DST_BUSECC_groupEntries[SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_P2P_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS] =
13043 {
13044  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_P2P_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_BRIDGE_DST_BUSECC_GROUP_0_CHECKER_TYPE,
13045  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_P2P_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_BRIDGE_DST_BUSECC_GROUP_0_WIDTH },
13046  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_P2P_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_BRIDGE_DST_BUSECC_GROUP_1_CHECKER_TYPE,
13047  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_P2P_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_BRIDGE_DST_BUSECC_GROUP_1_WIDTH },
13048  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_P2P_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_BRIDGE_DST_BUSECC_GROUP_2_CHECKER_TYPE,
13049  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_P2P_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_BRIDGE_DST_BUSECC_GROUP_2_WIDTH },
13050  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_P2P_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_BRIDGE_DST_BUSECC_GROUP_3_CHECKER_TYPE,
13051  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_P2P_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_BRIDGE_DST_BUSECC_GROUP_3_WIDTH },
13052  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_P2P_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_BRIDGE_DST_BUSECC_GROUP_4_CHECKER_TYPE,
13053  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_P2P_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_BRIDGE_DST_BUSECC_GROUP_4_WIDTH },
13054 };
13055 
13061 static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_P2M_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_BRIDGE_SRC_BUSECC_groupEntries[SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_P2M_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS] =
13062 {
13063  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_P2M_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_BRIDGE_SRC_BUSECC_GROUP_0_CHECKER_TYPE,
13064  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_P2M_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_BRIDGE_SRC_BUSECC_GROUP_0_WIDTH },
13065  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_P2M_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_BRIDGE_SRC_BUSECC_GROUP_1_CHECKER_TYPE,
13066  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_P2M_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_BRIDGE_SRC_BUSECC_GROUP_1_WIDTH },
13067  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_P2M_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_BRIDGE_SRC_BUSECC_GROUP_2_CHECKER_TYPE,
13068  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_P2M_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_BRIDGE_SRC_BUSECC_GROUP_2_WIDTH },
13069  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_P2M_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_BRIDGE_SRC_BUSECC_GROUP_3_CHECKER_TYPE,
13070  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_P2M_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_BRIDGE_SRC_BUSECC_GROUP_3_WIDTH },
13071  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_P2M_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_BRIDGE_SRC_BUSECC_GROUP_4_CHECKER_TYPE,
13072  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_P2M_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_BRIDGE_SRC_BUSECC_GROUP_4_WIDTH },
13073  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_P2M_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_BRIDGE_SRC_BUSECC_GROUP_5_CHECKER_TYPE,
13074  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_P2M_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_BRIDGE_SRC_BUSECC_GROUP_5_WIDTH },
13075  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_P2M_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_BRIDGE_SRC_BUSECC_GROUP_6_CHECKER_TYPE,
13076  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_P2M_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_BRIDGE_SRC_BUSECC_GROUP_6_WIDTH },
13077  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_P2M_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_BRIDGE_SRC_BUSECC_GROUP_7_CHECKER_TYPE,
13078  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_P2M_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_BRIDGE_SRC_BUSECC_GROUP_7_WIDTH },
13079  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_P2M_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_BRIDGE_SRC_BUSECC_GROUP_8_CHECKER_TYPE,
13080  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_P2M_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_BRIDGE_SRC_BUSECC_GROUP_8_WIDTH },
13081  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_P2M_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_BRIDGE_SRC_BUSECC_GROUP_9_CHECKER_TYPE,
13082  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_P2M_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_BRIDGE_SRC_BUSECC_GROUP_9_WIDTH },
13083  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_P2M_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_BRIDGE_SRC_BUSECC_GROUP_10_CHECKER_TYPE,
13084  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_P2M_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_BRIDGE_SRC_BUSECC_GROUP_10_WIDTH },
13085  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_P2M_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_BRIDGE_SRC_BUSECC_GROUP_11_CHECKER_TYPE,
13086  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_P2M_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_BRIDGE_SRC_BUSECC_GROUP_11_WIDTH },
13087  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_P2M_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_BRIDGE_SRC_BUSECC_GROUP_12_CHECKER_TYPE,
13088  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_P2M_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_BRIDGE_SRC_BUSECC_GROUP_12_WIDTH },
13089  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_P2M_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_BRIDGE_SRC_BUSECC_GROUP_13_CHECKER_TYPE,
13090  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_P2M_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_BRIDGE_SRC_BUSECC_GROUP_13_WIDTH },
13091  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_P2M_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_BRIDGE_SRC_BUSECC_GROUP_14_CHECKER_TYPE,
13092  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_P2M_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_BRIDGE_SRC_BUSECC_GROUP_14_WIDTH },
13093  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_P2M_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_BRIDGE_SRC_BUSECC_GROUP_15_CHECKER_TYPE,
13094  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_P2M_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_BRIDGE_SRC_BUSECC_GROUP_15_WIDTH },
13095  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_P2M_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_BRIDGE_SRC_BUSECC_GROUP_16_CHECKER_TYPE,
13096  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_P2M_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_BRIDGE_SRC_BUSECC_GROUP_16_WIDTH },
13097 };
13098 
13104 static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_P2M_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_BRIDGE_DST_BUSECC_groupEntries[SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_P2M_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS] =
13105 {
13106  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_P2M_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_BRIDGE_DST_BUSECC_GROUP_0_CHECKER_TYPE,
13107  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_P2M_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_BRIDGE_DST_BUSECC_GROUP_0_WIDTH },
13108  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_P2M_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_BRIDGE_DST_BUSECC_GROUP_1_CHECKER_TYPE,
13109  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_P2M_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_BRIDGE_DST_BUSECC_GROUP_1_WIDTH },
13110  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_P2M_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_BRIDGE_DST_BUSECC_GROUP_2_CHECKER_TYPE,
13111  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_P2M_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_BRIDGE_DST_BUSECC_GROUP_2_WIDTH },
13112  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_P2M_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_BRIDGE_DST_BUSECC_GROUP_3_CHECKER_TYPE,
13113  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_P2M_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_BRIDGE_DST_BUSECC_GROUP_3_WIDTH },
13114  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_P2M_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_BRIDGE_DST_BUSECC_GROUP_4_CHECKER_TYPE,
13115  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_P2M_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_BRIDGE_DST_BUSECC_GROUP_4_WIDTH },
13116  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_P2M_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_BRIDGE_DST_BUSECC_GROUP_5_CHECKER_TYPE,
13117  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_P2M_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_BRIDGE_DST_BUSECC_GROUP_5_WIDTH },
13118  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_P2M_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_BRIDGE_DST_BUSECC_GROUP_6_CHECKER_TYPE,
13119  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_P2M_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_BRIDGE_DST_BUSECC_GROUP_6_WIDTH },
13120  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_P2M_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_BRIDGE_DST_BUSECC_GROUP_7_CHECKER_TYPE,
13121  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_P2M_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_BRIDGE_DST_BUSECC_GROUP_7_WIDTH },
13122  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_P2M_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_BRIDGE_DST_BUSECC_GROUP_8_CHECKER_TYPE,
13123  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_P2M_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_BRIDGE_DST_BUSECC_GROUP_8_WIDTH },
13124  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_P2M_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_BRIDGE_DST_BUSECC_GROUP_9_CHECKER_TYPE,
13125  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_P2M_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_BRIDGE_DST_BUSECC_GROUP_9_WIDTH },
13126  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_P2M_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_BRIDGE_DST_BUSECC_GROUP_10_CHECKER_TYPE,
13127  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_P2M_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_BRIDGE_DST_BUSECC_GROUP_10_WIDTH },
13128 };
13129 
13135 static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_BRIDGE_SRC_BUSECC_groupEntries[SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS] =
13136 {
13137  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_BRIDGE_SRC_BUSECC_GROUP_0_CHECKER_TYPE,
13138  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_BRIDGE_SRC_BUSECC_GROUP_0_WIDTH },
13139  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_BRIDGE_SRC_BUSECC_GROUP_1_CHECKER_TYPE,
13140  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_BRIDGE_SRC_BUSECC_GROUP_1_WIDTH },
13141  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_BRIDGE_SRC_BUSECC_GROUP_2_CHECKER_TYPE,
13142  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_BRIDGE_SRC_BUSECC_GROUP_2_WIDTH },
13143  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_BRIDGE_SRC_BUSECC_GROUP_3_CHECKER_TYPE,
13144  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_BRIDGE_SRC_BUSECC_GROUP_3_WIDTH },
13145  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_BRIDGE_SRC_BUSECC_GROUP_4_CHECKER_TYPE,
13146  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_BRIDGE_SRC_BUSECC_GROUP_4_WIDTH },
13147  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_BRIDGE_SRC_BUSECC_GROUP_5_CHECKER_TYPE,
13148  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_BRIDGE_SRC_BUSECC_GROUP_5_WIDTH },
13149  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_BRIDGE_SRC_BUSECC_GROUP_6_CHECKER_TYPE,
13150  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_BRIDGE_SRC_BUSECC_GROUP_6_WIDTH },
13151  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_BRIDGE_SRC_BUSECC_GROUP_7_CHECKER_TYPE,
13152  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_BRIDGE_SRC_BUSECC_GROUP_7_WIDTH },
13153  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_BRIDGE_SRC_BUSECC_GROUP_8_CHECKER_TYPE,
13154  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_BRIDGE_SRC_BUSECC_GROUP_8_WIDTH },
13155  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_BRIDGE_SRC_BUSECC_GROUP_9_CHECKER_TYPE,
13156  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_BRIDGE_SRC_BUSECC_GROUP_9_WIDTH },
13157  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_BRIDGE_SRC_BUSECC_GROUP_10_CHECKER_TYPE,
13158  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_BRIDGE_SRC_BUSECC_GROUP_10_WIDTH },
13159  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_BRIDGE_SRC_BUSECC_GROUP_11_CHECKER_TYPE,
13160  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_BRIDGE_SRC_BUSECC_GROUP_11_WIDTH },
13161  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_BRIDGE_SRC_BUSECC_GROUP_12_CHECKER_TYPE,
13162  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_BRIDGE_SRC_BUSECC_GROUP_12_WIDTH },
13163  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_BRIDGE_SRC_BUSECC_GROUP_13_CHECKER_TYPE,
13164  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_BRIDGE_SRC_BUSECC_GROUP_13_WIDTH },
13165  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_BRIDGE_SRC_BUSECC_GROUP_14_CHECKER_TYPE,
13166  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_BRIDGE_SRC_BUSECC_GROUP_14_WIDTH },
13167  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_BRIDGE_SRC_BUSECC_GROUP_15_CHECKER_TYPE,
13168  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_BRIDGE_SRC_BUSECC_GROUP_15_WIDTH },
13169  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_BRIDGE_SRC_BUSECC_GROUP_16_CHECKER_TYPE,
13170  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_BRIDGE_SRC_BUSECC_GROUP_16_WIDTH },
13171 };
13172 
13178 static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_BRIDGE_DST_BUSECC_groupEntries[SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS] =
13179 {
13180  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_BRIDGE_DST_BUSECC_GROUP_0_CHECKER_TYPE,
13181  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_BRIDGE_DST_BUSECC_GROUP_0_WIDTH },
13182  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_BRIDGE_DST_BUSECC_GROUP_1_CHECKER_TYPE,
13183  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_BRIDGE_DST_BUSECC_GROUP_1_WIDTH },
13184  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_BRIDGE_DST_BUSECC_GROUP_2_CHECKER_TYPE,
13185  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_BRIDGE_DST_BUSECC_GROUP_2_WIDTH },
13186  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_BRIDGE_DST_BUSECC_GROUP_3_CHECKER_TYPE,
13187  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_BRIDGE_DST_BUSECC_GROUP_3_WIDTH },
13188  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_BRIDGE_DST_BUSECC_GROUP_4_CHECKER_TYPE,
13189  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_BRIDGE_DST_BUSECC_GROUP_4_WIDTH },
13190  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_BRIDGE_DST_BUSECC_GROUP_5_CHECKER_TYPE,
13191  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_BRIDGE_DST_BUSECC_GROUP_5_WIDTH },
13192  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_BRIDGE_DST_BUSECC_GROUP_6_CHECKER_TYPE,
13193  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_BRIDGE_DST_BUSECC_GROUP_6_WIDTH },
13194  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_BRIDGE_DST_BUSECC_GROUP_7_CHECKER_TYPE,
13195  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_BRIDGE_DST_BUSECC_GROUP_7_WIDTH },
13196  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_BRIDGE_DST_BUSECC_GROUP_8_CHECKER_TYPE,
13197  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_BRIDGE_DST_BUSECC_GROUP_8_WIDTH },
13198  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_BRIDGE_DST_BUSECC_GROUP_9_CHECKER_TYPE,
13199  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_BRIDGE_DST_BUSECC_GROUP_9_WIDTH },
13200  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_BRIDGE_DST_BUSECC_GROUP_10_CHECKER_TYPE,
13201  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_BRIDGE_DST_BUSECC_GROUP_10_WIDTH },
13202  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_BRIDGE_DST_BUSECC_GROUP_11_CHECKER_TYPE,
13203  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_BRIDGE_DST_BUSECC_GROUP_11_WIDTH },
13204  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_BRIDGE_DST_BUSECC_GROUP_12_CHECKER_TYPE,
13205  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_BRIDGE_DST_BUSECC_GROUP_12_WIDTH },
13206  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_BRIDGE_DST_BUSECC_GROUP_13_CHECKER_TYPE,
13207  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_BRIDGE_DST_BUSECC_GROUP_13_WIDTH },
13208 };
13209 
13215 static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IPULSAR_ULS_MCU_0_CPU0_CFG_SLV_P2P_BRIDGE_IPULSAR_ULS_MCU_0_CPU0_CFG_SLV_BRIDGE_BUSECC_groupEntries[SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IPULSAR_ULS_MCU_0_CPU0_CFG_SLV_P2P_BRIDGE_IPULSAR_ULS_MCU_0_CPU0_CFG_SLV_BRIDGE_BUSECC_MAX_NUM_CHECKERS] =
13216 {
13217  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IPULSAR_ULS_MCU_0_CPU0_CFG_SLV_P2P_BRIDGE_IPULSAR_ULS_MCU_0_CPU0_CFG_SLV_BRIDGE_BUSECC_GROUP_0_CHECKER_TYPE,
13218  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IPULSAR_ULS_MCU_0_CPU0_CFG_SLV_P2P_BRIDGE_IPULSAR_ULS_MCU_0_CPU0_CFG_SLV_BRIDGE_BUSECC_GROUP_0_WIDTH },
13219  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IPULSAR_ULS_MCU_0_CPU0_CFG_SLV_P2P_BRIDGE_IPULSAR_ULS_MCU_0_CPU0_CFG_SLV_BRIDGE_BUSECC_GROUP_1_CHECKER_TYPE,
13220  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IPULSAR_ULS_MCU_0_CPU0_CFG_SLV_P2P_BRIDGE_IPULSAR_ULS_MCU_0_CPU0_CFG_SLV_BRIDGE_BUSECC_GROUP_1_WIDTH },
13221  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IPULSAR_ULS_MCU_0_CPU0_CFG_SLV_P2P_BRIDGE_IPULSAR_ULS_MCU_0_CPU0_CFG_SLV_BRIDGE_BUSECC_GROUP_2_CHECKER_TYPE,
13222  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IPULSAR_ULS_MCU_0_CPU0_CFG_SLV_P2P_BRIDGE_IPULSAR_ULS_MCU_0_CPU0_CFG_SLV_BRIDGE_BUSECC_GROUP_2_WIDTH },
13223  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IPULSAR_ULS_MCU_0_CPU0_CFG_SLV_P2P_BRIDGE_IPULSAR_ULS_MCU_0_CPU0_CFG_SLV_BRIDGE_BUSECC_GROUP_3_CHECKER_TYPE,
13224  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IPULSAR_ULS_MCU_0_CPU0_CFG_SLV_P2P_BRIDGE_IPULSAR_ULS_MCU_0_CPU0_CFG_SLV_BRIDGE_BUSECC_GROUP_3_WIDTH },
13225  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IPULSAR_ULS_MCU_0_CPU0_CFG_SLV_P2P_BRIDGE_IPULSAR_ULS_MCU_0_CPU0_CFG_SLV_BRIDGE_BUSECC_GROUP_4_CHECKER_TYPE,
13226  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IPULSAR_ULS_MCU_0_CPU0_CFG_SLV_P2P_BRIDGE_IPULSAR_ULS_MCU_0_CPU0_CFG_SLV_BRIDGE_BUSECC_GROUP_4_WIDTH },
13227  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IPULSAR_ULS_MCU_0_CPU0_CFG_SLV_P2P_BRIDGE_IPULSAR_ULS_MCU_0_CPU0_CFG_SLV_BRIDGE_BUSECC_GROUP_5_CHECKER_TYPE,
13228  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IPULSAR_ULS_MCU_0_CPU0_CFG_SLV_P2P_BRIDGE_IPULSAR_ULS_MCU_0_CPU0_CFG_SLV_BRIDGE_BUSECC_GROUP_5_WIDTH },
13229  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IPULSAR_ULS_MCU_0_CPU0_CFG_SLV_P2P_BRIDGE_IPULSAR_ULS_MCU_0_CPU0_CFG_SLV_BRIDGE_BUSECC_GROUP_6_CHECKER_TYPE,
13230  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IPULSAR_ULS_MCU_0_CPU0_CFG_SLV_P2P_BRIDGE_IPULSAR_ULS_MCU_0_CPU0_CFG_SLV_BRIDGE_BUSECC_GROUP_6_WIDTH },
13231  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IPULSAR_ULS_MCU_0_CPU0_CFG_SLV_P2P_BRIDGE_IPULSAR_ULS_MCU_0_CPU0_CFG_SLV_BRIDGE_BUSECC_GROUP_7_CHECKER_TYPE,
13232  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IPULSAR_ULS_MCU_0_CPU0_CFG_SLV_P2P_BRIDGE_IPULSAR_ULS_MCU_0_CPU0_CFG_SLV_BRIDGE_BUSECC_GROUP_7_WIDTH },
13233  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IPULSAR_ULS_MCU_0_CPU0_CFG_SLV_P2P_BRIDGE_IPULSAR_ULS_MCU_0_CPU0_CFG_SLV_BRIDGE_BUSECC_GROUP_8_CHECKER_TYPE,
13234  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IPULSAR_ULS_MCU_0_CPU0_CFG_SLV_P2P_BRIDGE_IPULSAR_ULS_MCU_0_CPU0_CFG_SLV_BRIDGE_BUSECC_GROUP_8_WIDTH },
13235  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IPULSAR_ULS_MCU_0_CPU0_CFG_SLV_P2P_BRIDGE_IPULSAR_ULS_MCU_0_CPU0_CFG_SLV_BRIDGE_BUSECC_GROUP_9_CHECKER_TYPE,
13236  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IPULSAR_ULS_MCU_0_CPU0_CFG_SLV_P2P_BRIDGE_IPULSAR_ULS_MCU_0_CPU0_CFG_SLV_BRIDGE_BUSECC_GROUP_9_WIDTH },
13237  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IPULSAR_ULS_MCU_0_CPU0_CFG_SLV_P2P_BRIDGE_IPULSAR_ULS_MCU_0_CPU0_CFG_SLV_BRIDGE_BUSECC_GROUP_10_CHECKER_TYPE,
13238  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IPULSAR_ULS_MCU_0_CPU0_CFG_SLV_P2P_BRIDGE_IPULSAR_ULS_MCU_0_CPU0_CFG_SLV_BRIDGE_BUSECC_GROUP_10_WIDTH },
13239  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IPULSAR_ULS_MCU_0_CPU0_CFG_SLV_P2P_BRIDGE_IPULSAR_ULS_MCU_0_CPU0_CFG_SLV_BRIDGE_BUSECC_GROUP_11_CHECKER_TYPE,
13240  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IPULSAR_ULS_MCU_0_CPU0_CFG_SLV_P2P_BRIDGE_IPULSAR_ULS_MCU_0_CPU0_CFG_SLV_BRIDGE_BUSECC_GROUP_11_WIDTH },
13241  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IPULSAR_ULS_MCU_0_CPU0_CFG_SLV_P2P_BRIDGE_IPULSAR_ULS_MCU_0_CPU0_CFG_SLV_BRIDGE_BUSECC_GROUP_12_CHECKER_TYPE,
13242  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IPULSAR_ULS_MCU_0_CPU0_CFG_SLV_P2P_BRIDGE_IPULSAR_ULS_MCU_0_CPU0_CFG_SLV_BRIDGE_BUSECC_GROUP_12_WIDTH },
13243 };
13244 
13250 static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IMSRAM32KX64E_MCU_1_CFG_P2P_BRIDGE_IMSRAM32KX64E_MCU_1_CFG_BRIDGE_BUSECC_groupEntries[SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IMSRAM32KX64E_MCU_1_CFG_P2P_BRIDGE_IMSRAM32KX64E_MCU_1_CFG_BRIDGE_BUSECC_MAX_NUM_CHECKERS] =
13251 {
13252  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IMSRAM32KX64E_MCU_1_CFG_P2P_BRIDGE_IMSRAM32KX64E_MCU_1_CFG_BRIDGE_BUSECC_GROUP_0_CHECKER_TYPE,
13253  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IMSRAM32KX64E_MCU_1_CFG_P2P_BRIDGE_IMSRAM32KX64E_MCU_1_CFG_BRIDGE_BUSECC_GROUP_0_WIDTH },
13254  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IMSRAM32KX64E_MCU_1_CFG_P2P_BRIDGE_IMSRAM32KX64E_MCU_1_CFG_BRIDGE_BUSECC_GROUP_1_CHECKER_TYPE,
13255  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IMSRAM32KX64E_MCU_1_CFG_P2P_BRIDGE_IMSRAM32KX64E_MCU_1_CFG_BRIDGE_BUSECC_GROUP_1_WIDTH },
13256  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IMSRAM32KX64E_MCU_1_CFG_P2P_BRIDGE_IMSRAM32KX64E_MCU_1_CFG_BRIDGE_BUSECC_GROUP_2_CHECKER_TYPE,
13257  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IMSRAM32KX64E_MCU_1_CFG_P2P_BRIDGE_IMSRAM32KX64E_MCU_1_CFG_BRIDGE_BUSECC_GROUP_2_WIDTH },
13258  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IMSRAM32KX64E_MCU_1_CFG_P2P_BRIDGE_IMSRAM32KX64E_MCU_1_CFG_BRIDGE_BUSECC_GROUP_3_CHECKER_TYPE,
13259  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IMSRAM32KX64E_MCU_1_CFG_P2P_BRIDGE_IMSRAM32KX64E_MCU_1_CFG_BRIDGE_BUSECC_GROUP_3_WIDTH },
13260  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IMSRAM32KX64E_MCU_1_CFG_P2P_BRIDGE_IMSRAM32KX64E_MCU_1_CFG_BRIDGE_BUSECC_GROUP_4_CHECKER_TYPE,
13261  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IMSRAM32KX64E_MCU_1_CFG_P2P_BRIDGE_IMSRAM32KX64E_MCU_1_CFG_BRIDGE_BUSECC_GROUP_4_WIDTH },
13262  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IMSRAM32KX64E_MCU_1_CFG_P2P_BRIDGE_IMSRAM32KX64E_MCU_1_CFG_BRIDGE_BUSECC_GROUP_5_CHECKER_TYPE,
13263  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IMSRAM32KX64E_MCU_1_CFG_P2P_BRIDGE_IMSRAM32KX64E_MCU_1_CFG_BRIDGE_BUSECC_GROUP_5_WIDTH },
13264  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IMSRAM32KX64E_MCU_1_CFG_P2P_BRIDGE_IMSRAM32KX64E_MCU_1_CFG_BRIDGE_BUSECC_GROUP_6_CHECKER_TYPE,
13265  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IMSRAM32KX64E_MCU_1_CFG_P2P_BRIDGE_IMSRAM32KX64E_MCU_1_CFG_BRIDGE_BUSECC_GROUP_6_WIDTH },
13266  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IMSRAM32KX64E_MCU_1_CFG_P2P_BRIDGE_IMSRAM32KX64E_MCU_1_CFG_BRIDGE_BUSECC_GROUP_7_CHECKER_TYPE,
13267  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IMSRAM32KX64E_MCU_1_CFG_P2P_BRIDGE_IMSRAM32KX64E_MCU_1_CFG_BRIDGE_BUSECC_GROUP_7_WIDTH },
13268  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IMSRAM32KX64E_MCU_1_CFG_P2P_BRIDGE_IMSRAM32KX64E_MCU_1_CFG_BRIDGE_BUSECC_GROUP_8_CHECKER_TYPE,
13269  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IMSRAM32KX64E_MCU_1_CFG_P2P_BRIDGE_IMSRAM32KX64E_MCU_1_CFG_BRIDGE_BUSECC_GROUP_8_WIDTH },
13270  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IMSRAM32KX64E_MCU_1_CFG_P2P_BRIDGE_IMSRAM32KX64E_MCU_1_CFG_BRIDGE_BUSECC_GROUP_9_CHECKER_TYPE,
13271  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IMSRAM32KX64E_MCU_1_CFG_P2P_BRIDGE_IMSRAM32KX64E_MCU_1_CFG_BRIDGE_BUSECC_GROUP_9_WIDTH },
13272  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IMSRAM32KX64E_MCU_1_CFG_P2P_BRIDGE_IMSRAM32KX64E_MCU_1_CFG_BRIDGE_BUSECC_GROUP_10_CHECKER_TYPE,
13273  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IMSRAM32KX64E_MCU_1_CFG_P2P_BRIDGE_IMSRAM32KX64E_MCU_1_CFG_BRIDGE_BUSECC_GROUP_10_WIDTH },
13274  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IMSRAM32KX64E_MCU_1_CFG_P2P_BRIDGE_IMSRAM32KX64E_MCU_1_CFG_BRIDGE_BUSECC_GROUP_11_CHECKER_TYPE,
13275  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IMSRAM32KX64E_MCU_1_CFG_P2P_BRIDGE_IMSRAM32KX64E_MCU_1_CFG_BRIDGE_BUSECC_GROUP_11_WIDTH },
13276  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IMSRAM32KX64E_MCU_1_CFG_P2P_BRIDGE_IMSRAM32KX64E_MCU_1_CFG_BRIDGE_BUSECC_GROUP_12_CHECKER_TYPE,
13277  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IMSRAM32KX64E_MCU_1_CFG_P2P_BRIDGE_IMSRAM32KX64E_MCU_1_CFG_BRIDGE_BUSECC_GROUP_12_WIDTH },
13278 };
13279 
13285 static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ISAM62A_MCU_PULSAR_UL_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM62A_MCU_PULSAR_UL_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_groupEntries[SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ISAM62A_MCU_PULSAR_UL_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM62A_MCU_PULSAR_UL_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_MAX_NUM_CHECKERS] =
13286 {
13287  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ISAM62A_MCU_PULSAR_UL_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM62A_MCU_PULSAR_UL_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_GROUP_0_CHECKER_TYPE,
13288  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ISAM62A_MCU_PULSAR_UL_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM62A_MCU_PULSAR_UL_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_GROUP_0_WIDTH },
13289  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ISAM62A_MCU_PULSAR_UL_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM62A_MCU_PULSAR_UL_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_GROUP_1_CHECKER_TYPE,
13290  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ISAM62A_MCU_PULSAR_UL_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM62A_MCU_PULSAR_UL_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_GROUP_1_WIDTH },
13291  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ISAM62A_MCU_PULSAR_UL_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM62A_MCU_PULSAR_UL_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_GROUP_2_CHECKER_TYPE,
13292  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ISAM62A_MCU_PULSAR_UL_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM62A_MCU_PULSAR_UL_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_GROUP_2_WIDTH },
13293  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ISAM62A_MCU_PULSAR_UL_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM62A_MCU_PULSAR_UL_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_GROUP_3_CHECKER_TYPE,
13294  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ISAM62A_MCU_PULSAR_UL_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM62A_MCU_PULSAR_UL_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_GROUP_3_WIDTH },
13295  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ISAM62A_MCU_PULSAR_UL_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM62A_MCU_PULSAR_UL_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_GROUP_4_CHECKER_TYPE,
13296  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ISAM62A_MCU_PULSAR_UL_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM62A_MCU_PULSAR_UL_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_GROUP_4_WIDTH },
13297  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ISAM62A_MCU_PULSAR_UL_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM62A_MCU_PULSAR_UL_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_GROUP_5_CHECKER_TYPE,
13298  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ISAM62A_MCU_PULSAR_UL_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM62A_MCU_PULSAR_UL_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_GROUP_5_WIDTH },
13299  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ISAM62A_MCU_PULSAR_UL_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM62A_MCU_PULSAR_UL_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_GROUP_6_CHECKER_TYPE,
13300  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ISAM62A_MCU_PULSAR_UL_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM62A_MCU_PULSAR_UL_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_GROUP_6_WIDTH },
13301  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ISAM62A_MCU_PULSAR_UL_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM62A_MCU_PULSAR_UL_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_GROUP_7_CHECKER_TYPE,
13302  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ISAM62A_MCU_PULSAR_UL_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM62A_MCU_PULSAR_UL_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_GROUP_7_WIDTH },
13303  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ISAM62A_MCU_PULSAR_UL_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM62A_MCU_PULSAR_UL_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_GROUP_8_CHECKER_TYPE,
13304  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ISAM62A_MCU_PULSAR_UL_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM62A_MCU_PULSAR_UL_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_GROUP_8_WIDTH },
13305  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ISAM62A_MCU_PULSAR_UL_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM62A_MCU_PULSAR_UL_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_GROUP_9_CHECKER_TYPE,
13306  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ISAM62A_MCU_PULSAR_UL_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM62A_MCU_PULSAR_UL_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_GROUP_9_WIDTH },
13307  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ISAM62A_MCU_PULSAR_UL_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM62A_MCU_PULSAR_UL_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_GROUP_10_CHECKER_TYPE,
13308  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ISAM62A_MCU_PULSAR_UL_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM62A_MCU_PULSAR_UL_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_GROUP_10_WIDTH },
13309  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ISAM62A_MCU_PULSAR_UL_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM62A_MCU_PULSAR_UL_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_GROUP_11_CHECKER_TYPE,
13310  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ISAM62A_MCU_PULSAR_UL_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM62A_MCU_PULSAR_UL_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_GROUP_11_WIDTH },
13311  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ISAM62A_MCU_PULSAR_UL_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM62A_MCU_PULSAR_UL_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_GROUP_12_CHECKER_TYPE,
13312  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ISAM62A_MCU_PULSAR_UL_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM62A_MCU_PULSAR_UL_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_GROUP_12_WIDTH },
13313 };
13314 
13320 static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IMSRAM32KX64E_MCU_0_CFG_P2P_BRIDGE_IMSRAM32KX64E_MCU_0_CFG_BRIDGE_BUSECC_groupEntries[SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IMSRAM32KX64E_MCU_0_CFG_P2P_BRIDGE_IMSRAM32KX64E_MCU_0_CFG_BRIDGE_BUSECC_MAX_NUM_CHECKERS] =
13321 {
13322  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IMSRAM32KX64E_MCU_0_CFG_P2P_BRIDGE_IMSRAM32KX64E_MCU_0_CFG_BRIDGE_BUSECC_GROUP_0_CHECKER_TYPE,
13323  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IMSRAM32KX64E_MCU_0_CFG_P2P_BRIDGE_IMSRAM32KX64E_MCU_0_CFG_BRIDGE_BUSECC_GROUP_0_WIDTH },
13324  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IMSRAM32KX64E_MCU_0_CFG_P2P_BRIDGE_IMSRAM32KX64E_MCU_0_CFG_BRIDGE_BUSECC_GROUP_1_CHECKER_TYPE,
13325  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IMSRAM32KX64E_MCU_0_CFG_P2P_BRIDGE_IMSRAM32KX64E_MCU_0_CFG_BRIDGE_BUSECC_GROUP_1_WIDTH },
13326  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IMSRAM32KX64E_MCU_0_CFG_P2P_BRIDGE_IMSRAM32KX64E_MCU_0_CFG_BRIDGE_BUSECC_GROUP_2_CHECKER_TYPE,
13327  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IMSRAM32KX64E_MCU_0_CFG_P2P_BRIDGE_IMSRAM32KX64E_MCU_0_CFG_BRIDGE_BUSECC_GROUP_2_WIDTH },
13328  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IMSRAM32KX64E_MCU_0_CFG_P2P_BRIDGE_IMSRAM32KX64E_MCU_0_CFG_BRIDGE_BUSECC_GROUP_3_CHECKER_TYPE,
13329  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IMSRAM32KX64E_MCU_0_CFG_P2P_BRIDGE_IMSRAM32KX64E_MCU_0_CFG_BRIDGE_BUSECC_GROUP_3_WIDTH },
13330  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IMSRAM32KX64E_MCU_0_CFG_P2P_BRIDGE_IMSRAM32KX64E_MCU_0_CFG_BRIDGE_BUSECC_GROUP_4_CHECKER_TYPE,
13331  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IMSRAM32KX64E_MCU_0_CFG_P2P_BRIDGE_IMSRAM32KX64E_MCU_0_CFG_BRIDGE_BUSECC_GROUP_4_WIDTH },
13332  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IMSRAM32KX64E_MCU_0_CFG_P2P_BRIDGE_IMSRAM32KX64E_MCU_0_CFG_BRIDGE_BUSECC_GROUP_5_CHECKER_TYPE,
13333  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IMSRAM32KX64E_MCU_0_CFG_P2P_BRIDGE_IMSRAM32KX64E_MCU_0_CFG_BRIDGE_BUSECC_GROUP_5_WIDTH },
13334  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IMSRAM32KX64E_MCU_0_CFG_P2P_BRIDGE_IMSRAM32KX64E_MCU_0_CFG_BRIDGE_BUSECC_GROUP_6_CHECKER_TYPE,
13335  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IMSRAM32KX64E_MCU_0_CFG_P2P_BRIDGE_IMSRAM32KX64E_MCU_0_CFG_BRIDGE_BUSECC_GROUP_6_WIDTH },
13336  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IMSRAM32KX64E_MCU_0_CFG_P2P_BRIDGE_IMSRAM32KX64E_MCU_0_CFG_BRIDGE_BUSECC_GROUP_7_CHECKER_TYPE,
13337  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IMSRAM32KX64E_MCU_0_CFG_P2P_BRIDGE_IMSRAM32KX64E_MCU_0_CFG_BRIDGE_BUSECC_GROUP_7_WIDTH },
13338  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IMSRAM32KX64E_MCU_0_CFG_P2P_BRIDGE_IMSRAM32KX64E_MCU_0_CFG_BRIDGE_BUSECC_GROUP_8_CHECKER_TYPE,
13339  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IMSRAM32KX64E_MCU_0_CFG_P2P_BRIDGE_IMSRAM32KX64E_MCU_0_CFG_BRIDGE_BUSECC_GROUP_8_WIDTH },
13340  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IMSRAM32KX64E_MCU_0_CFG_P2P_BRIDGE_IMSRAM32KX64E_MCU_0_CFG_BRIDGE_BUSECC_GROUP_9_CHECKER_TYPE,
13341  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IMSRAM32KX64E_MCU_0_CFG_P2P_BRIDGE_IMSRAM32KX64E_MCU_0_CFG_BRIDGE_BUSECC_GROUP_9_WIDTH },
13342  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IMSRAM32KX64E_MCU_0_CFG_P2P_BRIDGE_IMSRAM32KX64E_MCU_0_CFG_BRIDGE_BUSECC_GROUP_10_CHECKER_TYPE,
13343  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IMSRAM32KX64E_MCU_0_CFG_P2P_BRIDGE_IMSRAM32KX64E_MCU_0_CFG_BRIDGE_BUSECC_GROUP_10_WIDTH },
13344  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IMSRAM32KX64E_MCU_0_CFG_P2P_BRIDGE_IMSRAM32KX64E_MCU_0_CFG_BRIDGE_BUSECC_GROUP_11_CHECKER_TYPE,
13345  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IMSRAM32KX64E_MCU_0_CFG_P2P_BRIDGE_IMSRAM32KX64E_MCU_0_CFG_BRIDGE_BUSECC_GROUP_11_WIDTH },
13346  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IMSRAM32KX64E_MCU_0_CFG_P2P_BRIDGE_IMSRAM32KX64E_MCU_0_CFG_BRIDGE_BUSECC_GROUP_12_CHECKER_TYPE,
13347  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IMSRAM32KX64E_MCU_0_CFG_P2P_BRIDGE_IMSRAM32KX64E_MCU_0_CFG_BRIDGE_BUSECC_GROUP_12_WIDTH },
13348 };
13349 
13355 static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_EXPORT_AM67_MCU_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM67_MCU_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_SRC_BUSECC_groupEntries[SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_EXPORT_AM67_MCU_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM67_MCU_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS] =
13356 {
13357  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_EXPORT_AM67_MCU_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM67_MCU_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_SRC_BUSECC_GROUP_0_CHECKER_TYPE,
13358  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_EXPORT_AM67_MCU_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM67_MCU_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_SRC_BUSECC_GROUP_0_WIDTH },
13359  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_EXPORT_AM67_MCU_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM67_MCU_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_SRC_BUSECC_GROUP_1_CHECKER_TYPE,
13360  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_EXPORT_AM67_MCU_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM67_MCU_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_SRC_BUSECC_GROUP_1_WIDTH },
13361  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_EXPORT_AM67_MCU_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM67_MCU_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_SRC_BUSECC_GROUP_2_CHECKER_TYPE,
13362  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_EXPORT_AM67_MCU_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM67_MCU_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_SRC_BUSECC_GROUP_2_WIDTH },
13363  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_EXPORT_AM67_MCU_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM67_MCU_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_SRC_BUSECC_GROUP_3_CHECKER_TYPE,
13364  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_EXPORT_AM67_MCU_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM67_MCU_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_SRC_BUSECC_GROUP_3_WIDTH },
13365  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_EXPORT_AM67_MCU_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM67_MCU_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_SRC_BUSECC_GROUP_4_CHECKER_TYPE,
13366  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_EXPORT_AM67_MCU_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM67_MCU_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_SRC_BUSECC_GROUP_4_WIDTH },
13367  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_EXPORT_AM67_MCU_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM67_MCU_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_SRC_BUSECC_GROUP_5_CHECKER_TYPE,
13368  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_EXPORT_AM67_MCU_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM67_MCU_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_SRC_BUSECC_GROUP_5_WIDTH },
13369  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_EXPORT_AM67_MCU_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM67_MCU_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_SRC_BUSECC_GROUP_6_CHECKER_TYPE,
13370  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_EXPORT_AM67_MCU_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM67_MCU_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_SRC_BUSECC_GROUP_6_WIDTH },
13371  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_EXPORT_AM67_MCU_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM67_MCU_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_SRC_BUSECC_GROUP_7_CHECKER_TYPE,
13372  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_EXPORT_AM67_MCU_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM67_MCU_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_SRC_BUSECC_GROUP_7_WIDTH },
13373  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_EXPORT_AM67_MCU_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM67_MCU_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_SRC_BUSECC_GROUP_8_CHECKER_TYPE,
13374  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_EXPORT_AM67_MCU_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM67_MCU_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_SRC_BUSECC_GROUP_8_WIDTH },
13375  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_EXPORT_AM67_MCU_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM67_MCU_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_SRC_BUSECC_GROUP_9_CHECKER_TYPE,
13376  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_EXPORT_AM67_MCU_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM67_MCU_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_SRC_BUSECC_GROUP_9_WIDTH },
13377  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_EXPORT_AM67_MCU_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM67_MCU_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_SRC_BUSECC_GROUP_10_CHECKER_TYPE,
13378  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_EXPORT_AM67_MCU_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM67_MCU_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_SRC_BUSECC_GROUP_10_WIDTH },
13379  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_EXPORT_AM67_MCU_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM67_MCU_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_SRC_BUSECC_GROUP_11_CHECKER_TYPE,
13380  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_EXPORT_AM67_MCU_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM67_MCU_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_SRC_BUSECC_GROUP_11_WIDTH },
13381  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_EXPORT_AM67_MCU_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM67_MCU_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_SRC_BUSECC_GROUP_12_CHECKER_TYPE,
13382  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_EXPORT_AM67_MCU_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM67_MCU_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_SRC_BUSECC_GROUP_12_WIDTH },
13383  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_EXPORT_AM67_MCU_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM67_MCU_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_SRC_BUSECC_GROUP_13_CHECKER_TYPE,
13384  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_EXPORT_AM67_MCU_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM67_MCU_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_SRC_BUSECC_GROUP_13_WIDTH },
13385  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_EXPORT_AM67_MCU_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM67_MCU_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_SRC_BUSECC_GROUP_14_CHECKER_TYPE,
13386  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_EXPORT_AM67_MCU_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM67_MCU_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_SRC_BUSECC_GROUP_14_WIDTH },
13387  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_EXPORT_AM67_MCU_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM67_MCU_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_SRC_BUSECC_GROUP_15_CHECKER_TYPE,
13388  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_EXPORT_AM67_MCU_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM67_MCU_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_SRC_BUSECC_GROUP_15_WIDTH },
13389  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_EXPORT_AM67_MCU_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM67_MCU_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_SRC_BUSECC_GROUP_16_CHECKER_TYPE,
13390  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_EXPORT_AM67_MCU_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM67_MCU_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_SRC_BUSECC_GROUP_16_WIDTH },
13391 };
13392 
13398 static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_EXPORT_AM67_MCU_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM67_MCU_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_DST_BUSECC_groupEntries[SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_EXPORT_AM67_MCU_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM67_MCU_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS] =
13399 {
13400  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_EXPORT_AM67_MCU_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM67_MCU_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_DST_BUSECC_GROUP_0_CHECKER_TYPE,
13401  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_EXPORT_AM67_MCU_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM67_MCU_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_DST_BUSECC_GROUP_0_WIDTH },
13402  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_EXPORT_AM67_MCU_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM67_MCU_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_DST_BUSECC_GROUP_1_CHECKER_TYPE,
13403  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_EXPORT_AM67_MCU_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM67_MCU_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_DST_BUSECC_GROUP_1_WIDTH },
13404  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_EXPORT_AM67_MCU_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM67_MCU_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_DST_BUSECC_GROUP_2_CHECKER_TYPE,
13405  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_EXPORT_AM67_MCU_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM67_MCU_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_DST_BUSECC_GROUP_2_WIDTH },
13406  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_EXPORT_AM67_MCU_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM67_MCU_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_DST_BUSECC_GROUP_3_CHECKER_TYPE,
13407  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_EXPORT_AM67_MCU_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM67_MCU_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_DST_BUSECC_GROUP_3_WIDTH },
13408  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_EXPORT_AM67_MCU_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM67_MCU_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_DST_BUSECC_GROUP_4_CHECKER_TYPE,
13409  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_EXPORT_AM67_MCU_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM67_MCU_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_DST_BUSECC_GROUP_4_WIDTH },
13410  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_EXPORT_AM67_MCU_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM67_MCU_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_DST_BUSECC_GROUP_5_CHECKER_TYPE,
13411  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_EXPORT_AM67_MCU_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM67_MCU_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_DST_BUSECC_GROUP_5_WIDTH },
13412  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_EXPORT_AM67_MCU_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM67_MCU_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_DST_BUSECC_GROUP_6_CHECKER_TYPE,
13413  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_EXPORT_AM67_MCU_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM67_MCU_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_DST_BUSECC_GROUP_6_WIDTH },
13414  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_EXPORT_AM67_MCU_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM67_MCU_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_DST_BUSECC_GROUP_7_CHECKER_TYPE,
13415  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_EXPORT_AM67_MCU_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM67_MCU_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_DST_BUSECC_GROUP_7_WIDTH },
13416  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_EXPORT_AM67_MCU_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM67_MCU_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_DST_BUSECC_GROUP_8_CHECKER_TYPE,
13417  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_EXPORT_AM67_MCU_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM67_MCU_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_DST_BUSECC_GROUP_8_WIDTH },
13418  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_EXPORT_AM67_MCU_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM67_MCU_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_DST_BUSECC_GROUP_9_CHECKER_TYPE,
13419  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_EXPORT_AM67_MCU_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM67_MCU_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_DST_BUSECC_GROUP_9_WIDTH },
13420  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_EXPORT_AM67_MCU_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM67_MCU_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_DST_BUSECC_GROUP_10_CHECKER_TYPE,
13421  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_EXPORT_AM67_MCU_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM67_MCU_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_DST_BUSECC_GROUP_10_WIDTH },
13422  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_EXPORT_AM67_MCU_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM67_MCU_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_DST_BUSECC_GROUP_11_CHECKER_TYPE,
13423  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_EXPORT_AM67_MCU_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM67_MCU_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_DST_BUSECC_GROUP_11_WIDTH },
13424  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_EXPORT_AM67_MCU_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM67_MCU_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_DST_BUSECC_GROUP_12_CHECKER_TYPE,
13425  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_EXPORT_AM67_MCU_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM67_MCU_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_DST_BUSECC_GROUP_12_WIDTH },
13426  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_EXPORT_AM67_MCU_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM67_MCU_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_DST_BUSECC_GROUP_13_CHECKER_TYPE,
13427  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_EXPORT_AM67_MCU_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM67_MCU_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_DST_BUSECC_GROUP_13_WIDTH },
13428 };
13429 
13435 static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ISAM67_MCU_MCU_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM67_MCU_MCU_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_groupEntries[SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ISAM67_MCU_MCU_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM67_MCU_MCU_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_MAX_NUM_CHECKERS] =
13436 {
13437  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ISAM67_MCU_MCU_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM67_MCU_MCU_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_GROUP_0_CHECKER_TYPE,
13438  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ISAM67_MCU_MCU_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM67_MCU_MCU_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_GROUP_0_WIDTH },
13439  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ISAM67_MCU_MCU_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM67_MCU_MCU_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_GROUP_1_CHECKER_TYPE,
13440  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ISAM67_MCU_MCU_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM67_MCU_MCU_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_GROUP_1_WIDTH },
13441  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ISAM67_MCU_MCU_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM67_MCU_MCU_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_GROUP_2_CHECKER_TYPE,
13442  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ISAM67_MCU_MCU_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM67_MCU_MCU_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_GROUP_2_WIDTH },
13443  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ISAM67_MCU_MCU_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM67_MCU_MCU_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_GROUP_3_CHECKER_TYPE,
13444  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ISAM67_MCU_MCU_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM67_MCU_MCU_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_GROUP_3_WIDTH },
13445  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ISAM67_MCU_MCU_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM67_MCU_MCU_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_GROUP_4_CHECKER_TYPE,
13446  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ISAM67_MCU_MCU_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM67_MCU_MCU_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_GROUP_4_WIDTH },
13447  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ISAM67_MCU_MCU_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM67_MCU_MCU_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_GROUP_5_CHECKER_TYPE,
13448  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ISAM67_MCU_MCU_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM67_MCU_MCU_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_GROUP_5_WIDTH },
13449  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ISAM67_MCU_MCU_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM67_MCU_MCU_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_GROUP_6_CHECKER_TYPE,
13450  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ISAM67_MCU_MCU_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM67_MCU_MCU_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_GROUP_6_WIDTH },
13451  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ISAM67_MCU_MCU_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM67_MCU_MCU_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_GROUP_7_CHECKER_TYPE,
13452  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ISAM67_MCU_MCU_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM67_MCU_MCU_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_GROUP_7_WIDTH },
13453  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ISAM67_MCU_MCU_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM67_MCU_MCU_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_GROUP_8_CHECKER_TYPE,
13454  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ISAM67_MCU_MCU_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM67_MCU_MCU_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_GROUP_8_WIDTH },
13455  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ISAM67_MCU_MCU_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM67_MCU_MCU_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_GROUP_9_CHECKER_TYPE,
13456  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ISAM67_MCU_MCU_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM67_MCU_MCU_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_GROUP_9_WIDTH },
13457  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ISAM67_MCU_MCU_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM67_MCU_MCU_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_GROUP_10_CHECKER_TYPE,
13458  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ISAM67_MCU_MCU_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM67_MCU_MCU_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_GROUP_10_WIDTH },
13459  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ISAM67_MCU_MCU_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM67_MCU_MCU_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_GROUP_11_CHECKER_TYPE,
13460  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ISAM67_MCU_MCU_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM67_MCU_MCU_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_GROUP_11_WIDTH },
13461  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ISAM67_MCU_MCU_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM67_MCU_MCU_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_GROUP_12_CHECKER_TYPE,
13462  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ISAM67_MCU_MCU_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM67_MCU_MCU_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_GROUP_12_WIDTH },
13463 };
13464 
13470 static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_CFG_P2P_BRIDGE_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_CFG_BRIDGE_SRC_BUSECC_groupEntries[SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_CFG_P2P_BRIDGE_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_CFG_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS] =
13471 {
13472  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_CFG_P2P_BRIDGE_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_CFG_BRIDGE_SRC_BUSECC_GROUP_0_CHECKER_TYPE,
13473  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_CFG_P2P_BRIDGE_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_CFG_BRIDGE_SRC_BUSECC_GROUP_0_WIDTH },
13474  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_CFG_P2P_BRIDGE_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_CFG_BRIDGE_SRC_BUSECC_GROUP_1_CHECKER_TYPE,
13475  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_CFG_P2P_BRIDGE_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_CFG_BRIDGE_SRC_BUSECC_GROUP_1_WIDTH },
13476  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_CFG_P2P_BRIDGE_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_CFG_BRIDGE_SRC_BUSECC_GROUP_2_CHECKER_TYPE,
13477  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_CFG_P2P_BRIDGE_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_CFG_BRIDGE_SRC_BUSECC_GROUP_2_WIDTH },
13478  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_CFG_P2P_BRIDGE_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_CFG_BRIDGE_SRC_BUSECC_GROUP_3_CHECKER_TYPE,
13479  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_CFG_P2P_BRIDGE_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_CFG_BRIDGE_SRC_BUSECC_GROUP_3_WIDTH },
13480  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_CFG_P2P_BRIDGE_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_CFG_BRIDGE_SRC_BUSECC_GROUP_4_CHECKER_TYPE,
13481  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_CFG_P2P_BRIDGE_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_CFG_BRIDGE_SRC_BUSECC_GROUP_4_WIDTH },
13482  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_CFG_P2P_BRIDGE_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_CFG_BRIDGE_SRC_BUSECC_GROUP_5_CHECKER_TYPE,
13483  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_CFG_P2P_BRIDGE_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_CFG_BRIDGE_SRC_BUSECC_GROUP_5_WIDTH },
13484  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_CFG_P2P_BRIDGE_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_CFG_BRIDGE_SRC_BUSECC_GROUP_6_CHECKER_TYPE,
13485  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_CFG_P2P_BRIDGE_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_CFG_BRIDGE_SRC_BUSECC_GROUP_6_WIDTH },
13486  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_CFG_P2P_BRIDGE_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_CFG_BRIDGE_SRC_BUSECC_GROUP_7_CHECKER_TYPE,
13487  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_CFG_P2P_BRIDGE_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_CFG_BRIDGE_SRC_BUSECC_GROUP_7_WIDTH },
13488  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_CFG_P2P_BRIDGE_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_CFG_BRIDGE_SRC_BUSECC_GROUP_8_CHECKER_TYPE,
13489  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_CFG_P2P_BRIDGE_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_CFG_BRIDGE_SRC_BUSECC_GROUP_8_WIDTH },
13490  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_CFG_P2P_BRIDGE_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_CFG_BRIDGE_SRC_BUSECC_GROUP_9_CHECKER_TYPE,
13491  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_CFG_P2P_BRIDGE_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_CFG_BRIDGE_SRC_BUSECC_GROUP_9_WIDTH },
13492  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_CFG_P2P_BRIDGE_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_CFG_BRIDGE_SRC_BUSECC_GROUP_10_CHECKER_TYPE,
13493  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_CFG_P2P_BRIDGE_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_CFG_BRIDGE_SRC_BUSECC_GROUP_10_WIDTH },
13494  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_CFG_P2P_BRIDGE_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_CFG_BRIDGE_SRC_BUSECC_GROUP_11_CHECKER_TYPE,
13495  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_CFG_P2P_BRIDGE_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_CFG_BRIDGE_SRC_BUSECC_GROUP_11_WIDTH },
13496  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_CFG_P2P_BRIDGE_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_CFG_BRIDGE_SRC_BUSECC_GROUP_12_CHECKER_TYPE,
13497  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_CFG_P2P_BRIDGE_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_CFG_BRIDGE_SRC_BUSECC_GROUP_12_WIDTH },
13498  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_CFG_P2P_BRIDGE_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_CFG_BRIDGE_SRC_BUSECC_GROUP_13_CHECKER_TYPE,
13499  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_CFG_P2P_BRIDGE_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_CFG_BRIDGE_SRC_BUSECC_GROUP_13_WIDTH },
13500  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_CFG_P2P_BRIDGE_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_CFG_BRIDGE_SRC_BUSECC_GROUP_14_CHECKER_TYPE,
13501  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_CFG_P2P_BRIDGE_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_CFG_BRIDGE_SRC_BUSECC_GROUP_14_WIDTH },
13502  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_CFG_P2P_BRIDGE_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_CFG_BRIDGE_SRC_BUSECC_GROUP_15_CHECKER_TYPE,
13503  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_CFG_P2P_BRIDGE_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_CFG_BRIDGE_SRC_BUSECC_GROUP_15_WIDTH },
13504  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_CFG_P2P_BRIDGE_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_CFG_BRIDGE_SRC_BUSECC_GROUP_16_CHECKER_TYPE,
13505  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_CFG_P2P_BRIDGE_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_CFG_BRIDGE_SRC_BUSECC_GROUP_16_WIDTH },
13506 };
13507 
13513 static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_CFG_P2P_BRIDGE_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_CFG_BRIDGE_DST_BUSECC_groupEntries[SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_CFG_P2P_BRIDGE_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_CFG_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS] =
13514 {
13515  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_CFG_P2P_BRIDGE_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_CFG_BRIDGE_DST_BUSECC_GROUP_0_CHECKER_TYPE,
13516  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_CFG_P2P_BRIDGE_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_CFG_BRIDGE_DST_BUSECC_GROUP_0_WIDTH },
13517  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_CFG_P2P_BRIDGE_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_CFG_BRIDGE_DST_BUSECC_GROUP_1_CHECKER_TYPE,
13518  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_CFG_P2P_BRIDGE_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_CFG_BRIDGE_DST_BUSECC_GROUP_1_WIDTH },
13519  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_CFG_P2P_BRIDGE_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_CFG_BRIDGE_DST_BUSECC_GROUP_2_CHECKER_TYPE,
13520  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_CFG_P2P_BRIDGE_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_CFG_BRIDGE_DST_BUSECC_GROUP_2_WIDTH },
13521  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_CFG_P2P_BRIDGE_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_CFG_BRIDGE_DST_BUSECC_GROUP_3_CHECKER_TYPE,
13522  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_CFG_P2P_BRIDGE_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_CFG_BRIDGE_DST_BUSECC_GROUP_3_WIDTH },
13523  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_CFG_P2P_BRIDGE_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_CFG_BRIDGE_DST_BUSECC_GROUP_4_CHECKER_TYPE,
13524  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_CFG_P2P_BRIDGE_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_CFG_BRIDGE_DST_BUSECC_GROUP_4_WIDTH },
13525  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_CFG_P2P_BRIDGE_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_CFG_BRIDGE_DST_BUSECC_GROUP_5_CHECKER_TYPE,
13526  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_CFG_P2P_BRIDGE_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_CFG_BRIDGE_DST_BUSECC_GROUP_5_WIDTH },
13527  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_CFG_P2P_BRIDGE_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_CFG_BRIDGE_DST_BUSECC_GROUP_6_CHECKER_TYPE,
13528  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_CFG_P2P_BRIDGE_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_CFG_BRIDGE_DST_BUSECC_GROUP_6_WIDTH },
13529 };
13530 
13536 static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IAM67_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM67_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_groupEntries[SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IAM67_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM67_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS] =
13537 {
13538  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IAM67_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM67_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_0_CHECKER_TYPE,
13539  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IAM67_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM67_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_0_WIDTH },
13540  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IAM67_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM67_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_1_CHECKER_TYPE,
13541  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IAM67_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM67_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_1_WIDTH },
13542  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IAM67_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM67_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_2_CHECKER_TYPE,
13543  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IAM67_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM67_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_2_WIDTH },
13544  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IAM67_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM67_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_3_CHECKER_TYPE,
13545  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IAM67_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM67_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_3_WIDTH },
13546  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IAM67_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM67_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_4_CHECKER_TYPE,
13547  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IAM67_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM67_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_4_WIDTH },
13548  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IAM67_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM67_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_5_CHECKER_TYPE,
13549  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IAM67_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM67_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_5_WIDTH },
13550  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IAM67_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM67_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_6_CHECKER_TYPE,
13551  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IAM67_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM67_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_6_WIDTH },
13552  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IAM67_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM67_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_7_CHECKER_TYPE,
13553  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IAM67_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM67_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_7_WIDTH },
13554  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IAM67_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM67_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_8_CHECKER_TYPE,
13555  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IAM67_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM67_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_8_WIDTH },
13556  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IAM67_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM67_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_9_CHECKER_TYPE,
13557  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IAM67_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM67_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_9_WIDTH },
13558  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IAM67_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM67_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_10_CHECKER_TYPE,
13559  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IAM67_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM67_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_10_WIDTH },
13560  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IAM67_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM67_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_11_CHECKER_TYPE,
13561  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IAM67_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM67_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_11_WIDTH },
13562  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IAM67_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM67_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_12_CHECKER_TYPE,
13563  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IAM67_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM67_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_12_WIDTH },
13564  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IAM67_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM67_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_13_CHECKER_TYPE,
13565  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IAM67_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM67_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_13_WIDTH },
13566  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IAM67_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM67_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_14_CHECKER_TYPE,
13567  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IAM67_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM67_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_14_WIDTH },
13568  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IAM67_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM67_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_15_CHECKER_TYPE,
13569  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IAM67_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM67_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_15_WIDTH },
13570  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IAM67_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM67_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_16_CHECKER_TYPE,
13571  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IAM67_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM67_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_16_WIDTH },
13572 };
13573 
13579 static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IAM67_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM67_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_groupEntries[SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IAM67_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM67_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS] =
13580 {
13581  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IAM67_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM67_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_GROUP_0_CHECKER_TYPE,
13582  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IAM67_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM67_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_GROUP_0_WIDTH },
13583  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IAM67_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM67_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_GROUP_1_CHECKER_TYPE,
13584  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IAM67_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM67_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_GROUP_1_WIDTH },
13585  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IAM67_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM67_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_GROUP_2_CHECKER_TYPE,
13586  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IAM67_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM67_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_GROUP_2_WIDTH },
13587  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IAM67_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM67_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_GROUP_3_CHECKER_TYPE,
13588  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IAM67_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM67_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_GROUP_3_WIDTH },
13589  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IAM67_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM67_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_GROUP_4_CHECKER_TYPE,
13590  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IAM67_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM67_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_GROUP_4_WIDTH },
13591  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IAM67_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM67_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_GROUP_5_CHECKER_TYPE,
13592  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IAM67_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM67_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_GROUP_5_WIDTH },
13593  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IAM67_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM67_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_GROUP_6_CHECKER_TYPE,
13594  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IAM67_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM67_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_GROUP_6_WIDTH },
13595 };
13596 
13602 static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_groupEntries[SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_MAX_NUM_CHECKERS] =
13603 {
13604  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_0_CHECKER_TYPE,
13605  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_0_WIDTH },
13606  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_1_CHECKER_TYPE,
13607  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_1_WIDTH },
13608  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_2_CHECKER_TYPE,
13609  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_2_WIDTH },
13610  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_3_CHECKER_TYPE,
13611  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_3_WIDTH },
13612  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_4_CHECKER_TYPE,
13613  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_4_WIDTH },
13614  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_5_CHECKER_TYPE,
13615  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_5_WIDTH },
13616  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_6_CHECKER_TYPE,
13617  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_6_WIDTH },
13618  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_7_CHECKER_TYPE,
13619  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_7_WIDTH },
13620  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_8_CHECKER_TYPE,
13621  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_8_WIDTH },
13622  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_9_CHECKER_TYPE,
13623  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_9_WIDTH },
13624  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_10_CHECKER_TYPE,
13625  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_10_WIDTH },
13626  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_11_CHECKER_TYPE,
13627  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_11_WIDTH },
13628  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_12_CHECKER_TYPE,
13629  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_12_WIDTH },
13630  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_13_CHECKER_TYPE,
13631  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_13_WIDTH },
13632  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_14_CHECKER_TYPE,
13633  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_14_WIDTH },
13634  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_15_CHECKER_TYPE,
13635  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_15_WIDTH },
13636  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_16_CHECKER_TYPE,
13637  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_16_WIDTH },
13638  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_17_CHECKER_TYPE,
13639  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_17_WIDTH },
13640  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_18_CHECKER_TYPE,
13641  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_18_WIDTH },
13642  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_19_CHECKER_TYPE,
13643  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_19_WIDTH },
13644  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_20_CHECKER_TYPE,
13645  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_20_WIDTH },
13646  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_21_CHECKER_TYPE,
13647  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_21_WIDTH },
13648  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_22_CHECKER_TYPE,
13649  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_22_WIDTH },
13650  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_23_CHECKER_TYPE,
13651  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_23_WIDTH },
13652  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_24_CHECKER_TYPE,
13653  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_24_WIDTH },
13654  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_25_CHECKER_TYPE,
13655  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_25_WIDTH },
13656  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_26_CHECKER_TYPE,
13657  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_26_WIDTH },
13658  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_27_CHECKER_TYPE,
13659  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_27_WIDTH },
13660  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_28_CHECKER_TYPE,
13661  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_28_WIDTH },
13662  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_29_CHECKER_TYPE,
13663  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_29_WIDTH },
13664  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_30_CHECKER_TYPE,
13665  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_30_WIDTH },
13666  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_31_CHECKER_TYPE,
13667  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_31_WIDTH },
13668  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_32_CHECKER_TYPE,
13669  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_32_WIDTH },
13670  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_33_CHECKER_TYPE,
13671  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_33_WIDTH },
13672  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_34_CHECKER_TYPE,
13673  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_34_WIDTH },
13674  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_35_CHECKER_TYPE,
13675  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_35_WIDTH },
13676  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_36_CHECKER_TYPE,
13677  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_36_WIDTH },
13678  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_37_CHECKER_TYPE,
13679  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_37_WIDTH },
13680  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_38_CHECKER_TYPE,
13681  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_38_WIDTH },
13682  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_39_CHECKER_TYPE,
13683  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_39_WIDTH },
13684  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_40_CHECKER_TYPE,
13685  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_40_WIDTH },
13686  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_41_CHECKER_TYPE,
13687  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_41_WIDTH },
13688  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_42_CHECKER_TYPE,
13689  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_42_WIDTH },
13690  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_43_CHECKER_TYPE,
13691  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_43_WIDTH },
13692  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_44_CHECKER_TYPE,
13693  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_44_WIDTH },
13694  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_45_CHECKER_TYPE,
13695  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_45_WIDTH },
13696  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_46_CHECKER_TYPE,
13697  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_46_WIDTH },
13698  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_47_CHECKER_TYPE,
13699  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_47_WIDTH },
13700  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_48_CHECKER_TYPE,
13701  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_48_WIDTH },
13702  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_49_CHECKER_TYPE,
13703  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_49_WIDTH },
13704  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_50_CHECKER_TYPE,
13705  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_50_WIDTH },
13706  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_51_CHECKER_TYPE,
13707  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_51_WIDTH },
13708  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_52_CHECKER_TYPE,
13709  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_52_WIDTH },
13710  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_53_CHECKER_TYPE,
13711  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_53_WIDTH },
13712  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_54_CHECKER_TYPE,
13713  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_54_WIDTH },
13714  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_55_CHECKER_TYPE,
13715  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_55_WIDTH },
13716  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_56_CHECKER_TYPE,
13717  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_56_WIDTH },
13718  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_57_CHECKER_TYPE,
13719  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_57_WIDTH },
13720  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_58_CHECKER_TYPE,
13721  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_58_WIDTH },
13722  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_59_CHECKER_TYPE,
13723  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_59_WIDTH },
13724  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_60_CHECKER_TYPE,
13725  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_60_WIDTH },
13726  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_61_CHECKER_TYPE,
13727  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_61_WIDTH },
13728  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_62_CHECKER_TYPE,
13729  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_62_WIDTH },
13730  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_63_CHECKER_TYPE,
13731  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_63_WIDTH },
13732  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_64_CHECKER_TYPE,
13733  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_64_WIDTH },
13734  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_65_CHECKER_TYPE,
13735  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_65_WIDTH },
13736  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_66_CHECKER_TYPE,
13737  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_66_WIDTH },
13738  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_67_CHECKER_TYPE,
13739  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_67_WIDTH },
13740  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_68_CHECKER_TYPE,
13741  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_68_WIDTH },
13742  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_69_CHECKER_TYPE,
13743  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_69_WIDTH },
13744  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_70_CHECKER_TYPE,
13745  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_70_WIDTH },
13746  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_71_CHECKER_TYPE,
13747  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_71_WIDTH },
13748  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_72_CHECKER_TYPE,
13749  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_72_WIDTH },
13750  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_73_CHECKER_TYPE,
13751  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_73_WIDTH },
13752  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_74_CHECKER_TYPE,
13753  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_74_WIDTH },
13754  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_75_CHECKER_TYPE,
13755  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_75_WIDTH },
13756  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_76_CHECKER_TYPE,
13757  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_76_WIDTH },
13758  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_77_CHECKER_TYPE,
13759  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_77_WIDTH },
13760  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_78_CHECKER_TYPE,
13761  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_78_WIDTH },
13762  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_79_CHECKER_TYPE,
13763  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_79_WIDTH },
13764  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_80_CHECKER_TYPE,
13765  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_80_WIDTH },
13766  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_81_CHECKER_TYPE,
13767  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_81_WIDTH },
13768  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_82_CHECKER_TYPE,
13769  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_82_WIDTH },
13770  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_83_CHECKER_TYPE,
13771  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_83_WIDTH },
13772  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_84_CHECKER_TYPE,
13773  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_84_WIDTH },
13774  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_85_CHECKER_TYPE,
13775  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_85_WIDTH },
13776  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_86_CHECKER_TYPE,
13777  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_86_WIDTH },
13778  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_87_CHECKER_TYPE,
13779  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_87_WIDTH },
13780  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_88_CHECKER_TYPE,
13781  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_88_WIDTH },
13782  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_89_CHECKER_TYPE,
13783  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_89_WIDTH },
13784  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_90_CHECKER_TYPE,
13785  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_90_WIDTH },
13786  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_91_CHECKER_TYPE,
13787  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_91_WIDTH },
13788  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_92_CHECKER_TYPE,
13789  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_92_WIDTH },
13790  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_93_CHECKER_TYPE,
13791  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_93_WIDTH },
13792  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_94_CHECKER_TYPE,
13793  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_94_WIDTH },
13794  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_95_CHECKER_TYPE,
13795  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_95_WIDTH },
13796  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_96_CHECKER_TYPE,
13797  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_96_WIDTH },
13798  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_97_CHECKER_TYPE,
13799  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_97_WIDTH },
13800  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_98_CHECKER_TYPE,
13801  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_98_WIDTH },
13802  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_99_CHECKER_TYPE,
13803  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_99_WIDTH },
13804  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_100_CHECKER_TYPE,
13805  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_100_WIDTH },
13806  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_101_CHECKER_TYPE,
13807  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_101_WIDTH },
13808  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_102_CHECKER_TYPE,
13809  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_102_WIDTH },
13810  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_103_CHECKER_TYPE,
13811  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_103_WIDTH },
13812  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_104_CHECKER_TYPE,
13813  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_104_WIDTH },
13814  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_105_CHECKER_TYPE,
13815  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_105_WIDTH },
13816  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_106_CHECKER_TYPE,
13817  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_106_WIDTH },
13818  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_107_CHECKER_TYPE,
13819  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_107_WIDTH },
13820  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_108_CHECKER_TYPE,
13821  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_108_WIDTH },
13822  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_109_CHECKER_TYPE,
13823  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_109_WIDTH },
13824  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_110_CHECKER_TYPE,
13825  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_110_WIDTH },
13826  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_111_CHECKER_TYPE,
13827  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_111_WIDTH },
13828  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_112_CHECKER_TYPE,
13829  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_112_WIDTH },
13830  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_113_CHECKER_TYPE,
13831  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_113_WIDTH },
13832  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_114_CHECKER_TYPE,
13833  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_114_WIDTH },
13834  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_115_CHECKER_TYPE,
13835  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_115_WIDTH },
13836  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_116_CHECKER_TYPE,
13837  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_116_WIDTH },
13838  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_117_CHECKER_TYPE,
13839  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_117_WIDTH },
13840  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_118_CHECKER_TYPE,
13841  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_118_WIDTH },
13842  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_119_CHECKER_TYPE,
13843  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_119_WIDTH },
13844  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_120_CHECKER_TYPE,
13845  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_120_WIDTH },
13846  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_121_CHECKER_TYPE,
13847  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_121_WIDTH },
13848  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_122_CHECKER_TYPE,
13849  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_122_WIDTH },
13850  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_123_CHECKER_TYPE,
13851  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_123_WIDTH },
13852  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_124_CHECKER_TYPE,
13853  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_124_WIDTH },
13854  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_125_CHECKER_TYPE,
13855  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_125_WIDTH },
13856  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_126_CHECKER_TYPE,
13857  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_126_WIDTH },
13858  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_127_CHECKER_TYPE,
13859  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_127_WIDTH },
13860  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_128_CHECKER_TYPE,
13861  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_128_WIDTH },
13862  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_129_CHECKER_TYPE,
13863  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_129_WIDTH },
13864  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_130_CHECKER_TYPE,
13865  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_130_WIDTH },
13866  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_131_CHECKER_TYPE,
13867  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_131_WIDTH },
13868  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_132_CHECKER_TYPE,
13869  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_132_WIDTH },
13870  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_133_CHECKER_TYPE,
13871  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_133_WIDTH },
13872  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_134_CHECKER_TYPE,
13873  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_134_WIDTH },
13874  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_135_CHECKER_TYPE,
13875  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_135_WIDTH },
13876  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_136_CHECKER_TYPE,
13877  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_136_WIDTH },
13878  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_137_CHECKER_TYPE,
13879  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_137_WIDTH },
13880  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_138_CHECKER_TYPE,
13881  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_138_WIDTH },
13882  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_139_CHECKER_TYPE,
13883  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_139_WIDTH },
13884  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_140_CHECKER_TYPE,
13885  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_140_WIDTH },
13886  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_141_CHECKER_TYPE,
13887  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_141_WIDTH },
13888  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_142_CHECKER_TYPE,
13889  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_142_WIDTH },
13890  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_143_CHECKER_TYPE,
13891  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_143_WIDTH },
13892  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_144_CHECKER_TYPE,
13893  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_144_WIDTH },
13894  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_145_CHECKER_TYPE,
13895  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_145_WIDTH },
13896  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_146_CHECKER_TYPE,
13897  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_146_WIDTH },
13898  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_147_CHECKER_TYPE,
13899  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_147_WIDTH },
13900  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_148_CHECKER_TYPE,
13901  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_148_WIDTH },
13902  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_149_CHECKER_TYPE,
13903  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_149_WIDTH },
13904  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_150_CHECKER_TYPE,
13905  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_150_WIDTH },
13906  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_151_CHECKER_TYPE,
13907  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_151_WIDTH },
13908  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_152_CHECKER_TYPE,
13909  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_152_WIDTH },
13910  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_153_CHECKER_TYPE,
13911  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_153_WIDTH },
13912  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_154_CHECKER_TYPE,
13913  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_154_WIDTH },
13914  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_155_CHECKER_TYPE,
13915  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_155_WIDTH },
13916  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_156_CHECKER_TYPE,
13917  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_156_WIDTH },
13918  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_157_CHECKER_TYPE,
13919  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_157_WIDTH },
13920  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_158_CHECKER_TYPE,
13921  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_158_WIDTH },
13922  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_159_CHECKER_TYPE,
13923  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_159_WIDTH },
13924  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_160_CHECKER_TYPE,
13925  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_160_WIDTH },
13926  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_161_CHECKER_TYPE,
13927  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_161_WIDTH },
13928  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_162_CHECKER_TYPE,
13929  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_162_WIDTH },
13930  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_163_CHECKER_TYPE,
13931  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_163_WIDTH },
13932  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_164_CHECKER_TYPE,
13933  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_164_WIDTH },
13934  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_165_CHECKER_TYPE,
13935  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_165_WIDTH },
13936  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_166_CHECKER_TYPE,
13937  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_166_WIDTH },
13938  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_167_CHECKER_TYPE,
13939  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_167_WIDTH },
13940  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_168_CHECKER_TYPE,
13941  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_168_WIDTH },
13942  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_169_CHECKER_TYPE,
13943  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_169_WIDTH },
13944  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_170_CHECKER_TYPE,
13945  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_170_WIDTH },
13946  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_171_CHECKER_TYPE,
13947  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_171_WIDTH },
13948  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_172_CHECKER_TYPE,
13949  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_172_WIDTH },
13950  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_173_CHECKER_TYPE,
13951  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_173_WIDTH },
13952  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_174_CHECKER_TYPE,
13953  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_174_WIDTH },
13954  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_175_CHECKER_TYPE,
13955  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_175_WIDTH },
13956  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_176_CHECKER_TYPE,
13957  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_176_WIDTH },
13958  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_177_CHECKER_TYPE,
13959  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_177_WIDTH },
13960  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_178_CHECKER_TYPE,
13961  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_178_WIDTH },
13962  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_179_CHECKER_TYPE,
13963  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_179_WIDTH },
13964  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_180_CHECKER_TYPE,
13965  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_180_WIDTH },
13966  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_181_CHECKER_TYPE,
13967  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_181_WIDTH },
13968  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_182_CHECKER_TYPE,
13969  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_182_WIDTH },
13970  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_183_CHECKER_TYPE,
13971  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_183_WIDTH },
13972  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_184_CHECKER_TYPE,
13973  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_184_WIDTH },
13974  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_185_CHECKER_TYPE,
13975  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_185_WIDTH },
13976  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_186_CHECKER_TYPE,
13977  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_186_WIDTH },
13978  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_187_CHECKER_TYPE,
13979  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_187_WIDTH },
13980  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_188_CHECKER_TYPE,
13981  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_188_WIDTH },
13982  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_189_CHECKER_TYPE,
13983  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_189_WIDTH },
13984  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_190_CHECKER_TYPE,
13985  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_190_WIDTH },
13986  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_191_CHECKER_TYPE,
13987  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_191_WIDTH },
13988  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_192_CHECKER_TYPE,
13989  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_192_WIDTH },
13990  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_193_CHECKER_TYPE,
13991  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_193_WIDTH },
13992  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_194_CHECKER_TYPE,
13993  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_194_WIDTH },
13994  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_195_CHECKER_TYPE,
13995  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_195_WIDTH },
13996  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_196_CHECKER_TYPE,
13997  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_196_WIDTH },
13998  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_197_CHECKER_TYPE,
13999  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_197_WIDTH },
14000  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_198_CHECKER_TYPE,
14001  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_198_WIDTH },
14002  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_199_CHECKER_TYPE,
14003  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_199_WIDTH },
14004  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_200_CHECKER_TYPE,
14005  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_200_WIDTH },
14006  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_201_CHECKER_TYPE,
14007  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_201_WIDTH },
14008  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_202_CHECKER_TYPE,
14009  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_202_WIDTH },
14010  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_203_CHECKER_TYPE,
14011  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_203_WIDTH },
14012  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_204_CHECKER_TYPE,
14013  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_204_WIDTH },
14014  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_205_CHECKER_TYPE,
14015  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_205_WIDTH },
14016  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_206_CHECKER_TYPE,
14017  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_206_WIDTH },
14018  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_207_CHECKER_TYPE,
14019  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_207_WIDTH },
14020  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_208_CHECKER_TYPE,
14021  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_208_WIDTH },
14022  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_209_CHECKER_TYPE,
14023  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_209_WIDTH },
14024  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_210_CHECKER_TYPE,
14025  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_210_WIDTH },
14026  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_211_CHECKER_TYPE,
14027  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_211_WIDTH },
14028  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_212_CHECKER_TYPE,
14029  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_212_WIDTH },
14030  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_213_CHECKER_TYPE,
14031  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_213_WIDTH },
14032  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_214_CHECKER_TYPE,
14033  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_214_WIDTH },
14034  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_215_CHECKER_TYPE,
14035  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_215_WIDTH },
14036  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_216_CHECKER_TYPE,
14037  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_216_WIDTH },
14038  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_217_CHECKER_TYPE,
14039  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_217_WIDTH },
14040  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_218_CHECKER_TYPE,
14041  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_218_WIDTH },
14042  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_219_CHECKER_TYPE,
14043  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_219_WIDTH },
14044  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_220_CHECKER_TYPE,
14045  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_220_WIDTH },
14046  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_221_CHECKER_TYPE,
14047  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_221_WIDTH },
14048  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_222_CHECKER_TYPE,
14049  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_222_WIDTH },
14050  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_223_CHECKER_TYPE,
14051  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_223_WIDTH },
14052  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_224_CHECKER_TYPE,
14053  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_224_WIDTH },
14054  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_225_CHECKER_TYPE,
14055  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_225_WIDTH },
14056  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_226_CHECKER_TYPE,
14057  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_226_WIDTH },
14058  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_227_CHECKER_TYPE,
14059  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_227_WIDTH },
14060  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_228_CHECKER_TYPE,
14061  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_228_WIDTH },
14062  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_229_CHECKER_TYPE,
14063  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_229_WIDTH },
14064  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_230_CHECKER_TYPE,
14065  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_230_WIDTH },
14066  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_231_CHECKER_TYPE,
14067  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_231_WIDTH },
14068  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_232_CHECKER_TYPE,
14069  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_232_WIDTH },
14070  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_233_CHECKER_TYPE,
14071  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_233_WIDTH },
14072  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_234_CHECKER_TYPE,
14073  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_234_WIDTH },
14074  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_235_CHECKER_TYPE,
14075  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_235_WIDTH },
14076  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_236_CHECKER_TYPE,
14077  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_236_WIDTH },
14078  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_237_CHECKER_TYPE,
14079  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_237_WIDTH },
14080  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_238_CHECKER_TYPE,
14081  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_238_WIDTH },
14082  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_239_CHECKER_TYPE,
14083  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_239_WIDTH },
14084  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_240_CHECKER_TYPE,
14085  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_240_WIDTH },
14086  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_241_CHECKER_TYPE,
14087  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_241_WIDTH },
14088  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_242_CHECKER_TYPE,
14089  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_242_WIDTH },
14090  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_243_CHECKER_TYPE,
14091  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_243_WIDTH },
14092  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_244_CHECKER_TYPE,
14093  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_244_WIDTH },
14094  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_245_CHECKER_TYPE,
14095  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_245_WIDTH },
14096  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_246_CHECKER_TYPE,
14097  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_246_WIDTH },
14098  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_247_CHECKER_TYPE,
14099  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_247_WIDTH },
14100  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_248_CHECKER_TYPE,
14101  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_248_WIDTH },
14102  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_249_CHECKER_TYPE,
14103  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_249_WIDTH },
14104  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_250_CHECKER_TYPE,
14105  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_250_WIDTH },
14106  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_251_CHECKER_TYPE,
14107  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_251_WIDTH },
14108  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_252_CHECKER_TYPE,
14109  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_252_WIDTH },
14110  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_253_CHECKER_TYPE,
14111  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_253_WIDTH },
14112  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_254_CHECKER_TYPE,
14113  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_254_WIDTH },
14114  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_255_CHECKER_TYPE,
14115  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_255_WIDTH },
14116 };
14117 
14123 static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_groupEntries[SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_MAX_NUM_CHECKERS] =
14124 {
14125  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_0_CHECKER_TYPE,
14126  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_0_WIDTH },
14127  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_1_CHECKER_TYPE,
14128  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_1_WIDTH },
14129  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_2_CHECKER_TYPE,
14130  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_2_WIDTH },
14131  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_3_CHECKER_TYPE,
14132  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_3_WIDTH },
14133  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_4_CHECKER_TYPE,
14134  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_4_WIDTH },
14135  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_5_CHECKER_TYPE,
14136  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_5_WIDTH },
14137  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_6_CHECKER_TYPE,
14138  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_6_WIDTH },
14139  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_7_CHECKER_TYPE,
14140  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_7_WIDTH },
14141  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_8_CHECKER_TYPE,
14142  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_8_WIDTH },
14143  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_9_CHECKER_TYPE,
14144  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_9_WIDTH },
14145  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_10_CHECKER_TYPE,
14146  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_10_WIDTH },
14147  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_11_CHECKER_TYPE,
14148  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_11_WIDTH },
14149  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_12_CHECKER_TYPE,
14150  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_12_WIDTH },
14151  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_13_CHECKER_TYPE,
14152  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_13_WIDTH },
14153  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_14_CHECKER_TYPE,
14154  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_14_WIDTH },
14155  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_15_CHECKER_TYPE,
14156  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_15_WIDTH },
14157  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_16_CHECKER_TYPE,
14158  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_16_WIDTH },
14159  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_17_CHECKER_TYPE,
14160  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_17_WIDTH },
14161  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_18_CHECKER_TYPE,
14162  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_18_WIDTH },
14163  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_19_CHECKER_TYPE,
14164  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_19_WIDTH },
14165  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_20_CHECKER_TYPE,
14166  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_20_WIDTH },
14167  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_21_CHECKER_TYPE,
14168  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_21_WIDTH },
14169  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_22_CHECKER_TYPE,
14170  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_22_WIDTH },
14171  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_23_CHECKER_TYPE,
14172  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_23_WIDTH },
14173  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_24_CHECKER_TYPE,
14174  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_24_WIDTH },
14175  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_25_CHECKER_TYPE,
14176  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_25_WIDTH },
14177  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_26_CHECKER_TYPE,
14178  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_26_WIDTH },
14179  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_27_CHECKER_TYPE,
14180  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_27_WIDTH },
14181  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_28_CHECKER_TYPE,
14182  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_28_WIDTH },
14183  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_29_CHECKER_TYPE,
14184  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_29_WIDTH },
14185  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_30_CHECKER_TYPE,
14186  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_30_WIDTH },
14187  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_31_CHECKER_TYPE,
14188  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_31_WIDTH },
14189  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_32_CHECKER_TYPE,
14190  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_32_WIDTH },
14191  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_33_CHECKER_TYPE,
14192  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_33_WIDTH },
14193  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_34_CHECKER_TYPE,
14194  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_34_WIDTH },
14195  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_35_CHECKER_TYPE,
14196  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_35_WIDTH },
14197  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_36_CHECKER_TYPE,
14198  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_36_WIDTH },
14199  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_37_CHECKER_TYPE,
14200  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_37_WIDTH },
14201  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_38_CHECKER_TYPE,
14202  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_38_WIDTH },
14203  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_39_CHECKER_TYPE,
14204  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_39_WIDTH },
14205  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_40_CHECKER_TYPE,
14206  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_40_WIDTH },
14207  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_41_CHECKER_TYPE,
14208  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_41_WIDTH },
14209  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_42_CHECKER_TYPE,
14210  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_42_WIDTH },
14211  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_43_CHECKER_TYPE,
14212  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_43_WIDTH },
14213  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_44_CHECKER_TYPE,
14214  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_44_WIDTH },
14215  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_45_CHECKER_TYPE,
14216  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_45_WIDTH },
14217  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_46_CHECKER_TYPE,
14218  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_46_WIDTH },
14219  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_47_CHECKER_TYPE,
14220  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_47_WIDTH },
14221  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_48_CHECKER_TYPE,
14222  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_48_WIDTH },
14223  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_49_CHECKER_TYPE,
14224  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_49_WIDTH },
14225  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_50_CHECKER_TYPE,
14226  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_50_WIDTH },
14227  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_51_CHECKER_TYPE,
14228  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_51_WIDTH },
14229  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_52_CHECKER_TYPE,
14230  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_52_WIDTH },
14231  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_53_CHECKER_TYPE,
14232  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_53_WIDTH },
14233  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_54_CHECKER_TYPE,
14234  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_54_WIDTH },
14235  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_55_CHECKER_TYPE,
14236  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_55_WIDTH },
14237  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_56_CHECKER_TYPE,
14238  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_56_WIDTH },
14239  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_57_CHECKER_TYPE,
14240  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_57_WIDTH },
14241  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_58_CHECKER_TYPE,
14242  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_58_WIDTH },
14243  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_59_CHECKER_TYPE,
14244  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_59_WIDTH },
14245  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_60_CHECKER_TYPE,
14246  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_60_WIDTH },
14247  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_61_CHECKER_TYPE,
14248  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_61_WIDTH },
14249  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_62_CHECKER_TYPE,
14250  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_62_WIDTH },
14251  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_63_CHECKER_TYPE,
14252  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_63_WIDTH },
14253  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_64_CHECKER_TYPE,
14254  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_64_WIDTH },
14255  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_65_CHECKER_TYPE,
14256  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_65_WIDTH },
14257  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_66_CHECKER_TYPE,
14258  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_66_WIDTH },
14259  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_67_CHECKER_TYPE,
14260  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_67_WIDTH },
14261  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_68_CHECKER_TYPE,
14262  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_68_WIDTH },
14263  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_69_CHECKER_TYPE,
14264  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_69_WIDTH },
14265  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_70_CHECKER_TYPE,
14266  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_70_WIDTH },
14267  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_71_CHECKER_TYPE,
14268  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_71_WIDTH },
14269  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_72_CHECKER_TYPE,
14270  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_72_WIDTH },
14271  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_73_CHECKER_TYPE,
14272  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_73_WIDTH },
14273  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_74_CHECKER_TYPE,
14274  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_74_WIDTH },
14275  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_75_CHECKER_TYPE,
14276  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_75_WIDTH },
14277  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_76_CHECKER_TYPE,
14278  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_76_WIDTH },
14279  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_77_CHECKER_TYPE,
14280  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_77_WIDTH },
14281  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_78_CHECKER_TYPE,
14282  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_78_WIDTH },
14283  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_79_CHECKER_TYPE,
14284  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_79_WIDTH },
14285  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_80_CHECKER_TYPE,
14286  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_80_WIDTH },
14287  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_81_CHECKER_TYPE,
14288  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_81_WIDTH },
14289  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_82_CHECKER_TYPE,
14290  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_82_WIDTH },
14291  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_83_CHECKER_TYPE,
14292  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_83_WIDTH },
14293  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_84_CHECKER_TYPE,
14294  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_84_WIDTH },
14295  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_85_CHECKER_TYPE,
14296  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_85_WIDTH },
14297  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_86_CHECKER_TYPE,
14298  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_86_WIDTH },
14299  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_87_CHECKER_TYPE,
14300  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_87_WIDTH },
14301  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_88_CHECKER_TYPE,
14302  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_88_WIDTH },
14303  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_89_CHECKER_TYPE,
14304  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_89_WIDTH },
14305  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_90_CHECKER_TYPE,
14306  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_90_WIDTH },
14307  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_91_CHECKER_TYPE,
14308  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_91_WIDTH },
14309  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_92_CHECKER_TYPE,
14310  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_92_WIDTH },
14311  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_93_CHECKER_TYPE,
14312  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_93_WIDTH },
14313  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_94_CHECKER_TYPE,
14314  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_94_WIDTH },
14315  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_95_CHECKER_TYPE,
14316  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_95_WIDTH },
14317  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_96_CHECKER_TYPE,
14318  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_96_WIDTH },
14319  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_97_CHECKER_TYPE,
14320  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_97_WIDTH },
14321  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_98_CHECKER_TYPE,
14322  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_98_WIDTH },
14323  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_99_CHECKER_TYPE,
14324  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_99_WIDTH },
14325  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_100_CHECKER_TYPE,
14326  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_100_WIDTH },
14327  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_101_CHECKER_TYPE,
14328  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_101_WIDTH },
14329  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_102_CHECKER_TYPE,
14330  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_102_WIDTH },
14331  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_103_CHECKER_TYPE,
14332  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_103_WIDTH },
14333  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_104_CHECKER_TYPE,
14334  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_104_WIDTH },
14335  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_105_CHECKER_TYPE,
14336  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_105_WIDTH },
14337  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_106_CHECKER_TYPE,
14338  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_106_WIDTH },
14339  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_107_CHECKER_TYPE,
14340  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_107_WIDTH },
14341  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_108_CHECKER_TYPE,
14342  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_108_WIDTH },
14343  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_109_CHECKER_TYPE,
14344  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_109_WIDTH },
14345  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_110_CHECKER_TYPE,
14346  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_110_WIDTH },
14347  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_111_CHECKER_TYPE,
14348  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_111_WIDTH },
14349  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_112_CHECKER_TYPE,
14350  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_112_WIDTH },
14351  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_113_CHECKER_TYPE,
14352  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_113_WIDTH },
14353  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_114_CHECKER_TYPE,
14354  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_114_WIDTH },
14355  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_115_CHECKER_TYPE,
14356  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_115_WIDTH },
14357  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_116_CHECKER_TYPE,
14358  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_116_WIDTH },
14359  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_117_CHECKER_TYPE,
14360  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_117_WIDTH },
14361  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_118_CHECKER_TYPE,
14362  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_118_WIDTH },
14363  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_119_CHECKER_TYPE,
14364  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_119_WIDTH },
14365  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_120_CHECKER_TYPE,
14366  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_120_WIDTH },
14367  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_121_CHECKER_TYPE,
14368  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_121_WIDTH },
14369  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_122_CHECKER_TYPE,
14370  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_122_WIDTH },
14371  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_123_CHECKER_TYPE,
14372  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_123_WIDTH },
14373  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_124_CHECKER_TYPE,
14374  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_124_WIDTH },
14375  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_125_CHECKER_TYPE,
14376  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_125_WIDTH },
14377  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_126_CHECKER_TYPE,
14378  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_126_WIDTH },
14379  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_127_CHECKER_TYPE,
14380  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_127_WIDTH },
14381  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_128_CHECKER_TYPE,
14382  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_128_WIDTH },
14383  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_129_CHECKER_TYPE,
14384  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_129_WIDTH },
14385  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_130_CHECKER_TYPE,
14386  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_130_WIDTH },
14387  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_131_CHECKER_TYPE,
14388  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_131_WIDTH },
14389  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_132_CHECKER_TYPE,
14390  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_132_WIDTH },
14391  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_133_CHECKER_TYPE,
14392  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_133_WIDTH },
14393  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_134_CHECKER_TYPE,
14394  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_134_WIDTH },
14395  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_135_CHECKER_TYPE,
14396  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_135_WIDTH },
14397  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_136_CHECKER_TYPE,
14398  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_136_WIDTH },
14399  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_137_CHECKER_TYPE,
14400  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_137_WIDTH },
14401  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_138_CHECKER_TYPE,
14402  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_138_WIDTH },
14403  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_139_CHECKER_TYPE,
14404  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_139_WIDTH },
14405  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_140_CHECKER_TYPE,
14406  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_140_WIDTH },
14407  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_141_CHECKER_TYPE,
14408  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_141_WIDTH },
14409  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_142_CHECKER_TYPE,
14410  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_142_WIDTH },
14411  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_143_CHECKER_TYPE,
14412  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_143_WIDTH },
14413  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_144_CHECKER_TYPE,
14414  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_144_WIDTH },
14415  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_145_CHECKER_TYPE,
14416  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_145_WIDTH },
14417  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_146_CHECKER_TYPE,
14418  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_146_WIDTH },
14419  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_147_CHECKER_TYPE,
14420  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_147_WIDTH },
14421  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_148_CHECKER_TYPE,
14422  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_148_WIDTH },
14423  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_149_CHECKER_TYPE,
14424  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_149_WIDTH },
14425  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_150_CHECKER_TYPE,
14426  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_150_WIDTH },
14427  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_151_CHECKER_TYPE,
14428  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_151_WIDTH },
14429  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_152_CHECKER_TYPE,
14430  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_152_WIDTH },
14431  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_153_CHECKER_TYPE,
14432  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_153_WIDTH },
14433  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_154_CHECKER_TYPE,
14434  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_154_WIDTH },
14435  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_155_CHECKER_TYPE,
14436  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_155_WIDTH },
14437  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_156_CHECKER_TYPE,
14438  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_156_WIDTH },
14439  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_157_CHECKER_TYPE,
14440  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_157_WIDTH },
14441  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_158_CHECKER_TYPE,
14442  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_158_WIDTH },
14443  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_159_CHECKER_TYPE,
14444  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_159_WIDTH },
14445  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_160_CHECKER_TYPE,
14446  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_160_WIDTH },
14447  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_161_CHECKER_TYPE,
14448  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_161_WIDTH },
14449  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_162_CHECKER_TYPE,
14450  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_162_WIDTH },
14451  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_163_CHECKER_TYPE,
14452  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_163_WIDTH },
14453  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_164_CHECKER_TYPE,
14454  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_164_WIDTH },
14455  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_165_CHECKER_TYPE,
14456  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_165_WIDTH },
14457  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_166_CHECKER_TYPE,
14458  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_166_WIDTH },
14459  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_167_CHECKER_TYPE,
14460  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_167_WIDTH },
14461  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_168_CHECKER_TYPE,
14462  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_168_WIDTH },
14463  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_169_CHECKER_TYPE,
14464  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_169_WIDTH },
14465  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_170_CHECKER_TYPE,
14466  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_170_WIDTH },
14467  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_171_CHECKER_TYPE,
14468  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_171_WIDTH },
14469  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_172_CHECKER_TYPE,
14470  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_172_WIDTH },
14471  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_173_CHECKER_TYPE,
14472  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_173_WIDTH },
14473  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_174_CHECKER_TYPE,
14474  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_174_WIDTH },
14475  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_175_CHECKER_TYPE,
14476  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_175_WIDTH },
14477  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_176_CHECKER_TYPE,
14478  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_176_WIDTH },
14479  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_177_CHECKER_TYPE,
14480  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_177_WIDTH },
14481  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_178_CHECKER_TYPE,
14482  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_178_WIDTH },
14483  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_179_CHECKER_TYPE,
14484  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_179_WIDTH },
14485  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_180_CHECKER_TYPE,
14486  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_180_WIDTH },
14487  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_181_CHECKER_TYPE,
14488  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_181_WIDTH },
14489  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_182_CHECKER_TYPE,
14490  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_182_WIDTH },
14491  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_183_CHECKER_TYPE,
14492  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_183_WIDTH },
14493  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_184_CHECKER_TYPE,
14494  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_184_WIDTH },
14495  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_185_CHECKER_TYPE,
14496  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_185_WIDTH },
14497  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_186_CHECKER_TYPE,
14498  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_186_WIDTH },
14499  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_187_CHECKER_TYPE,
14500  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_187_WIDTH },
14501  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_188_CHECKER_TYPE,
14502  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_188_WIDTH },
14503  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_189_CHECKER_TYPE,
14504  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_189_WIDTH },
14505  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_190_CHECKER_TYPE,
14506  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_190_WIDTH },
14507  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_191_CHECKER_TYPE,
14508  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_191_WIDTH },
14509  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_192_CHECKER_TYPE,
14510  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_192_WIDTH },
14511  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_193_CHECKER_TYPE,
14512  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_193_WIDTH },
14513  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_194_CHECKER_TYPE,
14514  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_194_WIDTH },
14515  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_195_CHECKER_TYPE,
14516  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_195_WIDTH },
14517  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_196_CHECKER_TYPE,
14518  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_196_WIDTH },
14519  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_197_CHECKER_TYPE,
14520  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_197_WIDTH },
14521  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_198_CHECKER_TYPE,
14522  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_198_WIDTH },
14523  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_199_CHECKER_TYPE,
14524  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_199_WIDTH },
14525  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_200_CHECKER_TYPE,
14526  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_200_WIDTH },
14527  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_201_CHECKER_TYPE,
14528  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_201_WIDTH },
14529  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_202_CHECKER_TYPE,
14530  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_202_WIDTH },
14531  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_203_CHECKER_TYPE,
14532  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_203_WIDTH },
14533  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_204_CHECKER_TYPE,
14534  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_204_WIDTH },
14535  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_205_CHECKER_TYPE,
14536  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_205_WIDTH },
14537  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_206_CHECKER_TYPE,
14538  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_206_WIDTH },
14539  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_207_CHECKER_TYPE,
14540  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_207_WIDTH },
14541  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_208_CHECKER_TYPE,
14542  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_208_WIDTH },
14543  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_209_CHECKER_TYPE,
14544  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_209_WIDTH },
14545  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_210_CHECKER_TYPE,
14546  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_210_WIDTH },
14547  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_211_CHECKER_TYPE,
14548  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_211_WIDTH },
14549  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_212_CHECKER_TYPE,
14550  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_212_WIDTH },
14551  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_213_CHECKER_TYPE,
14552  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_213_WIDTH },
14553  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_214_CHECKER_TYPE,
14554  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_214_WIDTH },
14555  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_215_CHECKER_TYPE,
14556  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_215_WIDTH },
14557 };
14558 
14564 static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_groupEntries[SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_MAX_NUM_CHECKERS] =
14565 {
14566  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_0_CHECKER_TYPE,
14567  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_0_WIDTH },
14568  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_1_CHECKER_TYPE,
14569  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_1_WIDTH },
14570  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_2_CHECKER_TYPE,
14571  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_2_WIDTH },
14572  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_3_CHECKER_TYPE,
14573  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_3_WIDTH },
14574  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_4_CHECKER_TYPE,
14575  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_4_WIDTH },
14576  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_5_CHECKER_TYPE,
14577  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_5_WIDTH },
14578  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_6_CHECKER_TYPE,
14579  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_6_WIDTH },
14580  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_7_CHECKER_TYPE,
14581  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_7_WIDTH },
14582  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_8_CHECKER_TYPE,
14583  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_8_WIDTH },
14584  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_9_CHECKER_TYPE,
14585  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_9_WIDTH },
14586  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_10_CHECKER_TYPE,
14587  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_10_WIDTH },
14588  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_11_CHECKER_TYPE,
14589  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_11_WIDTH },
14590  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_12_CHECKER_TYPE,
14591  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_12_WIDTH },
14592  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_13_CHECKER_TYPE,
14593  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_13_WIDTH },
14594  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_14_CHECKER_TYPE,
14595  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_14_WIDTH },
14596  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_15_CHECKER_TYPE,
14597  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_15_WIDTH },
14598  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_16_CHECKER_TYPE,
14599  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_16_WIDTH },
14600  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_17_CHECKER_TYPE,
14601  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_17_WIDTH },
14602  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_18_CHECKER_TYPE,
14603  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_18_WIDTH },
14604  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_19_CHECKER_TYPE,
14605  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_19_WIDTH },
14606  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_20_CHECKER_TYPE,
14607  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_20_WIDTH },
14608  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_21_CHECKER_TYPE,
14609  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_21_WIDTH },
14610  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_22_CHECKER_TYPE,
14611  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_22_WIDTH },
14612  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_23_CHECKER_TYPE,
14613  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_23_WIDTH },
14614  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_24_CHECKER_TYPE,
14615  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_24_WIDTH },
14616  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_25_CHECKER_TYPE,
14617  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_25_WIDTH },
14618  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_26_CHECKER_TYPE,
14619  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_26_WIDTH },
14620  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_27_CHECKER_TYPE,
14621  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_27_WIDTH },
14622  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_28_CHECKER_TYPE,
14623  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_28_WIDTH },
14624  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_29_CHECKER_TYPE,
14625  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_29_WIDTH },
14626  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_30_CHECKER_TYPE,
14627  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_30_WIDTH },
14628  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_31_CHECKER_TYPE,
14629  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_31_WIDTH },
14630  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_32_CHECKER_TYPE,
14631  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_32_WIDTH },
14632  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_33_CHECKER_TYPE,
14633  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_33_WIDTH },
14634  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_34_CHECKER_TYPE,
14635  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_34_WIDTH },
14636  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_35_CHECKER_TYPE,
14637  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_35_WIDTH },
14638  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_36_CHECKER_TYPE,
14639  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_36_WIDTH },
14640  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_37_CHECKER_TYPE,
14641  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_37_WIDTH },
14642  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_38_CHECKER_TYPE,
14643  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_38_WIDTH },
14644  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_39_CHECKER_TYPE,
14645  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_39_WIDTH },
14646  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_40_CHECKER_TYPE,
14647  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_40_WIDTH },
14648  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_41_CHECKER_TYPE,
14649  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_41_WIDTH },
14650  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_42_CHECKER_TYPE,
14651  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_42_WIDTH },
14652  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_43_CHECKER_TYPE,
14653  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_43_WIDTH },
14654  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_44_CHECKER_TYPE,
14655  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_44_WIDTH },
14656  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_45_CHECKER_TYPE,
14657  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_45_WIDTH },
14658  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_46_CHECKER_TYPE,
14659  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_46_WIDTH },
14660  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_47_CHECKER_TYPE,
14661  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_47_WIDTH },
14662  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_48_CHECKER_TYPE,
14663  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_48_WIDTH },
14664  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_49_CHECKER_TYPE,
14665  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_49_WIDTH },
14666  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_50_CHECKER_TYPE,
14667  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_50_WIDTH },
14668  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_51_CHECKER_TYPE,
14669  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_51_WIDTH },
14670  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_52_CHECKER_TYPE,
14671  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_52_WIDTH },
14672  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_53_CHECKER_TYPE,
14673  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_53_WIDTH },
14674  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_54_CHECKER_TYPE,
14675  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_54_WIDTH },
14676  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_55_CHECKER_TYPE,
14677  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_55_WIDTH },
14678  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_56_CHECKER_TYPE,
14679  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_56_WIDTH },
14680  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_57_CHECKER_TYPE,
14681  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_57_WIDTH },
14682  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_58_CHECKER_TYPE,
14683  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_58_WIDTH },
14684  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_59_CHECKER_TYPE,
14685  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_59_WIDTH },
14686  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_60_CHECKER_TYPE,
14687  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_60_WIDTH },
14688  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_61_CHECKER_TYPE,
14689  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_61_WIDTH },
14690  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_62_CHECKER_TYPE,
14691  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_62_WIDTH },
14692  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_63_CHECKER_TYPE,
14693  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_63_WIDTH },
14694  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_64_CHECKER_TYPE,
14695  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_64_WIDTH },
14696  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_65_CHECKER_TYPE,
14697  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_65_WIDTH },
14698  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_66_CHECKER_TYPE,
14699  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_66_WIDTH },
14700  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_67_CHECKER_TYPE,
14701  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_67_WIDTH },
14702  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_68_CHECKER_TYPE,
14703  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_68_WIDTH },
14704  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_69_CHECKER_TYPE,
14705  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_69_WIDTH },
14706  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_70_CHECKER_TYPE,
14707  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_70_WIDTH },
14708  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_71_CHECKER_TYPE,
14709  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_71_WIDTH },
14710  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_72_CHECKER_TYPE,
14711  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_72_WIDTH },
14712  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_73_CHECKER_TYPE,
14713  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_73_WIDTH },
14714  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_74_CHECKER_TYPE,
14715  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_74_WIDTH },
14716  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_75_CHECKER_TYPE,
14717  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_75_WIDTH },
14718  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_76_CHECKER_TYPE,
14719  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_76_WIDTH },
14720  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_77_CHECKER_TYPE,
14721  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_77_WIDTH },
14722  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_78_CHECKER_TYPE,
14723  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_78_WIDTH },
14724  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_79_CHECKER_TYPE,
14725  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_79_WIDTH },
14726  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_80_CHECKER_TYPE,
14727  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_80_WIDTH },
14728  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_81_CHECKER_TYPE,
14729  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_81_WIDTH },
14730  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_82_CHECKER_TYPE,
14731  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_82_WIDTH },
14732  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_83_CHECKER_TYPE,
14733  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_83_WIDTH },
14734  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_84_CHECKER_TYPE,
14735  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_84_WIDTH },
14736  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_85_CHECKER_TYPE,
14737  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_85_WIDTH },
14738  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_86_CHECKER_TYPE,
14739  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_86_WIDTH },
14740  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_87_CHECKER_TYPE,
14741  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_87_WIDTH },
14742  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_88_CHECKER_TYPE,
14743  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_88_WIDTH },
14744  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_89_CHECKER_TYPE,
14745  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_89_WIDTH },
14746  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_90_CHECKER_TYPE,
14747  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_90_WIDTH },
14748  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_91_CHECKER_TYPE,
14749  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_91_WIDTH },
14750  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_92_CHECKER_TYPE,
14751  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_92_WIDTH },
14752  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_93_CHECKER_TYPE,
14753  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_93_WIDTH },
14754  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_94_CHECKER_TYPE,
14755  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_94_WIDTH },
14756  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_95_CHECKER_TYPE,
14757  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_95_WIDTH },
14758  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_96_CHECKER_TYPE,
14759  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_96_WIDTH },
14760  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_97_CHECKER_TYPE,
14761  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_97_WIDTH },
14762  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_98_CHECKER_TYPE,
14763  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_98_WIDTH },
14764  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_99_CHECKER_TYPE,
14765  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_99_WIDTH },
14766  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_100_CHECKER_TYPE,
14767  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_100_WIDTH },
14768  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_101_CHECKER_TYPE,
14769  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_101_WIDTH },
14770  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_102_CHECKER_TYPE,
14771  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_102_WIDTH },
14772  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_103_CHECKER_TYPE,
14773  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_103_WIDTH },
14774  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_104_CHECKER_TYPE,
14775  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_104_WIDTH },
14776  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_105_CHECKER_TYPE,
14777  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_105_WIDTH },
14778  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_106_CHECKER_TYPE,
14779  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_106_WIDTH },
14780  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_107_CHECKER_TYPE,
14781  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_107_WIDTH },
14782  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_108_CHECKER_TYPE,
14783  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_108_WIDTH },
14784  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_109_CHECKER_TYPE,
14785  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_109_WIDTH },
14786  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_110_CHECKER_TYPE,
14787  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_110_WIDTH },
14788  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_111_CHECKER_TYPE,
14789  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_111_WIDTH },
14790  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_112_CHECKER_TYPE,
14791  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_112_WIDTH },
14792  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_113_CHECKER_TYPE,
14793  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_113_WIDTH },
14794  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_114_CHECKER_TYPE,
14795  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_114_WIDTH },
14796  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_115_CHECKER_TYPE,
14797  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_115_WIDTH },
14798  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_116_CHECKER_TYPE,
14799  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_116_WIDTH },
14800  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_117_CHECKER_TYPE,
14801  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_117_WIDTH },
14802  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_118_CHECKER_TYPE,
14803  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_118_WIDTH },
14804  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_119_CHECKER_TYPE,
14805  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_119_WIDTH },
14806  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_120_CHECKER_TYPE,
14807  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_120_WIDTH },
14808  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_121_CHECKER_TYPE,
14809  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_121_WIDTH },
14810  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_122_CHECKER_TYPE,
14811  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_122_WIDTH },
14812  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_123_CHECKER_TYPE,
14813  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_123_WIDTH },
14814  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_124_CHECKER_TYPE,
14815  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_124_WIDTH },
14816  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_125_CHECKER_TYPE,
14817  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_125_WIDTH },
14818  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_126_CHECKER_TYPE,
14819  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_126_WIDTH },
14820  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_127_CHECKER_TYPE,
14821  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_127_WIDTH },
14822  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_128_CHECKER_TYPE,
14823  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_128_WIDTH },
14824  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_129_CHECKER_TYPE,
14825  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_129_WIDTH },
14826  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_130_CHECKER_TYPE,
14827  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_130_WIDTH },
14828  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_131_CHECKER_TYPE,
14829  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_131_WIDTH },
14830  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_132_CHECKER_TYPE,
14831  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_132_WIDTH },
14832  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_133_CHECKER_TYPE,
14833  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_133_WIDTH },
14834  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_134_CHECKER_TYPE,
14835  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_134_WIDTH },
14836  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_135_CHECKER_TYPE,
14837  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_135_WIDTH },
14838  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_136_CHECKER_TYPE,
14839  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_136_WIDTH },
14840  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_137_CHECKER_TYPE,
14841  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_137_WIDTH },
14842  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_138_CHECKER_TYPE,
14843  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_138_WIDTH },
14844  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_139_CHECKER_TYPE,
14845  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_139_WIDTH },
14846  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_140_CHECKER_TYPE,
14847  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_140_WIDTH },
14848  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_141_CHECKER_TYPE,
14849  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_141_WIDTH },
14850  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_142_CHECKER_TYPE,
14851  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_142_WIDTH },
14852  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_143_CHECKER_TYPE,
14853  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_143_WIDTH },
14854  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_144_CHECKER_TYPE,
14855  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_144_WIDTH },
14856  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_145_CHECKER_TYPE,
14857  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_145_WIDTH },
14858  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_146_CHECKER_TYPE,
14859  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_146_WIDTH },
14860  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_147_CHECKER_TYPE,
14861  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_147_WIDTH },
14862  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_148_CHECKER_TYPE,
14863  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_148_WIDTH },
14864  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_149_CHECKER_TYPE,
14865  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_149_WIDTH },
14866  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_150_CHECKER_TYPE,
14867  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_150_WIDTH },
14868  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_151_CHECKER_TYPE,
14869  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_151_WIDTH },
14870  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_152_CHECKER_TYPE,
14871  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_152_WIDTH },
14872  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_153_CHECKER_TYPE,
14873  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_153_WIDTH },
14874  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_154_CHECKER_TYPE,
14875  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_154_WIDTH },
14876  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_155_CHECKER_TYPE,
14877  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_155_WIDTH },
14878  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_156_CHECKER_TYPE,
14879  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_156_WIDTH },
14880  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_157_CHECKER_TYPE,
14881  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_157_WIDTH },
14882  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_158_CHECKER_TYPE,
14883  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_158_WIDTH },
14884  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_159_CHECKER_TYPE,
14885  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_159_WIDTH },
14886  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_160_CHECKER_TYPE,
14887  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_160_WIDTH },
14888  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_161_CHECKER_TYPE,
14889  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_161_WIDTH },
14890  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_162_CHECKER_TYPE,
14891  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_162_WIDTH },
14892  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_163_CHECKER_TYPE,
14893  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_163_WIDTH },
14894  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_164_CHECKER_TYPE,
14895  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_164_WIDTH },
14896  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_165_CHECKER_TYPE,
14897  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_165_WIDTH },
14898  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_166_CHECKER_TYPE,
14899  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_166_WIDTH },
14900  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_167_CHECKER_TYPE,
14901  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_167_WIDTH },
14902  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_168_CHECKER_TYPE,
14903  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_168_WIDTH },
14904  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_169_CHECKER_TYPE,
14905  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_169_WIDTH },
14906  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_170_CHECKER_TYPE,
14907  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_170_WIDTH },
14908  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_171_CHECKER_TYPE,
14909  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_171_WIDTH },
14910  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_172_CHECKER_TYPE,
14911  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_172_WIDTH },
14912  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_173_CHECKER_TYPE,
14913  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_173_WIDTH },
14914  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_174_CHECKER_TYPE,
14915  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_174_WIDTH },
14916  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_175_CHECKER_TYPE,
14917  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_175_WIDTH },
14918  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_176_CHECKER_TYPE,
14919  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_176_WIDTH },
14920  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_177_CHECKER_TYPE,
14921  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_177_WIDTH },
14922  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_178_CHECKER_TYPE,
14923  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_178_WIDTH },
14924  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_179_CHECKER_TYPE,
14925  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_179_WIDTH },
14926  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_180_CHECKER_TYPE,
14927  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_180_WIDTH },
14928  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_181_CHECKER_TYPE,
14929  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_181_WIDTH },
14930  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_182_CHECKER_TYPE,
14931  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_182_WIDTH },
14932  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_183_CHECKER_TYPE,
14933  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_183_WIDTH },
14934  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_184_CHECKER_TYPE,
14935  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_184_WIDTH },
14936  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_185_CHECKER_TYPE,
14937  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_185_WIDTH },
14938  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_186_CHECKER_TYPE,
14939  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_186_WIDTH },
14940  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_187_CHECKER_TYPE,
14941  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_187_WIDTH },
14942  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_188_CHECKER_TYPE,
14943  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_188_WIDTH },
14944  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_189_CHECKER_TYPE,
14945  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_189_WIDTH },
14946  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_190_CHECKER_TYPE,
14947  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_190_WIDTH },
14948  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_191_CHECKER_TYPE,
14949  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_191_WIDTH },
14950  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_192_CHECKER_TYPE,
14951  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_192_WIDTH },
14952  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_193_CHECKER_TYPE,
14953  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_193_WIDTH },
14954  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_194_CHECKER_TYPE,
14955  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_194_WIDTH },
14956  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_195_CHECKER_TYPE,
14957  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_195_WIDTH },
14958  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_196_CHECKER_TYPE,
14959  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_196_WIDTH },
14960  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_197_CHECKER_TYPE,
14961  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_197_WIDTH },
14962  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_198_CHECKER_TYPE,
14963  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_198_WIDTH },
14964  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_199_CHECKER_TYPE,
14965  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_199_WIDTH },
14966  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_200_CHECKER_TYPE,
14967  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_200_WIDTH },
14968  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_201_CHECKER_TYPE,
14969  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_201_WIDTH },
14970  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_202_CHECKER_TYPE,
14971  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_202_WIDTH },
14972  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_203_CHECKER_TYPE,
14973  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_203_WIDTH },
14974  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_204_CHECKER_TYPE,
14975  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_204_WIDTH },
14976  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_205_CHECKER_TYPE,
14977  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_205_WIDTH },
14978  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_206_CHECKER_TYPE,
14979  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_206_WIDTH },
14980  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_207_CHECKER_TYPE,
14981  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_207_WIDTH },
14982  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_208_CHECKER_TYPE,
14983  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_208_WIDTH },
14984  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_209_CHECKER_TYPE,
14985  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_209_WIDTH },
14986  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_210_CHECKER_TYPE,
14987  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_210_WIDTH },
14988  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_211_CHECKER_TYPE,
14989  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_211_WIDTH },
14990  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_212_CHECKER_TYPE,
14991  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_212_WIDTH },
14992  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_213_CHECKER_TYPE,
14993  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_213_WIDTH },
14994  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_214_CHECKER_TYPE,
14995  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_214_WIDTH },
14996  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_215_CHECKER_TYPE,
14997  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_215_WIDTH },
14998  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_216_CHECKER_TYPE,
14999  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_216_WIDTH },
15000  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_217_CHECKER_TYPE,
15001  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_217_WIDTH },
15002  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_218_CHECKER_TYPE,
15003  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_218_WIDTH },
15004  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_219_CHECKER_TYPE,
15005  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_219_WIDTH },
15006  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_220_CHECKER_TYPE,
15007  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_220_WIDTH },
15008  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_221_CHECKER_TYPE,
15009  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_221_WIDTH },
15010  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_222_CHECKER_TYPE,
15011  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_222_WIDTH },
15012  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_223_CHECKER_TYPE,
15013  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_223_WIDTH },
15014  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_224_CHECKER_TYPE,
15015  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_224_WIDTH },
15016  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_225_CHECKER_TYPE,
15017  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_225_WIDTH },
15018  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_226_CHECKER_TYPE,
15019  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_226_WIDTH },
15020  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_227_CHECKER_TYPE,
15021  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_227_WIDTH },
15022  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_228_CHECKER_TYPE,
15023  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_228_WIDTH },
15024  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_229_CHECKER_TYPE,
15025  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_229_WIDTH },
15026  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_230_CHECKER_TYPE,
15027  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_230_WIDTH },
15028  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_231_CHECKER_TYPE,
15029  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_231_WIDTH },
15030  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_232_CHECKER_TYPE,
15031  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_232_WIDTH },
15032  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_233_CHECKER_TYPE,
15033  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_233_WIDTH },
15034  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_234_CHECKER_TYPE,
15035  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_234_WIDTH },
15036  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_235_CHECKER_TYPE,
15037  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_235_WIDTH },
15038  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_236_CHECKER_TYPE,
15039  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_236_WIDTH },
15040  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_237_CHECKER_TYPE,
15041  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_237_WIDTH },
15042  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_238_CHECKER_TYPE,
15043  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_238_WIDTH },
15044  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_239_CHECKER_TYPE,
15045  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_239_WIDTH },
15046  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_240_CHECKER_TYPE,
15047  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_240_WIDTH },
15048  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_241_CHECKER_TYPE,
15049  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_241_WIDTH },
15050  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_242_CHECKER_TYPE,
15051  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_242_WIDTH },
15052  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_243_CHECKER_TYPE,
15053  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_243_WIDTH },
15054  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_244_CHECKER_TYPE,
15055  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_244_WIDTH },
15056  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_245_CHECKER_TYPE,
15057  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_245_WIDTH },
15058  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_246_CHECKER_TYPE,
15059  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_246_WIDTH },
15060  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_247_CHECKER_TYPE,
15061  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_247_WIDTH },
15062  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_248_CHECKER_TYPE,
15063  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_248_WIDTH },
15064  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_249_CHECKER_TYPE,
15065  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_249_WIDTH },
15066  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_250_CHECKER_TYPE,
15067  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_250_WIDTH },
15068  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_251_CHECKER_TYPE,
15069  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_251_WIDTH },
15070  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_252_CHECKER_TYPE,
15071  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_252_WIDTH },
15072  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_253_CHECKER_TYPE,
15073  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_253_WIDTH },
15074  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_254_CHECKER_TYPE,
15075  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_254_WIDTH },
15076  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_255_CHECKER_TYPE,
15077  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_255_WIDTH },
15078 };
15079 
15085 static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_groupEntries[SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_MAX_NUM_CHECKERS] =
15086 {
15087  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_0_CHECKER_TYPE,
15088  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_0_WIDTH },
15089  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_1_CHECKER_TYPE,
15090  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_1_WIDTH },
15091  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_2_CHECKER_TYPE,
15092  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_2_WIDTH },
15093  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_3_CHECKER_TYPE,
15094  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_3_WIDTH },
15095  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_4_CHECKER_TYPE,
15096  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_4_WIDTH },
15097  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_5_CHECKER_TYPE,
15098  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_5_WIDTH },
15099  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_6_CHECKER_TYPE,
15100  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_6_WIDTH },
15101  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_7_CHECKER_TYPE,
15102  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_7_WIDTH },
15103  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_8_CHECKER_TYPE,
15104  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_8_WIDTH },
15105  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_9_CHECKER_TYPE,
15106  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_9_WIDTH },
15107  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_10_CHECKER_TYPE,
15108  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_10_WIDTH },
15109  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_11_CHECKER_TYPE,
15110  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_11_WIDTH },
15111  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_12_CHECKER_TYPE,
15112  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_12_WIDTH },
15113  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_13_CHECKER_TYPE,
15114  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_13_WIDTH },
15115  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_14_CHECKER_TYPE,
15116  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_14_WIDTH },
15117  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_15_CHECKER_TYPE,
15118  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_15_WIDTH },
15119  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_16_CHECKER_TYPE,
15120  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_16_WIDTH },
15121  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_17_CHECKER_TYPE,
15122  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_17_WIDTH },
15123  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_18_CHECKER_TYPE,
15124  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_18_WIDTH },
15125  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_19_CHECKER_TYPE,
15126  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_19_WIDTH },
15127  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_20_CHECKER_TYPE,
15128  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_20_WIDTH },
15129  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_21_CHECKER_TYPE,
15130  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_21_WIDTH },
15131  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_22_CHECKER_TYPE,
15132  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_22_WIDTH },
15133  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_23_CHECKER_TYPE,
15134  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_23_WIDTH },
15135  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_24_CHECKER_TYPE,
15136  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_24_WIDTH },
15137  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_25_CHECKER_TYPE,
15138  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_25_WIDTH },
15139  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_26_CHECKER_TYPE,
15140  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_26_WIDTH },
15141  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_27_CHECKER_TYPE,
15142  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_27_WIDTH },
15143  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_28_CHECKER_TYPE,
15144  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_28_WIDTH },
15145  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_29_CHECKER_TYPE,
15146  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_29_WIDTH },
15147  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_30_CHECKER_TYPE,
15148  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_30_WIDTH },
15149  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_31_CHECKER_TYPE,
15150  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_31_WIDTH },
15151  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_32_CHECKER_TYPE,
15152  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_32_WIDTH },
15153  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_33_CHECKER_TYPE,
15154  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_33_WIDTH },
15155  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_34_CHECKER_TYPE,
15156  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_34_WIDTH },
15157  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_35_CHECKER_TYPE,
15158  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_35_WIDTH },
15159  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_36_CHECKER_TYPE,
15160  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_36_WIDTH },
15161  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_37_CHECKER_TYPE,
15162  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_37_WIDTH },
15163  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_38_CHECKER_TYPE,
15164  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_38_WIDTH },
15165  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_39_CHECKER_TYPE,
15166  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_39_WIDTH },
15167  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_40_CHECKER_TYPE,
15168  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_40_WIDTH },
15169  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_41_CHECKER_TYPE,
15170  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_41_WIDTH },
15171  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_42_CHECKER_TYPE,
15172  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_42_WIDTH },
15173  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_43_CHECKER_TYPE,
15174  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_43_WIDTH },
15175  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_44_CHECKER_TYPE,
15176  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_44_WIDTH },
15177  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_45_CHECKER_TYPE,
15178  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_45_WIDTH },
15179  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_46_CHECKER_TYPE,
15180  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_46_WIDTH },
15181  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_47_CHECKER_TYPE,
15182  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_47_WIDTH },
15183  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_48_CHECKER_TYPE,
15184  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_48_WIDTH },
15185  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_49_CHECKER_TYPE,
15186  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_49_WIDTH },
15187  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_50_CHECKER_TYPE,
15188  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_50_WIDTH },
15189  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_51_CHECKER_TYPE,
15190  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_51_WIDTH },
15191  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_52_CHECKER_TYPE,
15192  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_52_WIDTH },
15193  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_53_CHECKER_TYPE,
15194  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_53_WIDTH },
15195  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_54_CHECKER_TYPE,
15196  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_54_WIDTH },
15197  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_55_CHECKER_TYPE,
15198  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_55_WIDTH },
15199  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_56_CHECKER_TYPE,
15200  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_56_WIDTH },
15201  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_57_CHECKER_TYPE,
15202  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_57_WIDTH },
15203  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_58_CHECKER_TYPE,
15204  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_58_WIDTH },
15205  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_59_CHECKER_TYPE,
15206  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_59_WIDTH },
15207  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_60_CHECKER_TYPE,
15208  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_60_WIDTH },
15209  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_61_CHECKER_TYPE,
15210  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_61_WIDTH },
15211  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_62_CHECKER_TYPE,
15212  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_62_WIDTH },
15213  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_63_CHECKER_TYPE,
15214  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_63_WIDTH },
15215  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_64_CHECKER_TYPE,
15216  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_64_WIDTH },
15217  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_65_CHECKER_TYPE,
15218  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_65_WIDTH },
15219  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_66_CHECKER_TYPE,
15220  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_66_WIDTH },
15221  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_67_CHECKER_TYPE,
15222  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_67_WIDTH },
15223  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_68_CHECKER_TYPE,
15224  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_68_WIDTH },
15225  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_69_CHECKER_TYPE,
15226  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_69_WIDTH },
15227  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_70_CHECKER_TYPE,
15228  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_70_WIDTH },
15229  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_71_CHECKER_TYPE,
15230  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_71_WIDTH },
15231  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_72_CHECKER_TYPE,
15232  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_72_WIDTH },
15233  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_73_CHECKER_TYPE,
15234  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_73_WIDTH },
15235  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_74_CHECKER_TYPE,
15236  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_74_WIDTH },
15237  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_75_CHECKER_TYPE,
15238  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_75_WIDTH },
15239  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_76_CHECKER_TYPE,
15240  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_76_WIDTH },
15241  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_77_CHECKER_TYPE,
15242  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_77_WIDTH },
15243  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_78_CHECKER_TYPE,
15244  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_78_WIDTH },
15245  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_79_CHECKER_TYPE,
15246  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_79_WIDTH },
15247  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_80_CHECKER_TYPE,
15248  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_80_WIDTH },
15249  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_81_CHECKER_TYPE,
15250  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_81_WIDTH },
15251  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_82_CHECKER_TYPE,
15252  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_82_WIDTH },
15253  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_83_CHECKER_TYPE,
15254  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_83_WIDTH },
15255  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_84_CHECKER_TYPE,
15256  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_84_WIDTH },
15257  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_85_CHECKER_TYPE,
15258  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_85_WIDTH },
15259  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_86_CHECKER_TYPE,
15260  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_86_WIDTH },
15261  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_87_CHECKER_TYPE,
15262  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_87_WIDTH },
15263  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_88_CHECKER_TYPE,
15264  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_88_WIDTH },
15265  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_89_CHECKER_TYPE,
15266  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_89_WIDTH },
15267  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_90_CHECKER_TYPE,
15268  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_90_WIDTH },
15269  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_91_CHECKER_TYPE,
15270  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_91_WIDTH },
15271  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_92_CHECKER_TYPE,
15272  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_92_WIDTH },
15273  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_93_CHECKER_TYPE,
15274  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_93_WIDTH },
15275  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_94_CHECKER_TYPE,
15276  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_94_WIDTH },
15277  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_95_CHECKER_TYPE,
15278  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_95_WIDTH },
15279  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_96_CHECKER_TYPE,
15280  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_96_WIDTH },
15281  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_97_CHECKER_TYPE,
15282  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_97_WIDTH },
15283  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_98_CHECKER_TYPE,
15284  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_98_WIDTH },
15285  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_99_CHECKER_TYPE,
15286  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_99_WIDTH },
15287  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_100_CHECKER_TYPE,
15288  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_100_WIDTH },
15289  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_101_CHECKER_TYPE,
15290  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_101_WIDTH },
15291  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_102_CHECKER_TYPE,
15292  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_102_WIDTH },
15293  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_103_CHECKER_TYPE,
15294  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_103_WIDTH },
15295  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_104_CHECKER_TYPE,
15296  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_104_WIDTH },
15297  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_105_CHECKER_TYPE,
15298  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_105_WIDTH },
15299  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_106_CHECKER_TYPE,
15300  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_106_WIDTH },
15301  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_107_CHECKER_TYPE,
15302  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_107_WIDTH },
15303  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_108_CHECKER_TYPE,
15304  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_108_WIDTH },
15305  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_109_CHECKER_TYPE,
15306  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_109_WIDTH },
15307  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_110_CHECKER_TYPE,
15308  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_110_WIDTH },
15309  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_111_CHECKER_TYPE,
15310  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_111_WIDTH },
15311  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_112_CHECKER_TYPE,
15312  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_112_WIDTH },
15313  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_113_CHECKER_TYPE,
15314  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_113_WIDTH },
15315  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_114_CHECKER_TYPE,
15316  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_114_WIDTH },
15317  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_115_CHECKER_TYPE,
15318  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_115_WIDTH },
15319  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_116_CHECKER_TYPE,
15320  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_116_WIDTH },
15321  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_117_CHECKER_TYPE,
15322  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_117_WIDTH },
15323  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_118_CHECKER_TYPE,
15324  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_118_WIDTH },
15325  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_119_CHECKER_TYPE,
15326  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_119_WIDTH },
15327  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_120_CHECKER_TYPE,
15328  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_120_WIDTH },
15329  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_121_CHECKER_TYPE,
15330  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_121_WIDTH },
15331  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_122_CHECKER_TYPE,
15332  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_122_WIDTH },
15333  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_123_CHECKER_TYPE,
15334  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_123_WIDTH },
15335  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_124_CHECKER_TYPE,
15336  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_124_WIDTH },
15337  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_125_CHECKER_TYPE,
15338  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_125_WIDTH },
15339  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_126_CHECKER_TYPE,
15340  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_126_WIDTH },
15341  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_127_CHECKER_TYPE,
15342  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_127_WIDTH },
15343  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_128_CHECKER_TYPE,
15344  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_128_WIDTH },
15345  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_129_CHECKER_TYPE,
15346  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_129_WIDTH },
15347  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_130_CHECKER_TYPE,
15348  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_130_WIDTH },
15349  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_131_CHECKER_TYPE,
15350  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_131_WIDTH },
15351  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_132_CHECKER_TYPE,
15352  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_132_WIDTH },
15353  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_133_CHECKER_TYPE,
15354  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_133_WIDTH },
15355 };
15356 
15362 static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_groupEntries[SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_MAX_NUM_CHECKERS] =
15363 {
15364  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_0_CHECKER_TYPE,
15365  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_0_WIDTH },
15366  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_1_CHECKER_TYPE,
15367  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_1_WIDTH },
15368  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_2_CHECKER_TYPE,
15369  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_2_WIDTH },
15370  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_3_CHECKER_TYPE,
15371  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_3_WIDTH },
15372  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_4_CHECKER_TYPE,
15373  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_4_WIDTH },
15374  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_5_CHECKER_TYPE,
15375  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_5_WIDTH },
15376  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_6_CHECKER_TYPE,
15377  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_6_WIDTH },
15378  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_7_CHECKER_TYPE,
15379  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_7_WIDTH },
15380  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_8_CHECKER_TYPE,
15381  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_8_WIDTH },
15382  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_9_CHECKER_TYPE,
15383  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_9_WIDTH },
15384  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_10_CHECKER_TYPE,
15385  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_10_WIDTH },
15386  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_11_CHECKER_TYPE,
15387  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_11_WIDTH },
15388  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_12_CHECKER_TYPE,
15389  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_12_WIDTH },
15390  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_13_CHECKER_TYPE,
15391  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_13_WIDTH },
15392  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_14_CHECKER_TYPE,
15393  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_14_WIDTH },
15394  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_15_CHECKER_TYPE,
15395  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_15_WIDTH },
15396  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_16_CHECKER_TYPE,
15397  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_16_WIDTH },
15398  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_17_CHECKER_TYPE,
15399  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_17_WIDTH },
15400  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_18_CHECKER_TYPE,
15401  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_18_WIDTH },
15402  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_19_CHECKER_TYPE,
15403  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_19_WIDTH },
15404  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_20_CHECKER_TYPE,
15405  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_20_WIDTH },
15406  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_21_CHECKER_TYPE,
15407  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_21_WIDTH },
15408  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_22_CHECKER_TYPE,
15409  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_22_WIDTH },
15410  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_23_CHECKER_TYPE,
15411  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_23_WIDTH },
15412  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_24_CHECKER_TYPE,
15413  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_24_WIDTH },
15414  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_25_CHECKER_TYPE,
15415  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_25_WIDTH },
15416  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_26_CHECKER_TYPE,
15417  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_26_WIDTH },
15418  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_27_CHECKER_TYPE,
15419  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_27_WIDTH },
15420  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_28_CHECKER_TYPE,
15421  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_28_WIDTH },
15422  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_29_CHECKER_TYPE,
15423  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_29_WIDTH },
15424  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_30_CHECKER_TYPE,
15425  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_30_WIDTH },
15426  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_31_CHECKER_TYPE,
15427  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_31_WIDTH },
15428  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_32_CHECKER_TYPE,
15429  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_32_WIDTH },
15430  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_33_CHECKER_TYPE,
15431  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_33_WIDTH },
15432  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_34_CHECKER_TYPE,
15433  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_34_WIDTH },
15434  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_35_CHECKER_TYPE,
15435  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_35_WIDTH },
15436  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_36_CHECKER_TYPE,
15437  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_36_WIDTH },
15438  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_37_CHECKER_TYPE,
15439  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_37_WIDTH },
15440  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_38_CHECKER_TYPE,
15441  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_38_WIDTH },
15442  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_39_CHECKER_TYPE,
15443  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_39_WIDTH },
15444  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_40_CHECKER_TYPE,
15445  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_40_WIDTH },
15446  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_41_CHECKER_TYPE,
15447  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_41_WIDTH },
15448  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_42_CHECKER_TYPE,
15449  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_42_WIDTH },
15450  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_43_CHECKER_TYPE,
15451  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_43_WIDTH },
15452  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_44_CHECKER_TYPE,
15453  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_44_WIDTH },
15454  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_45_CHECKER_TYPE,
15455  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_45_WIDTH },
15456  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_46_CHECKER_TYPE,
15457  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_46_WIDTH },
15458  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_47_CHECKER_TYPE,
15459  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_47_WIDTH },
15460  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_48_CHECKER_TYPE,
15461  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_48_WIDTH },
15462  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_49_CHECKER_TYPE,
15463  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_49_WIDTH },
15464  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_50_CHECKER_TYPE,
15465  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_50_WIDTH },
15466  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_51_CHECKER_TYPE,
15467  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_51_WIDTH },
15468  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_52_CHECKER_TYPE,
15469  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_52_WIDTH },
15470  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_53_CHECKER_TYPE,
15471  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_53_WIDTH },
15472  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_54_CHECKER_TYPE,
15473  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_54_WIDTH },
15474  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_55_CHECKER_TYPE,
15475  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_55_WIDTH },
15476  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_56_CHECKER_TYPE,
15477  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_56_WIDTH },
15478  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_57_CHECKER_TYPE,
15479  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_57_WIDTH },
15480  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_58_CHECKER_TYPE,
15481  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_58_WIDTH },
15482  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_59_CHECKER_TYPE,
15483  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_59_WIDTH },
15484  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_60_CHECKER_TYPE,
15485  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_60_WIDTH },
15486  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_61_CHECKER_TYPE,
15487  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_61_WIDTH },
15488  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_62_CHECKER_TYPE,
15489  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_62_WIDTH },
15490  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_63_CHECKER_TYPE,
15491  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_63_WIDTH },
15492  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_64_CHECKER_TYPE,
15493  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_64_WIDTH },
15494  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_65_CHECKER_TYPE,
15495  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_65_WIDTH },
15496  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_66_CHECKER_TYPE,
15497  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_66_WIDTH },
15498  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_67_CHECKER_TYPE,
15499  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_67_WIDTH },
15500  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_68_CHECKER_TYPE,
15501  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_68_WIDTH },
15502  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_69_CHECKER_TYPE,
15503  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_69_WIDTH },
15504  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_70_CHECKER_TYPE,
15505  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_70_WIDTH },
15506  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_71_CHECKER_TYPE,
15507  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_71_WIDTH },
15508  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_72_CHECKER_TYPE,
15509  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_72_WIDTH },
15510  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_73_CHECKER_TYPE,
15511  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_73_WIDTH },
15512  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_74_CHECKER_TYPE,
15513  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_74_WIDTH },
15514  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_75_CHECKER_TYPE,
15515  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_75_WIDTH },
15516  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_76_CHECKER_TYPE,
15517  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_76_WIDTH },
15518  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_77_CHECKER_TYPE,
15519  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_77_WIDTH },
15520  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_78_CHECKER_TYPE,
15521  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_78_WIDTH },
15522  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_79_CHECKER_TYPE,
15523  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_79_WIDTH },
15524  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_80_CHECKER_TYPE,
15525  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_80_WIDTH },
15526  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_81_CHECKER_TYPE,
15527  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_81_WIDTH },
15528  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_82_CHECKER_TYPE,
15529  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_82_WIDTH },
15530  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_83_CHECKER_TYPE,
15531  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_83_WIDTH },
15532  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_84_CHECKER_TYPE,
15533  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_84_WIDTH },
15534  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_85_CHECKER_TYPE,
15535  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_85_WIDTH },
15536  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_86_CHECKER_TYPE,
15537  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_86_WIDTH },
15538  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_87_CHECKER_TYPE,
15539  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_87_WIDTH },
15540  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_88_CHECKER_TYPE,
15541  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_88_WIDTH },
15542  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_89_CHECKER_TYPE,
15543  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_89_WIDTH },
15544  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_90_CHECKER_TYPE,
15545  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_90_WIDTH },
15546  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_91_CHECKER_TYPE,
15547  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_91_WIDTH },
15548  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_92_CHECKER_TYPE,
15549  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_92_WIDTH },
15550  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_93_CHECKER_TYPE,
15551  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_93_WIDTH },
15552  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_94_CHECKER_TYPE,
15553  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_94_WIDTH },
15554  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_95_CHECKER_TYPE,
15555  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_95_WIDTH },
15556  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_96_CHECKER_TYPE,
15557  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_96_WIDTH },
15558  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_97_CHECKER_TYPE,
15559  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_97_WIDTH },
15560  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_98_CHECKER_TYPE,
15561  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_98_WIDTH },
15562  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_99_CHECKER_TYPE,
15563  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_99_WIDTH },
15564  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_100_CHECKER_TYPE,
15565  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_100_WIDTH },
15566  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_101_CHECKER_TYPE,
15567  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_101_WIDTH },
15568  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_102_CHECKER_TYPE,
15569  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_102_WIDTH },
15570  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_103_CHECKER_TYPE,
15571  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_103_WIDTH },
15572  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_104_CHECKER_TYPE,
15573  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_104_WIDTH },
15574  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_105_CHECKER_TYPE,
15575  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_105_WIDTH },
15576  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_106_CHECKER_TYPE,
15577  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_106_WIDTH },
15578  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_107_CHECKER_TYPE,
15579  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_107_WIDTH },
15580  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_108_CHECKER_TYPE,
15581  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_108_WIDTH },
15582  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_109_CHECKER_TYPE,
15583  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_109_WIDTH },
15584  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_110_CHECKER_TYPE,
15585  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_110_WIDTH },
15586  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_111_CHECKER_TYPE,
15587  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_111_WIDTH },
15588  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_112_CHECKER_TYPE,
15589  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_112_WIDTH },
15590  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_113_CHECKER_TYPE,
15591  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_113_WIDTH },
15592  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_114_CHECKER_TYPE,
15593  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_114_WIDTH },
15594  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_115_CHECKER_TYPE,
15595  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_115_WIDTH },
15596  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_116_CHECKER_TYPE,
15597  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_116_WIDTH },
15598  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_117_CHECKER_TYPE,
15599  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_117_WIDTH },
15600  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_118_CHECKER_TYPE,
15601  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_118_WIDTH },
15602  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_119_CHECKER_TYPE,
15603  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_119_WIDTH },
15604  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_120_CHECKER_TYPE,
15605  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_120_WIDTH },
15606  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_121_CHECKER_TYPE,
15607  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_121_WIDTH },
15608  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_122_CHECKER_TYPE,
15609  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_122_WIDTH },
15610  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_123_CHECKER_TYPE,
15611  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_123_WIDTH },
15612  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_124_CHECKER_TYPE,
15613  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_124_WIDTH },
15614  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_125_CHECKER_TYPE,
15615  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_125_WIDTH },
15616  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_126_CHECKER_TYPE,
15617  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_126_WIDTH },
15618  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_127_CHECKER_TYPE,
15619  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_127_WIDTH },
15620  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_128_CHECKER_TYPE,
15621  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_128_WIDTH },
15622  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_129_CHECKER_TYPE,
15623  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_129_WIDTH },
15624  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_130_CHECKER_TYPE,
15625  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_130_WIDTH },
15626  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_131_CHECKER_TYPE,
15627  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_131_WIDTH },
15628  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_132_CHECKER_TYPE,
15629  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_132_WIDTH },
15630  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_133_CHECKER_TYPE,
15631  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_133_WIDTH },
15632  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_134_CHECKER_TYPE,
15633  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_134_WIDTH },
15634  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_135_CHECKER_TYPE,
15635  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_135_WIDTH },
15636  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_136_CHECKER_TYPE,
15637  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_136_WIDTH },
15638  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_137_CHECKER_TYPE,
15639  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_137_WIDTH },
15640  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_138_CHECKER_TYPE,
15641  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_138_WIDTH },
15642  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_139_CHECKER_TYPE,
15643  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_139_WIDTH },
15644  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_140_CHECKER_TYPE,
15645  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_140_WIDTH },
15646  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_141_CHECKER_TYPE,
15647  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_141_WIDTH },
15648  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_142_CHECKER_TYPE,
15649  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_142_WIDTH },
15650  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_143_CHECKER_TYPE,
15651  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_143_WIDTH },
15652  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_144_CHECKER_TYPE,
15653  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_144_WIDTH },
15654  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_145_CHECKER_TYPE,
15655  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_145_WIDTH },
15656  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_146_CHECKER_TYPE,
15657  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_146_WIDTH },
15658  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_147_CHECKER_TYPE,
15659  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_147_WIDTH },
15660  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_148_CHECKER_TYPE,
15661  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_148_WIDTH },
15662  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_149_CHECKER_TYPE,
15663  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_149_WIDTH },
15664  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_150_CHECKER_TYPE,
15665  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_150_WIDTH },
15666  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_151_CHECKER_TYPE,
15667  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_151_WIDTH },
15668  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_152_CHECKER_TYPE,
15669  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_152_WIDTH },
15670  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_153_CHECKER_TYPE,
15671  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_153_WIDTH },
15672  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_154_CHECKER_TYPE,
15673  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_154_WIDTH },
15674  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_155_CHECKER_TYPE,
15675  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_155_WIDTH },
15676  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_156_CHECKER_TYPE,
15677  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_156_WIDTH },
15678  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_157_CHECKER_TYPE,
15679  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_157_WIDTH },
15680  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_158_CHECKER_TYPE,
15681  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_158_WIDTH },
15682  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_159_CHECKER_TYPE,
15683  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_159_WIDTH },
15684  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_160_CHECKER_TYPE,
15685  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_160_WIDTH },
15686  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_161_CHECKER_TYPE,
15687  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_161_WIDTH },
15688  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_162_CHECKER_TYPE,
15689  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_162_WIDTH },
15690  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_163_CHECKER_TYPE,
15691  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_163_WIDTH },
15692  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_164_CHECKER_TYPE,
15693  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_164_WIDTH },
15694  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_165_CHECKER_TYPE,
15695  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_165_WIDTH },
15696  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_166_CHECKER_TYPE,
15697  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_166_WIDTH },
15698  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_167_CHECKER_TYPE,
15699  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_167_WIDTH },
15700  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_168_CHECKER_TYPE,
15701  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_168_WIDTH },
15702  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_169_CHECKER_TYPE,
15703  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_169_WIDTH },
15704  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_170_CHECKER_TYPE,
15705  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_170_WIDTH },
15706  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_171_CHECKER_TYPE,
15707  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_171_WIDTH },
15708  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_172_CHECKER_TYPE,
15709  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_172_WIDTH },
15710  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_173_CHECKER_TYPE,
15711  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_173_WIDTH },
15712  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_174_CHECKER_TYPE,
15713  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_174_WIDTH },
15714  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_175_CHECKER_TYPE,
15715  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_175_WIDTH },
15716  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_176_CHECKER_TYPE,
15717  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_176_WIDTH },
15718  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_177_CHECKER_TYPE,
15719  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_177_WIDTH },
15720  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_178_CHECKER_TYPE,
15721  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_178_WIDTH },
15722  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_179_CHECKER_TYPE,
15723  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_179_WIDTH },
15724  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_180_CHECKER_TYPE,
15725  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_180_WIDTH },
15726  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_181_CHECKER_TYPE,
15727  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_181_WIDTH },
15728  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_182_CHECKER_TYPE,
15729  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_182_WIDTH },
15730  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_183_CHECKER_TYPE,
15731  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_183_WIDTH },
15732  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_184_CHECKER_TYPE,
15733  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_184_WIDTH },
15734  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_185_CHECKER_TYPE,
15735  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_185_WIDTH },
15736  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_186_CHECKER_TYPE,
15737  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_186_WIDTH },
15738  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_187_CHECKER_TYPE,
15739  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_187_WIDTH },
15740  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_188_CHECKER_TYPE,
15741  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_188_WIDTH },
15742  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_189_CHECKER_TYPE,
15743  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_189_WIDTH },
15744  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_190_CHECKER_TYPE,
15745  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_190_WIDTH },
15746  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_191_CHECKER_TYPE,
15747  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_191_WIDTH },
15748  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_192_CHECKER_TYPE,
15749  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_192_WIDTH },
15750  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_193_CHECKER_TYPE,
15751  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_193_WIDTH },
15752  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_194_CHECKER_TYPE,
15753  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_194_WIDTH },
15754  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_195_CHECKER_TYPE,
15755  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_195_WIDTH },
15756  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_196_CHECKER_TYPE,
15757  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_196_WIDTH },
15758  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_197_CHECKER_TYPE,
15759  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_197_WIDTH },
15760  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_198_CHECKER_TYPE,
15761  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_198_WIDTH },
15762  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_199_CHECKER_TYPE,
15763  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_199_WIDTH },
15764  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_200_CHECKER_TYPE,
15765  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_200_WIDTH },
15766  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_201_CHECKER_TYPE,
15767  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_201_WIDTH },
15768  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_202_CHECKER_TYPE,
15769  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_202_WIDTH },
15770  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_203_CHECKER_TYPE,
15771  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_203_WIDTH },
15772  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_204_CHECKER_TYPE,
15773  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_204_WIDTH },
15774  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_205_CHECKER_TYPE,
15775  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_205_WIDTH },
15776  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_206_CHECKER_TYPE,
15777  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_206_WIDTH },
15778  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_207_CHECKER_TYPE,
15779  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_207_WIDTH },
15780  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_208_CHECKER_TYPE,
15781  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_208_WIDTH },
15782  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_209_CHECKER_TYPE,
15783  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_209_WIDTH },
15784  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_210_CHECKER_TYPE,
15785  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_210_WIDTH },
15786  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_211_CHECKER_TYPE,
15787  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_211_WIDTH },
15788  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_212_CHECKER_TYPE,
15789  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_212_WIDTH },
15790  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_213_CHECKER_TYPE,
15791  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_213_WIDTH },
15792  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_214_CHECKER_TYPE,
15793  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_214_WIDTH },
15794  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_215_CHECKER_TYPE,
15795  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_215_WIDTH },
15796  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_216_CHECKER_TYPE,
15797  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_216_WIDTH },
15798  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_217_CHECKER_TYPE,
15799  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_217_WIDTH },
15800  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_218_CHECKER_TYPE,
15801  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_218_WIDTH },
15802  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_219_CHECKER_TYPE,
15803  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_219_WIDTH },
15804  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_220_CHECKER_TYPE,
15805  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_220_WIDTH },
15806  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_221_CHECKER_TYPE,
15807  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_221_WIDTH },
15808  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_222_CHECKER_TYPE,
15809  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_222_WIDTH },
15810  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_223_CHECKER_TYPE,
15811  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_223_WIDTH },
15812  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_224_CHECKER_TYPE,
15813  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_224_WIDTH },
15814  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_225_CHECKER_TYPE,
15815  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_225_WIDTH },
15816  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_226_CHECKER_TYPE,
15817  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_226_WIDTH },
15818  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_227_CHECKER_TYPE,
15819  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_227_WIDTH },
15820  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_228_CHECKER_TYPE,
15821  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_228_WIDTH },
15822  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_229_CHECKER_TYPE,
15823  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_229_WIDTH },
15824  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_230_CHECKER_TYPE,
15825  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_230_WIDTH },
15826  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_231_CHECKER_TYPE,
15827  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_231_WIDTH },
15828  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_232_CHECKER_TYPE,
15829  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_232_WIDTH },
15830  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_233_CHECKER_TYPE,
15831  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_233_WIDTH },
15832  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_234_CHECKER_TYPE,
15833  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_234_WIDTH },
15834  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_235_CHECKER_TYPE,
15835  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_235_WIDTH },
15836  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_236_CHECKER_TYPE,
15837  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_236_WIDTH },
15838  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_237_CHECKER_TYPE,
15839  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_237_WIDTH },
15840  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_238_CHECKER_TYPE,
15841  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_238_WIDTH },
15842  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_239_CHECKER_TYPE,
15843  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_239_WIDTH },
15844  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_240_CHECKER_TYPE,
15845  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_240_WIDTH },
15846  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_241_CHECKER_TYPE,
15847  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_241_WIDTH },
15848  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_242_CHECKER_TYPE,
15849  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_242_WIDTH },
15850  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_243_CHECKER_TYPE,
15851  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_243_WIDTH },
15852  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_244_CHECKER_TYPE,
15853  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_244_WIDTH },
15854  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_245_CHECKER_TYPE,
15855  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_245_WIDTH },
15856  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_246_CHECKER_TYPE,
15857  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_246_WIDTH },
15858  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_247_CHECKER_TYPE,
15859  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_247_WIDTH },
15860  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_248_CHECKER_TYPE,
15861  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_248_WIDTH },
15862  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_249_CHECKER_TYPE,
15863  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_249_WIDTH },
15864  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_250_CHECKER_TYPE,
15865  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_250_WIDTH },
15866  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_251_CHECKER_TYPE,
15867  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_251_WIDTH },
15868  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_252_CHECKER_TYPE,
15869  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_252_WIDTH },
15870  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_253_CHECKER_TYPE,
15871  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_253_WIDTH },
15872  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_254_CHECKER_TYPE,
15873  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_254_WIDTH },
15874  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_255_CHECKER_TYPE,
15875  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_255_WIDTH },
15876 };
15877 
15883 static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_groupEntries[SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_MAX_NUM_CHECKERS] =
15884 {
15885  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_0_CHECKER_TYPE,
15886  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_0_WIDTH },
15887  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_1_CHECKER_TYPE,
15888  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_1_WIDTH },
15889  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_2_CHECKER_TYPE,
15890  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_2_WIDTH },
15891  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_3_CHECKER_TYPE,
15892  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_3_WIDTH },
15893  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_4_CHECKER_TYPE,
15894  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_4_WIDTH },
15895  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_5_CHECKER_TYPE,
15896  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_5_WIDTH },
15897  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_6_CHECKER_TYPE,
15898  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_6_WIDTH },
15899  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_7_CHECKER_TYPE,
15900  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_7_WIDTH },
15901  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_8_CHECKER_TYPE,
15902  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_8_WIDTH },
15903  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_9_CHECKER_TYPE,
15904  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_9_WIDTH },
15905  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_10_CHECKER_TYPE,
15906  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_10_WIDTH },
15907  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_11_CHECKER_TYPE,
15908  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_11_WIDTH },
15909  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_12_CHECKER_TYPE,
15910  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_12_WIDTH },
15911  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_13_CHECKER_TYPE,
15912  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_13_WIDTH },
15913  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_14_CHECKER_TYPE,
15914  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_14_WIDTH },
15915  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_15_CHECKER_TYPE,
15916  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_15_WIDTH },
15917  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_16_CHECKER_TYPE,
15918  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_16_WIDTH },
15919  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_17_CHECKER_TYPE,
15920  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_17_WIDTH },
15921  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_18_CHECKER_TYPE,
15922  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_18_WIDTH },
15923  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_19_CHECKER_TYPE,
15924  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_19_WIDTH },
15925  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_20_CHECKER_TYPE,
15926  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_20_WIDTH },
15927  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_21_CHECKER_TYPE,
15928  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_21_WIDTH },
15929  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_22_CHECKER_TYPE,
15930  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_22_WIDTH },
15931  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_23_CHECKER_TYPE,
15932  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_23_WIDTH },
15933  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_24_CHECKER_TYPE,
15934  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_24_WIDTH },
15935  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_25_CHECKER_TYPE,
15936  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_25_WIDTH },
15937  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_26_CHECKER_TYPE,
15938  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_26_WIDTH },
15939  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_27_CHECKER_TYPE,
15940  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_27_WIDTH },
15941  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_28_CHECKER_TYPE,
15942  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_28_WIDTH },
15943  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_29_CHECKER_TYPE,
15944  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_29_WIDTH },
15945  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_30_CHECKER_TYPE,
15946  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_30_WIDTH },
15947  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_31_CHECKER_TYPE,
15948  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_31_WIDTH },
15949  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_32_CHECKER_TYPE,
15950  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_32_WIDTH },
15951  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_33_CHECKER_TYPE,
15952  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_33_WIDTH },
15953  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_34_CHECKER_TYPE,
15954  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_34_WIDTH },
15955  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_35_CHECKER_TYPE,
15956  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_35_WIDTH },
15957  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_36_CHECKER_TYPE,
15958  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_36_WIDTH },
15959  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_37_CHECKER_TYPE,
15960  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_37_WIDTH },
15961  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_38_CHECKER_TYPE,
15962  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_38_WIDTH },
15963  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_39_CHECKER_TYPE,
15964  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_39_WIDTH },
15965  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_40_CHECKER_TYPE,
15966  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_40_WIDTH },
15967  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_41_CHECKER_TYPE,
15968  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_41_WIDTH },
15969  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_42_CHECKER_TYPE,
15970  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_42_WIDTH },
15971  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_43_CHECKER_TYPE,
15972  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_43_WIDTH },
15973  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_44_CHECKER_TYPE,
15974  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_44_WIDTH },
15975  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_45_CHECKER_TYPE,
15976  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_45_WIDTH },
15977  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_46_CHECKER_TYPE,
15978  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_46_WIDTH },
15979  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_47_CHECKER_TYPE,
15980  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_47_WIDTH },
15981  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_48_CHECKER_TYPE,
15982  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_48_WIDTH },
15983  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_49_CHECKER_TYPE,
15984  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_49_WIDTH },
15985  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_50_CHECKER_TYPE,
15986  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_50_WIDTH },
15987  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_51_CHECKER_TYPE,
15988  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_51_WIDTH },
15989  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_52_CHECKER_TYPE,
15990  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_52_WIDTH },
15991  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_53_CHECKER_TYPE,
15992  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_53_WIDTH },
15993  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_54_CHECKER_TYPE,
15994  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_54_WIDTH },
15995  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_55_CHECKER_TYPE,
15996  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_55_WIDTH },
15997  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_56_CHECKER_TYPE,
15998  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_56_WIDTH },
15999  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_57_CHECKER_TYPE,
16000  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_57_WIDTH },
16001  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_58_CHECKER_TYPE,
16002  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_58_WIDTH },
16003  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_59_CHECKER_TYPE,
16004  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_59_WIDTH },
16005  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_60_CHECKER_TYPE,
16006  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_60_WIDTH },
16007  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_61_CHECKER_TYPE,
16008  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_61_WIDTH },
16009  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_62_CHECKER_TYPE,
16010  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_62_WIDTH },
16011  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_63_CHECKER_TYPE,
16012  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_63_WIDTH },
16013  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_64_CHECKER_TYPE,
16014  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_64_WIDTH },
16015  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_65_CHECKER_TYPE,
16016  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_65_WIDTH },
16017  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_66_CHECKER_TYPE,
16018  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_66_WIDTH },
16019  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_67_CHECKER_TYPE,
16020  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_67_WIDTH },
16021  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_68_CHECKER_TYPE,
16022  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_68_WIDTH },
16023  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_69_CHECKER_TYPE,
16024  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_69_WIDTH },
16025  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_70_CHECKER_TYPE,
16026  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_70_WIDTH },
16027  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_71_CHECKER_TYPE,
16028  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_71_WIDTH },
16029  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_72_CHECKER_TYPE,
16030  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_72_WIDTH },
16031  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_73_CHECKER_TYPE,
16032  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_73_WIDTH },
16033  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_74_CHECKER_TYPE,
16034  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_74_WIDTH },
16035  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_75_CHECKER_TYPE,
16036  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_75_WIDTH },
16037  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_76_CHECKER_TYPE,
16038  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_76_WIDTH },
16039  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_77_CHECKER_TYPE,
16040  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_77_WIDTH },
16041  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_78_CHECKER_TYPE,
16042  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_78_WIDTH },
16043  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_79_CHECKER_TYPE,
16044  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_79_WIDTH },
16045  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_80_CHECKER_TYPE,
16046  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_80_WIDTH },
16047  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_81_CHECKER_TYPE,
16048  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_81_WIDTH },
16049  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_82_CHECKER_TYPE,
16050  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_82_WIDTH },
16051  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_83_CHECKER_TYPE,
16052  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_83_WIDTH },
16053  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_84_CHECKER_TYPE,
16054  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_84_WIDTH },
16055  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_85_CHECKER_TYPE,
16056  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_85_WIDTH },
16057  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_86_CHECKER_TYPE,
16058  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_86_WIDTH },
16059  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_87_CHECKER_TYPE,
16060  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_87_WIDTH },
16061  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_88_CHECKER_TYPE,
16062  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_88_WIDTH },
16063  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_89_CHECKER_TYPE,
16064  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_89_WIDTH },
16065  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_90_CHECKER_TYPE,
16066  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_90_WIDTH },
16067  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_91_CHECKER_TYPE,
16068  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_91_WIDTH },
16069  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_92_CHECKER_TYPE,
16070  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_92_WIDTH },
16071  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_93_CHECKER_TYPE,
16072  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_93_WIDTH },
16073  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_94_CHECKER_TYPE,
16074  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_94_WIDTH },
16075  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_95_CHECKER_TYPE,
16076  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_95_WIDTH },
16077  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_96_CHECKER_TYPE,
16078  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_96_WIDTH },
16079  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_97_CHECKER_TYPE,
16080  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_97_WIDTH },
16081  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_98_CHECKER_TYPE,
16082  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_98_WIDTH },
16083  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_99_CHECKER_TYPE,
16084  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_99_WIDTH },
16085  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_100_CHECKER_TYPE,
16086  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_100_WIDTH },
16087  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_101_CHECKER_TYPE,
16088  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_101_WIDTH },
16089  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_102_CHECKER_TYPE,
16090  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_102_WIDTH },
16091  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_103_CHECKER_TYPE,
16092  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_103_WIDTH },
16093  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_104_CHECKER_TYPE,
16094  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_104_WIDTH },
16095  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_105_CHECKER_TYPE,
16096  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_105_WIDTH },
16097  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_106_CHECKER_TYPE,
16098  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_106_WIDTH },
16099  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_107_CHECKER_TYPE,
16100  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_107_WIDTH },
16101  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_108_CHECKER_TYPE,
16102  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_108_WIDTH },
16103  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_109_CHECKER_TYPE,
16104  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_109_WIDTH },
16105  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_110_CHECKER_TYPE,
16106  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_110_WIDTH },
16107  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_111_CHECKER_TYPE,
16108  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_111_WIDTH },
16109  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_112_CHECKER_TYPE,
16110  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_112_WIDTH },
16111  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_113_CHECKER_TYPE,
16112  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_113_WIDTH },
16113  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_114_CHECKER_TYPE,
16114  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_114_WIDTH },
16115  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_115_CHECKER_TYPE,
16116  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_115_WIDTH },
16117  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_116_CHECKER_TYPE,
16118  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_116_WIDTH },
16119  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_117_CHECKER_TYPE,
16120  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_117_WIDTH },
16121  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_118_CHECKER_TYPE,
16122  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_118_WIDTH },
16123  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_119_CHECKER_TYPE,
16124  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_119_WIDTH },
16125  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_120_CHECKER_TYPE,
16126  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_120_WIDTH },
16127  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_121_CHECKER_TYPE,
16128  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_121_WIDTH },
16129  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_122_CHECKER_TYPE,
16130  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_122_WIDTH },
16131  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_123_CHECKER_TYPE,
16132  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_123_WIDTH },
16133  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_124_CHECKER_TYPE,
16134  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_124_WIDTH },
16135  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_125_CHECKER_TYPE,
16136  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_125_WIDTH },
16137  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_126_CHECKER_TYPE,
16138  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_126_WIDTH },
16139  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_127_CHECKER_TYPE,
16140  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_127_WIDTH },
16141  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_128_CHECKER_TYPE,
16142  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_128_WIDTH },
16143  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_129_CHECKER_TYPE,
16144  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_129_WIDTH },
16145  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_130_CHECKER_TYPE,
16146  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_130_WIDTH },
16147  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_131_CHECKER_TYPE,
16148  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_131_WIDTH },
16149  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_132_CHECKER_TYPE,
16150  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_132_WIDTH },
16151  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_133_CHECKER_TYPE,
16152  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_133_WIDTH },
16153  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_134_CHECKER_TYPE,
16154  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_134_WIDTH },
16155  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_135_CHECKER_TYPE,
16156  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_135_WIDTH },
16157  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_136_CHECKER_TYPE,
16158  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_136_WIDTH },
16159  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_137_CHECKER_TYPE,
16160  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_137_WIDTH },
16161  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_138_CHECKER_TYPE,
16162  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_138_WIDTH },
16163  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_139_CHECKER_TYPE,
16164  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_139_WIDTH },
16165  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_140_CHECKER_TYPE,
16166  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_140_WIDTH },
16167  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_141_CHECKER_TYPE,
16168  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_141_WIDTH },
16169  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_142_CHECKER_TYPE,
16170  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_142_WIDTH },
16171  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_143_CHECKER_TYPE,
16172  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_143_WIDTH },
16173  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_144_CHECKER_TYPE,
16174  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_144_WIDTH },
16175  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_145_CHECKER_TYPE,
16176  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_145_WIDTH },
16177  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_146_CHECKER_TYPE,
16178  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_146_WIDTH },
16179  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_147_CHECKER_TYPE,
16180  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_147_WIDTH },
16181  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_148_CHECKER_TYPE,
16182  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_148_WIDTH },
16183  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_149_CHECKER_TYPE,
16184  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_149_WIDTH },
16185  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_150_CHECKER_TYPE,
16186  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_150_WIDTH },
16187 };
16188 
16194 static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_CBASS_DEFAULT_MMRS_AM67_MCU_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_groupEntries[SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_CBASS_DEFAULT_MMRS_AM67_MCU_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS] =
16195 {
16196  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_CBASS_DEFAULT_MMRS_AM67_MCU_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
16197  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_CBASS_DEFAULT_MMRS_AM67_MCU_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
16198  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_CBASS_DEFAULT_MMRS_AM67_MCU_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
16199  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_CBASS_DEFAULT_MMRS_AM67_MCU_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
16200  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_CBASS_DEFAULT_MMRS_AM67_MCU_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
16201  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_CBASS_DEFAULT_MMRS_AM67_MCU_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
16202  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_CBASS_DEFAULT_MMRS_AM67_MCU_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
16203  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_CBASS_DEFAULT_MMRS_AM67_MCU_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
16204  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_CBASS_DEFAULT_MMRS_AM67_MCU_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
16205  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_CBASS_DEFAULT_MMRS_AM67_MCU_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
16206  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_CBASS_DEFAULT_MMRS_AM67_MCU_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_5_CHECKER_TYPE,
16207  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_CBASS_DEFAULT_MMRS_AM67_MCU_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_5_WIDTH },
16208  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_CBASS_DEFAULT_MMRS_AM67_MCU_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_6_CHECKER_TYPE,
16209  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_CBASS_DEFAULT_MMRS_AM67_MCU_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_6_WIDTH },
16210  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_CBASS_DEFAULT_MMRS_AM67_MCU_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_7_CHECKER_TYPE,
16211  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_CBASS_DEFAULT_MMRS_AM67_MCU_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_7_WIDTH },
16212 };
16213 
16219 static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_groupEntries[SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_MAX_NUM_CHECKERS] =
16220 {
16221  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_0_CHECKER_TYPE,
16222  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_0_WIDTH },
16223  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_1_CHECKER_TYPE,
16224  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_1_WIDTH },
16225  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_2_CHECKER_TYPE,
16226  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_2_WIDTH },
16227  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_3_CHECKER_TYPE,
16228  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_3_WIDTH },
16229  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_4_CHECKER_TYPE,
16230  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_4_WIDTH },
16231  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_5_CHECKER_TYPE,
16232  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_5_WIDTH },
16233  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_6_CHECKER_TYPE,
16234  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_6_WIDTH },
16235  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_7_CHECKER_TYPE,
16236  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_7_WIDTH },
16237  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_8_CHECKER_TYPE,
16238  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_8_WIDTH },
16239  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_9_CHECKER_TYPE,
16240  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_9_WIDTH },
16241  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_10_CHECKER_TYPE,
16242  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_10_WIDTH },
16243  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_11_CHECKER_TYPE,
16244  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_11_WIDTH },
16245  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_12_CHECKER_TYPE,
16246  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_12_WIDTH },
16247  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_13_CHECKER_TYPE,
16248  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_13_WIDTH },
16249  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_14_CHECKER_TYPE,
16250  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_14_WIDTH },
16251  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_15_CHECKER_TYPE,
16252  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_15_WIDTH },
16253  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_16_CHECKER_TYPE,
16254  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_16_WIDTH },
16255  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_17_CHECKER_TYPE,
16256  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_17_WIDTH },
16257  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_18_CHECKER_TYPE,
16258  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_18_WIDTH },
16259 };
16260 
16266 static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_groupEntries[SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS] =
16267 {
16268  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
16269  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
16270  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
16271  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
16272  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
16273  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
16274  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
16275  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
16276  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
16277  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
16278  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_5_CHECKER_TYPE,
16279  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_5_WIDTH },
16280  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_6_CHECKER_TYPE,
16281  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_6_WIDTH },
16282  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_7_CHECKER_TYPE,
16283  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_7_WIDTH },
16284  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_8_CHECKER_TYPE,
16285  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_8_WIDTH },
16286  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_9_CHECKER_TYPE,
16287  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_9_WIDTH },
16288  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_10_CHECKER_TYPE,
16289  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_10_WIDTH },
16290  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_11_CHECKER_TYPE,
16291  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_11_WIDTH },
16292  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_12_CHECKER_TYPE,
16293  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_12_WIDTH },
16294  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_13_CHECKER_TYPE,
16295  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_13_WIDTH },
16296  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_14_CHECKER_TYPE,
16297  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_14_WIDTH },
16298  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_15_CHECKER_TYPE,
16299  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_15_WIDTH },
16300  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_16_CHECKER_TYPE,
16301  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_16_WIDTH },
16302  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_17_CHECKER_TYPE,
16303  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_17_WIDTH },
16304  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_18_CHECKER_TYPE,
16305  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_18_WIDTH },
16306  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_19_CHECKER_TYPE,
16307  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_19_WIDTH },
16308  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_20_CHECKER_TYPE,
16309  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_20_WIDTH },
16310  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_21_CHECKER_TYPE,
16311  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_21_WIDTH },
16312  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_22_CHECKER_TYPE,
16313  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_22_WIDTH },
16314  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_23_CHECKER_TYPE,
16315  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_23_WIDTH },
16316  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_24_CHECKER_TYPE,
16317  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_24_WIDTH },
16318  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_25_CHECKER_TYPE,
16319  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_25_WIDTH },
16320  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_26_CHECKER_TYPE,
16321  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_26_WIDTH },
16322  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_27_CHECKER_TYPE,
16323  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_27_WIDTH },
16324  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_28_CHECKER_TYPE,
16325  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_28_WIDTH },
16326  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_29_CHECKER_TYPE,
16327  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_29_WIDTH },
16328  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_30_CHECKER_TYPE,
16329  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_30_WIDTH },
16330  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_31_CHECKER_TYPE,
16331  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_31_WIDTH },
16332  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_32_CHECKER_TYPE,
16333  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_32_WIDTH },
16334  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_33_CHECKER_TYPE,
16335  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_33_WIDTH },
16336  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_34_CHECKER_TYPE,
16337  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_34_WIDTH },
16338  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_35_CHECKER_TYPE,
16339  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_35_WIDTH },
16340  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_36_CHECKER_TYPE,
16341  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_36_WIDTH },
16342  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_37_CHECKER_TYPE,
16343  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_37_WIDTH },
16344  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_38_CHECKER_TYPE,
16345  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_38_WIDTH },
16346  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_39_CHECKER_TYPE,
16347  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_39_WIDTH },
16348  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_40_CHECKER_TYPE,
16349  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_40_WIDTH },
16350  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_41_CHECKER_TYPE,
16351  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_41_WIDTH },
16352 };
16353 
16359 static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_CBASS_DEFAULT_ERR_AM67_MCU_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_groupEntries[SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_CBASS_DEFAULT_ERR_AM67_MCU_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS] =
16360 {
16361  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_CBASS_DEFAULT_ERR_AM67_MCU_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
16362  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_CBASS_DEFAULT_ERR_AM67_MCU_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
16363  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_CBASS_DEFAULT_ERR_AM67_MCU_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
16364  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_CBASS_DEFAULT_ERR_AM67_MCU_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
16365  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_CBASS_DEFAULT_ERR_AM67_MCU_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
16366  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_CBASS_DEFAULT_ERR_AM67_MCU_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
16367  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_CBASS_DEFAULT_ERR_AM67_MCU_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
16368  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_CBASS_DEFAULT_ERR_AM67_MCU_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
16369  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_CBASS_DEFAULT_ERR_AM67_MCU_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
16370  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_CBASS_DEFAULT_ERR_AM67_MCU_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
16371 };
16372 
16378 static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_groupEntries[SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_MAX_NUM_CHECKERS] =
16379 {
16380  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_0_CHECKER_TYPE,
16381  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_0_WIDTH },
16382  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_1_CHECKER_TYPE,
16383  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_1_WIDTH },
16384  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_2_CHECKER_TYPE,
16385  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_2_WIDTH },
16386  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_3_CHECKER_TYPE,
16387  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_3_WIDTH },
16388  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_4_CHECKER_TYPE,
16389  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_4_WIDTH },
16390  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_5_CHECKER_TYPE,
16391  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_5_WIDTH },
16392  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_6_CHECKER_TYPE,
16393  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_6_WIDTH },
16394  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_7_CHECKER_TYPE,
16395  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_7_WIDTH },
16396  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_8_CHECKER_TYPE,
16397  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_8_WIDTH },
16398  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_9_CHECKER_TYPE,
16399  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_9_WIDTH },
16400  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_10_CHECKER_TYPE,
16401  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_10_WIDTH },
16402  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_11_CHECKER_TYPE,
16403  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_11_WIDTH },
16404  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_12_CHECKER_TYPE,
16405  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_12_WIDTH },
16406  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_13_CHECKER_TYPE,
16407  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_13_WIDTH },
16408  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_14_CHECKER_TYPE,
16409  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_14_WIDTH },
16410  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_15_CHECKER_TYPE,
16411  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_15_WIDTH },
16412  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_16_CHECKER_TYPE,
16413  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_16_WIDTH },
16414  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_17_CHECKER_TYPE,
16415  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_17_WIDTH },
16416  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_18_CHECKER_TYPE,
16417  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_18_WIDTH },
16418 };
16419 
16425 static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ERR_SCR_AM67_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_groupEntries[SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ERR_SCR_AM67_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS] =
16426 {
16427  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ERR_SCR_AM67_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
16428  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ERR_SCR_AM67_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
16429  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ERR_SCR_AM67_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
16430  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ERR_SCR_AM67_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
16431  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ERR_SCR_AM67_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
16432  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ERR_SCR_AM67_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
16433  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ERR_SCR_AM67_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
16434  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ERR_SCR_AM67_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
16435  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ERR_SCR_AM67_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
16436  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ERR_SCR_AM67_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
16437  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ERR_SCR_AM67_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_5_CHECKER_TYPE,
16438  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ERR_SCR_AM67_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_5_WIDTH },
16439  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ERR_SCR_AM67_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_6_CHECKER_TYPE,
16440  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ERR_SCR_AM67_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_6_WIDTH },
16441  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ERR_SCR_AM67_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_7_CHECKER_TYPE,
16442  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ERR_SCR_AM67_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_7_WIDTH },
16443  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ERR_SCR_AM67_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_8_CHECKER_TYPE,
16444  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ERR_SCR_AM67_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_8_WIDTH },
16445  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ERR_SCR_AM67_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_9_CHECKER_TYPE,
16446  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ERR_SCR_AM67_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_9_WIDTH },
16447  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ERR_SCR_AM67_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_10_CHECKER_TYPE,
16448  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ERR_SCR_AM67_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_10_WIDTH },
16449  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ERR_SCR_AM67_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_11_CHECKER_TYPE,
16450  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ERR_SCR_AM67_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_11_WIDTH },
16451  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ERR_SCR_AM67_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_12_CHECKER_TYPE,
16452  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ERR_SCR_AM67_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_12_WIDTH },
16453  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ERR_SCR_AM67_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_13_CHECKER_TYPE,
16454  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ERR_SCR_AM67_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_13_WIDTH },
16455  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ERR_SCR_AM67_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_14_CHECKER_TYPE,
16456  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ERR_SCR_AM67_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_14_WIDTH },
16457  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ERR_SCR_AM67_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_15_CHECKER_TYPE,
16458  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ERR_SCR_AM67_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_15_WIDTH },
16459  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ERR_SCR_AM67_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_16_CHECKER_TYPE,
16460  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ERR_SCR_AM67_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_16_WIDTH },
16461  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ERR_SCR_AM67_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_17_CHECKER_TYPE,
16462  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ERR_SCR_AM67_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_17_WIDTH },
16463  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ERR_SCR_AM67_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_18_CHECKER_TYPE,
16464  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ERR_SCR_AM67_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_18_WIDTH },
16465  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ERR_SCR_AM67_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_19_CHECKER_TYPE,
16466  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ERR_SCR_AM67_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_19_WIDTH },
16467  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ERR_SCR_AM67_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_20_CHECKER_TYPE,
16468  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ERR_SCR_AM67_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_20_WIDTH },
16469  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ERR_SCR_AM67_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_21_CHECKER_TYPE,
16470  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ERR_SCR_AM67_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_21_WIDTH },
16471  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ERR_SCR_AM67_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_22_CHECKER_TYPE,
16472  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ERR_SCR_AM67_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_22_WIDTH },
16473  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ERR_SCR_AM67_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_23_CHECKER_TYPE,
16474  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ERR_SCR_AM67_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_23_WIDTH },
16475  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ERR_SCR_AM67_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_24_CHECKER_TYPE,
16476  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ERR_SCR_AM67_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_24_WIDTH },
16477  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ERR_SCR_AM67_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_25_CHECKER_TYPE,
16478  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ERR_SCR_AM67_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_25_WIDTH },
16479  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ERR_SCR_AM67_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_26_CHECKER_TYPE,
16480  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ERR_SCR_AM67_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_26_WIDTH },
16481  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ERR_SCR_AM67_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_27_CHECKER_TYPE,
16482  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ERR_SCR_AM67_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_27_WIDTH },
16483  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ERR_SCR_AM67_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_28_CHECKER_TYPE,
16484  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ERR_SCR_AM67_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_28_WIDTH },
16485  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ERR_SCR_AM67_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_29_CHECKER_TYPE,
16486  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ERR_SCR_AM67_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_29_WIDTH },
16487  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ERR_SCR_AM67_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_30_CHECKER_TYPE,
16488  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ERR_SCR_AM67_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_30_WIDTH },
16489  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ERR_SCR_AM67_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_31_CHECKER_TYPE,
16490  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ERR_SCR_AM67_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_31_WIDTH },
16491  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ERR_SCR_AM67_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_32_CHECKER_TYPE,
16492  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ERR_SCR_AM67_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_32_WIDTH },
16493  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ERR_SCR_AM67_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_33_CHECKER_TYPE,
16494  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ERR_SCR_AM67_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_33_WIDTH },
16495  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ERR_SCR_AM67_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_34_CHECKER_TYPE,
16496  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ERR_SCR_AM67_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_34_WIDTH },
16497  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ERR_SCR_AM67_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_35_CHECKER_TYPE,
16498  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ERR_SCR_AM67_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_35_WIDTH },
16499  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ERR_SCR_AM67_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_36_CHECKER_TYPE,
16500  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ERR_SCR_AM67_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_36_WIDTH },
16501  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ERR_SCR_AM67_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_37_CHECKER_TYPE,
16502  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ERR_SCR_AM67_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_37_WIDTH },
16503  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ERR_SCR_AM67_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_38_CHECKER_TYPE,
16504  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ERR_SCR_AM67_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_38_WIDTH },
16505  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ERR_SCR_AM67_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_39_CHECKER_TYPE,
16506  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ERR_SCR_AM67_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_39_WIDTH },
16507  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ERR_SCR_AM67_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_40_CHECKER_TYPE,
16508  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ERR_SCR_AM67_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_40_WIDTH },
16509  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ERR_SCR_AM67_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_41_CHECKER_TYPE,
16510  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ERR_SCR_AM67_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_41_WIDTH },
16511 };
16512 
16518 static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_groupEntries[SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_MAX_NUM_CHECKERS] =
16519 {
16520  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_0_CHECKER_TYPE,
16521  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_0_WIDTH },
16522  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_1_CHECKER_TYPE,
16523  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_1_WIDTH },
16524  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_2_CHECKER_TYPE,
16525  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_2_WIDTH },
16526  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_3_CHECKER_TYPE,
16527  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_3_WIDTH },
16528  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_4_CHECKER_TYPE,
16529  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_4_WIDTH },
16530  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_5_CHECKER_TYPE,
16531  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_5_WIDTH },
16532  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_6_CHECKER_TYPE,
16533  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_6_WIDTH },
16534  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_7_CHECKER_TYPE,
16535  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_7_WIDTH },
16536  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_8_CHECKER_TYPE,
16537  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_8_WIDTH },
16538  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_9_CHECKER_TYPE,
16539  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_9_WIDTH },
16540  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_10_CHECKER_TYPE,
16541  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_10_WIDTH },
16542  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_11_CHECKER_TYPE,
16543  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_11_WIDTH },
16544  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_12_CHECKER_TYPE,
16545  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_12_WIDTH },
16546  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_13_CHECKER_TYPE,
16547  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_13_WIDTH },
16548  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_14_CHECKER_TYPE,
16549  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_14_WIDTH },
16550  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_15_CHECKER_TYPE,
16551  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_15_WIDTH },
16552  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_16_CHECKER_TYPE,
16553  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_16_WIDTH },
16554  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_17_CHECKER_TYPE,
16555  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_17_WIDTH },
16556  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_18_CHECKER_TYPE,
16557  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_18_WIDTH },
16558  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_19_CHECKER_TYPE,
16559  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_19_WIDTH },
16560  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_20_CHECKER_TYPE,
16561  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_20_WIDTH },
16562  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_21_CHECKER_TYPE,
16563  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_21_WIDTH },
16564  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_22_CHECKER_TYPE,
16565  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_22_WIDTH },
16566  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_23_CHECKER_TYPE,
16567  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_23_WIDTH },
16568  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_24_CHECKER_TYPE,
16569  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_24_WIDTH },
16570  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_25_CHECKER_TYPE,
16571  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_25_WIDTH },
16572  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_26_CHECKER_TYPE,
16573  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_26_WIDTH },
16574  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_27_CHECKER_TYPE,
16575  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_27_WIDTH },
16576  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_28_CHECKER_TYPE,
16577  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_28_WIDTH },
16578  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_29_CHECKER_TYPE,
16579  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_29_WIDTH },
16580  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_30_CHECKER_TYPE,
16581  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_30_WIDTH },
16582  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_31_CHECKER_TYPE,
16583  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_31_WIDTH },
16584  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_32_CHECKER_TYPE,
16585  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_32_WIDTH },
16586  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_33_CHECKER_TYPE,
16587  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_33_WIDTH },
16588  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_34_CHECKER_TYPE,
16589  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_34_WIDTH },
16590  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_35_CHECKER_TYPE,
16591  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_35_WIDTH },
16592  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_36_CHECKER_TYPE,
16593  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_36_WIDTH },
16594  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_37_CHECKER_TYPE,
16595  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_37_WIDTH },
16596  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_38_CHECKER_TYPE,
16597  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_38_WIDTH },
16598  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_39_CHECKER_TYPE,
16599  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_39_WIDTH },
16600  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_40_CHECKER_TYPE,
16601  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_40_WIDTH },
16602  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_41_CHECKER_TYPE,
16603  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_41_WIDTH },
16604  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_42_CHECKER_TYPE,
16605  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_42_WIDTH },
16606  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_43_CHECKER_TYPE,
16607  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_43_WIDTH },
16608  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_44_CHECKER_TYPE,
16609  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_44_WIDTH },
16610  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_45_CHECKER_TYPE,
16611  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_45_WIDTH },
16612  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_46_CHECKER_TYPE,
16613  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_46_WIDTH },
16614  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_47_CHECKER_TYPE,
16615  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_47_WIDTH },
16616  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_48_CHECKER_TYPE,
16617  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_48_WIDTH },
16618  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_49_CHECKER_TYPE,
16619  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_49_WIDTH },
16620  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_50_CHECKER_TYPE,
16621  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_50_WIDTH },
16622  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_51_CHECKER_TYPE,
16623  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_51_WIDTH },
16624  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_52_CHECKER_TYPE,
16625  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_52_WIDTH },
16626  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_53_CHECKER_TYPE,
16627  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_53_WIDTH },
16628  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_54_CHECKER_TYPE,
16629  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_54_WIDTH },
16630  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_55_CHECKER_TYPE,
16631  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_55_WIDTH },
16632  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_56_CHECKER_TYPE,
16633  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_56_WIDTH },
16634  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_57_CHECKER_TYPE,
16635  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_57_WIDTH },
16636  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_58_CHECKER_TYPE,
16637  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_58_WIDTH },
16638  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_59_CHECKER_TYPE,
16639  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_59_WIDTH },
16640  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_60_CHECKER_TYPE,
16641  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_60_WIDTH },
16642  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_61_CHECKER_TYPE,
16643  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_61_WIDTH },
16644  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_62_CHECKER_TYPE,
16645  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_62_WIDTH },
16646  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_63_CHECKER_TYPE,
16647  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_63_WIDTH },
16648  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_64_CHECKER_TYPE,
16649  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_64_WIDTH },
16650  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_65_CHECKER_TYPE,
16651  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_65_WIDTH },
16652  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_66_CHECKER_TYPE,
16653  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_66_WIDTH },
16654  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_67_CHECKER_TYPE,
16655  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_67_WIDTH },
16656  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_68_CHECKER_TYPE,
16657  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_68_WIDTH },
16658  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_69_CHECKER_TYPE,
16659  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_69_WIDTH },
16660  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_70_CHECKER_TYPE,
16661  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_70_WIDTH },
16662  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_71_CHECKER_TYPE,
16663  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_71_WIDTH },
16664  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_72_CHECKER_TYPE,
16665  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_72_WIDTH },
16666  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_73_CHECKER_TYPE,
16667  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_73_WIDTH },
16668  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_74_CHECKER_TYPE,
16669  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_74_WIDTH },
16670  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_75_CHECKER_TYPE,
16671  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_75_WIDTH },
16672  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_76_CHECKER_TYPE,
16673  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_76_WIDTH },
16674  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_77_CHECKER_TYPE,
16675  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_77_WIDTH },
16676  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_78_CHECKER_TYPE,
16677  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_78_WIDTH },
16678  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_79_CHECKER_TYPE,
16679  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_79_WIDTH },
16680  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_80_CHECKER_TYPE,
16681  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_80_WIDTH },
16682 };
16683 
16689 static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_groupEntries[SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_MAX_NUM_CHECKERS] =
16690 {
16691  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_0_CHECKER_TYPE,
16692  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_0_WIDTH },
16693  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_1_CHECKER_TYPE,
16694  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_1_WIDTH },
16695  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_2_CHECKER_TYPE,
16696  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_2_WIDTH },
16697  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_3_CHECKER_TYPE,
16698  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_3_WIDTH },
16699  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_4_CHECKER_TYPE,
16700  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_4_WIDTH },
16701  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_5_CHECKER_TYPE,
16702  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_5_WIDTH },
16703  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_6_CHECKER_TYPE,
16704  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_6_WIDTH },
16705  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_7_CHECKER_TYPE,
16706  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_7_WIDTH },
16707  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_8_CHECKER_TYPE,
16708  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_8_WIDTH },
16709  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_9_CHECKER_TYPE,
16710  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_9_WIDTH },
16711  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_10_CHECKER_TYPE,
16712  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_10_WIDTH },
16713  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_11_CHECKER_TYPE,
16714  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_11_WIDTH },
16715  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_12_CHECKER_TYPE,
16716  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_12_WIDTH },
16717  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_13_CHECKER_TYPE,
16718  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_13_WIDTH },
16719  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_14_CHECKER_TYPE,
16720  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_14_WIDTH },
16721  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_15_CHECKER_TYPE,
16722  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_15_WIDTH },
16723  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_16_CHECKER_TYPE,
16724  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_16_WIDTH },
16725  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_17_CHECKER_TYPE,
16726  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_17_WIDTH },
16727  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_18_CHECKER_TYPE,
16728  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_18_WIDTH },
16729  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_19_CHECKER_TYPE,
16730  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_19_WIDTH },
16731  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_20_CHECKER_TYPE,
16732  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_20_WIDTH },
16733  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_21_CHECKER_TYPE,
16734  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_21_WIDTH },
16735  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_22_CHECKER_TYPE,
16736  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_22_WIDTH },
16737  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_23_CHECKER_TYPE,
16738  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_23_WIDTH },
16739  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_24_CHECKER_TYPE,
16740  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_24_WIDTH },
16741  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_25_CHECKER_TYPE,
16742  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_25_WIDTH },
16743  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_26_CHECKER_TYPE,
16744  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_26_WIDTH },
16745  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_27_CHECKER_TYPE,
16746  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_27_WIDTH },
16747  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_28_CHECKER_TYPE,
16748  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_28_WIDTH },
16749  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_29_CHECKER_TYPE,
16750  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_29_WIDTH },
16751  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_30_CHECKER_TYPE,
16752  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_30_WIDTH },
16753  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_31_CHECKER_TYPE,
16754  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_31_WIDTH },
16755  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_32_CHECKER_TYPE,
16756  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_32_WIDTH },
16757  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_33_CHECKER_TYPE,
16758  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_33_WIDTH },
16759  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_34_CHECKER_TYPE,
16760  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_34_WIDTH },
16761  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_35_CHECKER_TYPE,
16762  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_35_WIDTH },
16763  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_36_CHECKER_TYPE,
16764  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_36_WIDTH },
16765  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_37_CHECKER_TYPE,
16766  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_37_WIDTH },
16767  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_38_CHECKER_TYPE,
16768  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_38_WIDTH },
16769  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_39_CHECKER_TYPE,
16770  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_39_WIDTH },
16771  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_40_CHECKER_TYPE,
16772  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_40_WIDTH },
16773  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_41_CHECKER_TYPE,
16774  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_41_WIDTH },
16775  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_42_CHECKER_TYPE,
16776  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_42_WIDTH },
16777  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_43_CHECKER_TYPE,
16778  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_43_WIDTH },
16779  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_44_CHECKER_TYPE,
16780  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_44_WIDTH },
16781  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_45_CHECKER_TYPE,
16782  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_45_WIDTH },
16783  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_46_CHECKER_TYPE,
16784  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_46_WIDTH },
16785  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_47_CHECKER_TYPE,
16786  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_47_WIDTH },
16787  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_48_CHECKER_TYPE,
16788  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_48_WIDTH },
16789  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_49_CHECKER_TYPE,
16790  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_49_WIDTH },
16791  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_50_CHECKER_TYPE,
16792  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_50_WIDTH },
16793  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_51_CHECKER_TYPE,
16794  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_51_WIDTH },
16795  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_52_CHECKER_TYPE,
16796  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_52_WIDTH },
16797  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_53_CHECKER_TYPE,
16798  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_53_WIDTH },
16799  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_54_CHECKER_TYPE,
16800  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_54_WIDTH },
16801  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_55_CHECKER_TYPE,
16802  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_55_WIDTH },
16803  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_56_CHECKER_TYPE,
16804  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_56_WIDTH },
16805  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_57_CHECKER_TYPE,
16806  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_57_WIDTH },
16807  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_58_CHECKER_TYPE,
16808  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_58_WIDTH },
16809  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_59_CHECKER_TYPE,
16810  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_59_WIDTH },
16811  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_60_CHECKER_TYPE,
16812  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_60_WIDTH },
16813  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_61_CHECKER_TYPE,
16814  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_61_WIDTH },
16815  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_62_CHECKER_TYPE,
16816  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_62_WIDTH },
16817  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_63_CHECKER_TYPE,
16818  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_63_WIDTH },
16819  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_64_CHECKER_TYPE,
16820  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_64_WIDTH },
16821  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_65_CHECKER_TYPE,
16822  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_65_WIDTH },
16823  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_66_CHECKER_TYPE,
16824  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_66_WIDTH },
16825  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_67_CHECKER_TYPE,
16826  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_67_WIDTH },
16827  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_68_CHECKER_TYPE,
16828  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_68_WIDTH },
16829  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_69_CHECKER_TYPE,
16830  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_69_WIDTH },
16831  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_70_CHECKER_TYPE,
16832  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_70_WIDTH },
16833  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_71_CHECKER_TYPE,
16834  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_71_WIDTH },
16835  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_72_CHECKER_TYPE,
16836  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_72_WIDTH },
16837  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_73_CHECKER_TYPE,
16838  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_73_WIDTH },
16839  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_74_CHECKER_TYPE,
16840  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_74_WIDTH },
16841  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_75_CHECKER_TYPE,
16842  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_75_WIDTH },
16843  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_76_CHECKER_TYPE,
16844  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_76_WIDTH },
16845  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_77_CHECKER_TYPE,
16846  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_77_WIDTH },
16847  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_78_CHECKER_TYPE,
16848  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_78_WIDTH },
16849  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_79_CHECKER_TYPE,
16850  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_79_WIDTH },
16851  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_80_CHECKER_TYPE,
16852  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_80_WIDTH },
16853  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_81_CHECKER_TYPE,
16854  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_81_WIDTH },
16855  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_82_CHECKER_TYPE,
16856  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_82_WIDTH },
16857  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_83_CHECKER_TYPE,
16858  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_83_WIDTH },
16859  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_84_CHECKER_TYPE,
16860  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_84_WIDTH },
16861  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_85_CHECKER_TYPE,
16862  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_85_WIDTH },
16863  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_86_CHECKER_TYPE,
16864  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_86_WIDTH },
16865  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_87_CHECKER_TYPE,
16866  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_87_WIDTH },
16867  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_88_CHECKER_TYPE,
16868  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_88_WIDTH },
16869  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_89_CHECKER_TYPE,
16870  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_89_WIDTH },
16871  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_90_CHECKER_TYPE,
16872  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_90_WIDTH },
16873  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_91_CHECKER_TYPE,
16874  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_91_WIDTH },
16875  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_92_CHECKER_TYPE,
16876  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_92_WIDTH },
16877  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_93_CHECKER_TYPE,
16878  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_93_WIDTH },
16879  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_94_CHECKER_TYPE,
16880  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_94_WIDTH },
16881  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_95_CHECKER_TYPE,
16882  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_95_WIDTH },
16883  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_96_CHECKER_TYPE,
16884  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_96_WIDTH },
16885  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_97_CHECKER_TYPE,
16886  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_97_WIDTH },
16887  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_98_CHECKER_TYPE,
16888  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_98_WIDTH },
16889  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_99_CHECKER_TYPE,
16890  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_99_WIDTH },
16891  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_100_CHECKER_TYPE,
16892  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_100_WIDTH },
16893  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_101_CHECKER_TYPE,
16894  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_101_WIDTH },
16895  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_102_CHECKER_TYPE,
16896  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_102_WIDTH },
16897  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_103_CHECKER_TYPE,
16898  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_103_WIDTH },
16899  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_104_CHECKER_TYPE,
16900  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_104_WIDTH },
16901  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_105_CHECKER_TYPE,
16902  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_105_WIDTH },
16903  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_106_CHECKER_TYPE,
16904  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_106_WIDTH },
16905  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_107_CHECKER_TYPE,
16906  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_107_WIDTH },
16907  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_108_CHECKER_TYPE,
16908  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_108_WIDTH },
16909  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_109_CHECKER_TYPE,
16910  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_109_WIDTH },
16911  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_110_CHECKER_TYPE,
16912  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_110_WIDTH },
16913  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_111_CHECKER_TYPE,
16914  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_111_WIDTH },
16915  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_112_CHECKER_TYPE,
16916  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_112_WIDTH },
16917  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_113_CHECKER_TYPE,
16918  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_113_WIDTH },
16919  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_114_CHECKER_TYPE,
16920  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_114_WIDTH },
16921  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_115_CHECKER_TYPE,
16922  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_115_WIDTH },
16923  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_116_CHECKER_TYPE,
16924  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_116_WIDTH },
16925  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_117_CHECKER_TYPE,
16926  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_117_WIDTH },
16927  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_118_CHECKER_TYPE,
16928  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_118_WIDTH },
16929  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_119_CHECKER_TYPE,
16930  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_119_WIDTH },
16931  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_120_CHECKER_TYPE,
16932  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_120_WIDTH },
16933  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_121_CHECKER_TYPE,
16934  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_121_WIDTH },
16935  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_122_CHECKER_TYPE,
16936  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_122_WIDTH },
16937  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_123_CHECKER_TYPE,
16938  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_123_WIDTH },
16939  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_124_CHECKER_TYPE,
16940  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_124_WIDTH },
16941  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_125_CHECKER_TYPE,
16942  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_125_WIDTH },
16943  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_126_CHECKER_TYPE,
16944  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_126_WIDTH },
16945  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_127_CHECKER_TYPE,
16946  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_127_WIDTH },
16947  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_128_CHECKER_TYPE,
16948  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_128_WIDTH },
16949  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_129_CHECKER_TYPE,
16950  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_129_WIDTH },
16951  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_130_CHECKER_TYPE,
16952  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_130_WIDTH },
16953  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_131_CHECKER_TYPE,
16954  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_131_WIDTH },
16955  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_132_CHECKER_TYPE,
16956  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_132_WIDTH },
16957  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_133_CHECKER_TYPE,
16958  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_133_WIDTH },
16959  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_134_CHECKER_TYPE,
16960  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_134_WIDTH },
16961 };
16962 
16968 static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_groupEntries[SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_MAX_NUM_CHECKERS] =
16969 {
16970  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_0_CHECKER_TYPE,
16971  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_0_WIDTH },
16972  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_1_CHECKER_TYPE,
16973  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_1_WIDTH },
16974  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_2_CHECKER_TYPE,
16975  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_2_WIDTH },
16976  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_3_CHECKER_TYPE,
16977  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_3_WIDTH },
16978  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_4_CHECKER_TYPE,
16979  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_4_WIDTH },
16980  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_5_CHECKER_TYPE,
16981  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_5_WIDTH },
16982  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_6_CHECKER_TYPE,
16983  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_6_WIDTH },
16984  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_7_CHECKER_TYPE,
16985  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_7_WIDTH },
16986  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_8_CHECKER_TYPE,
16987  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_8_WIDTH },
16988  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_9_CHECKER_TYPE,
16989  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_9_WIDTH },
16990  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_10_CHECKER_TYPE,
16991  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_10_WIDTH },
16992  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_11_CHECKER_TYPE,
16993  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_11_WIDTH },
16994  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_12_CHECKER_TYPE,
16995  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_12_WIDTH },
16996  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_13_CHECKER_TYPE,
16997  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_13_WIDTH },
16998  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_14_CHECKER_TYPE,
16999  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_14_WIDTH },
17000  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_15_CHECKER_TYPE,
17001  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_15_WIDTH },
17002  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_16_CHECKER_TYPE,
17003  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_16_WIDTH },
17004  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_17_CHECKER_TYPE,
17005  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_17_WIDTH },
17006  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_18_CHECKER_TYPE,
17007  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_18_WIDTH },
17008  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_19_CHECKER_TYPE,
17009  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_19_WIDTH },
17010  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_20_CHECKER_TYPE,
17011  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_20_WIDTH },
17012  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_21_CHECKER_TYPE,
17013  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_21_WIDTH },
17014  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_22_CHECKER_TYPE,
17015  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_22_WIDTH },
17016  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_23_CHECKER_TYPE,
17017  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_23_WIDTH },
17018  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_24_CHECKER_TYPE,
17019  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_24_WIDTH },
17020  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_25_CHECKER_TYPE,
17021  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_25_WIDTH },
17022  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_26_CHECKER_TYPE,
17023  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_26_WIDTH },
17024  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_27_CHECKER_TYPE,
17025  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_27_WIDTH },
17026  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_28_CHECKER_TYPE,
17027  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_28_WIDTH },
17028  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_29_CHECKER_TYPE,
17029  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_29_WIDTH },
17030  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_30_CHECKER_TYPE,
17031  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_30_WIDTH },
17032  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_31_CHECKER_TYPE,
17033  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_31_WIDTH },
17034  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_32_CHECKER_TYPE,
17035  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_32_WIDTH },
17036  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_33_CHECKER_TYPE,
17037  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_33_WIDTH },
17038  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_34_CHECKER_TYPE,
17039  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_34_WIDTH },
17040  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_35_CHECKER_TYPE,
17041  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_35_WIDTH },
17042  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_36_CHECKER_TYPE,
17043  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_36_WIDTH },
17044  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_37_CHECKER_TYPE,
17045  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_37_WIDTH },
17046  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_38_CHECKER_TYPE,
17047  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_38_WIDTH },
17048  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_39_CHECKER_TYPE,
17049  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_39_WIDTH },
17050  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_40_CHECKER_TYPE,
17051  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_40_WIDTH },
17052  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_41_CHECKER_TYPE,
17053  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_41_WIDTH },
17054  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_42_CHECKER_TYPE,
17055  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_42_WIDTH },
17056  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_43_CHECKER_TYPE,
17057  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_43_WIDTH },
17058  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_44_CHECKER_TYPE,
17059  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_44_WIDTH },
17060  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_45_CHECKER_TYPE,
17061  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_45_WIDTH },
17062  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_46_CHECKER_TYPE,
17063  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_46_WIDTH },
17064  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_47_CHECKER_TYPE,
17065  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_47_WIDTH },
17066  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_48_CHECKER_TYPE,
17067  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_48_WIDTH },
17068  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_49_CHECKER_TYPE,
17069  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_49_WIDTH },
17070  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_50_CHECKER_TYPE,
17071  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_50_WIDTH },
17072  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_51_CHECKER_TYPE,
17073  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_51_WIDTH },
17074  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_52_CHECKER_TYPE,
17075  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_52_WIDTH },
17076  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_53_CHECKER_TYPE,
17077  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_53_WIDTH },
17078  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_54_CHECKER_TYPE,
17079  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_54_WIDTH },
17080  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_55_CHECKER_TYPE,
17081  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_55_WIDTH },
17082  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_56_CHECKER_TYPE,
17083  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_56_WIDTH },
17084  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_57_CHECKER_TYPE,
17085  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_57_WIDTH },
17086  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_58_CHECKER_TYPE,
17087  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_58_WIDTH },
17088  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_59_CHECKER_TYPE,
17089  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_59_WIDTH },
17090  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_60_CHECKER_TYPE,
17091  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_60_WIDTH },
17092  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_61_CHECKER_TYPE,
17093  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_61_WIDTH },
17094  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_62_CHECKER_TYPE,
17095  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_62_WIDTH },
17096  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_63_CHECKER_TYPE,
17097  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_63_WIDTH },
17098  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_64_CHECKER_TYPE,
17099  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_64_WIDTH },
17100  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_65_CHECKER_TYPE,
17101  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_65_WIDTH },
17102  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_66_CHECKER_TYPE,
17103  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_66_WIDTH },
17104  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_67_CHECKER_TYPE,
17105  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_67_WIDTH },
17106  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_68_CHECKER_TYPE,
17107  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_68_WIDTH },
17108  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_69_CHECKER_TYPE,
17109  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_69_WIDTH },
17110  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_70_CHECKER_TYPE,
17111  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_70_WIDTH },
17112  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_71_CHECKER_TYPE,
17113  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_71_WIDTH },
17114  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_72_CHECKER_TYPE,
17115  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_72_WIDTH },
17116  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_73_CHECKER_TYPE,
17117  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_73_WIDTH },
17118  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_74_CHECKER_TYPE,
17119  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_74_WIDTH },
17120  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_75_CHECKER_TYPE,
17121  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_75_WIDTH },
17122  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_76_CHECKER_TYPE,
17123  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_76_WIDTH },
17124  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_77_CHECKER_TYPE,
17125  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_77_WIDTH },
17126  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_78_CHECKER_TYPE,
17127  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_78_WIDTH },
17128  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_79_CHECKER_TYPE,
17129  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_79_WIDTH },
17130  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_80_CHECKER_TYPE,
17131  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_80_WIDTH },
17132  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_81_CHECKER_TYPE,
17133  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_81_WIDTH },
17134  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_82_CHECKER_TYPE,
17135  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_82_WIDTH },
17136  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_83_CHECKER_TYPE,
17137  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_83_WIDTH },
17138  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_84_CHECKER_TYPE,
17139  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_84_WIDTH },
17140  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_85_CHECKER_TYPE,
17141  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_85_WIDTH },
17142  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_86_CHECKER_TYPE,
17143  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_86_WIDTH },
17144  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_87_CHECKER_TYPE,
17145  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_87_WIDTH },
17146  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_88_CHECKER_TYPE,
17147  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_88_WIDTH },
17148  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_89_CHECKER_TYPE,
17149  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_89_WIDTH },
17150  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_90_CHECKER_TYPE,
17151  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_90_WIDTH },
17152  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_91_CHECKER_TYPE,
17153  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_91_WIDTH },
17154  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_92_CHECKER_TYPE,
17155  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_92_WIDTH },
17156  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_93_CHECKER_TYPE,
17157  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_93_WIDTH },
17158  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_94_CHECKER_TYPE,
17159  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_94_WIDTH },
17160  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_95_CHECKER_TYPE,
17161  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_95_WIDTH },
17162  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_96_CHECKER_TYPE,
17163  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_96_WIDTH },
17164  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_97_CHECKER_TYPE,
17165  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_97_WIDTH },
17166  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_98_CHECKER_TYPE,
17167  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_98_WIDTH },
17168  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_99_CHECKER_TYPE,
17169  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_99_WIDTH },
17170  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_100_CHECKER_TYPE,
17171  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_100_WIDTH },
17172 };
17173 
17179 static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_SAM67_MCU_MCU_ECC_AGGR_EDC_CTRL_groupEntries[SDL_MCU_ECC_AGGR0_SAM67_MCU_MCU_ECC_AGGR_EDC_CTRL_MAX_NUM_CHECKERS] =
17180 {
17181  { SDL_MCU_ECC_AGGR0_SAM67_MCU_MCU_ECC_AGGR_EDC_CTRL_GROUP_0_CHECKER_TYPE,
17182  SDL_MCU_ECC_AGGR0_SAM67_MCU_MCU_ECC_AGGR_EDC_CTRL_GROUP_0_WIDTH },
17183  { SDL_MCU_ECC_AGGR0_SAM67_MCU_MCU_ECC_AGGR_EDC_CTRL_GROUP_1_CHECKER_TYPE,
17184  SDL_MCU_ECC_AGGR0_SAM67_MCU_MCU_ECC_AGGR_EDC_CTRL_GROUP_1_WIDTH },
17185  { SDL_MCU_ECC_AGGR0_SAM67_MCU_MCU_ECC_AGGR_EDC_CTRL_GROUP_2_CHECKER_TYPE,
17186  SDL_MCU_ECC_AGGR0_SAM67_MCU_MCU_ECC_AGGR_EDC_CTRL_GROUP_2_WIDTH },
17187  { SDL_MCU_ECC_AGGR0_SAM67_MCU_MCU_ECC_AGGR_EDC_CTRL_GROUP_3_CHECKER_TYPE,
17188  SDL_MCU_ECC_AGGR0_SAM67_MCU_MCU_ECC_AGGR_EDC_CTRL_GROUP_3_WIDTH },
17189  { SDL_MCU_ECC_AGGR0_SAM67_MCU_MCU_ECC_AGGR_EDC_CTRL_GROUP_4_CHECKER_TYPE,
17190  SDL_MCU_ECC_AGGR0_SAM67_MCU_MCU_ECC_AGGR_EDC_CTRL_GROUP_4_WIDTH },
17191  { SDL_MCU_ECC_AGGR0_SAM67_MCU_MCU_ECC_AGGR_EDC_CTRL_GROUP_5_CHECKER_TYPE,
17192  SDL_MCU_ECC_AGGR0_SAM67_MCU_MCU_ECC_AGGR_EDC_CTRL_GROUP_5_WIDTH },
17193 };
17194 
17199 static const SDL_MemConfig_t SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_MemEntries[SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES] =
17200 {
17201  { SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_ID, 0x0020718000u,
17202  SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_SIZE, 4u,
17203  SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_ROW_WIDTH, ((bool)true) },
17204 };
17205 
17211 static const SDL_GrpChkConfig_t SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_groupEntries[SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_MAX_NUM_CHECKERS] =
17212 {
17213  { SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_GROUP_0_CHECKER_TYPE,
17214  SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_GROUP_0_WIDTH },
17215 };
17216 
17221 static const SDL_MemConfig_t SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_MemEntries[SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES] =
17222 {
17223  { SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_ID, 0x0020708000u,
17224  SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_SIZE, 4u,
17225  SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_ROW_WIDTH, ((bool)true) },
17226 };
17227 
17233 static const SDL_GrpChkConfig_t SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_groupEntries[SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_MAX_NUM_CHECKERS] =
17234 {
17235  { SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_GROUP_0_CHECKER_TYPE,
17236  SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_GROUP_0_WIDTH },
17237 };
17238 
17243 static const SDL_MemConfig_t SDL_MMCSD0_EMMC8SS_16FFC_ECC_AGGR_TXMEM_MemEntries[SDL_MMCSD0_EMMC8SS_16FFC_ECC_AGGR_TXMEM_RAM_IDS_TOTAL_ENTRIES] =
17244 {
17245  { SDL_MMCSD0_EMMC8SS_16FFC_ECC_AGGR_TXMEM_EMMC8SS_16FFC_SDHC_WRAP_TXMEM_RAM_ID, 0u,
17246  SDL_MMCSD0_EMMC8SS_16FFC_ECC_AGGR_TXMEM_EMMC8SS_16FFC_SDHC_WRAP_TXMEM_RAM_SIZE, 4u,
17247  SDL_MMCSD0_EMMC8SS_16FFC_ECC_AGGR_TXMEM_EMMC8SS_16FFC_SDHC_WRAP_TXMEM_ROW_WIDTH, ((bool)false) },
17248 };
17249 
17254 static const SDL_MemConfig_t SDL_MMCSD0_EMMC8SS_16FFC_ECC_AGGR_RXMEM_MemEntries[SDL_MMCSD0_EMMC8SS_16FFC_ECC_AGGR_RXMEM_RAM_IDS_TOTAL_ENTRIES] =
17255 {
17256  { SDL_MMCSD0_EMMC8SS_16FFC_ECC_AGGR_RXMEM_EMMC8SS_16FFC_SDHC_WRAP_RXMEM_RAM_ID, 0u,
17257  SDL_MMCSD0_EMMC8SS_16FFC_ECC_AGGR_RXMEM_EMMC8SS_16FFC_SDHC_WRAP_RXMEM_RAM_SIZE, 4u,
17258  SDL_MMCSD0_EMMC8SS_16FFC_ECC_AGGR_RXMEM_EMMC8SS_16FFC_SDHC_WRAP_RXMEM_ROW_WIDTH, ((bool)false) },
17259 };
17260 
17265 static const SDL_MemConfig_t SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_MemEntries[SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_RAM_IDS_TOTAL_ENTRIES] =
17266 {
17267  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_IDATA_SPRAM_BANK0_LO_ECC_SVBUS_RAM_ID, 0u,
17268  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_IDATA_SPRAM_BANK0_LO_ECC_SVBUS_RAM_SIZE, 4u,
17269  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_IDATA_SPRAM_BANK0_LO_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
17270  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_IDATA_SPRAM_BANK0_HI_ECC_SVBUS_RAM_ID, 0u,
17271  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_IDATA_SPRAM_BANK0_HI_ECC_SVBUS_RAM_SIZE, 4u,
17272  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_IDATA_SPRAM_BANK0_HI_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
17273  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_IDATA_SPRAM_BANK1_LO_ECC_SVBUS_RAM_ID, 0u,
17274  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_IDATA_SPRAM_BANK1_LO_ECC_SVBUS_RAM_SIZE, 4u,
17275  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_IDATA_SPRAM_BANK1_LO_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
17276  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_IDATA_SPRAM_BANK1_HI_ECC_SVBUS_RAM_ID, 0u,
17277  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_IDATA_SPRAM_BANK1_HI_ECC_SVBUS_RAM_SIZE, 4u,
17278  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_IDATA_SPRAM_BANK1_HI_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
17279  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_ITAG_SPRAM_RAM0_ECC_SVBUS_RAM_ID, 0u,
17280  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_ITAG_SPRAM_RAM0_ECC_SVBUS_RAM_SIZE, 4u,
17281  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_ITAG_SPRAM_RAM0_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
17282  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_ITAG_SPRAM_RAM1_ECC_SVBUS_RAM_ID, 0u,
17283  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_ITAG_SPRAM_RAM1_ECC_SVBUS_RAM_SIZE, 4u,
17284  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_ITAG_SPRAM_RAM1_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
17285  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DDATA_SPRAM_BANK0_ECC_SVBUS_RAM_ID, 0u,
17286  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DDATA_SPRAM_BANK0_ECC_SVBUS_RAM_SIZE, 4u,
17287  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DDATA_SPRAM_BANK0_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
17288  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DDATA_SPRAM_BANK1_ECC_SVBUS_RAM_ID, 0u,
17289  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DDATA_SPRAM_BANK1_ECC_SVBUS_RAM_SIZE, 4u,
17290  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DDATA_SPRAM_BANK1_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
17291  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DDATA_SPRAM_BANK2_ECC_SVBUS_RAM_ID, 0u,
17292  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DDATA_SPRAM_BANK2_ECC_SVBUS_RAM_SIZE, 4u,
17293  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DDATA_SPRAM_BANK2_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
17294  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DDATA_SPRAM_BANK3_ECC_SVBUS_RAM_ID, 0u,
17295  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DDATA_SPRAM_BANK3_ECC_SVBUS_RAM_SIZE, 4u,
17296  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DDATA_SPRAM_BANK3_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
17297  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DDATA_SPRAM_BANK4_ECC_SVBUS_RAM_ID, 0u,
17298  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DDATA_SPRAM_BANK4_ECC_SVBUS_RAM_SIZE, 4u,
17299  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DDATA_SPRAM_BANK4_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
17300  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DDATA_SPRAM_BANK5_ECC_SVBUS_RAM_ID, 0u,
17301  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DDATA_SPRAM_BANK5_ECC_SVBUS_RAM_SIZE, 4u,
17302  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DDATA_SPRAM_BANK5_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
17303  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DDATA_SPRAM_BANK6_ECC_SVBUS_RAM_ID, 0u,
17304  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DDATA_SPRAM_BANK6_ECC_SVBUS_RAM_SIZE, 4u,
17305  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DDATA_SPRAM_BANK6_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
17306  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DDATA_SPRAM_BANK7_ECC_SVBUS_RAM_ID, 0u,
17307  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DDATA_SPRAM_BANK7_ECC_SVBUS_RAM_SIZE, 4u,
17308  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DDATA_SPRAM_BANK7_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
17309  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DTAG_SPRAM_BANK0_ECC_SVBUS_RAM_ID, 0u,
17310  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DTAG_SPRAM_BANK0_ECC_SVBUS_RAM_SIZE, 4u,
17311  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DTAG_SPRAM_BANK0_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
17312  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DTAG_SPRAM_BANK1_ECC_SVBUS_RAM_ID, 0u,
17313  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DTAG_SPRAM_BANK1_ECC_SVBUS_RAM_SIZE, 4u,
17314  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DTAG_SPRAM_BANK1_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
17315  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DTAG_SPRAM_BANK2_ECC_SVBUS_RAM_ID, 0u,
17316  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DTAG_SPRAM_BANK2_ECC_SVBUS_RAM_SIZE, 4u,
17317  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DTAG_SPRAM_BANK2_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
17318  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DTAG_SPRAM_BANK3_ECC_SVBUS_RAM_ID, 0u,
17319  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DTAG_SPRAM_BANK3_ECC_SVBUS_RAM_SIZE, 4u,
17320  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DTAG_SPRAM_BANK3_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
17321  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DDIRTY_SPRAM_ECC_SVBUS_RAM_ID, 0u,
17322  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DDIRTY_SPRAM_ECC_SVBUS_RAM_SIZE, 4u,
17323  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DDIRTY_SPRAM_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
17324  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_TLB_SPRAM_BANK0_ECC_SVBUS_RAM_ID, 0u,
17325  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_TLB_SPRAM_BANK0_ECC_SVBUS_RAM_SIZE, 4u,
17326  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_TLB_SPRAM_BANK0_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
17327  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_TLB_SPRAM_BANK1_ECC_SVBUS_RAM_ID, 0u,
17328  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_TLB_SPRAM_BANK1_ECC_SVBUS_RAM_SIZE, 4u,
17329  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_TLB_SPRAM_BANK1_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
17330  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_TLB_SPRAM_BANK2_ECC_SVBUS_RAM_ID, 0u,
17331  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_TLB_SPRAM_BANK2_ECC_SVBUS_RAM_SIZE, 4u,
17332  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_TLB_SPRAM_BANK2_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
17333  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_TLB_SPRAM_BANK3_ECC_SVBUS_RAM_ID, 0u,
17334  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_TLB_SPRAM_BANK3_ECC_SVBUS_RAM_SIZE, 4u,
17335  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_TLB_SPRAM_BANK3_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
17336  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY0_ECC_SVBUS_RAM_ID, 0u,
17337  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY0_ECC_SVBUS_RAM_SIZE, 4u,
17338  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY0_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
17339  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY1_ECC_SVBUS_RAM_ID, 0u,
17340  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY1_ECC_SVBUS_RAM_SIZE, 4u,
17341  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY1_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
17342  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY2_ECC_SVBUS_RAM_ID, 0u,
17343  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY2_ECC_SVBUS_RAM_SIZE, 4u,
17344  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY2_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
17345  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY3_ECC_SVBUS_RAM_ID, 0u,
17346  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY3_ECC_SVBUS_RAM_SIZE, 4u,
17347  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY3_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
17348 };
17349 
17354 static const SDL_MemConfig_t SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_MemEntries[SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_RAM_IDS_TOTAL_ENTRIES] =
17355 {
17356  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_IDATA_SPRAM_BANK0_LO_ECC_SVBUS_RAM_ID, 0u,
17357  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_IDATA_SPRAM_BANK0_LO_ECC_SVBUS_RAM_SIZE, 4u,
17358  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_IDATA_SPRAM_BANK0_LO_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
17359  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_IDATA_SPRAM_BANK0_HI_ECC_SVBUS_RAM_ID, 0u,
17360  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_IDATA_SPRAM_BANK0_HI_ECC_SVBUS_RAM_SIZE, 4u,
17361  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_IDATA_SPRAM_BANK0_HI_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
17362  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_IDATA_SPRAM_BANK1_LO_ECC_SVBUS_RAM_ID, 0u,
17363  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_IDATA_SPRAM_BANK1_LO_ECC_SVBUS_RAM_SIZE, 4u,
17364  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_IDATA_SPRAM_BANK1_LO_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
17365  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_IDATA_SPRAM_BANK1_HI_ECC_SVBUS_RAM_ID, 0u,
17366  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_IDATA_SPRAM_BANK1_HI_ECC_SVBUS_RAM_SIZE, 4u,
17367  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_IDATA_SPRAM_BANK1_HI_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
17368  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_ITAG_SPRAM_RAM0_ECC_SVBUS_RAM_ID, 0u,
17369  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_ITAG_SPRAM_RAM0_ECC_SVBUS_RAM_SIZE, 4u,
17370  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_ITAG_SPRAM_RAM0_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
17371  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_ITAG_SPRAM_RAM1_ECC_SVBUS_RAM_ID, 0u,
17372  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_ITAG_SPRAM_RAM1_ECC_SVBUS_RAM_SIZE, 4u,
17373  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_ITAG_SPRAM_RAM1_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
17374  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DDATA_SPRAM_BANK0_ECC_SVBUS_RAM_ID, 0u,
17375  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DDATA_SPRAM_BANK0_ECC_SVBUS_RAM_SIZE, 4u,
17376  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DDATA_SPRAM_BANK0_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
17377  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DDATA_SPRAM_BANK1_ECC_SVBUS_RAM_ID, 0u,
17378  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DDATA_SPRAM_BANK1_ECC_SVBUS_RAM_SIZE, 4u,
17379  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DDATA_SPRAM_BANK1_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
17380  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DDATA_SPRAM_BANK2_ECC_SVBUS_RAM_ID, 0u,
17381  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DDATA_SPRAM_BANK2_ECC_SVBUS_RAM_SIZE, 4u,
17382  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DDATA_SPRAM_BANK2_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
17383  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DDATA_SPRAM_BANK3_ECC_SVBUS_RAM_ID, 0u,
17384  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DDATA_SPRAM_BANK3_ECC_SVBUS_RAM_SIZE, 4u,
17385  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DDATA_SPRAM_BANK3_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
17386  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DDATA_SPRAM_BANK4_ECC_SVBUS_RAM_ID, 0u,
17387  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DDATA_SPRAM_BANK4_ECC_SVBUS_RAM_SIZE, 4u,
17388  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DDATA_SPRAM_BANK4_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
17389  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DDATA_SPRAM_BANK5_ECC_SVBUS_RAM_ID, 0u,
17390  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DDATA_SPRAM_BANK5_ECC_SVBUS_RAM_SIZE, 4u,
17391  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DDATA_SPRAM_BANK5_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
17392  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DDATA_SPRAM_BANK6_ECC_SVBUS_RAM_ID, 0u,
17393  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DDATA_SPRAM_BANK6_ECC_SVBUS_RAM_SIZE, 4u,
17394  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DDATA_SPRAM_BANK6_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
17395  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DDATA_SPRAM_BANK7_ECC_SVBUS_RAM_ID, 0u,
17396  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DDATA_SPRAM_BANK7_ECC_SVBUS_RAM_SIZE, 4u,
17397  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DDATA_SPRAM_BANK7_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
17398  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DTAG_SPRAM_BANK0_ECC_SVBUS_RAM_ID, 0u,
17399  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DTAG_SPRAM_BANK0_ECC_SVBUS_RAM_SIZE, 4u,
17400  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DTAG_SPRAM_BANK0_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
17401  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DTAG_SPRAM_BANK1_ECC_SVBUS_RAM_ID, 0u,
17402  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DTAG_SPRAM_BANK1_ECC_SVBUS_RAM_SIZE, 4u,
17403  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DTAG_SPRAM_BANK1_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
17404  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DTAG_SPRAM_BANK2_ECC_SVBUS_RAM_ID, 0u,
17405  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DTAG_SPRAM_BANK2_ECC_SVBUS_RAM_SIZE, 4u,
17406  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DTAG_SPRAM_BANK2_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
17407  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DTAG_SPRAM_BANK3_ECC_SVBUS_RAM_ID, 0u,
17408  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DTAG_SPRAM_BANK3_ECC_SVBUS_RAM_SIZE, 4u,
17409  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DTAG_SPRAM_BANK3_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
17410  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DDIRTY_SPRAM_ECC_SVBUS_RAM_ID, 0u,
17411  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DDIRTY_SPRAM_ECC_SVBUS_RAM_SIZE, 4u,
17412  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DDIRTY_SPRAM_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
17413  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_TLB_SPRAM_BANK0_ECC_SVBUS_RAM_ID, 0u,
17414  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_TLB_SPRAM_BANK0_ECC_SVBUS_RAM_SIZE, 4u,
17415  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_TLB_SPRAM_BANK0_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
17416  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_TLB_SPRAM_BANK1_ECC_SVBUS_RAM_ID, 0u,
17417  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_TLB_SPRAM_BANK1_ECC_SVBUS_RAM_SIZE, 4u,
17418  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_TLB_SPRAM_BANK1_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
17419  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_TLB_SPRAM_BANK2_ECC_SVBUS_RAM_ID, 0u,
17420  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_TLB_SPRAM_BANK2_ECC_SVBUS_RAM_SIZE, 4u,
17421  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_TLB_SPRAM_BANK2_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
17422  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_TLB_SPRAM_BANK3_ECC_SVBUS_RAM_ID, 0u,
17423  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_TLB_SPRAM_BANK3_ECC_SVBUS_RAM_SIZE, 4u,
17424  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_TLB_SPRAM_BANK3_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
17425  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY0_ECC_SVBUS_RAM_ID, 0u,
17426  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY0_ECC_SVBUS_RAM_SIZE, 4u,
17427  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY0_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
17428  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY1_ECC_SVBUS_RAM_ID, 0u,
17429  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY1_ECC_SVBUS_RAM_SIZE, 4u,
17430  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY1_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
17431  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY2_ECC_SVBUS_RAM_ID, 0u,
17432  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY2_ECC_SVBUS_RAM_SIZE, 4u,
17433  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY2_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
17434  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY3_ECC_SVBUS_RAM_ID, 0u,
17435  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY3_ECC_SVBUS_RAM_SIZE, 4u,
17436  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY3_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
17437 };
17438 
17443 static const SDL_MemConfig_t SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_MemEntries[SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_RAM_IDS_TOTAL_ENTRIES] =
17444 {
17445  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_IDATA_SPRAM_BANK0_LO_ECC_SVBUS_RAM_ID, 0u,
17446  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_IDATA_SPRAM_BANK0_LO_ECC_SVBUS_RAM_SIZE, 4u,
17447  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_IDATA_SPRAM_BANK0_LO_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
17448  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_IDATA_SPRAM_BANK0_HI_ECC_SVBUS_RAM_ID, 0u,
17449  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_IDATA_SPRAM_BANK0_HI_ECC_SVBUS_RAM_SIZE, 4u,
17450  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_IDATA_SPRAM_BANK0_HI_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
17451  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_IDATA_SPRAM_BANK1_LO_ECC_SVBUS_RAM_ID, 0u,
17452  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_IDATA_SPRAM_BANK1_LO_ECC_SVBUS_RAM_SIZE, 4u,
17453  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_IDATA_SPRAM_BANK1_LO_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
17454  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_IDATA_SPRAM_BANK1_HI_ECC_SVBUS_RAM_ID, 0u,
17455  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_IDATA_SPRAM_BANK1_HI_ECC_SVBUS_RAM_SIZE, 4u,
17456  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_IDATA_SPRAM_BANK1_HI_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
17457  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_ITAG_SPRAM_RAM0_ECC_SVBUS_RAM_ID, 0u,
17458  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_ITAG_SPRAM_RAM0_ECC_SVBUS_RAM_SIZE, 4u,
17459  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_ITAG_SPRAM_RAM0_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
17460  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_ITAG_SPRAM_RAM1_ECC_SVBUS_RAM_ID, 0u,
17461  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_ITAG_SPRAM_RAM1_ECC_SVBUS_RAM_SIZE, 4u,
17462  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_ITAG_SPRAM_RAM1_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
17463  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DDATA_SPRAM_BANK0_ECC_SVBUS_RAM_ID, 0u,
17464  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DDATA_SPRAM_BANK0_ECC_SVBUS_RAM_SIZE, 4u,
17465  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DDATA_SPRAM_BANK0_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
17466  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DDATA_SPRAM_BANK1_ECC_SVBUS_RAM_ID, 0u,
17467  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DDATA_SPRAM_BANK1_ECC_SVBUS_RAM_SIZE, 4u,
17468  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DDATA_SPRAM_BANK1_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
17469  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DDATA_SPRAM_BANK2_ECC_SVBUS_RAM_ID, 0u,
17470  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DDATA_SPRAM_BANK2_ECC_SVBUS_RAM_SIZE, 4u,
17471  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DDATA_SPRAM_BANK2_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
17472  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DDATA_SPRAM_BANK3_ECC_SVBUS_RAM_ID, 0u,
17473  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DDATA_SPRAM_BANK3_ECC_SVBUS_RAM_SIZE, 4u,
17474  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DDATA_SPRAM_BANK3_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
17475  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DDATA_SPRAM_BANK4_ECC_SVBUS_RAM_ID, 0u,
17476  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DDATA_SPRAM_BANK4_ECC_SVBUS_RAM_SIZE, 4u,
17477  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DDATA_SPRAM_BANK4_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
17478  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DDATA_SPRAM_BANK5_ECC_SVBUS_RAM_ID, 0u,
17479  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DDATA_SPRAM_BANK5_ECC_SVBUS_RAM_SIZE, 4u,
17480  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DDATA_SPRAM_BANK5_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
17481  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DDATA_SPRAM_BANK6_ECC_SVBUS_RAM_ID, 0u,
17482  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DDATA_SPRAM_BANK6_ECC_SVBUS_RAM_SIZE, 4u,
17483  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DDATA_SPRAM_BANK6_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
17484  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DDATA_SPRAM_BANK7_ECC_SVBUS_RAM_ID, 0u,
17485  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DDATA_SPRAM_BANK7_ECC_SVBUS_RAM_SIZE, 4u,
17486  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DDATA_SPRAM_BANK7_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
17487  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DTAG_SPRAM_BANK0_ECC_SVBUS_RAM_ID, 0u,
17488  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DTAG_SPRAM_BANK0_ECC_SVBUS_RAM_SIZE, 4u,
17489  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DTAG_SPRAM_BANK0_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
17490  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DTAG_SPRAM_BANK1_ECC_SVBUS_RAM_ID, 0u,
17491  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DTAG_SPRAM_BANK1_ECC_SVBUS_RAM_SIZE, 4u,
17492  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DTAG_SPRAM_BANK1_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
17493  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DTAG_SPRAM_BANK2_ECC_SVBUS_RAM_ID, 0u,
17494  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DTAG_SPRAM_BANK2_ECC_SVBUS_RAM_SIZE, 4u,
17495  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DTAG_SPRAM_BANK2_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
17496  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DTAG_SPRAM_BANK3_ECC_SVBUS_RAM_ID, 0u,
17497  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DTAG_SPRAM_BANK3_ECC_SVBUS_RAM_SIZE, 4u,
17498  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DTAG_SPRAM_BANK3_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
17499  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DDIRTY_SPRAM_ECC_SVBUS_RAM_ID, 0u,
17500  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DDIRTY_SPRAM_ECC_SVBUS_RAM_SIZE, 4u,
17501  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DDIRTY_SPRAM_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
17502  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_TLB_SPRAM_BANK0_ECC_SVBUS_RAM_ID, 0u,
17503  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_TLB_SPRAM_BANK0_ECC_SVBUS_RAM_SIZE, 4u,
17504  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_TLB_SPRAM_BANK0_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
17505  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_TLB_SPRAM_BANK1_ECC_SVBUS_RAM_ID, 0u,
17506  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_TLB_SPRAM_BANK1_ECC_SVBUS_RAM_SIZE, 4u,
17507  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_TLB_SPRAM_BANK1_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
17508  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_TLB_SPRAM_BANK2_ECC_SVBUS_RAM_ID, 0u,
17509  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_TLB_SPRAM_BANK2_ECC_SVBUS_RAM_SIZE, 4u,
17510  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_TLB_SPRAM_BANK2_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
17511  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_TLB_SPRAM_BANK3_ECC_SVBUS_RAM_ID, 0u,
17512  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_TLB_SPRAM_BANK3_ECC_SVBUS_RAM_SIZE, 4u,
17513  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_TLB_SPRAM_BANK3_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
17514  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY0_ECC_SVBUS_RAM_ID, 0u,
17515  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY0_ECC_SVBUS_RAM_SIZE, 4u,
17516  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY0_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
17517  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY1_ECC_SVBUS_RAM_ID, 0u,
17518  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY1_ECC_SVBUS_RAM_SIZE, 4u,
17519  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY1_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
17520  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY2_ECC_SVBUS_RAM_ID, 0u,
17521  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY2_ECC_SVBUS_RAM_SIZE, 4u,
17522  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY2_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
17523  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY3_ECC_SVBUS_RAM_ID, 0u,
17524  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY3_ECC_SVBUS_RAM_SIZE, 4u,
17525  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY3_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
17526 };
17527 
17532 static const SDL_MemConfig_t SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_MemEntries[SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_RAM_IDS_TOTAL_ENTRIES] =
17533 {
17534  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_IDATA_SPRAM_BANK0_LO_ECC_SVBUS_RAM_ID, 0u,
17535  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_IDATA_SPRAM_BANK0_LO_ECC_SVBUS_RAM_SIZE, 4u,
17536  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_IDATA_SPRAM_BANK0_LO_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
17537  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_IDATA_SPRAM_BANK0_HI_ECC_SVBUS_RAM_ID, 0u,
17538  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_IDATA_SPRAM_BANK0_HI_ECC_SVBUS_RAM_SIZE, 4u,
17539  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_IDATA_SPRAM_BANK0_HI_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
17540  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_IDATA_SPRAM_BANK1_LO_ECC_SVBUS_RAM_ID, 0u,
17541  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_IDATA_SPRAM_BANK1_LO_ECC_SVBUS_RAM_SIZE, 4u,
17542  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_IDATA_SPRAM_BANK1_LO_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
17543  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_IDATA_SPRAM_BANK1_HI_ECC_SVBUS_RAM_ID, 0u,
17544  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_IDATA_SPRAM_BANK1_HI_ECC_SVBUS_RAM_SIZE, 4u,
17545  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_IDATA_SPRAM_BANK1_HI_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
17546  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_ITAG_SPRAM_RAM0_ECC_SVBUS_RAM_ID, 0u,
17547  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_ITAG_SPRAM_RAM0_ECC_SVBUS_RAM_SIZE, 4u,
17548  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_ITAG_SPRAM_RAM0_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
17549  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_ITAG_SPRAM_RAM1_ECC_SVBUS_RAM_ID, 0u,
17550  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_ITAG_SPRAM_RAM1_ECC_SVBUS_RAM_SIZE, 4u,
17551  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_ITAG_SPRAM_RAM1_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
17552  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DDATA_SPRAM_BANK0_ECC_SVBUS_RAM_ID, 0u,
17553  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DDATA_SPRAM_BANK0_ECC_SVBUS_RAM_SIZE, 4u,
17554  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DDATA_SPRAM_BANK0_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
17555  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DDATA_SPRAM_BANK1_ECC_SVBUS_RAM_ID, 0u,
17556  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DDATA_SPRAM_BANK1_ECC_SVBUS_RAM_SIZE, 4u,
17557  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DDATA_SPRAM_BANK1_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
17558  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DDATA_SPRAM_BANK2_ECC_SVBUS_RAM_ID, 0u,
17559  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DDATA_SPRAM_BANK2_ECC_SVBUS_RAM_SIZE, 4u,
17560  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DDATA_SPRAM_BANK2_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
17561  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DDATA_SPRAM_BANK3_ECC_SVBUS_RAM_ID, 0u,
17562  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DDATA_SPRAM_BANK3_ECC_SVBUS_RAM_SIZE, 4u,
17563  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DDATA_SPRAM_BANK3_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
17564  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DDATA_SPRAM_BANK4_ECC_SVBUS_RAM_ID, 0u,
17565  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DDATA_SPRAM_BANK4_ECC_SVBUS_RAM_SIZE, 4u,
17566  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DDATA_SPRAM_BANK4_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
17567  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DDATA_SPRAM_BANK5_ECC_SVBUS_RAM_ID, 0u,
17568  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DDATA_SPRAM_BANK5_ECC_SVBUS_RAM_SIZE, 4u,
17569  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DDATA_SPRAM_BANK5_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
17570  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DDATA_SPRAM_BANK6_ECC_SVBUS_RAM_ID, 0u,
17571  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DDATA_SPRAM_BANK6_ECC_SVBUS_RAM_SIZE, 4u,
17572  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DDATA_SPRAM_BANK6_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
17573  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DDATA_SPRAM_BANK7_ECC_SVBUS_RAM_ID, 0u,
17574  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DDATA_SPRAM_BANK7_ECC_SVBUS_RAM_SIZE, 4u,
17575  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DDATA_SPRAM_BANK7_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
17576  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DTAG_SPRAM_BANK0_ECC_SVBUS_RAM_ID, 0u,
17577  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DTAG_SPRAM_BANK0_ECC_SVBUS_RAM_SIZE, 4u,
17578  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DTAG_SPRAM_BANK0_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
17579  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DTAG_SPRAM_BANK1_ECC_SVBUS_RAM_ID, 0u,
17580  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DTAG_SPRAM_BANK1_ECC_SVBUS_RAM_SIZE, 4u,
17581  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DTAG_SPRAM_BANK1_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
17582  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DTAG_SPRAM_BANK2_ECC_SVBUS_RAM_ID, 0u,
17583  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DTAG_SPRAM_BANK2_ECC_SVBUS_RAM_SIZE, 4u,
17584  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DTAG_SPRAM_BANK2_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
17585  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DTAG_SPRAM_BANK3_ECC_SVBUS_RAM_ID, 0u,
17586  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DTAG_SPRAM_BANK3_ECC_SVBUS_RAM_SIZE, 4u,
17587  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DTAG_SPRAM_BANK3_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
17588  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DDIRTY_SPRAM_ECC_SVBUS_RAM_ID, 0u,
17589  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DDIRTY_SPRAM_ECC_SVBUS_RAM_SIZE, 4u,
17590  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DDIRTY_SPRAM_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
17591  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_TLB_SPRAM_BANK0_ECC_SVBUS_RAM_ID, 0u,
17592  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_TLB_SPRAM_BANK0_ECC_SVBUS_RAM_SIZE, 4u,
17593  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_TLB_SPRAM_BANK0_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
17594  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_TLB_SPRAM_BANK1_ECC_SVBUS_RAM_ID, 0u,
17595  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_TLB_SPRAM_BANK1_ECC_SVBUS_RAM_SIZE, 4u,
17596  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_TLB_SPRAM_BANK1_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
17597  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_TLB_SPRAM_BANK2_ECC_SVBUS_RAM_ID, 0u,
17598  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_TLB_SPRAM_BANK2_ECC_SVBUS_RAM_SIZE, 4u,
17599  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_TLB_SPRAM_BANK2_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
17600  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_TLB_SPRAM_BANK3_ECC_SVBUS_RAM_ID, 0u,
17601  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_TLB_SPRAM_BANK3_ECC_SVBUS_RAM_SIZE, 4u,
17602  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_TLB_SPRAM_BANK3_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
17603  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY0_ECC_SVBUS_RAM_ID, 0u,
17604  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY0_ECC_SVBUS_RAM_SIZE, 4u,
17605  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY0_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
17606  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY1_ECC_SVBUS_RAM_ID, 0u,
17607  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY1_ECC_SVBUS_RAM_SIZE, 4u,
17608  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY1_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
17609  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY2_ECC_SVBUS_RAM_ID, 0u,
17610  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY2_ECC_SVBUS_RAM_SIZE, 4u,
17611  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY2_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
17612  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY3_ECC_SVBUS_RAM_ID, 0u,
17613  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY3_ECC_SVBUS_RAM_SIZE, 4u,
17614  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY3_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
17615 };
17616 
17621 static const SDL_MemConfig_t SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_MemEntries[SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_RAM_IDS_TOTAL_ENTRIES] =
17622 {
17623  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY0_ECC_SVBUS_RAM_ID, 0u,
17624  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY0_ECC_SVBUS_RAM_SIZE, 4u,
17625  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY0_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
17626  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY1_ECC_SVBUS_RAM_ID, 0u,
17627  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY1_ECC_SVBUS_RAM_SIZE, 4u,
17628  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY1_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
17629  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY2_ECC_SVBUS_RAM_ID, 0u,
17630  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY2_ECC_SVBUS_RAM_SIZE, 4u,
17631  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY2_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
17632  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY3_ECC_SVBUS_RAM_ID, 0u,
17633  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY3_ECC_SVBUS_RAM_SIZE, 4u,
17634  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY3_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
17635  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY4_ECC_SVBUS_RAM_ID, 0u,
17636  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY4_ECC_SVBUS_RAM_SIZE, 4u,
17637  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY4_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
17638  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY5_ECC_SVBUS_RAM_ID, 0u,
17639  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY5_ECC_SVBUS_RAM_SIZE, 4u,
17640  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY5_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
17641  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY6_ECC_SVBUS_RAM_ID, 0u,
17642  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY6_ECC_SVBUS_RAM_SIZE, 4u,
17643  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY6_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
17644  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY7_ECC_SVBUS_RAM_ID, 0u,
17645  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY7_ECC_SVBUS_RAM_SIZE, 4u,
17646  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY7_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
17647  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY8_ECC_SVBUS_RAM_ID, 0u,
17648  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY8_ECC_SVBUS_RAM_SIZE, 4u,
17649  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY8_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
17650  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY9_ECC_SVBUS_RAM_ID, 0u,
17651  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY9_ECC_SVBUS_RAM_SIZE, 4u,
17652  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY9_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
17653  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY10_ECC_SVBUS_RAM_ID, 0u,
17654  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY10_ECC_SVBUS_RAM_SIZE, 4u,
17655  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY10_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
17656  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY11_ECC_SVBUS_RAM_ID, 0u,
17657  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY11_ECC_SVBUS_RAM_SIZE, 4u,
17658  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY11_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
17659  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY12_ECC_SVBUS_RAM_ID, 0u,
17660  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY12_ECC_SVBUS_RAM_SIZE, 4u,
17661  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY12_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
17662  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY13_ECC_SVBUS_RAM_ID, 0u,
17663  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY13_ECC_SVBUS_RAM_SIZE, 4u,
17664  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY13_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
17665  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY14_ECC_SVBUS_RAM_ID, 0u,
17666  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY14_ECC_SVBUS_RAM_SIZE, 4u,
17667  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY14_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
17668  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY15_ECC_SVBUS_RAM_ID, 0u,
17669  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY15_ECC_SVBUS_RAM_SIZE, 4u,
17670  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY15_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
17671  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_DATARAM_SPRAM_0_ECC_SVBUS_RAM_ID, 0u,
17672  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_DATARAM_SPRAM_0_ECC_SVBUS_RAM_SIZE, 4u,
17673  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_DATARAM_SPRAM_0_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
17674  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_DATARAM_SPRAM_1_ECC_SVBUS_RAM_ID, 0u,
17675  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_DATARAM_SPRAM_1_ECC_SVBUS_RAM_SIZE, 4u,
17676  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_DATARAM_SPRAM_1_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
17677  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_DATARAM_SPRAM_2_ECC_SVBUS_RAM_ID, 0u,
17678  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_DATARAM_SPRAM_2_ECC_SVBUS_RAM_SIZE, 4u,
17679  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_DATARAM_SPRAM_2_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
17680  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_DATARAM_SPRAM_3_ECC_SVBUS_RAM_ID, 0u,
17681  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_DATARAM_SPRAM_3_ECC_SVBUS_RAM_SIZE, 4u,
17682  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_DATARAM_SPRAM_3_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
17683  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_DATARAM_SPRAM_4_ECC_SVBUS_RAM_ID, 0u,
17684  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_DATARAM_SPRAM_4_ECC_SVBUS_RAM_SIZE, 4u,
17685  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_DATARAM_SPRAM_4_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
17686  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_DATARAM_SPRAM_5_ECC_SVBUS_RAM_ID, 0u,
17687  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_DATARAM_SPRAM_5_ECC_SVBUS_RAM_SIZE, 4u,
17688  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_DATARAM_SPRAM_5_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
17689  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_DATARAM_SPRAM_6_ECC_SVBUS_RAM_ID, 0u,
17690  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_DATARAM_SPRAM_6_ECC_SVBUS_RAM_SIZE, 4u,
17691  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_DATARAM_SPRAM_6_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
17692  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_DATARAM_SPRAM_7_ECC_SVBUS_RAM_ID, 0u,
17693  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_DATARAM_SPRAM_7_ECC_SVBUS_RAM_SIZE, 4u,
17694  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_DATARAM_SPRAM_7_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
17695 };
17696 
17701 static const SDL_MemConfig_t SDL_MCU_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_MemEntries[SDL_MCU_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES] =
17702 {
17703  { SDL_MCU_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_ID, 0x0004E00000u,
17704  SDL_MCU_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_SIZE, 4u,
17705  SDL_MCU_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_ROW_WIDTH, ((bool)true) },
17706 };
17707 
17713 static const SDL_GrpChkConfig_t SDL_MCU_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_groupEntries[SDL_MCU_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_MAX_NUM_CHECKERS] =
17714 {
17715  { SDL_MCU_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_GROUP_0_CHECKER_TYPE,
17716  SDL_MCU_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_GROUP_0_WIDTH },
17717 };
17722 static const SDL_RAMIdEntry_t SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_RamIdTable[SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_NUM_RAMS] =
17723 {
17724  { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_ITAG_RAM0_RAM_ID,
17725  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_ITAG_RAM0_INJECT_TYPE,
17726  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_ITAG_RAM0_ECC_TYPE,
17727  0u,
17728  NULL },
17729  { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_ITAG_RAM1_RAM_ID,
17730  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_ITAG_RAM1_INJECT_TYPE,
17731  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_ITAG_RAM1_ECC_TYPE,
17732  0u,
17733  NULL },
17734  { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_ITAG_RAM2_RAM_ID,
17735  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_ITAG_RAM2_INJECT_TYPE,
17736  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_ITAG_RAM2_ECC_TYPE,
17737  0u,
17738  NULL },
17739  { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_ITAG_RAM3_RAM_ID,
17740  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_ITAG_RAM3_INJECT_TYPE,
17741  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_ITAG_RAM3_ECC_TYPE,
17742  0u,
17743  NULL },
17744  { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_IDATA_BANK0_RAM_ID,
17745  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_IDATA_BANK0_INJECT_TYPE,
17746  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_IDATA_BANK0_ECC_TYPE,
17747  0u,
17748  NULL },
17749  { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_IDATA_BANK1_RAM_ID,
17750  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_IDATA_BANK1_INJECT_TYPE,
17751  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_IDATA_BANK1_ECC_TYPE,
17752  0u,
17753  NULL },
17754  { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_IDATA_BANK2_RAM_ID,
17755  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_IDATA_BANK2_INJECT_TYPE,
17756  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_IDATA_BANK2_ECC_TYPE,
17757  0u,
17758  NULL },
17759  { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_IDATA_BANK3_RAM_ID,
17760  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_IDATA_BANK3_INJECT_TYPE,
17761  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_IDATA_BANK3_ECC_TYPE,
17762  0u,
17763  NULL },
17764  { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DTAG_RAM0_RAM_ID,
17765  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DTAG_RAM0_INJECT_TYPE,
17766  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DTAG_RAM0_ECC_TYPE,
17767  0u,
17768  NULL },
17769  { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DTAG_RAM1_RAM_ID,
17770  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DTAG_RAM1_INJECT_TYPE,
17771  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DTAG_RAM1_ECC_TYPE,
17772  0u,
17773  NULL },
17774  { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DTAG_RAM2_RAM_ID,
17775  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DTAG_RAM2_INJECT_TYPE,
17776  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DTAG_RAM2_ECC_TYPE,
17777  0u,
17778  NULL },
17779  { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DTAG_RAM3_RAM_ID,
17780  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DTAG_RAM3_INJECT_TYPE,
17781  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DTAG_RAM3_ECC_TYPE,
17782  0u,
17783  NULL },
17784  { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDIRTY_RAM_RAM_ID,
17785  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDIRTY_RAM_INJECT_TYPE,
17786  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDIRTY_RAM_ECC_TYPE,
17787  0u,
17788  NULL },
17789  { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM0_RAM_ID,
17790  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM0_INJECT_TYPE,
17791  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM0_ECC_TYPE,
17792  0u,
17793  NULL },
17794  { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM1_RAM_ID,
17795  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM1_INJECT_TYPE,
17796  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM1_ECC_TYPE,
17797  0u,
17798  NULL },
17799  { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM2_RAM_ID,
17800  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM2_INJECT_TYPE,
17801  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM2_ECC_TYPE,
17802  0u,
17803  NULL },
17804  { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM3_RAM_ID,
17805  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM3_INJECT_TYPE,
17806  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM3_ECC_TYPE,
17807  0u,
17808  NULL },
17809  { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM4_RAM_ID,
17810  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM4_INJECT_TYPE,
17811  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM4_ECC_TYPE,
17812  0u,
17813  NULL },
17814  { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM5_RAM_ID,
17815  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM5_INJECT_TYPE,
17816  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM5_ECC_TYPE,
17817  0u,
17818  NULL },
17819  { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM6_RAM_ID,
17820  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM6_INJECT_TYPE,
17821  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM6_ECC_TYPE,
17822  0u,
17823  NULL },
17824  { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM7_RAM_ID,
17825  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM7_INJECT_TYPE,
17826  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM7_ECC_TYPE,
17827  0u,
17828  NULL },
17829  { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_ATCM0_BANK0_RAM_ID,
17830  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_ATCM0_BANK0_INJECT_TYPE,
17831  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_ATCM0_BANK0_ECC_TYPE,
17832  0u,
17833  NULL },
17834  { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_ATCM0_BANK1_RAM_ID,
17835  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_ATCM0_BANK1_INJECT_TYPE,
17836  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_ATCM0_BANK1_ECC_TYPE,
17837  0u,
17838  NULL },
17839  { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_B0TCM0_BANK0_RAM_ID,
17840  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_B0TCM0_BANK0_INJECT_TYPE,
17841  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_B0TCM0_BANK0_ECC_TYPE,
17842  0u,
17843  NULL },
17844  { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_B0TCM0_BANK1_RAM_ID,
17845  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_B0TCM0_BANK1_INJECT_TYPE,
17846  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_B0TCM0_BANK1_ECC_TYPE,
17847  0u,
17848  NULL },
17849  { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_B1TCM0_BANK0_RAM_ID,
17850  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_B1TCM0_BANK0_INJECT_TYPE,
17851  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_B1TCM0_BANK0_ECC_TYPE,
17852  0u,
17853  NULL },
17854  { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_B1TCM0_BANK1_RAM_ID,
17855  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_B1TCM0_BANK1_INJECT_TYPE,
17856  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_B1TCM0_BANK1_ECC_TYPE,
17857  0u,
17858  NULL },
17859  { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_PULSAR_KS_VIM_COMMON_CORE0_RAM_RAM_ID,
17860  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_PULSAR_KS_VIM_COMMON_CORE0_RAM_INJECT_TYPE,
17861  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_PULSAR_KS_VIM_COMMON_CORE0_RAM_ECC_TYPE,
17862  0u,
17863  NULL },
17864  { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_MEM_MST0_KSBUS_AXI2VBUSM_R_RDATA_BUFFER_RAM_ID,
17865  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_MEM_MST0_KSBUS_AXI2VBUSM_R_RDATA_BUFFER_INJECT_TYPE,
17866  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_MEM_MST0_KSBUS_AXI2VBUSM_R_RDATA_BUFFER_ECC_TYPE,
17867  0u,
17868  NULL },
17869 };
17870 
17875 static const SDL_RAMIdEntry_t SDL_DSS_DSI0_K3_DSS_DSI_DSI_TOP_ECC_AGGR_SYS_RamIdTable[SDL_DSS_DSI0_K3_DSS_DSI_DSI_TOP_ECC_AGGR_SYS_NUM_RAMS] =
17876 {
17877  { SDL_DSS_DSI0_K3_DSS_DSI_DSI_TOP_ECC_AGGR_SYS_K3_DSS_DSI_DSI_TOP_DSI_EDC_CTRL_SYS_EDC_CTRL_0_RAM_ID,
17878  SDL_DSS_DSI0_K3_DSS_DSI_DSI_TOP_ECC_AGGR_SYS_K3_DSS_DSI_DSI_TOP_DSI_EDC_CTRL_SYS_EDC_CTRL_0_INJECT_TYPE,
17879  SDL_DSS_DSI0_K3_DSS_DSI_DSI_TOP_ECC_AGGR_SYS_K3_DSS_DSI_DSI_TOP_DSI_EDC_CTRL_SYS_EDC_CTRL_0_ECC_TYPE,
17880  SDL_DSS_DSI0_K3_DSS_DSI_DSI_TOP_ECC_AGGR_SYS_K3_DSS_DSI_DSI_TOP_DSI_EDC_CTRL_SYS_EDC_CTRL_0_MAX_NUM_CHECKERS,
17881  SDL_DSS_DSI0_K3_DSS_DSI_DSI_TOP_ECC_AGGR_SYS_K3_DSS_DSI_DSI_TOP_DSI_EDC_CTRL_SYS_EDC_CTRL_0_groupEntries },
17882 };
17883 
17888 static const SDL_RAMIdEntry_t SDL_PSRAMECC0_PSRAM256X32E_ECC_AGGR_RamIdTable[SDL_PSRAMECC0_PSRAM256X32E_ECC_AGGR_NUM_RAMS] =
17889 {
17890  { SDL_PSRAMECC0_PSRAM256X32E_ECC_AGGR_PSRAM256X32E_PSRAM0_ECC_RAM_ID,
17891  SDL_PSRAMECC0_PSRAM256X32E_ECC_AGGR_PSRAM256X32E_PSRAM0_ECC_INJECT_TYPE,
17892  SDL_PSRAMECC0_PSRAM256X32E_ECC_AGGR_PSRAM256X32E_PSRAM0_ECC_ECC_TYPE,
17893  0u,
17894  NULL },
17895 };
17896 
17901 static const SDL_RAMIdEntry_t SDL_PSRAMECC1_PSRAM256X32E_ECC_AGGR_RamIdTable[SDL_PSRAMECC1_PSRAM256X32E_ECC_AGGR_NUM_RAMS] =
17902 {
17903  { SDL_PSRAMECC1_PSRAM256X32E_ECC_AGGR_PSRAM256X32E_PSRAM0_ECC_RAM_ID,
17904  SDL_PSRAMECC1_PSRAM256X32E_ECC_AGGR_PSRAM256X32E_PSRAM0_ECC_INJECT_TYPE,
17905  SDL_PSRAMECC1_PSRAM256X32E_ECC_AGGR_PSRAM256X32E_PSRAM0_ECC_ECC_TYPE,
17906  0u,
17907  NULL },
17908 };
17909 
17914 static const SDL_RAMIdEntry_t SDL_MSRAM_64K0_MSRAM2KX256E_ECC_AGGR_RamIdTable[SDL_MSRAM_64K0_MSRAM2KX256E_ECC_AGGR_NUM_RAMS] =
17915 {
17916  { SDL_MSRAM_64K0_MSRAM2KX256E_ECC_AGGR_MSRAM2KX256E_MSRAM0_ECC0_RAM_ID,
17917  SDL_MSRAM_64K0_MSRAM2KX256E_ECC_AGGR_MSRAM2KX256E_MSRAM0_ECC0_INJECT_TYPE,
17918  SDL_MSRAM_64K0_MSRAM2KX256E_ECC_AGGR_MSRAM2KX256E_MSRAM0_ECC0_ECC_TYPE,
17919  0u,
17920  NULL },
17921 };
17922 
17927 static const SDL_RAMIdEntry_t SDL_WKUP_ECC_AGGR2_RamIdTable[SDL_WKUP_ECC_AGGR2_NUM_RAMS] =
17928 {
17929  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_RAM_ID,
17930  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_INJECT_TYPE,
17931  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_ECC_TYPE,
17932  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_MAX_NUM_CHECKERS,
17933  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_groupEntries },
17934  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_RAM_ID,
17935  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_INJECT_TYPE,
17936  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_ECC_TYPE,
17937  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_MAX_NUM_CHECKERS,
17938  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_groupEntries },
17939  { SDL_WKUP_ECC_AGGR2_AM67_MCU_PLL_MMR_EDC_CTRL_BUSECC_RAM_ID,
17940  SDL_WKUP_ECC_AGGR2_AM67_MCU_PLL_MMR_EDC_CTRL_BUSECC_INJECT_TYPE,
17941  SDL_WKUP_ECC_AGGR2_AM67_MCU_PLL_MMR_EDC_CTRL_BUSECC_ECC_TYPE,
17942  SDL_WKUP_ECC_AGGR2_AM67_MCU_PLL_MMR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
17943  SDL_WKUP_ECC_AGGR2_AM67_MCU_PLL_MMR_EDC_CTRL_BUSECC_groupEntries },
17944  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_RAM_ID,
17945  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_INJECT_TYPE,
17946  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_ECC_TYPE,
17947  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_MAX_NUM_CHECKERS,
17948  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_groupEntries },
17949  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_RAM_ID,
17950  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_INJECT_TYPE,
17951  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_ECC_TYPE,
17952  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_MAX_NUM_CHECKERS,
17953  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_groupEntries },
17954  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_RAM_ID,
17955  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_INJECT_TYPE,
17956  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_ECC_TYPE,
17957  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_MAX_NUM_CHECKERS,
17958  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_groupEntries },
17959  { SDL_WKUP_ECC_AGGR2_ISAM67_DM2WS_VBUSM_GASKET_MCU_0_EDC_CTRL_RAM_ID,
17960  SDL_WKUP_ECC_AGGR2_ISAM67_DM2WS_VBUSM_GASKET_MCU_0_EDC_CTRL_INJECT_TYPE,
17961  SDL_WKUP_ECC_AGGR2_ISAM67_DM2WS_VBUSM_GASKET_MCU_0_EDC_CTRL_ECC_TYPE,
17962  SDL_WKUP_ECC_AGGR2_ISAM67_DM2WS_VBUSM_GASKET_MCU_0_EDC_CTRL_MAX_NUM_CHECKERS,
17963  SDL_WKUP_ECC_AGGR2_ISAM67_DM2WS_VBUSM_GASKET_MCU_0_EDC_CTRL_groupEntries },
17964  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_RAM_ID,
17965  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_INJECT_TYPE,
17966  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_ECC_TYPE,
17967  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_MAX_NUM_CHECKERS,
17968  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_groupEntries },
17969  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ISAM67_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM67_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_BRIDGE_BUSECC_RAM_ID,
17970  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ISAM67_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM67_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_BRIDGE_BUSECC_INJECT_TYPE,
17971  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ISAM67_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM67_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_BRIDGE_BUSECC_ECC_TYPE,
17972  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ISAM67_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM67_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_BRIDGE_BUSECC_MAX_NUM_CHECKERS,
17973  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ISAM67_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM67_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_BRIDGE_BUSECC_groupEntries },
17974  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_IAM67_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM67_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_BRIDGE_BUSECC_RAM_ID,
17975  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_IAM67_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM67_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_BRIDGE_BUSECC_INJECT_TYPE,
17976  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_IAM67_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM67_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_BRIDGE_BUSECC_ECC_TYPE,
17977  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_IAM67_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM67_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_BRIDGE_BUSECC_MAX_NUM_CHECKERS,
17978  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_IAM67_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM67_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_BRIDGE_BUSECC_groupEntries },
17979  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_RAM_ID,
17980  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_INJECT_TYPE,
17981  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_ECC_TYPE,
17982  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_MAX_NUM_CHECKERS,
17983  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_groupEntries },
17984  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_RAM_ID,
17985  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_INJECT_TYPE,
17986  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_ECC_TYPE,
17987  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_MAX_NUM_CHECKERS,
17988  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_groupEntries },
17989  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_CBASS_DEFAULT_ERR_AM67_WKUP_SAFE_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_RAM_ID,
17990  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_CBASS_DEFAULT_ERR_AM67_WKUP_SAFE_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_INJECT_TYPE,
17991  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_CBASS_DEFAULT_ERR_AM67_WKUP_SAFE_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_ECC_TYPE,
17992  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_CBASS_DEFAULT_ERR_AM67_WKUP_SAFE_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
17993  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_CBASS_DEFAULT_ERR_AM67_WKUP_SAFE_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_groupEntries },
17994  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_RAM_ID,
17995  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_INJECT_TYPE,
17996  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_ECC_TYPE,
17997  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_MAX_NUM_CHECKERS,
17998  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_groupEntries },
17999  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ERR_SCR_AM67_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_RAM_ID,
18000  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ERR_SCR_AM67_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_INJECT_TYPE,
18001  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ERR_SCR_AM67_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_ECC_TYPE,
18002  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ERR_SCR_AM67_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
18003  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ERR_SCR_AM67_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_groupEntries },
18004  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_RAM_ID,
18005  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_INJECT_TYPE,
18006  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_ECC_TYPE,
18007  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_MAX_NUM_CHECKERS,
18008  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_groupEntries },
18009  { SDL_WKUP_ECC_AGGR2_SAM67_WKUP_SAFE_ECC_AGGR_EDC_CTRL_RAM_ID,
18010  SDL_WKUP_ECC_AGGR2_SAM67_WKUP_SAFE_ECC_AGGR_EDC_CTRL_INJECT_TYPE,
18011  SDL_WKUP_ECC_AGGR2_SAM67_WKUP_SAFE_ECC_AGGR_EDC_CTRL_ECC_TYPE,
18012  SDL_WKUP_ECC_AGGR2_SAM67_WKUP_SAFE_ECC_AGGR_EDC_CTRL_MAX_NUM_CHECKERS,
18013  SDL_WKUP_ECC_AGGR2_SAM67_WKUP_SAFE_ECC_AGGR_EDC_CTRL_groupEntries },
18014 };
18015 
18020 static const SDL_RAMIdEntry_t SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_RamIdTable[SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_NUM_RAMS] =
18021 {
18022  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_IMAILBOX8_MAIN_0_RAMECC_RAM_ID,
18023  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_IMAILBOX8_MAIN_0_RAMECC_INJECT_TYPE,
18024  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_IMAILBOX8_MAIN_0_RAMECC_ECC_TYPE,
18025  0u,
18026  NULL },
18027  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_HSM_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_HSM_VBUSP_S_BRIDGE_BUSECC_RAM_ID,
18028  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_HSM_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_HSM_VBUSP_S_BRIDGE_BUSECC_INJECT_TYPE,
18029  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_HSM_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_HSM_VBUSP_S_BRIDGE_BUSECC_ECC_TYPE,
18030  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_HSM_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_HSM_VBUSP_S_BRIDGE_BUSECC_MAX_NUM_CHECKERS,
18031  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_HSM_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_HSM_VBUSP_S_BRIDGE_BUSECC_groupEntries },
18032  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_TIFS_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_TIFS_VBUSP_S_BRIDGE_BUSECC_RAM_ID,
18033  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_TIFS_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_TIFS_VBUSP_S_BRIDGE_BUSECC_INJECT_TYPE,
18034  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_TIFS_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_TIFS_VBUSP_S_BRIDGE_BUSECC_ECC_TYPE,
18035  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_TIFS_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_TIFS_VBUSP_S_BRIDGE_BUSECC_MAX_NUM_CHECKERS,
18036  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_TIFS_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_TIFS_VBUSP_S_BRIDGE_BUSECC_groupEntries },
18037  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_RAM_ID,
18038  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_INJECT_TYPE,
18039  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_ECC_TYPE,
18040  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_MAX_NUM_CHECKERS,
18041  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_groupEntries },
18042  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_RAM_ID,
18043  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_INJECT_TYPE,
18044  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_ECC_TYPE,
18045  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_MAX_NUM_CHECKERS,
18046  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_groupEntries },
18047  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_SRC_BUSECC_RAM_ID,
18048  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_SRC_BUSECC_INJECT_TYPE,
18049  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_SRC_BUSECC_ECC_TYPE,
18050  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS,
18051  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_SRC_BUSECC_groupEntries },
18052  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_DST_BUSECC_RAM_ID,
18053  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_DST_BUSECC_INJECT_TYPE,
18054  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_DST_BUSECC_ECC_TYPE,
18055  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS,
18056  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_DST_BUSECC_groupEntries },
18057  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_FW_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_RAM_ID,
18058  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_FW_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_INJECT_TYPE,
18059  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_FW_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_ECC_TYPE,
18060  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_FW_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_MAX_NUM_CHECKERS,
18061  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_FW_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_groupEntries },
18062  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_DMSS_CFG_SRC_BUSECC_RAM_ID,
18063  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_DMSS_CFG_SRC_BUSECC_INJECT_TYPE,
18064  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_DMSS_CFG_SRC_BUSECC_ECC_TYPE,
18065  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_DMSS_CFG_SRC_BUSECC_MAX_NUM_CHECKERS,
18066  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_DMSS_CFG_SRC_BUSECC_groupEntries },
18067  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_DMSS_CFG_DST_BUSECC_RAM_ID,
18068  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_DMSS_CFG_DST_BUSECC_INJECT_TYPE,
18069  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_DMSS_CFG_DST_BUSECC_ECC_TYPE,
18070  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_DMSS_CFG_DST_BUSECC_MAX_NUM_CHECKERS,
18071  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_DMSS_CFG_DST_BUSECC_groupEntries },
18072  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_PKTDMA_CRED_SRC_BUSECC_RAM_ID,
18073  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_PKTDMA_CRED_SRC_BUSECC_INJECT_TYPE,
18074  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_PKTDMA_CRED_SRC_BUSECC_ECC_TYPE,
18075  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_PKTDMA_CRED_SRC_BUSECC_MAX_NUM_CHECKERS,
18076  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_PKTDMA_CRED_SRC_BUSECC_groupEntries },
18077  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_PKTDMA_CRED_DST_BUSECC_RAM_ID,
18078  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_PKTDMA_CRED_DST_BUSECC_INJECT_TYPE,
18079  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_PKTDMA_CRED_DST_BUSECC_ECC_TYPE,
18080  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_PKTDMA_CRED_DST_BUSECC_MAX_NUM_CHECKERS,
18081  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_PKTDMA_CRED_DST_BUSECC_groupEntries },
18082 };
18083 
18088 static const SDL_RAMIdEntry_t SDL_DMASS1_DMSS_CSI_AM62A_ECCAGGR_RamIdTable[SDL_DMASS1_DMSS_CSI_AM62A_ECCAGGR_NUM_RAMS] =
18089 {
18090  { SDL_DMASS1_DMSS_CSI_AM62A_ECCAGGR_DMSS_CSI_AM62A_BCDMA_CFG_CONFIG_RAM_ID,
18091  SDL_DMASS1_DMSS_CSI_AM62A_ECCAGGR_DMSS_CSI_AM62A_BCDMA_CFG_CONFIG_INJECT_TYPE,
18092  SDL_DMASS1_DMSS_CSI_AM62A_ECCAGGR_DMSS_CSI_AM62A_BCDMA_CFG_CONFIG_ECC_TYPE,
18093  0u,
18094  NULL },
18095  { SDL_DMASS1_DMSS_CSI_AM62A_ECCAGGR_DMSS_CSI_AM62A_BCDMA_CFG_STATE_RAM_ID,
18096  SDL_DMASS1_DMSS_CSI_AM62A_ECCAGGR_DMSS_CSI_AM62A_BCDMA_CFG_STATE_INJECT_TYPE,
18097  SDL_DMASS1_DMSS_CSI_AM62A_ECCAGGR_DMSS_CSI_AM62A_BCDMA_CFG_STATE_ECC_TYPE,
18098  0u,
18099  NULL },
18100  { SDL_DMASS1_DMSS_CSI_AM62A_ECCAGGR_DMSS_CSI_AM62A_BCDMA_RPCFIFO_F0_RAM_ID,
18101  SDL_DMASS1_DMSS_CSI_AM62A_ECCAGGR_DMSS_CSI_AM62A_BCDMA_RPCFIFO_F0_INJECT_TYPE,
18102  SDL_DMASS1_DMSS_CSI_AM62A_ECCAGGR_DMSS_CSI_AM62A_BCDMA_RPCFIFO_F0_ECC_TYPE,
18103  0u,
18104  NULL },
18105  { SDL_DMASS1_DMSS_CSI_AM62A_ECCAGGR_DMSS_CSI_AM62A_BCDMA_RPCFIFO_F1_RAM_ID,
18106  SDL_DMASS1_DMSS_CSI_AM62A_ECCAGGR_DMSS_CSI_AM62A_BCDMA_RPCFIFO_F1_INJECT_TYPE,
18107  SDL_DMASS1_DMSS_CSI_AM62A_ECCAGGR_DMSS_CSI_AM62A_BCDMA_RPCFIFO_F1_ECC_TYPE,
18108  0u,
18109  NULL },
18110  { SDL_DMASS1_DMSS_CSI_AM62A_ECCAGGR_DMSS_CSI_AM62A_BCDMA_RPCFIFO_WC_RAM_ID,
18111  SDL_DMASS1_DMSS_CSI_AM62A_ECCAGGR_DMSS_CSI_AM62A_BCDMA_RPCFIFO_WC_INJECT_TYPE,
18112  SDL_DMASS1_DMSS_CSI_AM62A_ECCAGGR_DMSS_CSI_AM62A_BCDMA_RPCFIFO_WC_ECC_TYPE,
18113  0u,
18114  NULL },
18115  { SDL_DMASS1_DMSS_CSI_AM62A_ECCAGGR_DMSS_CSI_AM62A_BCDMA_STATS_STSR0_RAM_ID,
18116  SDL_DMASS1_DMSS_CSI_AM62A_ECCAGGR_DMSS_CSI_AM62A_BCDMA_STATS_STSR0_INJECT_TYPE,
18117  SDL_DMASS1_DMSS_CSI_AM62A_ECCAGGR_DMSS_CSI_AM62A_BCDMA_STATS_STSR0_ECC_TYPE,
18118  0u,
18119  NULL },
18120  { SDL_DMASS1_DMSS_CSI_AM62A_ECCAGGR_DMSS_CSI_AM62A_BCDMA_RINGOCC_CNTR_RAM_ID,
18121  SDL_DMASS1_DMSS_CSI_AM62A_ECCAGGR_DMSS_CSI_AM62A_BCDMA_RINGOCC_CNTR_INJECT_TYPE,
18122  SDL_DMASS1_DMSS_CSI_AM62A_ECCAGGR_DMSS_CSI_AM62A_BCDMA_RINGOCC_CNTR_ECC_TYPE,
18123  0u,
18124  NULL },
18125  { SDL_DMASS1_DMSS_CSI_AM62A_ECCAGGR_DMSS_CSI_AM62A_INTAGGR_STATREG_SR_SPRAM_8X128_SWW_SR_RAM_ID,
18126  SDL_DMASS1_DMSS_CSI_AM62A_ECCAGGR_DMSS_CSI_AM62A_INTAGGR_STATREG_SR_SPRAM_8X128_SWW_SR_INJECT_TYPE,
18127  SDL_DMASS1_DMSS_CSI_AM62A_ECCAGGR_DMSS_CSI_AM62A_INTAGGR_STATREG_SR_SPRAM_8X128_SWW_SR_ECC_TYPE,
18128  0u,
18129  NULL },
18130  { SDL_DMASS1_DMSS_CSI_AM62A_ECCAGGR_DMSS_CSI_AM62A_INTAGGR_COMMON_IM_TPRAM_153X34_SWW_SR_RAM_ID,
18131  SDL_DMASS1_DMSS_CSI_AM62A_ECCAGGR_DMSS_CSI_AM62A_INTAGGR_COMMON_IM_TPRAM_153X34_SWW_SR_INJECT_TYPE,
18132  SDL_DMASS1_DMSS_CSI_AM62A_ECCAGGR_DMSS_CSI_AM62A_INTAGGR_COMMON_IM_TPRAM_153X34_SWW_SR_ECC_TYPE,
18133  0u,
18134  NULL },
18135 };
18136 
18141 static const SDL_RAMIdEntry_t SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_RamIdTable[SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_NUM_RAMS] =
18142 {
18143  { SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_ECC0_RAM_ID,
18144  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_ECC0_INJECT_TYPE,
18145  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_ECC0_ECC_TYPE,
18146  0u,
18147  NULL },
18148  { SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_RAM_ID,
18149  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_INJECT_TYPE,
18150  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_ECC_TYPE,
18151  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_MAX_NUM_CHECKERS,
18152  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_groupEntries },
18153  { SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_ECC_AGGR_EDC_CTRL_RAM_ID,
18154  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_ECC_AGGR_EDC_CTRL_INJECT_TYPE,
18155  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_ECC_AGGR_EDC_CTRL_ECC_TYPE,
18156  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_ECC_AGGR_EDC_CTRL_MAX_NUM_CHECKERS,
18157  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_ECC_AGGR_EDC_CTRL_groupEntries },
18158 };
18159 
18164 static const SDL_RAMIdEntry_t SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_RamIdTable[SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_NUM_RAMS] =
18165 {
18166  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_ECCAGGR_EDC_CTRL_RAM_ID,
18167  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_ECCAGGR_EDC_CTRL_INJECT_TYPE,
18168  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_ECCAGGR_EDC_CTRL_ECC_TYPE,
18169  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_ECCAGGR_EDC_CTRL_MAX_NUM_CHECKERS,
18170  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_ECCAGGR_EDC_CTRL_groupEntries },
18171  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_RAM_ID,
18172  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_INJECT_TYPE,
18173  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_ECC_TYPE,
18174  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_MAX_NUM_CHECKERS,
18175  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_groupEntries },
18176  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_VBUSP_P2P_BRIDGE_EDC_CTRL_0_RAM_ID,
18177  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_VBUSP_P2P_BRIDGE_EDC_CTRL_0_INJECT_TYPE,
18178  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_VBUSP_P2P_BRIDGE_EDC_CTRL_0_ECC_TYPE,
18179  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_VBUSP_P2P_BRIDGE_EDC_CTRL_0_MAX_NUM_CHECKERS,
18180  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_VBUSP_P2P_BRIDGE_EDC_CTRL_0_groupEntries },
18181  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_RAM_ID,
18182  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_INJECT_TYPE,
18183  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_ECC_TYPE,
18184  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_MAX_NUM_CHECKERS,
18185  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_groupEntries },
18186 };
18187 
18192 static const SDL_RAMIdEntry_t SDL_WKUP_ECC_AGGR1_RamIdTable[SDL_WKUP_ECC_AGGR1_NUM_RAMS] =
18193 {
18194  { SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_ISAM67_DM_MCU_ECC_AGGR_WKUP_1_CFG_P2P_BRIDGE_ISAM67_DM_MCU_ECC_AGGR_WKUP_1_CFG_BRIDGE_DST_BUSECC_RAM_ID,
18195  SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_ISAM67_DM_MCU_ECC_AGGR_WKUP_1_CFG_P2P_BRIDGE_ISAM67_DM_MCU_ECC_AGGR_WKUP_1_CFG_BRIDGE_DST_BUSECC_INJECT_TYPE,
18196  SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_ISAM67_DM_MCU_ECC_AGGR_WKUP_1_CFG_P2P_BRIDGE_ISAM67_DM_MCU_ECC_AGGR_WKUP_1_CFG_BRIDGE_DST_BUSECC_ECC_TYPE,
18197  SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_ISAM67_DM_MCU_ECC_AGGR_WKUP_1_CFG_P2P_BRIDGE_ISAM67_DM_MCU_ECC_AGGR_WKUP_1_CFG_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS,
18198  SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_ISAM67_DM_MCU_ECC_AGGR_WKUP_1_CFG_P2P_BRIDGE_ISAM67_DM_MCU_ECC_AGGR_WKUP_1_CFG_BRIDGE_DST_BUSECC_groupEntries },
18199  { SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_RAM_ID,
18200  SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_INJECT_TYPE,
18201  SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_ECC_TYPE,
18202  SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
18203  SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_groupEntries },
18204  { SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_RAM_ID,
18205  SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_INJECT_TYPE,
18206  SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_ECC_TYPE,
18207  SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
18208  SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_groupEntries },
18209  { SDL_WKUP_ECC_AGGR1_AM67_MCU_FW_CBASS_IAM67_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM67_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_RAM_ID,
18210  SDL_WKUP_ECC_AGGR1_AM67_MCU_FW_CBASS_IAM67_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM67_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_INJECT_TYPE,
18211  SDL_WKUP_ECC_AGGR1_AM67_MCU_FW_CBASS_IAM67_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM67_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_ECC_TYPE,
18212  SDL_WKUP_ECC_AGGR1_AM67_MCU_FW_CBASS_IAM67_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM67_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS,
18213  SDL_WKUP_ECC_AGGR1_AM67_MCU_FW_CBASS_IAM67_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM67_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_groupEntries },
18214  { SDL_WKUP_ECC_AGGR1_AM67_MCU_FW_CBASS_IAM67_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM67_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_RAM_ID,
18215  SDL_WKUP_ECC_AGGR1_AM67_MCU_FW_CBASS_IAM67_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM67_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_INJECT_TYPE,
18216  SDL_WKUP_ECC_AGGR1_AM67_MCU_FW_CBASS_IAM67_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM67_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_ECC_TYPE,
18217  SDL_WKUP_ECC_AGGR1_AM67_MCU_FW_CBASS_IAM67_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM67_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS,
18218  SDL_WKUP_ECC_AGGR1_AM67_MCU_FW_CBASS_IAM67_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM67_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_groupEntries },
18219  { SDL_WKUP_ECC_AGGR1_AM67_MCU_FW_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_RAM_ID,
18220  SDL_WKUP_ECC_AGGR1_AM67_MCU_FW_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_INJECT_TYPE,
18221  SDL_WKUP_ECC_AGGR1_AM67_MCU_FW_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_ECC_TYPE,
18222  SDL_WKUP_ECC_AGGR1_AM67_MCU_FW_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_MAX_NUM_CHECKERS,
18223  SDL_WKUP_ECC_AGGR1_AM67_MCU_FW_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_groupEntries },
18224  { SDL_WKUP_ECC_AGGR1_SAM67_DM_MCU_ECC_AGGR_EDC_CTRL_RAM_ID,
18225  SDL_WKUP_ECC_AGGR1_SAM67_DM_MCU_ECC_AGGR_EDC_CTRL_INJECT_TYPE,
18226  SDL_WKUP_ECC_AGGR1_SAM67_DM_MCU_ECC_AGGR_EDC_CTRL_ECC_TYPE,
18227  SDL_WKUP_ECC_AGGR1_SAM67_DM_MCU_ECC_AGGR_EDC_CTRL_MAX_NUM_CHECKERS,
18228  SDL_WKUP_ECC_AGGR1_SAM67_DM_MCU_ECC_AGGR_EDC_CTRL_groupEntries },
18229 };
18230 
18235 static const SDL_RAMIdEntry_t SDL_FSS0_FSS_UL_OSPI0_OSPI_WRAP_ECC_AGGR_RamIdTable[SDL_FSS0_FSS_UL_OSPI0_OSPI_WRAP_ECC_AGGR_NUM_RAMS] =
18236 {
18237  { SDL_FSS0_FSS_UL_OSPI0_OSPI_WRAP_ECC_AGGR_OSPI_OSPI_WRAP_SRAM_RAM_ID,
18238  SDL_FSS0_FSS_UL_OSPI0_OSPI_WRAP_ECC_AGGR_OSPI_OSPI_WRAP_SRAM_INJECT_TYPE,
18239  SDL_FSS0_FSS_UL_OSPI0_OSPI_WRAP_ECC_AGGR_OSPI_OSPI_WRAP_SRAM_ECC_TYPE,
18240  0u,
18241  NULL },
18242 };
18243 
18248 static const SDL_RAMIdEntry_t SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_RamIdTable[SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_NUM_RAMS] =
18249 {
18250  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_ITAG_RAM0_RAM_ID,
18251  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_ITAG_RAM0_INJECT_TYPE,
18252  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_ITAG_RAM0_ECC_TYPE,
18253  0u,
18254  NULL },
18255  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_ITAG_RAM1_RAM_ID,
18256  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_ITAG_RAM1_INJECT_TYPE,
18257  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_ITAG_RAM1_ECC_TYPE,
18258  0u,
18259  NULL },
18260  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_ITAG_RAM2_RAM_ID,
18261  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_ITAG_RAM2_INJECT_TYPE,
18262  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_ITAG_RAM2_ECC_TYPE,
18263  0u,
18264  NULL },
18265  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_ITAG_RAM3_RAM_ID,
18266  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_ITAG_RAM3_INJECT_TYPE,
18267  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_ITAG_RAM3_ECC_TYPE,
18268  0u,
18269  NULL },
18270  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_IDATA_BANK0_RAM_ID,
18271  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_IDATA_BANK0_INJECT_TYPE,
18272  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_IDATA_BANK0_ECC_TYPE,
18273  0u,
18274  NULL },
18275  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_IDATA_BANK1_RAM_ID,
18276  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_IDATA_BANK1_INJECT_TYPE,
18277  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_IDATA_BANK1_ECC_TYPE,
18278  0u,
18279  NULL },
18280  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_IDATA_BANK2_RAM_ID,
18281  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_IDATA_BANK2_INJECT_TYPE,
18282  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_IDATA_BANK2_ECC_TYPE,
18283  0u,
18284  NULL },
18285  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_IDATA_BANK3_RAM_ID,
18286  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_IDATA_BANK3_INJECT_TYPE,
18287  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_IDATA_BANK3_ECC_TYPE,
18288  0u,
18289  NULL },
18290  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_DTAG_RAM0_RAM_ID,
18291  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_DTAG_RAM0_INJECT_TYPE,
18292  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_DTAG_RAM0_ECC_TYPE,
18293  0u,
18294  NULL },
18295  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_DTAG_RAM1_RAM_ID,
18296  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_DTAG_RAM1_INJECT_TYPE,
18297  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_DTAG_RAM1_ECC_TYPE,
18298  0u,
18299  NULL },
18300  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_DTAG_RAM2_RAM_ID,
18301  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_DTAG_RAM2_INJECT_TYPE,
18302  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_DTAG_RAM2_ECC_TYPE,
18303  0u,
18304  NULL },
18305  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_DTAG_RAM3_RAM_ID,
18306  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_DTAG_RAM3_INJECT_TYPE,
18307  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_DTAG_RAM3_ECC_TYPE,
18308  0u,
18309  NULL },
18310  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_DDIRTY_RAM_RAM_ID,
18311  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_DDIRTY_RAM_INJECT_TYPE,
18312  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_DDIRTY_RAM_ECC_TYPE,
18313  0u,
18314  NULL },
18315  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_DDATA_RAM0_RAM_ID,
18316  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_DDATA_RAM0_INJECT_TYPE,
18317  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_DDATA_RAM0_ECC_TYPE,
18318  0u,
18319  NULL },
18320  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_DDATA_RAM1_RAM_ID,
18321  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_DDATA_RAM1_INJECT_TYPE,
18322  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_DDATA_RAM1_ECC_TYPE,
18323  0u,
18324  NULL },
18325  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_DDATA_RAM2_RAM_ID,
18326  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_DDATA_RAM2_INJECT_TYPE,
18327  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_DDATA_RAM2_ECC_TYPE,
18328  0u,
18329  NULL },
18330  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_DDATA_RAM3_RAM_ID,
18331  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_DDATA_RAM3_INJECT_TYPE,
18332  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_DDATA_RAM3_ECC_TYPE,
18333  0u,
18334  NULL },
18335  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_DDATA_RAM4_RAM_ID,
18336  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_DDATA_RAM4_INJECT_TYPE,
18337  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_DDATA_RAM4_ECC_TYPE,
18338  0u,
18339  NULL },
18340  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_DDATA_RAM5_RAM_ID,
18341  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_DDATA_RAM5_INJECT_TYPE,
18342  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_DDATA_RAM5_ECC_TYPE,
18343  0u,
18344  NULL },
18345  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_DDATA_RAM6_RAM_ID,
18346  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_DDATA_RAM6_INJECT_TYPE,
18347  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_DDATA_RAM6_ECC_TYPE,
18348  0u,
18349  NULL },
18350  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_DDATA_RAM7_RAM_ID,
18351  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_DDATA_RAM7_INJECT_TYPE,
18352  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_DDATA_RAM7_ECC_TYPE,
18353  0u,
18354  NULL },
18355  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_ATCM0_BANK0_RAM_ID,
18356  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_ATCM0_BANK0_INJECT_TYPE,
18357  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_ATCM0_BANK0_ECC_TYPE,
18358  0u,
18359  NULL },
18360  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_ATCM0_BANK1_RAM_ID,
18361  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_ATCM0_BANK1_INJECT_TYPE,
18362  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_ATCM0_BANK1_ECC_TYPE,
18363  0u,
18364  NULL },
18365  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_B0TCM0_BANK0_RAM_ID,
18366  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_B0TCM0_BANK0_INJECT_TYPE,
18367  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_B0TCM0_BANK0_ECC_TYPE,
18368  0u,
18369  NULL },
18370  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_B0TCM0_BANK1_RAM_ID,
18371  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_B0TCM0_BANK1_INJECT_TYPE,
18372  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_B0TCM0_BANK1_ECC_TYPE,
18373  0u,
18374  NULL },
18375  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_B1TCM0_BANK0_RAM_ID,
18376  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_B1TCM0_BANK0_INJECT_TYPE,
18377  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_B1TCM0_BANK0_ECC_TYPE,
18378  0u,
18379  NULL },
18380  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_B1TCM0_BANK1_RAM_ID,
18381  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_B1TCM0_BANK1_INJECT_TYPE,
18382  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_B1TCM0_BANK1_ECC_TYPE,
18383  0u,
18384  NULL },
18385  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_KS_VIM_RAMECC_RAM_ID,
18386  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_KS_VIM_RAMECC_INJECT_TYPE,
18387  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_KS_VIM_RAMECC_ECC_TYPE,
18388  0u,
18389  NULL },
18390  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_VBUSM2AXI_EDC_RAM_ID,
18391  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_VBUSM2AXI_EDC_INJECT_TYPE,
18392  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_VBUSM2AXI_EDC_ECC_TYPE,
18393  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_VBUSM2AXI_EDC_MAX_NUM_CHECKERS,
18394  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_VBUSM2AXI_EDC_groupEntries },
18395  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_AXI2VBUSM_MEM_MST_RAMECC_RAM_ID,
18396  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_AXI2VBUSM_MEM_MST_RAMECC_INJECT_TYPE,
18397  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_AXI2VBUSM_MEM_MST_RAMECC_ECC_TYPE,
18398  0u,
18399  NULL },
18400  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_RAM_ID,
18401  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_INJECT_TYPE,
18402  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_ECC_TYPE,
18403  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_MAX_NUM_CHECKERS,
18404  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_groupEntries },
18405  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_0_RAM_ID,
18406  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_0_INJECT_TYPE,
18407  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_0_ECC_TYPE,
18408  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_0_MAX_NUM_CHECKERS,
18409  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_0_groupEntries },
18410  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_SCRP_EDC_RAM_ID,
18411  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_SCRP_EDC_INJECT_TYPE,
18412  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_SCRP_EDC_ECC_TYPE,
18413  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_SCRP_EDC_MAX_NUM_CHECKERS,
18414  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_SCRP_EDC_groupEntries },
18415  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_RAM_ID,
18416  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_INJECT_TYPE,
18417  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_ECC_TYPE,
18418  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
18419  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_groupEntries },
18420  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_ECC_AGGR_EDC_CTRL_RAM_ID,
18421  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_ECC_AGGR_EDC_CTRL_INJECT_TYPE,
18422  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_ECC_AGGR_EDC_CTRL_ECC_TYPE,
18423  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_ECC_AGGR_EDC_CTRL_MAX_NUM_CHECKERS,
18424  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_ECC_AGGR_EDC_CTRL_groupEntries },
18425 };
18426 
18431 static const SDL_RAMIdEntry_t SDL_GICSS0_GIC500SS_1_4_ECC_AGGR_RamIdTable[SDL_GICSS0_GIC500SS_1_4_ECC_AGGR_NUM_RAMS] =
18432 {
18433  { SDL_GICSS0_GIC500SS_1_4_ECC_AGGR_ICB_RAMECC_RAM_ID,
18434  SDL_GICSS0_GIC500SS_1_4_ECC_AGGR_ICB_RAMECC_INJECT_TYPE,
18435  SDL_GICSS0_GIC500SS_1_4_ECC_AGGR_ICB_RAMECC_ECC_TYPE,
18436  0u,
18437  NULL },
18438  { SDL_GICSS0_GIC500SS_1_4_ECC_AGGR_ITE_RAMECC_RAM_ID,
18439  SDL_GICSS0_GIC500SS_1_4_ECC_AGGR_ITE_RAMECC_INJECT_TYPE,
18440  SDL_GICSS0_GIC500SS_1_4_ECC_AGGR_ITE_RAMECC_ECC_TYPE,
18441  0u,
18442  NULL },
18443  { SDL_GICSS0_GIC500SS_1_4_ECC_AGGR_LPI_RAMECC_RAM_ID,
18444  SDL_GICSS0_GIC500SS_1_4_ECC_AGGR_LPI_RAMECC_INJECT_TYPE,
18445  SDL_GICSS0_GIC500SS_1_4_ECC_AGGR_LPI_RAMECC_ECC_TYPE,
18446  0u,
18447  NULL },
18448 };
18449 
18454 static const SDL_RAMIdEntry_t SDL_CPSW0_CPSW_3GUSS_AM67_CORE_ECC_CPSW_ECC_AGGR_RamIdTable[SDL_CPSW0_CPSW_3GUSS_AM67_CORE_ECC_CPSW_ECC_AGGR_NUM_RAMS] =
18455 {
18456  { SDL_CPSW0_CPSW_3GUSS_AM67_CORE_ECC_CPSW_ECC_AGGR_ALE_RAM_RAM_ID,
18457  SDL_CPSW0_CPSW_3GUSS_AM67_CORE_ECC_CPSW_ECC_AGGR_ALE_RAM_INJECT_TYPE,
18458  SDL_CPSW0_CPSW_3GUSS_AM67_CORE_ECC_CPSW_ECC_AGGR_ALE_RAM_ECC_TYPE,
18459  0u,
18460  NULL },
18461  { SDL_CPSW0_CPSW_3GUSS_AM67_CORE_ECC_CPSW_ECC_AGGR_CPSW_3GU_AM67_CORE_ECC_ECC_CTRL1_RAM_ID,
18462  SDL_CPSW0_CPSW_3GUSS_AM67_CORE_ECC_CPSW_ECC_AGGR_CPSW_3GU_AM67_CORE_ECC_ECC_CTRL1_INJECT_TYPE,
18463  SDL_CPSW0_CPSW_3GUSS_AM67_CORE_ECC_CPSW_ECC_AGGR_CPSW_3GU_AM67_CORE_ECC_ECC_CTRL1_ECC_TYPE,
18464  0u,
18465  NULL },
18466  { SDL_CPSW0_CPSW_3GUSS_AM67_CORE_ECC_CPSW_ECC_AGGR_CPSW_3GU_AM67_CORE_ECC_ECC_CTRL2_RAM_ID,
18467  SDL_CPSW0_CPSW_3GUSS_AM67_CORE_ECC_CPSW_ECC_AGGR_CPSW_3GU_AM67_CORE_ECC_ECC_CTRL2_INJECT_TYPE,
18468  SDL_CPSW0_CPSW_3GUSS_AM67_CORE_ECC_CPSW_ECC_AGGR_CPSW_3GU_AM67_CORE_ECC_ECC_CTRL2_ECC_TYPE,
18469  0u,
18470  NULL },
18471  { SDL_CPSW0_CPSW_3GUSS_AM67_CORE_ECC_CPSW_ECC_AGGR_CPSW_3GU_AM67_CORE_ECC_ECC_CTRL3_RAM_ID,
18472  SDL_CPSW0_CPSW_3GUSS_AM67_CORE_ECC_CPSW_ECC_AGGR_CPSW_3GU_AM67_CORE_ECC_ECC_CTRL3_INJECT_TYPE,
18473  SDL_CPSW0_CPSW_3GUSS_AM67_CORE_ECC_CPSW_ECC_AGGR_CPSW_3GU_AM67_CORE_ECC_ECC_CTRL3_ECC_TYPE,
18474  0u,
18475  NULL },
18476  { SDL_CPSW0_CPSW_3GUSS_AM67_CORE_ECC_CPSW_ECC_AGGR_CPSW_3GU_AM67_CORE_ECC_ECC_CTRL4_RAM_ID,
18477  SDL_CPSW0_CPSW_3GUSS_AM67_CORE_ECC_CPSW_ECC_AGGR_CPSW_3GU_AM67_CORE_ECC_ECC_CTRL4_INJECT_TYPE,
18478  SDL_CPSW0_CPSW_3GUSS_AM67_CORE_ECC_CPSW_ECC_AGGR_CPSW_3GU_AM67_CORE_ECC_ECC_CTRL4_ECC_TYPE,
18479  0u,
18480  NULL },
18481  { SDL_CPSW0_CPSW_3GUSS_AM67_CORE_ECC_CPSW_ECC_AGGR_CPSW_3GU_AM67_CORE_ECC_ECC_CTRL5_RAM_ID,
18482  SDL_CPSW0_CPSW_3GUSS_AM67_CORE_ECC_CPSW_ECC_AGGR_CPSW_3GU_AM67_CORE_ECC_ECC_CTRL5_INJECT_TYPE,
18483  SDL_CPSW0_CPSW_3GUSS_AM67_CORE_ECC_CPSW_ECC_AGGR_CPSW_3GU_AM67_CORE_ECC_ECC_CTRL5_ECC_TYPE,
18484  0u,
18485  NULL },
18486  { SDL_CPSW0_CPSW_3GUSS_AM67_CORE_ECC_CPSW_ECC_AGGR_CPSW_3GU_AM67_CORE_ECC_ECC_CTRL6_RAM_ID,
18487  SDL_CPSW0_CPSW_3GUSS_AM67_CORE_ECC_CPSW_ECC_AGGR_CPSW_3GU_AM67_CORE_ECC_ECC_CTRL6_INJECT_TYPE,
18488  SDL_CPSW0_CPSW_3GUSS_AM67_CORE_ECC_CPSW_ECC_AGGR_CPSW_3GU_AM67_CORE_ECC_ECC_CTRL6_ECC_TYPE,
18489  0u,
18490  NULL },
18491  { SDL_CPSW0_CPSW_3GUSS_AM67_CORE_ECC_CPSW_ECC_AGGR_EST_RAM_RAM_ID,
18492  SDL_CPSW0_CPSW_3GUSS_AM67_CORE_ECC_CPSW_ECC_AGGR_EST_RAM_INJECT_TYPE,
18493  SDL_CPSW0_CPSW_3GUSS_AM67_CORE_ECC_CPSW_ECC_AGGR_EST_RAM_ECC_TYPE,
18494  0u,
18495  NULL },
18496 };
18497 
18502 static const SDL_RAMIdEntry_t SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_RamIdTable[SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_NUM_RAMS] =
18503 {
18504  { SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_EDC_CTRL_0_RAM_ID,
18505  SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_EDC_CTRL_0_INJECT_TYPE,
18506  SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_EDC_CTRL_0_ECC_TYPE,
18507  SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_EDC_CTRL_0_MAX_NUM_CHECKERS,
18508  SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_EDC_CTRL_0_groupEntries },
18509  { SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_RX_SHIM_DMA_PSIL_FIFO_RAM_ID,
18510  SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_RX_SHIM_DMA_PSIL_FIFO_INJECT_TYPE,
18511  SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_RX_SHIM_DMA_PSIL_FIFO_ECC_TYPE,
18512  0u,
18513  NULL },
18514  { SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_RAM_WRAPPER0_FIFO_RAM_ID,
18515  SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_RAM_WRAPPER0_FIFO_INJECT_TYPE,
18516  SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_RAM_WRAPPER0_FIFO_ECC_TYPE,
18517  0u,
18518  NULL },
18519  { SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_RAM_WRAPPER1_FIFO_RAM_ID,
18520  SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_RAM_WRAPPER1_FIFO_INJECT_TYPE,
18521  SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_RAM_WRAPPER1_FIFO_ECC_TYPE,
18522  0u,
18523  NULL },
18524  { SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_RAM_WRAPPER2_FIFO_RAM_ID,
18525  SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_RAM_WRAPPER2_FIFO_INJECT_TYPE,
18526  SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_RAM_WRAPPER2_FIFO_ECC_TYPE,
18527  0u,
18528  NULL },
18529  { SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_RAM_WRAPPER3_FIFO_RAM_ID,
18530  SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_RAM_WRAPPER3_FIFO_INJECT_TYPE,
18531  SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_RAM_WRAPPER3_FIFO_ECC_TYPE,
18532  0u,
18533  NULL },
18534  { SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_VP0_VP_FIFO_RAM_ID,
18535  SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_VP0_VP_FIFO_INJECT_TYPE,
18536  SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_VP0_VP_FIFO_ECC_TYPE,
18537  0u,
18538  NULL },
18539  { SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_VP1_VP_FIFO_RAM_ID,
18540  SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_VP1_VP_FIFO_INJECT_TYPE,
18541  SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_VP1_VP_FIFO_ECC_TYPE,
18542  0u,
18543  NULL },
18544 };
18545 
18550 static const SDL_RAMIdEntry_t SDL_PSCSS0_SAM67_MAIN_PSC_WRAP_ECC_AGGR_RamIdTable[SDL_PSCSS0_SAM67_MAIN_PSC_WRAP_ECC_AGGR_NUM_RAMS] =
18551 {
18552  { SDL_PSCSS0_SAM67_MAIN_PSC_WRAP_ECC_AGGR_AM62A_PSC_CHFW_CBASS_DST_FW_CH_VBUSP_TABLE_RAM_ID,
18553  SDL_PSCSS0_SAM67_MAIN_PSC_WRAP_ECC_AGGR_AM62A_PSC_CHFW_CBASS_DST_FW_CH_VBUSP_TABLE_INJECT_TYPE,
18554  SDL_PSCSS0_SAM67_MAIN_PSC_WRAP_ECC_AGGR_AM62A_PSC_CHFW_CBASS_DST_FW_CH_VBUSP_TABLE_ECC_TYPE,
18555  0u,
18556  NULL },
18557 };
18558 
18563 static const SDL_RAMIdEntry_t SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_RXMEM_RamIdTable[SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_RXMEM_NUM_RAMS] =
18564 {
18565  { SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_RXMEM_EMMCSD4SS_SDHC_WRAP_RXMEM_RAM_ID,
18566  SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_RXMEM_EMMCSD4SS_SDHC_WRAP_RXMEM_INJECT_TYPE,
18567  SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_RXMEM_EMMCSD4SS_SDHC_WRAP_RXMEM_ECC_TYPE,
18568  0u,
18569  NULL },
18570 };
18571 
18576 static const SDL_RAMIdEntry_t SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_TXMEM_RamIdTable[SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_TXMEM_NUM_RAMS] =
18577 {
18578  { SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_TXMEM_EMMCSD4SS_SDHC_WRAP_TXMEM_RAM_ID,
18579  SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_TXMEM_EMMCSD4SS_SDHC_WRAP_TXMEM_INJECT_TYPE,
18580  SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_TXMEM_EMMCSD4SS_SDHC_WRAP_TXMEM_ECC_TYPE,
18581  0u,
18582  NULL },
18583 };
18584 
18589 static const SDL_RAMIdEntry_t SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_RamIdTable[SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_NUM_RAMS] =
18590 {
18591  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_ECCAGGR_EDC_CTRL_RAM_ID,
18592  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_ECCAGGR_EDC_CTRL_INJECT_TYPE,
18593  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_ECCAGGR_EDC_CTRL_ECC_TYPE,
18594  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_ECCAGGR_EDC_CTRL_MAX_NUM_CHECKERS,
18595  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_ECCAGGR_EDC_CTRL_groupEntries },
18596  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_CFG_CONFIG_RAM_ID,
18597  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_CFG_CONFIG_INJECT_TYPE,
18598  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_CFG_CONFIG_ECC_TYPE,
18599  0u,
18600  NULL },
18601  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_CFG_STATE_RAM_ID,
18602  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_CFG_STATE_INJECT_TYPE,
18603  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_CFG_STATE_ECC_TYPE,
18604  0u,
18605  NULL },
18606  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_TPCFIFO_F0_RAM_ID,
18607  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_TPCFIFO_F0_INJECT_TYPE,
18608  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_TPCFIFO_F0_ECC_TYPE,
18609  0u,
18610  NULL },
18611  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_TPCFIFO_F1_RAM_ID,
18612  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_TPCFIFO_F1_INJECT_TYPE,
18613  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_TPCFIFO_F1_ECC_TYPE,
18614  0u,
18615  NULL },
18616  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_RPCFIFO_F0_RAM_ID,
18617  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_RPCFIFO_F0_INJECT_TYPE,
18618  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_RPCFIFO_F0_ECC_TYPE,
18619  0u,
18620  NULL },
18621  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_RPCFIFO_F1_RAM_ID,
18622  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_RPCFIFO_F1_INJECT_TYPE,
18623  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_RPCFIFO_F1_ECC_TYPE,
18624  0u,
18625  NULL },
18626  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_RPCFIFO_WC_RAM_ID,
18627  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_RPCFIFO_WC_INJECT_TYPE,
18628  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_RPCFIFO_WC_ECC_TYPE,
18629  0u,
18630  NULL },
18631  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_STATS_STST0_RAM_ID,
18632  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_STATS_STST0_INJECT_TYPE,
18633  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_STATS_STST0_ECC_TYPE,
18634  0u,
18635  NULL },
18636  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_STATS_STSR0_RAM_ID,
18637  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_STATS_STSR0_INJECT_TYPE,
18638  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_STATS_STSR0_ECC_TYPE,
18639  0u,
18640  NULL },
18641  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_RINGOCC_CNTR_RAM_ID,
18642  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_RINGOCC_CNTR_INJECT_TYPE,
18643  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_RINGOCC_CNTR_ECC_TYPE,
18644  0u,
18645  NULL },
18646  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_RAM_ID,
18647  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_INJECT_TYPE,
18648  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_ECC_TYPE,
18649  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_MAX_NUM_CHECKERS,
18650  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_groupEntries },
18651  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_EDC_CTRL_0_RAM_ID,
18652  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_EDC_CTRL_0_INJECT_TYPE,
18653  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_EDC_CTRL_0_ECC_TYPE,
18654  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_EDC_CTRL_0_MAX_NUM_CHECKERS,
18655  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_EDC_CTRL_0_groupEntries },
18656  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_STATREG_SR_SPRAM_8X128_SWW_SR_RAM_ID,
18657  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_STATREG_SR_SPRAM_8X128_SWW_SR_INJECT_TYPE,
18658  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_STATREG_SR_SPRAM_8X128_SWW_SR_ECC_TYPE,
18659  0u,
18660  NULL },
18661  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_COMMON_IM_TPRAM_158X34_SWW_SR_RAM_ID,
18662  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_COMMON_IM_TPRAM_158X34_SWW_SR_INJECT_TYPE,
18663  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_COMMON_IM_TPRAM_158X34_SWW_SR_ECC_TYPE,
18664  0u,
18665  NULL },
18666  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_RAM_ID,
18667  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_INJECT_TYPE,
18668  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_ECC_TYPE,
18669  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_MAX_NUM_CHECKERS,
18670  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_groupEntries },
18671  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_RAM_ID,
18672  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_INJECT_TYPE,
18673  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_ECC_TYPE,
18674  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_MAX_NUM_CHECKERS,
18675  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_groupEntries },
18676  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_STRAM_RAM_ID,
18677  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_STRAM_INJECT_TYPE,
18678  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_STRAM_ECC_TYPE,
18679  0u,
18680  NULL },
18681  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_BUF_STRAM_RAM_ID,
18682  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_BUF_STRAM_INJECT_TYPE,
18683  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_BUF_STRAM_ECC_TYPE,
18684  0u,
18685  NULL },
18686  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_BUF_BUFRAM_RAM_ID,
18687  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_BUF_BUFRAM_INJECT_TYPE,
18688  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_BUF_BUFRAM_ECC_TYPE,
18689  0u,
18690  NULL },
18691  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_RAM_ID,
18692  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_INJECT_TYPE,
18693  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_ECC_TYPE,
18694  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_MAX_NUM_CHECKERS,
18695  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_groupEntries },
18696  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_RAM_ID,
18697  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_INJECT_TYPE,
18698  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_ECC_TYPE,
18699  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS,
18700  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries },
18701  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_RAM_ID,
18702  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_INJECT_TYPE,
18703  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_ECC_TYPE,
18704  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_MAX_NUM_CHECKERS,
18705  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_groupEntries },
18706  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_VD2GCLK_EDC_CTRL_0_RAM_ID,
18707  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_VD2GCLK_EDC_CTRL_0_INJECT_TYPE,
18708  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_VD2GCLK_EDC_CTRL_0_ECC_TYPE,
18709  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_VD2GCLK_EDC_CTRL_0_MAX_NUM_CHECKERS,
18710  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_VD2GCLK_EDC_CTRL_0_groupEntries },
18711  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_ECC0_RAM_ID,
18712  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_ECC0_INJECT_TYPE,
18713  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_ECC0_ECC_TYPE,
18714  0u,
18715  NULL },
18716  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_RAM_ID,
18717  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_INJECT_TYPE,
18718  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_ECC_TYPE,
18719  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_MAX_NUM_CHECKERS,
18720  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_groupEntries },
18721  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_RAM_ID,
18722  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_INJECT_TYPE,
18723  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_ECC_TYPE,
18724  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_MAX_NUM_CHECKERS,
18725  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_groupEntries },
18726  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_RAM_ID,
18727  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_INJECT_TYPE,
18728  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_ECC_TYPE,
18729  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_MAX_NUM_CHECKERS,
18730  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_groupEntries },
18731  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_RAM_ID,
18732  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_INJECT_TYPE,
18733  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_ECC_TYPE,
18734  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_MAX_NUM_CHECKERS,
18735  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_groupEntries },
18736  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_RAM_ID,
18737  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_INJECT_TYPE,
18738  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_ECC_TYPE,
18739  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_MAX_NUM_CHECKERS,
18740  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_groupEntries },
18741  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_RAM_ID,
18742  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_INJECT_TYPE,
18743  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_ECC_TYPE,
18744  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_MAX_NUM_CHECKERS,
18745  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_groupEntries },
18746  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_RAM_ID,
18747  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_INJECT_TYPE,
18748  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_ECC_TYPE,
18749  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_MAX_NUM_CHECKERS,
18750  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_groupEntries },
18751  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_RAM_ID,
18752  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_INJECT_TYPE,
18753  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_ECC_TYPE,
18754  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_MAX_NUM_CHECKERS,
18755  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_groupEntries },
18756  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_RAM_ID,
18757  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_INJECT_TYPE,
18758  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_ECC_TYPE,
18759  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_MAX_NUM_CHECKERS,
18760  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_groupEntries },
18761  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_RAM_ID,
18762  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_INJECT_TYPE,
18763  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_ECC_TYPE,
18764  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_MAX_NUM_CHECKERS,
18765  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_groupEntries },
18766  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_INTAGGR_EVT_EDC_CTRL_0_RAM_ID,
18767  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_INTAGGR_EVT_EDC_CTRL_0_INJECT_TYPE,
18768  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_INTAGGR_EVT_EDC_CTRL_0_ECC_TYPE,
18769  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_INTAGGR_EVT_EDC_CTRL_0_MAX_NUM_CHECKERS,
18770  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_INTAGGR_EVT_EDC_CTRL_0_groupEntries },
18771  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_INTAGGR_CEVT_EDC_CTRL_0_RAM_ID,
18772  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_INTAGGR_CEVT_EDC_CTRL_0_INJECT_TYPE,
18773  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_INTAGGR_CEVT_EDC_CTRL_0_ECC_TYPE,
18774  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_INTAGGR_CEVT_EDC_CTRL_0_MAX_NUM_CHECKERS,
18775  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_INTAGGR_CEVT_EDC_CTRL_0_groupEntries },
18776  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_INTAGGR_MEVT_IN_EDC_CTRL_0_RAM_ID,
18777  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_INTAGGR_MEVT_IN_EDC_CTRL_0_INJECT_TYPE,
18778  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_INTAGGR_MEVT_IN_EDC_CTRL_0_ECC_TYPE,
18779  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_INTAGGR_MEVT_IN_EDC_CTRL_0_MAX_NUM_CHECKERS,
18780  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_INTAGGR_MEVT_IN_EDC_CTRL_0_groupEntries },
18781  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_RAM_ID,
18782  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_INJECT_TYPE,
18783  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_ECC_TYPE,
18784  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_MAX_NUM_CHECKERS,
18785  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_groupEntries },
18786  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CFG_EDC_CTRL_0_RAM_ID,
18787  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CFG_EDC_CTRL_0_INJECT_TYPE,
18788  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CFG_EDC_CTRL_0_ECC_TYPE,
18789  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CFG_EDC_CTRL_0_MAX_NUM_CHECKERS,
18790  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CFG_EDC_CTRL_0_groupEntries },
18791  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_RAM_ID,
18792  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_INJECT_TYPE,
18793  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_ECC_TYPE,
18794  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_MAX_NUM_CHECKERS,
18795  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_groupEntries },
18796  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_RAM_ID,
18797  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_INJECT_TYPE,
18798  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_ECC_TYPE,
18799  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_MAX_NUM_CHECKERS,
18800  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_groupEntries },
18801  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_RAM_ID,
18802  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_INJECT_TYPE,
18803  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_ECC_TYPE,
18804  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_MAX_NUM_CHECKERS,
18805  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_groupEntries },
18806  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_VD2GCLK_EDC_CTRL_0_RAM_ID,
18807  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_VD2GCLK_EDC_CTRL_0_INJECT_TYPE,
18808  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_VD2GCLK_EDC_CTRL_0_ECC_TYPE,
18809  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_VD2GCLK_EDC_CTRL_0_MAX_NUM_CHECKERS,
18810  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_VD2GCLK_EDC_CTRL_0_groupEntries },
18811  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_DMSS_CFG_P2P_BRIDGE_EDC_CTRL_0_RAM_ID,
18812  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_DMSS_CFG_P2P_BRIDGE_EDC_CTRL_0_INJECT_TYPE,
18813  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_DMSS_CFG_P2P_BRIDGE_EDC_CTRL_0_ECC_TYPE,
18814  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_DMSS_CFG_P2P_BRIDGE_EDC_CTRL_0_MAX_NUM_CHECKERS,
18815  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_DMSS_CFG_P2P_BRIDGE_EDC_CTRL_0_groupEntries },
18816  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_RAM_ID,
18817  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_INJECT_TYPE,
18818  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_ECC_TYPE,
18819  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_MAX_NUM_CHECKERS,
18820  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_groupEntries },
18821  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_RAM_ID,
18822  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_INJECT_TYPE,
18823  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_ECC_TYPE,
18824  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_MAX_NUM_CHECKERS,
18825  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_groupEntries },
18826 };
18827 
18832 static const SDL_RAMIdEntry_t SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_RamIdTable[SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_NUM_RAMS] =
18833 {
18834  { SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_PKTRAM0_ECC_RAM_ID,
18835  SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_PKTRAM0_ECC_INJECT_TYPE,
18836  SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_PKTRAM0_ECC_ECC_TYPE,
18837  0u,
18838  NULL },
18839  { SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_PKTRAM1_ECC_RAM_ID,
18840  SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_PKTRAM1_ECC_INJECT_TYPE,
18841  SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_PKTRAM1_ECC_ECC_TYPE,
18842  0u,
18843  NULL },
18844  { SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_PKA_PROG_RAM_ECC_RAM_ID,
18845  SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_PKA_PROG_RAM_ECC_INJECT_TYPE,
18846  SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_PKA_PROG_RAM_ECC_ECC_TYPE,
18847  0u,
18848  NULL },
18849  { SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_ENCR_CTXRAM_BANK01_ECC_RAM_ID,
18850  SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_ENCR_CTXRAM_BANK01_ECC_INJECT_TYPE,
18851  SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_ENCR_CTXRAM_BANK01_ECC_ECC_TYPE,
18852  0u,
18853  NULL },
18854  { SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_ENCR_CTXRAM_BANK23_ECC_RAM_ID,
18855  SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_ENCR_CTXRAM_BANK23_ECC_INJECT_TYPE,
18856  SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_ENCR_CTXRAM_BANK23_ECC_ECC_TYPE,
18857  0u,
18858  NULL },
18859  { SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_ENCR_CTXRAM_BANK4_ECC_RAM_ID,
18860  SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_ENCR_CTXRAM_BANK4_ECC_INJECT_TYPE,
18861  SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_ENCR_CTXRAM_BANK4_ECC_ECC_TYPE,
18862  0u,
18863  NULL },
18864  { SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_AUTH_CTXRAM_BANK01_ECC_RAM_ID,
18865  SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_AUTH_CTXRAM_BANK01_ECC_INJECT_TYPE,
18866  SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_AUTH_CTXRAM_BANK01_ECC_ECC_TYPE,
18867  0u,
18868  NULL },
18869  { SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_AUTH_CTXRAM_BANK23_ECC_RAM_ID,
18870  SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_AUTH_CTXRAM_BANK23_ECC_INJECT_TYPE,
18871  SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_AUTH_CTXRAM_BANK23_ECC_ECC_TYPE,
18872  0u,
18873  NULL },
18874  { SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_AUTH_CTXRAM_BANK45_ECC_RAM_ID,
18875  SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_AUTH_CTXRAM_BANK45_ECC_INJECT_TYPE,
18876  SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_AUTH_CTXRAM_BANK45_ECC_ECC_TYPE,
18877  0u,
18878  NULL },
18879  { SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_AUTH_CTXRAM_BANK67_ECC_RAM_ID,
18880  SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_AUTH_CTXRAM_BANK67_ECC_INJECT_TYPE,
18881  SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_AUTH_CTXRAM_BANK67_ECC_ECC_TYPE,
18882  0u,
18883  NULL },
18884  { SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_AUTH_CTXRAM_BANK89_ECC_RAM_ID,
18885  SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_AUTH_CTXRAM_BANK89_ECC_INJECT_TYPE,
18886  SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_AUTH_CTXRAM_BANK89_ECC_ECC_TYPE,
18887  0u,
18888  NULL },
18889  { SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_AUTH_CTXRAM_BANK10_ECC_RAM_ID,
18890  SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_AUTH_CTXRAM_BANK10_ECC_INJECT_TYPE,
18891  SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_AUTH_CTXRAM_BANK10_ECC_ECC_TYPE,
18892  0u,
18893  NULL },
18894 };
18895 
18900 static const SDL_RAMIdEntry_t SDL_MCU_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_RamIdTable[SDL_MCU_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_NUM_RAMS] =
18901 {
18902  { SDL_MCU_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_ID,
18903  SDL_MCU_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_INJECT_TYPE,
18904  SDL_MCU_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_ECC_TYPE,
18905  0u,
18906  NULL },
18907  { SDL_MCU_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_RAM_ID,
18908  SDL_MCU_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_INJECT_TYPE,
18909  SDL_MCU_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_ECC_TYPE,
18910  SDL_MCU_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_MAX_NUM_CHECKERS,
18911  SDL_MCU_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_groupEntries },
18912 };
18913 
18918 static const SDL_RAMIdEntry_t SDL_WKUP_ECC_AGGR0_RamIdTable[SDL_WKUP_ECC_AGGR0_NUM_RAMS] =
18919 {
18920  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_RAM_ID,
18921  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_INJECT_TYPE,
18922  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ECC_TYPE,
18923  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
18924  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries },
18925  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_RAM_ID,
18926  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_INJECT_TYPE,
18927  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_ECC_TYPE,
18928  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
18929  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_groupEntries },
18930  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISAM67_DM_MCU_ECC_AGGR_WKUP_1_CFG_P2P_BRIDGE_ISAM67_DM_MCU_ECC_AGGR_WKUP_1_CFG_BRIDGE_SRC_BUSECC_RAM_ID,
18931  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISAM67_DM_MCU_ECC_AGGR_WKUP_1_CFG_P2P_BRIDGE_ISAM67_DM_MCU_ECC_AGGR_WKUP_1_CFG_BRIDGE_SRC_BUSECC_INJECT_TYPE,
18932  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISAM67_DM_MCU_ECC_AGGR_WKUP_1_CFG_P2P_BRIDGE_ISAM67_DM_MCU_ECC_AGGR_WKUP_1_CFG_BRIDGE_SRC_BUSECC_ECC_TYPE,
18933  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISAM67_DM_MCU_ECC_AGGR_WKUP_1_CFG_P2P_BRIDGE_ISAM67_DM_MCU_ECC_AGGR_WKUP_1_CFG_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS,
18934  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISAM67_DM_MCU_ECC_AGGR_WKUP_1_CFG_P2P_BRIDGE_ISAM67_DM_MCU_ECC_AGGR_WKUP_1_CFG_BRIDGE_SRC_BUSECC_groupEntries },
18935  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_IK3VTM_N16FFC_WKUP_0_VBUSP_P2P_BRIDGE_IK3VTM_N16FFC_WKUP_0_VBUSP_BRIDGE_BUSECC_RAM_ID,
18936  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_IK3VTM_N16FFC_WKUP_0_VBUSP_P2P_BRIDGE_IK3VTM_N16FFC_WKUP_0_VBUSP_BRIDGE_BUSECC_INJECT_TYPE,
18937  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_IK3VTM_N16FFC_WKUP_0_VBUSP_P2P_BRIDGE_IK3VTM_N16FFC_WKUP_0_VBUSP_BRIDGE_BUSECC_ECC_TYPE,
18938  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_IK3VTM_N16FFC_WKUP_0_VBUSP_P2P_BRIDGE_IK3VTM_N16FFC_WKUP_0_VBUSP_BRIDGE_BUSECC_MAX_NUM_CHECKERS,
18939  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_IK3VTM_N16FFC_WKUP_0_VBUSP_P2P_BRIDGE_IK3VTM_N16FFC_WKUP_0_VBUSP_BRIDGE_BUSECC_groupEntries },
18940  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISAM67_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM67_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_SRC_BUSECC_RAM_ID,
18941  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISAM67_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM67_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_SRC_BUSECC_INJECT_TYPE,
18942  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISAM67_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM67_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_SRC_BUSECC_ECC_TYPE,
18943  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISAM67_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM67_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS,
18944  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISAM67_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM67_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_SRC_BUSECC_groupEntries },
18945  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISAM67_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM67_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_DST_BUSECC_RAM_ID,
18946  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISAM67_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM67_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_DST_BUSECC_INJECT_TYPE,
18947  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISAM67_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM67_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_DST_BUSECC_ECC_TYPE,
18948  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISAM67_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM67_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS,
18949  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISAM67_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM67_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_DST_BUSECC_groupEntries },
18950  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_RAM_ID,
18951  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_INJECT_TYPE,
18952  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ECC_TYPE,
18953  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
18954  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries },
18955  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_RAM_ID,
18956  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_INJECT_TYPE,
18957  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ECC_TYPE,
18958  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
18959  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries },
18960  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_RAM_ID,
18961  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_INJECT_TYPE,
18962  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_ECC_TYPE,
18963  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_MAX_NUM_CHECKERS,
18964  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_groupEntries },
18965  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_RAM_ID,
18966  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_INJECT_TYPE,
18967  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_ECC_TYPE,
18968  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_MAX_NUM_CHECKERS,
18969  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_groupEntries },
18970  { SDL_WKUP_ECC_AGGR0_SAM67_DM_DM_ECC_AGGR_EDC_CTRL_RAM_ID,
18971  SDL_WKUP_ECC_AGGR0_SAM67_DM_DM_ECC_AGGR_EDC_CTRL_INJECT_TYPE,
18972  SDL_WKUP_ECC_AGGR0_SAM67_DM_DM_ECC_AGGR_EDC_CTRL_ECC_TYPE,
18973  SDL_WKUP_ECC_AGGR0_SAM67_DM_DM_ECC_AGGR_EDC_CTRL_MAX_NUM_CHECKERS,
18974  SDL_WKUP_ECC_AGGR0_SAM67_DM_DM_ECC_AGGR_EDC_CTRL_groupEntries },
18975 };
18976 
18981 static const SDL_RAMIdEntry_t SDL_DMASS0_ECC_AGGR_0_RamIdTable[SDL_DMASS0_ECC_AGGR_0_NUM_RAMS] =
18982 {
18983  { SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_PKTDMA_CFG_CONFIG_RAM_ID,
18984  SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_PKTDMA_CFG_CONFIG_INJECT_TYPE,
18985  SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_PKTDMA_CFG_CONFIG_ECC_TYPE,
18986  0u,
18987  NULL },
18988  { SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_PKTDMA_CFG_STATE_RAM_ID,
18989  SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_PKTDMA_CFG_STATE_INJECT_TYPE,
18990  SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_PKTDMA_CFG_STATE_ECC_TYPE,
18991  0u,
18992  NULL },
18993  { SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_PKTDMA_TPCFIFO_F0_RAM_ID,
18994  SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_PKTDMA_TPCFIFO_F0_INJECT_TYPE,
18995  SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_PKTDMA_TPCFIFO_F0_ECC_TYPE,
18996  0u,
18997  NULL },
18998  { SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_PKTDMA_TPCFIFO_F1_RAM_ID,
18999  SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_PKTDMA_TPCFIFO_F1_INJECT_TYPE,
19000  SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_PKTDMA_TPCFIFO_F1_ECC_TYPE,
19001  0u,
19002  NULL },
19003  { SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_PKTDMA_RPCFIFO_F0_RAM_ID,
19004  SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_PKTDMA_RPCFIFO_F0_INJECT_TYPE,
19005  SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_PKTDMA_RPCFIFO_F0_ECC_TYPE,
19006  0u,
19007  NULL },
19008  { SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_PKTDMA_RPCFIFO_F1_RAM_ID,
19009  SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_PKTDMA_RPCFIFO_F1_INJECT_TYPE,
19010  SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_PKTDMA_RPCFIFO_F1_ECC_TYPE,
19011  0u,
19012  NULL },
19013  { SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_PKTDMA_RPCFIFO_WC_RAM_ID,
19014  SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_PKTDMA_RPCFIFO_WC_INJECT_TYPE,
19015  SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_PKTDMA_RPCFIFO_WC_ECC_TYPE,
19016  0u,
19017  NULL },
19018  { SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_PKTDMA_STATS_STST0_RAM_ID,
19019  SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_PKTDMA_STATS_STST0_INJECT_TYPE,
19020  SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_PKTDMA_STATS_STST0_ECC_TYPE,
19021  0u,
19022  NULL },
19023  { SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_PKTDMA_STATS_STSR0_RAM_ID,
19024  SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_PKTDMA_STATS_STSR0_INJECT_TYPE,
19025  SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_PKTDMA_STATS_STSR0_ECC_TYPE,
19026  0u,
19027  NULL },
19028  { SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_PKTDMA_RINGOCC_CNTR_RAM_ID,
19029  SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_PKTDMA_RINGOCC_CNTR_INJECT_TYPE,
19030  SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_PKTDMA_RINGOCC_CNTR_ECC_TYPE,
19031  0u,
19032  NULL },
19033  { SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_BCDMA_CFG_CONFIG_RAM_ID,
19034  SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_BCDMA_CFG_CONFIG_INJECT_TYPE,
19035  SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_BCDMA_CFG_CONFIG_ECC_TYPE,
19036  0u,
19037  NULL },
19038  { SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_BCDMA_CFG_STATE_RAM_ID,
19039  SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_BCDMA_CFG_STATE_INJECT_TYPE,
19040  SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_BCDMA_CFG_STATE_ECC_TYPE,
19041  0u,
19042  NULL },
19043  { SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_BCDMA_PCFIFO_DFIFO_F0_RAM_ID,
19044  SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_BCDMA_PCFIFO_DFIFO_F0_INJECT_TYPE,
19045  SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_BCDMA_PCFIFO_DFIFO_F0_ECC_TYPE,
19046  0u,
19047  NULL },
19048  { SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_BCDMA_PCFIFO_DFIFO_F1_RAM_ID,
19049  SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_BCDMA_PCFIFO_DFIFO_F1_INJECT_TYPE,
19050  SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_BCDMA_PCFIFO_DFIFO_F1_ECC_TYPE,
19051  0u,
19052  NULL },
19053  { SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_BCDMA_TPCFIFO_F0_RAM_ID,
19054  SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_BCDMA_TPCFIFO_F0_INJECT_TYPE,
19055  SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_BCDMA_TPCFIFO_F0_ECC_TYPE,
19056  0u,
19057  NULL },
19058  { SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_BCDMA_TPCFIFO_F1_RAM_ID,
19059  SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_BCDMA_TPCFIFO_F1_INJECT_TYPE,
19060  SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_BCDMA_TPCFIFO_F1_ECC_TYPE,
19061  0u,
19062  NULL },
19063  { SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_BCDMA_RPCFIFO_F0_RAM_ID,
19064  SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_BCDMA_RPCFIFO_F0_INJECT_TYPE,
19065  SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_BCDMA_RPCFIFO_F0_ECC_TYPE,
19066  0u,
19067  NULL },
19068  { SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_BCDMA_RPCFIFO_F1_RAM_ID,
19069  SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_BCDMA_RPCFIFO_F1_INJECT_TYPE,
19070  SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_BCDMA_RPCFIFO_F1_ECC_TYPE,
19071  0u,
19072  NULL },
19073  { SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_BCDMA_RPCFIFO_WC_RAM_ID,
19074  SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_BCDMA_RPCFIFO_WC_INJECT_TYPE,
19075  SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_BCDMA_RPCFIFO_WC_ECC_TYPE,
19076  0u,
19077  NULL },
19078  { SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_BCDMA_STATS_STST0_RAM_ID,
19079  SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_BCDMA_STATS_STST0_INJECT_TYPE,
19080  SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_BCDMA_STATS_STST0_ECC_TYPE,
19081  0u,
19082  NULL },
19083  { SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_BCDMA_STATS_STSR0_RAM_ID,
19084  SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_BCDMA_STATS_STSR0_INJECT_TYPE,
19085  SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_BCDMA_STATS_STSR0_ECC_TYPE,
19086  0u,
19087  NULL },
19088  { SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_BCDMA_RINGOCC_CNTR_RAM_ID,
19089  SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_BCDMA_RINGOCC_CNTR_INJECT_TYPE,
19090  SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_BCDMA_RINGOCC_CNTR_ECC_TYPE,
19091  0u,
19092  NULL },
19093  { SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_INTAGGR_STATREG_SR_SPRAM_184X128_SWW_SR_RAM_ID,
19094  SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_INTAGGR_STATREG_SR_SPRAM_184X128_SWW_SR_INJECT_TYPE,
19095  SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_INTAGGR_STATREG_SR_SPRAM_184X128_SWW_SR_ECC_TYPE,
19096  0u,
19097  NULL },
19098  { SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_INTAGGR_COMMON_IM_TPRAM_1531X34_SWW_SR_RAM_ID,
19099  SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_INTAGGR_COMMON_IM_TPRAM_1531X34_SWW_SR_INJECT_TYPE,
19100  SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_INTAGGR_COMMON_IM_TPRAM_1531X34_SWW_SR_ECC_TYPE,
19101  0u,
19102  NULL },
19103  { SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_IPCSS_RINGACC_STRAM_RAM_ID,
19104  SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_IPCSS_RINGACC_STRAM_INJECT_TYPE,
19105  SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_IPCSS_RINGACC_STRAM_ECC_TYPE,
19106  0u,
19107  NULL },
19108  { SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_IPCSS_SEC_PROXY_BUF_STRAM_RAM_ID,
19109  SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_IPCSS_SEC_PROXY_BUF_STRAM_INJECT_TYPE,
19110  SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_IPCSS_SEC_PROXY_BUF_STRAM_ECC_TYPE,
19111  0u,
19112  NULL },
19113  { SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_IPCSS_SEC_PROXY_BUF_BUFRAM_RAM_ID,
19114  SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_IPCSS_SEC_PROXY_BUF_BUFRAM_INJECT_TYPE,
19115  SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_IPCSS_SEC_PROXY_BUF_BUFRAM_ECC_TYPE,
19116  0u,
19117  NULL },
19118  { SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_IPCSS_MSRAM_ECC0_RAM_ID,
19119  SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_IPCSS_MSRAM_ECC0_INJECT_TYPE,
19120  SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_IPCSS_MSRAM_ECC0_ECC_TYPE,
19121  0u,
19122  NULL },
19123 };
19124 
19129 static const SDL_RAMIdEntry_t SDL_PDMA0_SAM67_PDMA_SPI_ECCAGGR_RamIdTable[SDL_PDMA0_SAM67_PDMA_SPI_ECCAGGR_NUM_RAMS] =
19130 {
19131  { SDL_PDMA0_SAM67_PDMA_SPI_ECCAGGR_SAM67_PDMA_SPI_PDMA_CORE_TF0_F0_TPRAM_72X128_SBW_SR_RAM_ID,
19132  SDL_PDMA0_SAM67_PDMA_SPI_ECCAGGR_SAM67_PDMA_SPI_PDMA_CORE_TF0_F0_TPRAM_72X128_SBW_SR_INJECT_TYPE,
19133  SDL_PDMA0_SAM67_PDMA_SPI_ECCAGGR_SAM67_PDMA_SPI_PDMA_CORE_TF0_F0_TPRAM_72X128_SBW_SR_ECC_TYPE,
19134  0u,
19135  NULL },
19136  { SDL_PDMA0_SAM67_PDMA_SPI_ECCAGGR_SAM67_PDMA_SPI_PDMA_CORE_TF0_F1_TPRAM_72X128_SBW_SR_RAM_ID,
19137  SDL_PDMA0_SAM67_PDMA_SPI_ECCAGGR_SAM67_PDMA_SPI_PDMA_CORE_TF0_F1_TPRAM_72X128_SBW_SR_INJECT_TYPE,
19138  SDL_PDMA0_SAM67_PDMA_SPI_ECCAGGR_SAM67_PDMA_SPI_PDMA_CORE_TF0_F1_TPRAM_72X128_SBW_SR_ECC_TYPE,
19139  0u,
19140  NULL },
19141  { SDL_PDMA0_SAM67_PDMA_SPI_ECCAGGR_SAM67_PDMA_SPI_PDMA_CORE_RF0_F0_TPRAM_72X144_SBW_SR_RAM_ID,
19142  SDL_PDMA0_SAM67_PDMA_SPI_ECCAGGR_SAM67_PDMA_SPI_PDMA_CORE_RF0_F0_TPRAM_72X144_SBW_SR_INJECT_TYPE,
19143  SDL_PDMA0_SAM67_PDMA_SPI_ECCAGGR_SAM67_PDMA_SPI_PDMA_CORE_RF0_F0_TPRAM_72X144_SBW_SR_ECC_TYPE,
19144  0u,
19145  NULL },
19146  { SDL_PDMA0_SAM67_PDMA_SPI_ECCAGGR_SAM67_PDMA_SPI_PDMA_CORE_RF0_F1_TPRAM_72X144_SBW_SR_RAM_ID,
19147  SDL_PDMA0_SAM67_PDMA_SPI_ECCAGGR_SAM67_PDMA_SPI_PDMA_CORE_RF0_F1_TPRAM_72X144_SBW_SR_INJECT_TYPE,
19148  SDL_PDMA0_SAM67_PDMA_SPI_ECCAGGR_SAM67_PDMA_SPI_PDMA_CORE_RF0_F1_TPRAM_72X144_SBW_SR_ECC_TYPE,
19149  0u,
19150  NULL },
19151 };
19152 
19157 static const SDL_RAMIdEntry_t SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_RamIdTable[SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_NUM_RAMS] =
19158 {
19159  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_RAM_ID,
19160  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_INJECT_TYPE,
19161  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_ECC_TYPE,
19162  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_MAX_NUM_CHECKERS,
19163  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_groupEntries },
19164  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_RAM_ID,
19165  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_INJECT_TYPE,
19166  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_ECC_TYPE,
19167  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_MAX_NUM_CHECKERS,
19168  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_groupEntries },
19169  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_RAM_ID,
19170  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_INJECT_TYPE,
19171  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_ECC_TYPE,
19172  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_MAX_NUM_CHECKERS,
19173  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_groupEntries },
19174  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_CFG_SLV_DST_BUSECC_RAM_ID,
19175  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_CFG_SLV_DST_BUSECC_INJECT_TYPE,
19176  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_CFG_SLV_DST_BUSECC_ECC_TYPE,
19177  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_CFG_SLV_DST_BUSECC_MAX_NUM_CHECKERS,
19178  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_CFG_SLV_DST_BUSECC_groupEntries },
19179  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_PMST_SRC_BUSECC_RAM_ID,
19180  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_PMST_SRC_BUSECC_INJECT_TYPE,
19181  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_PMST_SRC_BUSECC_ECC_TYPE,
19182  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_PMST_SRC_BUSECC_MAX_NUM_CHECKERS,
19183  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_PMST_SRC_BUSECC_groupEntries },
19184  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__IECC_AGGR_CFG_DST_BUSECC_RAM_ID,
19185  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__IECC_AGGR_CFG_DST_BUSECC_INJECT_TYPE,
19186  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__IECC_AGGR_CFG_DST_BUSECC_ECC_TYPE,
19187  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__IECC_AGGR_CFG_DST_BUSECC_MAX_NUM_CHECKERS,
19188  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__IECC_AGGR_CFG_DST_BUSECC_groupEntries },
19189  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_SAM62A_MCU_PULSAR_UL_ECC_AGGR_EDC_CTRL_RAM_ID,
19190  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_SAM62A_MCU_PULSAR_UL_ECC_AGGR_EDC_CTRL_INJECT_TYPE,
19191  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_SAM62A_MCU_PULSAR_UL_ECC_AGGR_EDC_CTRL_ECC_TYPE,
19192  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_SAM62A_MCU_PULSAR_UL_ECC_AGGR_EDC_CTRL_MAX_NUM_CHECKERS,
19193  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_SAM62A_MCU_PULSAR_UL_ECC_AGGR_EDC_CTRL_groupEntries },
19194 };
19195 
19200 static const SDL_RAMIdEntry_t SDL_USB1_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_RamIdTable[SDL_USB1_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_NUM_RAMS] =
19201 {
19202  { SDL_USB1_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_USB2SS_16FFC_USB2SS_CORE_AXI2VBUSM_MST_KSBUS_AXI2VBUSM_R_RDATA_BUFFER_RAM_ID,
19203  SDL_USB1_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_USB2SS_16FFC_USB2SS_CORE_AXI2VBUSM_MST_KSBUS_AXI2VBUSM_R_RDATA_BUFFER_INJECT_TYPE,
19204  SDL_USB1_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_USB2SS_16FFC_USB2SS_CORE_AXI2VBUSM_MST_KSBUS_AXI2VBUSM_R_RDATA_BUFFER_ECC_TYPE,
19205  0u,
19206  NULL },
19207  { SDL_USB1_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_USB2SS_16FFC_USB2SS_CORE_RAMS_MEM_CTRL_RAM0_RAM_ID,
19208  SDL_USB1_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_USB2SS_16FFC_USB2SS_CORE_RAMS_MEM_CTRL_RAM0_INJECT_TYPE,
19209  SDL_USB1_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_USB2SS_16FFC_USB2SS_CORE_RAMS_MEM_CTRL_RAM0_ECC_TYPE,
19210  0u,
19211  NULL },
19212 };
19213 
19218 static const SDL_RAMIdEntry_t SDL_USB0_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_RamIdTable[SDL_USB0_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_NUM_RAMS] =
19219 {
19220  { SDL_USB0_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_USB2SS_16FFC_USB2SS_CORE_AXI2VBUSM_MST_KSBUS_AXI2VBUSM_R_RDATA_BUFFER_RAM_ID,
19221  SDL_USB0_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_USB2SS_16FFC_USB2SS_CORE_AXI2VBUSM_MST_KSBUS_AXI2VBUSM_R_RDATA_BUFFER_INJECT_TYPE,
19222  SDL_USB0_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_USB2SS_16FFC_USB2SS_CORE_AXI2VBUSM_MST_KSBUS_AXI2VBUSM_R_RDATA_BUFFER_ECC_TYPE,
19223  0u,
19224  NULL },
19225  { SDL_USB0_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_USB2SS_16FFC_USB2SS_CORE_RAMS_MEM_CTRL_RAM0_RAM_ID,
19226  SDL_USB0_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_USB2SS_16FFC_USB2SS_CORE_RAMS_MEM_CTRL_RAM0_INJECT_TYPE,
19227  SDL_USB0_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_USB2SS_16FFC_USB2SS_CORE_RAMS_MEM_CTRL_RAM0_ECC_TYPE,
19228  0u,
19229  NULL },
19230 };
19231 
19236 static const SDL_RAMIdEntry_t SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_RamIdTable[SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_NUM_RAMS] =
19237 {
19238  { SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_ECC0_RAM_ID,
19239  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_ECC0_INJECT_TYPE,
19240  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_ECC0_ECC_TYPE,
19241  0u,
19242  NULL },
19243  { SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_RAM_ID,
19244  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_INJECT_TYPE,
19245  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_ECC_TYPE,
19246  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_MAX_NUM_CHECKERS,
19247  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_groupEntries },
19248  { SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_ECC_AGGR_EDC_CTRL_RAM_ID,
19249  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_ECC_AGGR_EDC_CTRL_INJECT_TYPE,
19250  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_ECC_AGGR_EDC_CTRL_ECC_TYPE,
19251  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_ECC_AGGR_EDC_CTRL_MAX_NUM_CHECKERS,
19252  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_ECC_AGGR_EDC_CTRL_groupEntries },
19253 };
19254 
19259 static const SDL_RAMIdEntry_t SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_RXMEM_RamIdTable[SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_RXMEM_NUM_RAMS] =
19260 {
19261  { SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_RXMEM_EMMCSD4SS_SDHC_WRAP_RXMEM_RAM_ID,
19262  SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_RXMEM_EMMCSD4SS_SDHC_WRAP_RXMEM_INJECT_TYPE,
19263  SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_RXMEM_EMMCSD4SS_SDHC_WRAP_RXMEM_ECC_TYPE,
19264  0u,
19265  NULL },
19266 };
19267 
19272 static const SDL_RAMIdEntry_t SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_TXMEM_RamIdTable[SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_TXMEM_NUM_RAMS] =
19273 {
19274  { SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_TXMEM_EMMCSD4SS_SDHC_WRAP_TXMEM_RAM_ID,
19275  SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_TXMEM_EMMCSD4SS_SDHC_WRAP_TXMEM_INJECT_TYPE,
19276  SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_TXMEM_EMMCSD4SS_SDHC_WRAP_TXMEM_ECC_TYPE,
19277  0u,
19278  NULL },
19279 };
19280 
19285 static const SDL_RAMIdEntry_t SDL_WKUP_PSRAMECC_8K0_PSRAM8KX32E_ECC_AGGR_RamIdTable[SDL_WKUP_PSRAMECC_8K0_PSRAM8KX32E_ECC_AGGR_NUM_RAMS] =
19286 {
19287  { SDL_WKUP_PSRAMECC_8K0_PSRAM8KX32E_ECC_AGGR_PSRAM8KX32E_PSRAM0_ECC_RAM_ID,
19288  SDL_WKUP_PSRAMECC_8K0_PSRAM8KX32E_ECC_AGGR_PSRAM8KX32E_PSRAM0_ECC_INJECT_TYPE,
19289  SDL_WKUP_PSRAMECC_8K0_PSRAM8KX32E_ECC_AGGR_PSRAM8KX32E_PSRAM0_ECC_ECC_TYPE,
19290  0u,
19291  NULL },
19292 };
19293 
19298 static const SDL_RAMIdEntry_t SDL_PDMA1_SAM62_PDMA_UART_ECCAGGR_RamIdTable[SDL_PDMA1_SAM62_PDMA_UART_ECCAGGR_NUM_RAMS] =
19299 {
19300  { SDL_PDMA1_SAM62_PDMA_UART_ECCAGGR_SAM62_PDMA_UART_PDMA_CORE_TF0_F0_TPRAM_28X128_SBW_SR_RAM_ID,
19301  SDL_PDMA1_SAM62_PDMA_UART_ECCAGGR_SAM62_PDMA_UART_PDMA_CORE_TF0_F0_TPRAM_28X128_SBW_SR_INJECT_TYPE,
19302  SDL_PDMA1_SAM62_PDMA_UART_ECCAGGR_SAM62_PDMA_UART_PDMA_CORE_TF0_F0_TPRAM_28X128_SBW_SR_ECC_TYPE,
19303  0u,
19304  NULL },
19305  { SDL_PDMA1_SAM62_PDMA_UART_ECCAGGR_SAM62_PDMA_UART_PDMA_CORE_TF0_F1_TPRAM_28X128_SBW_SR_RAM_ID,
19306  SDL_PDMA1_SAM62_PDMA_UART_ECCAGGR_SAM62_PDMA_UART_PDMA_CORE_TF0_F1_TPRAM_28X128_SBW_SR_INJECT_TYPE,
19307  SDL_PDMA1_SAM62_PDMA_UART_ECCAGGR_SAM62_PDMA_UART_PDMA_CORE_TF0_F1_TPRAM_28X128_SBW_SR_ECC_TYPE,
19308  0u,
19309  NULL },
19310  { SDL_PDMA1_SAM62_PDMA_UART_ECCAGGR_SAM62_PDMA_UART_PDMA_CORE_RF0_F0_TPRAM_28X144_SBW_SR_RAM_ID,
19311  SDL_PDMA1_SAM62_PDMA_UART_ECCAGGR_SAM62_PDMA_UART_PDMA_CORE_RF0_F0_TPRAM_28X144_SBW_SR_INJECT_TYPE,
19312  SDL_PDMA1_SAM62_PDMA_UART_ECCAGGR_SAM62_PDMA_UART_PDMA_CORE_RF0_F0_TPRAM_28X144_SBW_SR_ECC_TYPE,
19313  0u,
19314  NULL },
19315  { SDL_PDMA1_SAM62_PDMA_UART_ECCAGGR_SAM62_PDMA_UART_PDMA_CORE_RF0_F1_TPRAM_28X144_SBW_SR_RAM_ID,
19316  SDL_PDMA1_SAM62_PDMA_UART_ECCAGGR_SAM62_PDMA_UART_PDMA_CORE_RF0_F1_TPRAM_28X144_SBW_SR_INJECT_TYPE,
19317  SDL_PDMA1_SAM62_PDMA_UART_ECCAGGR_SAM62_PDMA_UART_PDMA_CORE_RF0_F1_TPRAM_28X144_SBW_SR_ECC_TYPE,
19318  0u,
19319  NULL },
19320 };
19321 
19326 static const SDL_RAMIdEntry_t SDL_MCU_ECC_AGGR0_RamIdTable[SDL_MCU_ECC_AGGR0_NUM_RAMS] =
19327 {
19328  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_RAM_ID,
19329  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_INJECT_TYPE,
19330  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_ECC_TYPE,
19331  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_MAX_NUM_CHECKERS,
19332  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_groupEntries },
19333  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_CFG_SLV_SRC_BUSECC_RAM_ID,
19334  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_CFG_SLV_SRC_BUSECC_INJECT_TYPE,
19335  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_CFG_SLV_SRC_BUSECC_ECC_TYPE,
19336  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_CFG_SLV_SRC_BUSECC_MAX_NUM_CHECKERS,
19337  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_CFG_SLV_SRC_BUSECC_groupEntries },
19338  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_PMST_DST_BUSECC_RAM_ID,
19339  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_PMST_DST_BUSECC_INJECT_TYPE,
19340  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_PMST_DST_BUSECC_ECC_TYPE,
19341  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_PMST_DST_BUSECC_MAX_NUM_CHECKERS,
19342  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_PMST_DST_BUSECC_groupEntries },
19343  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_RAM_ID,
19344  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_INJECT_TYPE,
19345  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_ECC_TYPE,
19346  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_MAX_NUM_CHECKERS,
19347  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_groupEntries },
19348  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_RAM_ID,
19349  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_INJECT_TYPE,
19350  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_ECC_TYPE,
19351  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_MAX_NUM_CHECKERS,
19352  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_groupEntries },
19353  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__IECC_AGGR_CFG_SRC_BUSECC_RAM_ID,
19354  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__IECC_AGGR_CFG_SRC_BUSECC_INJECT_TYPE,
19355  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__IECC_AGGR_CFG_SRC_BUSECC_ECC_TYPE,
19356  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__IECC_AGGR_CFG_SRC_BUSECC_MAX_NUM_CHECKERS,
19357  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__IECC_AGGR_CFG_SRC_BUSECC_groupEntries },
19358  { SDL_MCU_ECC_AGGR0_ISAM67_DM2MCU_VBUSM_GASKET_MCU_0_EDC_CTRL_RAM_ID,
19359  SDL_MCU_ECC_AGGR0_ISAM67_DM2MCU_VBUSM_GASKET_MCU_0_EDC_CTRL_INJECT_TYPE,
19360  SDL_MCU_ECC_AGGR0_ISAM67_DM2MCU_VBUSM_GASKET_MCU_0_EDC_CTRL_ECC_TYPE,
19361  SDL_MCU_ECC_AGGR0_ISAM67_DM2MCU_VBUSM_GASKET_MCU_0_EDC_CTRL_MAX_NUM_CHECKERS,
19362  SDL_MCU_ECC_AGGR0_ISAM67_DM2MCU_VBUSM_GASKET_MCU_0_EDC_CTRL_groupEntries },
19363  { SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_WR_RAMECC_RAM_ID,
19364  SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_WR_RAMECC_INJECT_TYPE,
19365  SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_WR_RAMECC_ECC_TYPE,
19366  0u,
19367  NULL },
19368  { SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_RD_RAMECC_RAM_ID,
19369  SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_RD_RAMECC_INJECT_TYPE,
19370  SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_RD_RAMECC_ECC_TYPE,
19371  0u,
19372  NULL },
19373  { SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_RAM_ID,
19374  SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_INJECT_TYPE,
19375  SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_ECC_TYPE,
19376  SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_MAX_NUM_CHECKERS,
19377  SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_groupEntries },
19378  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_P2P_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_BRIDGE_SRC_BUSECC_RAM_ID,
19379  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_P2P_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_BRIDGE_SRC_BUSECC_INJECT_TYPE,
19380  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_P2P_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_BRIDGE_SRC_BUSECC_ECC_TYPE,
19381  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_P2P_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS,
19382  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_P2P_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_BRIDGE_SRC_BUSECC_groupEntries },
19383  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_P2P_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_BRIDGE_DST_BUSECC_RAM_ID,
19384  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_P2P_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_BRIDGE_DST_BUSECC_INJECT_TYPE,
19385  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_P2P_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_BRIDGE_DST_BUSECC_ECC_TYPE,
19386  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_P2P_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS,
19387  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_P2P_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_BRIDGE_DST_BUSECC_groupEntries },
19388  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_P2M_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_BRIDGE_SRC_BUSECC_RAM_ID,
19389  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_P2M_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_BRIDGE_SRC_BUSECC_INJECT_TYPE,
19390  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_P2M_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_BRIDGE_SRC_BUSECC_ECC_TYPE,
19391  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_P2M_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS,
19392  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_P2M_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_BRIDGE_SRC_BUSECC_groupEntries },
19393  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_P2M_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_BRIDGE_DST_BUSECC_RAM_ID,
19394  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_P2M_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_BRIDGE_DST_BUSECC_INJECT_TYPE,
19395  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_P2M_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_BRIDGE_DST_BUSECC_ECC_TYPE,
19396  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_P2M_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS,
19397  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_P2M_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_BRIDGE_DST_BUSECC_groupEntries },
19398  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_BRIDGE_SRC_BUSECC_RAM_ID,
19399  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_BRIDGE_SRC_BUSECC_INJECT_TYPE,
19400  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_BRIDGE_SRC_BUSECC_ECC_TYPE,
19401  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS,
19402  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_BRIDGE_SRC_BUSECC_groupEntries },
19403  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_BRIDGE_DST_BUSECC_RAM_ID,
19404  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_BRIDGE_DST_BUSECC_INJECT_TYPE,
19405  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_BRIDGE_DST_BUSECC_ECC_TYPE,
19406  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS,
19407  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_BRIDGE_DST_BUSECC_groupEntries },
19408  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IPULSAR_ULS_MCU_0_CPU0_CFG_SLV_P2P_BRIDGE_IPULSAR_ULS_MCU_0_CPU0_CFG_SLV_BRIDGE_BUSECC_RAM_ID,
19409  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IPULSAR_ULS_MCU_0_CPU0_CFG_SLV_P2P_BRIDGE_IPULSAR_ULS_MCU_0_CPU0_CFG_SLV_BRIDGE_BUSECC_INJECT_TYPE,
19410  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IPULSAR_ULS_MCU_0_CPU0_CFG_SLV_P2P_BRIDGE_IPULSAR_ULS_MCU_0_CPU0_CFG_SLV_BRIDGE_BUSECC_ECC_TYPE,
19411  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IPULSAR_ULS_MCU_0_CPU0_CFG_SLV_P2P_BRIDGE_IPULSAR_ULS_MCU_0_CPU0_CFG_SLV_BRIDGE_BUSECC_MAX_NUM_CHECKERS,
19412  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IPULSAR_ULS_MCU_0_CPU0_CFG_SLV_P2P_BRIDGE_IPULSAR_ULS_MCU_0_CPU0_CFG_SLV_BRIDGE_BUSECC_groupEntries },
19413  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IMSRAM32KX64E_MCU_1_CFG_P2P_BRIDGE_IMSRAM32KX64E_MCU_1_CFG_BRIDGE_BUSECC_RAM_ID,
19414  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IMSRAM32KX64E_MCU_1_CFG_P2P_BRIDGE_IMSRAM32KX64E_MCU_1_CFG_BRIDGE_BUSECC_INJECT_TYPE,
19415  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IMSRAM32KX64E_MCU_1_CFG_P2P_BRIDGE_IMSRAM32KX64E_MCU_1_CFG_BRIDGE_BUSECC_ECC_TYPE,
19416  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IMSRAM32KX64E_MCU_1_CFG_P2P_BRIDGE_IMSRAM32KX64E_MCU_1_CFG_BRIDGE_BUSECC_MAX_NUM_CHECKERS,
19417  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IMSRAM32KX64E_MCU_1_CFG_P2P_BRIDGE_IMSRAM32KX64E_MCU_1_CFG_BRIDGE_BUSECC_groupEntries },
19418  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ISAM62A_MCU_PULSAR_UL_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM62A_MCU_PULSAR_UL_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_RAM_ID,
19419  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ISAM62A_MCU_PULSAR_UL_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM62A_MCU_PULSAR_UL_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_INJECT_TYPE,
19420  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ISAM62A_MCU_PULSAR_UL_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM62A_MCU_PULSAR_UL_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_ECC_TYPE,
19421  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ISAM62A_MCU_PULSAR_UL_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM62A_MCU_PULSAR_UL_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_MAX_NUM_CHECKERS,
19422  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ISAM62A_MCU_PULSAR_UL_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM62A_MCU_PULSAR_UL_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_groupEntries },
19423  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IMSRAM32KX64E_MCU_0_CFG_P2P_BRIDGE_IMSRAM32KX64E_MCU_0_CFG_BRIDGE_BUSECC_RAM_ID,
19424  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IMSRAM32KX64E_MCU_0_CFG_P2P_BRIDGE_IMSRAM32KX64E_MCU_0_CFG_BRIDGE_BUSECC_INJECT_TYPE,
19425  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IMSRAM32KX64E_MCU_0_CFG_P2P_BRIDGE_IMSRAM32KX64E_MCU_0_CFG_BRIDGE_BUSECC_ECC_TYPE,
19426  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IMSRAM32KX64E_MCU_0_CFG_P2P_BRIDGE_IMSRAM32KX64E_MCU_0_CFG_BRIDGE_BUSECC_MAX_NUM_CHECKERS,
19427  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IMSRAM32KX64E_MCU_0_CFG_P2P_BRIDGE_IMSRAM32KX64E_MCU_0_CFG_BRIDGE_BUSECC_groupEntries },
19428  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_EXPORT_AM67_MCU_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM67_MCU_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_SRC_BUSECC_RAM_ID,
19429  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_EXPORT_AM67_MCU_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM67_MCU_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_SRC_BUSECC_INJECT_TYPE,
19430  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_EXPORT_AM67_MCU_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM67_MCU_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_SRC_BUSECC_ECC_TYPE,
19431  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_EXPORT_AM67_MCU_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM67_MCU_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS,
19432  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_EXPORT_AM67_MCU_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM67_MCU_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_SRC_BUSECC_groupEntries },
19433  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_EXPORT_AM67_MCU_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM67_MCU_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_DST_BUSECC_RAM_ID,
19434  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_EXPORT_AM67_MCU_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM67_MCU_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_DST_BUSECC_INJECT_TYPE,
19435  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_EXPORT_AM67_MCU_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM67_MCU_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_DST_BUSECC_ECC_TYPE,
19436  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_EXPORT_AM67_MCU_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM67_MCU_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS,
19437  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_EXPORT_AM67_MCU_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM67_MCU_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_DST_BUSECC_groupEntries },
19438  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ISAM67_MCU_MCU_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM67_MCU_MCU_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_RAM_ID,
19439  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ISAM67_MCU_MCU_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM67_MCU_MCU_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_INJECT_TYPE,
19440  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ISAM67_MCU_MCU_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM67_MCU_MCU_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_ECC_TYPE,
19441  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ISAM67_MCU_MCU_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM67_MCU_MCU_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_MAX_NUM_CHECKERS,
19442  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ISAM67_MCU_MCU_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM67_MCU_MCU_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_groupEntries },
19443  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_CFG_P2P_BRIDGE_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_CFG_BRIDGE_SRC_BUSECC_RAM_ID,
19444  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_CFG_P2P_BRIDGE_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_CFG_BRIDGE_SRC_BUSECC_INJECT_TYPE,
19445  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_CFG_P2P_BRIDGE_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_CFG_BRIDGE_SRC_BUSECC_ECC_TYPE,
19446  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_CFG_P2P_BRIDGE_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_CFG_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS,
19447  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_CFG_P2P_BRIDGE_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_CFG_BRIDGE_SRC_BUSECC_groupEntries },
19448  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_CFG_P2P_BRIDGE_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_CFG_BRIDGE_DST_BUSECC_RAM_ID,
19449  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_CFG_P2P_BRIDGE_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_CFG_BRIDGE_DST_BUSECC_INJECT_TYPE,
19450  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_CFG_P2P_BRIDGE_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_CFG_BRIDGE_DST_BUSECC_ECC_TYPE,
19451  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_CFG_P2P_BRIDGE_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_CFG_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS,
19452  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_CFG_P2P_BRIDGE_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_CFG_BRIDGE_DST_BUSECC_groupEntries },
19453  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IAM67_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM67_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_RAM_ID,
19454  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IAM67_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM67_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_INJECT_TYPE,
19455  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IAM67_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM67_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_ECC_TYPE,
19456  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IAM67_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM67_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS,
19457  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IAM67_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM67_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_groupEntries },
19458  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IAM67_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM67_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_RAM_ID,
19459  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IAM67_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM67_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_INJECT_TYPE,
19460  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IAM67_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM67_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_ECC_TYPE,
19461  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IAM67_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM67_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS,
19462  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IAM67_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM67_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_groupEntries },
19463  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_RAM_ID,
19464  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_INJECT_TYPE,
19465  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_ECC_TYPE,
19466  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_MAX_NUM_CHECKERS,
19467  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_groupEntries },
19468  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_RAM_ID,
19469  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_INJECT_TYPE,
19470  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_ECC_TYPE,
19471  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_MAX_NUM_CHECKERS,
19472  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_groupEntries },
19473  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_RAM_ID,
19474  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_INJECT_TYPE,
19475  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_ECC_TYPE,
19476  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_MAX_NUM_CHECKERS,
19477  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_groupEntries },
19478  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_RAM_ID,
19479  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_INJECT_TYPE,
19480  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_ECC_TYPE,
19481  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_MAX_NUM_CHECKERS,
19482  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_groupEntries },
19483  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_RAM_ID,
19484  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_INJECT_TYPE,
19485  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_ECC_TYPE,
19486  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_MAX_NUM_CHECKERS,
19487  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_groupEntries },
19488  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_RAM_ID,
19489  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_INJECT_TYPE,
19490  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_ECC_TYPE,
19491  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_MAX_NUM_CHECKERS,
19492  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_groupEntries },
19493  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_CBASS_DEFAULT_MMRS_AM67_MCU_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_RAM_ID,
19494  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_CBASS_DEFAULT_MMRS_AM67_MCU_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_INJECT_TYPE,
19495  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_CBASS_DEFAULT_MMRS_AM67_MCU_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_ECC_TYPE,
19496  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_CBASS_DEFAULT_MMRS_AM67_MCU_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
19497  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_CBASS_DEFAULT_MMRS_AM67_MCU_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_groupEntries },
19498  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_RAM_ID,
19499  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_INJECT_TYPE,
19500  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_ECC_TYPE,
19501  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_MAX_NUM_CHECKERS,
19502  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_groupEntries },
19503  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_RAM_ID,
19504  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_INJECT_TYPE,
19505  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_ECC_TYPE,
19506  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
19507  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_groupEntries },
19508  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_CBASS_DEFAULT_ERR_AM67_MCU_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_RAM_ID,
19509  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_CBASS_DEFAULT_ERR_AM67_MCU_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_INJECT_TYPE,
19510  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_CBASS_DEFAULT_ERR_AM67_MCU_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_ECC_TYPE,
19511  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_CBASS_DEFAULT_ERR_AM67_MCU_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
19512  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_CBASS_DEFAULT_ERR_AM67_MCU_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_groupEntries },
19513  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_RAM_ID,
19514  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_INJECT_TYPE,
19515  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_ECC_TYPE,
19516  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_MAX_NUM_CHECKERS,
19517  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_groupEntries },
19518  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ERR_SCR_AM67_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_RAM_ID,
19519  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ERR_SCR_AM67_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_INJECT_TYPE,
19520  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ERR_SCR_AM67_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_ECC_TYPE,
19521  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ERR_SCR_AM67_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
19522  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ERR_SCR_AM67_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_groupEntries },
19523  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_RAM_ID,
19524  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_INJECT_TYPE,
19525  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_ECC_TYPE,
19526  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_MAX_NUM_CHECKERS,
19527  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_groupEntries },
19528  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_RAM_ID,
19529  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_INJECT_TYPE,
19530  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_ECC_TYPE,
19531  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_MAX_NUM_CHECKERS,
19532  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_groupEntries },
19533  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_RAM_ID,
19534  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_INJECT_TYPE,
19535  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_ECC_TYPE,
19536  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_MAX_NUM_CHECKERS,
19537  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_groupEntries },
19538  { SDL_MCU_ECC_AGGR0_SAM67_MCU_MCU_ECC_AGGR_EDC_CTRL_RAM_ID,
19539  SDL_MCU_ECC_AGGR0_SAM67_MCU_MCU_ECC_AGGR_EDC_CTRL_INJECT_TYPE,
19540  SDL_MCU_ECC_AGGR0_SAM67_MCU_MCU_ECC_AGGR_EDC_CTRL_ECC_TYPE,
19541  SDL_MCU_ECC_AGGR0_SAM67_MCU_MCU_ECC_AGGR_EDC_CTRL_MAX_NUM_CHECKERS,
19542  SDL_MCU_ECC_AGGR0_SAM67_MCU_MCU_ECC_AGGR_EDC_CTRL_groupEntries },
19543 };
19544 
19549 static const SDL_RAMIdEntry_t SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_RamIdTable[SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_NUM_RAMS] =
19550 {
19551  { SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_ID,
19552  SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_INJECT_TYPE,
19553  SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_ECC_TYPE,
19554  0u,
19555  NULL },
19556  { SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_RAM_ID,
19557  SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_INJECT_TYPE,
19558  SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_ECC_TYPE,
19559  SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_MAX_NUM_CHECKERS,
19560  SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_groupEntries },
19561 };
19562 
19567 static const SDL_RAMIdEntry_t SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_RamIdTable[SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_NUM_RAMS] =
19568 {
19569  { SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_ID,
19570  SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_INJECT_TYPE,
19571  SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_ECC_TYPE,
19572  0u,
19573  NULL },
19574  { SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_RAM_ID,
19575  SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_INJECT_TYPE,
19576  SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_ECC_TYPE,
19577  SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_MAX_NUM_CHECKERS,
19578  SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_groupEntries },
19579 };
19580 
19585 static const SDL_RAMIdEntry_t SDL_MMCSD0_EMMC8SS_16FFC_ECC_AGGR_TXMEM_RamIdTable[SDL_MMCSD0_EMMC8SS_16FFC_ECC_AGGR_TXMEM_NUM_RAMS] =
19586 {
19587  { SDL_MMCSD0_EMMC8SS_16FFC_ECC_AGGR_TXMEM_EMMC8SS_16FFC_SDHC_WRAP_TXMEM_RAM_ID,
19588  SDL_MMCSD0_EMMC8SS_16FFC_ECC_AGGR_TXMEM_EMMC8SS_16FFC_SDHC_WRAP_TXMEM_INJECT_TYPE,
19589  SDL_MMCSD0_EMMC8SS_16FFC_ECC_AGGR_TXMEM_EMMC8SS_16FFC_SDHC_WRAP_TXMEM_ECC_TYPE,
19590  0u,
19591  NULL },
19592 };
19593 
19598 static const SDL_RAMIdEntry_t SDL_MMCSD0_EMMC8SS_16FFC_ECC_AGGR_RXMEM_RamIdTable[SDL_MMCSD0_EMMC8SS_16FFC_ECC_AGGR_RXMEM_NUM_RAMS] =
19599 {
19600  { SDL_MMCSD0_EMMC8SS_16FFC_ECC_AGGR_RXMEM_EMMC8SS_16FFC_SDHC_WRAP_RXMEM_RAM_ID,
19601  SDL_MMCSD0_EMMC8SS_16FFC_ECC_AGGR_RXMEM_EMMC8SS_16FFC_SDHC_WRAP_RXMEM_INJECT_TYPE,
19602  SDL_MMCSD0_EMMC8SS_16FFC_ECC_AGGR_RXMEM_EMMC8SS_16FFC_SDHC_WRAP_RXMEM_ECC_TYPE,
19603  0u,
19604  NULL },
19605 };
19606 
19611 static const SDL_RAMIdEntry_t SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_RamIdTable[SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_NUM_RAMS] =
19612 {
19613  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_IDATA_SPRAM_BANK0_LO_ECC_SVBUS_RAM_ID,
19614  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_IDATA_SPRAM_BANK0_LO_ECC_SVBUS_INJECT_TYPE,
19615  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_IDATA_SPRAM_BANK0_LO_ECC_SVBUS_ECC_TYPE,
19616  0u,
19617  NULL },
19618  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_IDATA_SPRAM_BANK0_HI_ECC_SVBUS_RAM_ID,
19619  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_IDATA_SPRAM_BANK0_HI_ECC_SVBUS_INJECT_TYPE,
19620  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_IDATA_SPRAM_BANK0_HI_ECC_SVBUS_ECC_TYPE,
19621  0u,
19622  NULL },
19623  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_IDATA_SPRAM_BANK1_LO_ECC_SVBUS_RAM_ID,
19624  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_IDATA_SPRAM_BANK1_LO_ECC_SVBUS_INJECT_TYPE,
19625  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_IDATA_SPRAM_BANK1_LO_ECC_SVBUS_ECC_TYPE,
19626  0u,
19627  NULL },
19628  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_IDATA_SPRAM_BANK1_HI_ECC_SVBUS_RAM_ID,
19629  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_IDATA_SPRAM_BANK1_HI_ECC_SVBUS_INJECT_TYPE,
19630  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_IDATA_SPRAM_BANK1_HI_ECC_SVBUS_ECC_TYPE,
19631  0u,
19632  NULL },
19633  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_ITAG_SPRAM_RAM0_ECC_SVBUS_RAM_ID,
19634  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_ITAG_SPRAM_RAM0_ECC_SVBUS_INJECT_TYPE,
19635  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_ITAG_SPRAM_RAM0_ECC_SVBUS_ECC_TYPE,
19636  0u,
19637  NULL },
19638  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_ITAG_SPRAM_RAM1_ECC_SVBUS_RAM_ID,
19639  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_ITAG_SPRAM_RAM1_ECC_SVBUS_INJECT_TYPE,
19640  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_ITAG_SPRAM_RAM1_ECC_SVBUS_ECC_TYPE,
19641  0u,
19642  NULL },
19643  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DDATA_SPRAM_BANK0_ECC_SVBUS_RAM_ID,
19644  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DDATA_SPRAM_BANK0_ECC_SVBUS_INJECT_TYPE,
19645  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DDATA_SPRAM_BANK0_ECC_SVBUS_ECC_TYPE,
19646  0u,
19647  NULL },
19648  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DDATA_SPRAM_BANK1_ECC_SVBUS_RAM_ID,
19649  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DDATA_SPRAM_BANK1_ECC_SVBUS_INJECT_TYPE,
19650  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DDATA_SPRAM_BANK1_ECC_SVBUS_ECC_TYPE,
19651  0u,
19652  NULL },
19653  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DDATA_SPRAM_BANK2_ECC_SVBUS_RAM_ID,
19654  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DDATA_SPRAM_BANK2_ECC_SVBUS_INJECT_TYPE,
19655  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DDATA_SPRAM_BANK2_ECC_SVBUS_ECC_TYPE,
19656  0u,
19657  NULL },
19658  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DDATA_SPRAM_BANK3_ECC_SVBUS_RAM_ID,
19659  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DDATA_SPRAM_BANK3_ECC_SVBUS_INJECT_TYPE,
19660  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DDATA_SPRAM_BANK3_ECC_SVBUS_ECC_TYPE,
19661  0u,
19662  NULL },
19663  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DDATA_SPRAM_BANK4_ECC_SVBUS_RAM_ID,
19664  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DDATA_SPRAM_BANK4_ECC_SVBUS_INJECT_TYPE,
19665  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DDATA_SPRAM_BANK4_ECC_SVBUS_ECC_TYPE,
19666  0u,
19667  NULL },
19668  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DDATA_SPRAM_BANK5_ECC_SVBUS_RAM_ID,
19669  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DDATA_SPRAM_BANK5_ECC_SVBUS_INJECT_TYPE,
19670  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DDATA_SPRAM_BANK5_ECC_SVBUS_ECC_TYPE,
19671  0u,
19672  NULL },
19673  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DDATA_SPRAM_BANK6_ECC_SVBUS_RAM_ID,
19674  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DDATA_SPRAM_BANK6_ECC_SVBUS_INJECT_TYPE,
19675  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DDATA_SPRAM_BANK6_ECC_SVBUS_ECC_TYPE,
19676  0u,
19677  NULL },
19678  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DDATA_SPRAM_BANK7_ECC_SVBUS_RAM_ID,
19679  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DDATA_SPRAM_BANK7_ECC_SVBUS_INJECT_TYPE,
19680  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DDATA_SPRAM_BANK7_ECC_SVBUS_ECC_TYPE,
19681  0u,
19682  NULL },
19683  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DTAG_SPRAM_BANK0_ECC_SVBUS_RAM_ID,
19684  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DTAG_SPRAM_BANK0_ECC_SVBUS_INJECT_TYPE,
19685  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DTAG_SPRAM_BANK0_ECC_SVBUS_ECC_TYPE,
19686  0u,
19687  NULL },
19688  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DTAG_SPRAM_BANK1_ECC_SVBUS_RAM_ID,
19689  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DTAG_SPRAM_BANK1_ECC_SVBUS_INJECT_TYPE,
19690  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DTAG_SPRAM_BANK1_ECC_SVBUS_ECC_TYPE,
19691  0u,
19692  NULL },
19693  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DTAG_SPRAM_BANK2_ECC_SVBUS_RAM_ID,
19694  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DTAG_SPRAM_BANK2_ECC_SVBUS_INJECT_TYPE,
19695  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DTAG_SPRAM_BANK2_ECC_SVBUS_ECC_TYPE,
19696  0u,
19697  NULL },
19698  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DTAG_SPRAM_BANK3_ECC_SVBUS_RAM_ID,
19699  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DTAG_SPRAM_BANK3_ECC_SVBUS_INJECT_TYPE,
19700  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DTAG_SPRAM_BANK3_ECC_SVBUS_ECC_TYPE,
19701  0u,
19702  NULL },
19703  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DDIRTY_SPRAM_ECC_SVBUS_RAM_ID,
19704  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DDIRTY_SPRAM_ECC_SVBUS_INJECT_TYPE,
19705  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DDIRTY_SPRAM_ECC_SVBUS_ECC_TYPE,
19706  0u,
19707  NULL },
19708  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_TLB_SPRAM_BANK0_ECC_SVBUS_RAM_ID,
19709  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_TLB_SPRAM_BANK0_ECC_SVBUS_INJECT_TYPE,
19710  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_TLB_SPRAM_BANK0_ECC_SVBUS_ECC_TYPE,
19711  0u,
19712  NULL },
19713  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_TLB_SPRAM_BANK1_ECC_SVBUS_RAM_ID,
19714  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_TLB_SPRAM_BANK1_ECC_SVBUS_INJECT_TYPE,
19715  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_TLB_SPRAM_BANK1_ECC_SVBUS_ECC_TYPE,
19716  0u,
19717  NULL },
19718  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_TLB_SPRAM_BANK2_ECC_SVBUS_RAM_ID,
19719  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_TLB_SPRAM_BANK2_ECC_SVBUS_INJECT_TYPE,
19720  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_TLB_SPRAM_BANK2_ECC_SVBUS_ECC_TYPE,
19721  0u,
19722  NULL },
19723  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_TLB_SPRAM_BANK3_ECC_SVBUS_RAM_ID,
19724  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_TLB_SPRAM_BANK3_ECC_SVBUS_INJECT_TYPE,
19725  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_TLB_SPRAM_BANK3_ECC_SVBUS_ECC_TYPE,
19726  0u,
19727  NULL },
19728  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY0_ECC_SVBUS_RAM_ID,
19729  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY0_ECC_SVBUS_INJECT_TYPE,
19730  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY0_ECC_SVBUS_ECC_TYPE,
19731  0u,
19732  NULL },
19733  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY1_ECC_SVBUS_RAM_ID,
19734  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY1_ECC_SVBUS_INJECT_TYPE,
19735  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY1_ECC_SVBUS_ECC_TYPE,
19736  0u,
19737  NULL },
19738  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY2_ECC_SVBUS_RAM_ID,
19739  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY2_ECC_SVBUS_INJECT_TYPE,
19740  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY2_ECC_SVBUS_ECC_TYPE,
19741  0u,
19742  NULL },
19743  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY3_ECC_SVBUS_RAM_ID,
19744  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY3_ECC_SVBUS_INJECT_TYPE,
19745  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY3_ECC_SVBUS_ECC_TYPE,
19746  0u,
19747  NULL },
19748 };
19749 
19754 static const SDL_RAMIdEntry_t SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_RamIdTable[SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_NUM_RAMS] =
19755 {
19756  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_IDATA_SPRAM_BANK0_LO_ECC_SVBUS_RAM_ID,
19757  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_IDATA_SPRAM_BANK0_LO_ECC_SVBUS_INJECT_TYPE,
19758  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_IDATA_SPRAM_BANK0_LO_ECC_SVBUS_ECC_TYPE,
19759  0u,
19760  NULL },
19761  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_IDATA_SPRAM_BANK0_HI_ECC_SVBUS_RAM_ID,
19762  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_IDATA_SPRAM_BANK0_HI_ECC_SVBUS_INJECT_TYPE,
19763  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_IDATA_SPRAM_BANK0_HI_ECC_SVBUS_ECC_TYPE,
19764  0u,
19765  NULL },
19766  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_IDATA_SPRAM_BANK1_LO_ECC_SVBUS_RAM_ID,
19767  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_IDATA_SPRAM_BANK1_LO_ECC_SVBUS_INJECT_TYPE,
19768  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_IDATA_SPRAM_BANK1_LO_ECC_SVBUS_ECC_TYPE,
19769  0u,
19770  NULL },
19771  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_IDATA_SPRAM_BANK1_HI_ECC_SVBUS_RAM_ID,
19772  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_IDATA_SPRAM_BANK1_HI_ECC_SVBUS_INJECT_TYPE,
19773  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_IDATA_SPRAM_BANK1_HI_ECC_SVBUS_ECC_TYPE,
19774  0u,
19775  NULL },
19776  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_ITAG_SPRAM_RAM0_ECC_SVBUS_RAM_ID,
19777  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_ITAG_SPRAM_RAM0_ECC_SVBUS_INJECT_TYPE,
19778  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_ITAG_SPRAM_RAM0_ECC_SVBUS_ECC_TYPE,
19779  0u,
19780  NULL },
19781  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_ITAG_SPRAM_RAM1_ECC_SVBUS_RAM_ID,
19782  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_ITAG_SPRAM_RAM1_ECC_SVBUS_INJECT_TYPE,
19783  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_ITAG_SPRAM_RAM1_ECC_SVBUS_ECC_TYPE,
19784  0u,
19785  NULL },
19786  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DDATA_SPRAM_BANK0_ECC_SVBUS_RAM_ID,
19787  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DDATA_SPRAM_BANK0_ECC_SVBUS_INJECT_TYPE,
19788  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DDATA_SPRAM_BANK0_ECC_SVBUS_ECC_TYPE,
19789  0u,
19790  NULL },
19791  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DDATA_SPRAM_BANK1_ECC_SVBUS_RAM_ID,
19792  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DDATA_SPRAM_BANK1_ECC_SVBUS_INJECT_TYPE,
19793  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DDATA_SPRAM_BANK1_ECC_SVBUS_ECC_TYPE,
19794  0u,
19795  NULL },
19796  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DDATA_SPRAM_BANK2_ECC_SVBUS_RAM_ID,
19797  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DDATA_SPRAM_BANK2_ECC_SVBUS_INJECT_TYPE,
19798  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DDATA_SPRAM_BANK2_ECC_SVBUS_ECC_TYPE,
19799  0u,
19800  NULL },
19801  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DDATA_SPRAM_BANK3_ECC_SVBUS_RAM_ID,
19802  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DDATA_SPRAM_BANK3_ECC_SVBUS_INJECT_TYPE,
19803  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DDATA_SPRAM_BANK3_ECC_SVBUS_ECC_TYPE,
19804  0u,
19805  NULL },
19806  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DDATA_SPRAM_BANK4_ECC_SVBUS_RAM_ID,
19807  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DDATA_SPRAM_BANK4_ECC_SVBUS_INJECT_TYPE,
19808  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DDATA_SPRAM_BANK4_ECC_SVBUS_ECC_TYPE,
19809  0u,
19810  NULL },
19811  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DDATA_SPRAM_BANK5_ECC_SVBUS_RAM_ID,
19812  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DDATA_SPRAM_BANK5_ECC_SVBUS_INJECT_TYPE,
19813  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DDATA_SPRAM_BANK5_ECC_SVBUS_ECC_TYPE,
19814  0u,
19815  NULL },
19816  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DDATA_SPRAM_BANK6_ECC_SVBUS_RAM_ID,
19817  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DDATA_SPRAM_BANK6_ECC_SVBUS_INJECT_TYPE,
19818  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DDATA_SPRAM_BANK6_ECC_SVBUS_ECC_TYPE,
19819  0u,
19820  NULL },
19821  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DDATA_SPRAM_BANK7_ECC_SVBUS_RAM_ID,
19822  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DDATA_SPRAM_BANK7_ECC_SVBUS_INJECT_TYPE,
19823  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DDATA_SPRAM_BANK7_ECC_SVBUS_ECC_TYPE,
19824  0u,
19825  NULL },
19826  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DTAG_SPRAM_BANK0_ECC_SVBUS_RAM_ID,
19827  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DTAG_SPRAM_BANK0_ECC_SVBUS_INJECT_TYPE,
19828  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DTAG_SPRAM_BANK0_ECC_SVBUS_ECC_TYPE,
19829  0u,
19830  NULL },
19831  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DTAG_SPRAM_BANK1_ECC_SVBUS_RAM_ID,
19832  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DTAG_SPRAM_BANK1_ECC_SVBUS_INJECT_TYPE,
19833  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DTAG_SPRAM_BANK1_ECC_SVBUS_ECC_TYPE,
19834  0u,
19835  NULL },
19836  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DTAG_SPRAM_BANK2_ECC_SVBUS_RAM_ID,
19837  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DTAG_SPRAM_BANK2_ECC_SVBUS_INJECT_TYPE,
19838  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DTAG_SPRAM_BANK2_ECC_SVBUS_ECC_TYPE,
19839  0u,
19840  NULL },
19841  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DTAG_SPRAM_BANK3_ECC_SVBUS_RAM_ID,
19842  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DTAG_SPRAM_BANK3_ECC_SVBUS_INJECT_TYPE,
19843  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DTAG_SPRAM_BANK3_ECC_SVBUS_ECC_TYPE,
19844  0u,
19845  NULL },
19846  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DDIRTY_SPRAM_ECC_SVBUS_RAM_ID,
19847  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DDIRTY_SPRAM_ECC_SVBUS_INJECT_TYPE,
19848  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DDIRTY_SPRAM_ECC_SVBUS_ECC_TYPE,
19849  0u,
19850  NULL },
19851  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_TLB_SPRAM_BANK0_ECC_SVBUS_RAM_ID,
19852  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_TLB_SPRAM_BANK0_ECC_SVBUS_INJECT_TYPE,
19853  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_TLB_SPRAM_BANK0_ECC_SVBUS_ECC_TYPE,
19854  0u,
19855  NULL },
19856  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_TLB_SPRAM_BANK1_ECC_SVBUS_RAM_ID,
19857  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_TLB_SPRAM_BANK1_ECC_SVBUS_INJECT_TYPE,
19858  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_TLB_SPRAM_BANK1_ECC_SVBUS_ECC_TYPE,
19859  0u,
19860  NULL },
19861  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_TLB_SPRAM_BANK2_ECC_SVBUS_RAM_ID,
19862  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_TLB_SPRAM_BANK2_ECC_SVBUS_INJECT_TYPE,
19863  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_TLB_SPRAM_BANK2_ECC_SVBUS_ECC_TYPE,
19864  0u,
19865  NULL },
19866  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_TLB_SPRAM_BANK3_ECC_SVBUS_RAM_ID,
19867  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_TLB_SPRAM_BANK3_ECC_SVBUS_INJECT_TYPE,
19868  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_TLB_SPRAM_BANK3_ECC_SVBUS_ECC_TYPE,
19869  0u,
19870  NULL },
19871  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY0_ECC_SVBUS_RAM_ID,
19872  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY0_ECC_SVBUS_INJECT_TYPE,
19873  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY0_ECC_SVBUS_ECC_TYPE,
19874  0u,
19875  NULL },
19876  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY1_ECC_SVBUS_RAM_ID,
19877  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY1_ECC_SVBUS_INJECT_TYPE,
19878  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY1_ECC_SVBUS_ECC_TYPE,
19879  0u,
19880  NULL },
19881  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY2_ECC_SVBUS_RAM_ID,
19882  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY2_ECC_SVBUS_INJECT_TYPE,
19883  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY2_ECC_SVBUS_ECC_TYPE,
19884  0u,
19885  NULL },
19886  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY3_ECC_SVBUS_RAM_ID,
19887  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY3_ECC_SVBUS_INJECT_TYPE,
19888  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY3_ECC_SVBUS_ECC_TYPE,
19889  0u,
19890  NULL },
19891 };
19892 
19897 static const SDL_RAMIdEntry_t SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_RamIdTable[SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_NUM_RAMS] =
19898 {
19899  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_IDATA_SPRAM_BANK0_LO_ECC_SVBUS_RAM_ID,
19900  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_IDATA_SPRAM_BANK0_LO_ECC_SVBUS_INJECT_TYPE,
19901  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_IDATA_SPRAM_BANK0_LO_ECC_SVBUS_ECC_TYPE,
19902  0u,
19903  NULL },
19904  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_IDATA_SPRAM_BANK0_HI_ECC_SVBUS_RAM_ID,
19905  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_IDATA_SPRAM_BANK0_HI_ECC_SVBUS_INJECT_TYPE,
19906  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_IDATA_SPRAM_BANK0_HI_ECC_SVBUS_ECC_TYPE,
19907  0u,
19908  NULL },
19909  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_IDATA_SPRAM_BANK1_LO_ECC_SVBUS_RAM_ID,
19910  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_IDATA_SPRAM_BANK1_LO_ECC_SVBUS_INJECT_TYPE,
19911  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_IDATA_SPRAM_BANK1_LO_ECC_SVBUS_ECC_TYPE,
19912  0u,
19913  NULL },
19914  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_IDATA_SPRAM_BANK1_HI_ECC_SVBUS_RAM_ID,
19915  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_IDATA_SPRAM_BANK1_HI_ECC_SVBUS_INJECT_TYPE,
19916  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_IDATA_SPRAM_BANK1_HI_ECC_SVBUS_ECC_TYPE,
19917  0u,
19918  NULL },
19919  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_ITAG_SPRAM_RAM0_ECC_SVBUS_RAM_ID,
19920  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_ITAG_SPRAM_RAM0_ECC_SVBUS_INJECT_TYPE,
19921  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_ITAG_SPRAM_RAM0_ECC_SVBUS_ECC_TYPE,
19922  0u,
19923  NULL },
19924  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_ITAG_SPRAM_RAM1_ECC_SVBUS_RAM_ID,
19925  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_ITAG_SPRAM_RAM1_ECC_SVBUS_INJECT_TYPE,
19926  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_ITAG_SPRAM_RAM1_ECC_SVBUS_ECC_TYPE,
19927  0u,
19928  NULL },
19929  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DDATA_SPRAM_BANK0_ECC_SVBUS_RAM_ID,
19930  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DDATA_SPRAM_BANK0_ECC_SVBUS_INJECT_TYPE,
19931  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DDATA_SPRAM_BANK0_ECC_SVBUS_ECC_TYPE,
19932  0u,
19933  NULL },
19934  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DDATA_SPRAM_BANK1_ECC_SVBUS_RAM_ID,
19935  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DDATA_SPRAM_BANK1_ECC_SVBUS_INJECT_TYPE,
19936  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DDATA_SPRAM_BANK1_ECC_SVBUS_ECC_TYPE,
19937  0u,
19938  NULL },
19939  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DDATA_SPRAM_BANK2_ECC_SVBUS_RAM_ID,
19940  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DDATA_SPRAM_BANK2_ECC_SVBUS_INJECT_TYPE,
19941  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DDATA_SPRAM_BANK2_ECC_SVBUS_ECC_TYPE,
19942  0u,
19943  NULL },
19944  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DDATA_SPRAM_BANK3_ECC_SVBUS_RAM_ID,
19945  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DDATA_SPRAM_BANK3_ECC_SVBUS_INJECT_TYPE,
19946  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DDATA_SPRAM_BANK3_ECC_SVBUS_ECC_TYPE,
19947  0u,
19948  NULL },
19949  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DDATA_SPRAM_BANK4_ECC_SVBUS_RAM_ID,
19950  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DDATA_SPRAM_BANK4_ECC_SVBUS_INJECT_TYPE,
19951  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DDATA_SPRAM_BANK4_ECC_SVBUS_ECC_TYPE,
19952  0u,
19953  NULL },
19954  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DDATA_SPRAM_BANK5_ECC_SVBUS_RAM_ID,
19955  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DDATA_SPRAM_BANK5_ECC_SVBUS_INJECT_TYPE,
19956  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DDATA_SPRAM_BANK5_ECC_SVBUS_ECC_TYPE,
19957  0u,
19958  NULL },
19959  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DDATA_SPRAM_BANK6_ECC_SVBUS_RAM_ID,
19960  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DDATA_SPRAM_BANK6_ECC_SVBUS_INJECT_TYPE,
19961  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DDATA_SPRAM_BANK6_ECC_SVBUS_ECC_TYPE,
19962  0u,
19963  NULL },
19964  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DDATA_SPRAM_BANK7_ECC_SVBUS_RAM_ID,
19965  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DDATA_SPRAM_BANK7_ECC_SVBUS_INJECT_TYPE,
19966  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DDATA_SPRAM_BANK7_ECC_SVBUS_ECC_TYPE,
19967  0u,
19968  NULL },
19969  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DTAG_SPRAM_BANK0_ECC_SVBUS_RAM_ID,
19970  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DTAG_SPRAM_BANK0_ECC_SVBUS_INJECT_TYPE,
19971  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DTAG_SPRAM_BANK0_ECC_SVBUS_ECC_TYPE,
19972  0u,
19973  NULL },
19974  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DTAG_SPRAM_BANK1_ECC_SVBUS_RAM_ID,
19975  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DTAG_SPRAM_BANK1_ECC_SVBUS_INJECT_TYPE,
19976  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DTAG_SPRAM_BANK1_ECC_SVBUS_ECC_TYPE,
19977  0u,
19978  NULL },
19979  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DTAG_SPRAM_BANK2_ECC_SVBUS_RAM_ID,
19980  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DTAG_SPRAM_BANK2_ECC_SVBUS_INJECT_TYPE,
19981  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DTAG_SPRAM_BANK2_ECC_SVBUS_ECC_TYPE,
19982  0u,
19983  NULL },
19984  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DTAG_SPRAM_BANK3_ECC_SVBUS_RAM_ID,
19985  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DTAG_SPRAM_BANK3_ECC_SVBUS_INJECT_TYPE,
19986  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DTAG_SPRAM_BANK3_ECC_SVBUS_ECC_TYPE,
19987  0u,
19988  NULL },
19989  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DDIRTY_SPRAM_ECC_SVBUS_RAM_ID,
19990  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DDIRTY_SPRAM_ECC_SVBUS_INJECT_TYPE,
19991  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DDIRTY_SPRAM_ECC_SVBUS_ECC_TYPE,
19992  0u,
19993  NULL },
19994  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_TLB_SPRAM_BANK0_ECC_SVBUS_RAM_ID,
19995  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_TLB_SPRAM_BANK0_ECC_SVBUS_INJECT_TYPE,
19996  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_TLB_SPRAM_BANK0_ECC_SVBUS_ECC_TYPE,
19997  0u,
19998  NULL },
19999  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_TLB_SPRAM_BANK1_ECC_SVBUS_RAM_ID,
20000  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_TLB_SPRAM_BANK1_ECC_SVBUS_INJECT_TYPE,
20001  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_TLB_SPRAM_BANK1_ECC_SVBUS_ECC_TYPE,
20002  0u,
20003  NULL },
20004  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_TLB_SPRAM_BANK2_ECC_SVBUS_RAM_ID,
20005  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_TLB_SPRAM_BANK2_ECC_SVBUS_INJECT_TYPE,
20006  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_TLB_SPRAM_BANK2_ECC_SVBUS_ECC_TYPE,
20007  0u,
20008  NULL },
20009  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_TLB_SPRAM_BANK3_ECC_SVBUS_RAM_ID,
20010  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_TLB_SPRAM_BANK3_ECC_SVBUS_INJECT_TYPE,
20011  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_TLB_SPRAM_BANK3_ECC_SVBUS_ECC_TYPE,
20012  0u,
20013  NULL },
20014  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY0_ECC_SVBUS_RAM_ID,
20015  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY0_ECC_SVBUS_INJECT_TYPE,
20016  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY0_ECC_SVBUS_ECC_TYPE,
20017  0u,
20018  NULL },
20019  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY1_ECC_SVBUS_RAM_ID,
20020  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY1_ECC_SVBUS_INJECT_TYPE,
20021  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY1_ECC_SVBUS_ECC_TYPE,
20022  0u,
20023  NULL },
20024  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY2_ECC_SVBUS_RAM_ID,
20025  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY2_ECC_SVBUS_INJECT_TYPE,
20026  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY2_ECC_SVBUS_ECC_TYPE,
20027  0u,
20028  NULL },
20029  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY3_ECC_SVBUS_RAM_ID,
20030  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY3_ECC_SVBUS_INJECT_TYPE,
20031  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY3_ECC_SVBUS_ECC_TYPE,
20032  0u,
20033  NULL },
20034 };
20035 
20040 static const SDL_RAMIdEntry_t SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_RamIdTable[SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_NUM_RAMS] =
20041 {
20042  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_IDATA_SPRAM_BANK0_LO_ECC_SVBUS_RAM_ID,
20043  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_IDATA_SPRAM_BANK0_LO_ECC_SVBUS_INJECT_TYPE,
20044  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_IDATA_SPRAM_BANK0_LO_ECC_SVBUS_ECC_TYPE,
20045  0u,
20046  NULL },
20047  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_IDATA_SPRAM_BANK0_HI_ECC_SVBUS_RAM_ID,
20048  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_IDATA_SPRAM_BANK0_HI_ECC_SVBUS_INJECT_TYPE,
20049  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_IDATA_SPRAM_BANK0_HI_ECC_SVBUS_ECC_TYPE,
20050  0u,
20051  NULL },
20052  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_IDATA_SPRAM_BANK1_LO_ECC_SVBUS_RAM_ID,
20053  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_IDATA_SPRAM_BANK1_LO_ECC_SVBUS_INJECT_TYPE,
20054  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_IDATA_SPRAM_BANK1_LO_ECC_SVBUS_ECC_TYPE,
20055  0u,
20056  NULL },
20057  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_IDATA_SPRAM_BANK1_HI_ECC_SVBUS_RAM_ID,
20058  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_IDATA_SPRAM_BANK1_HI_ECC_SVBUS_INJECT_TYPE,
20059  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_IDATA_SPRAM_BANK1_HI_ECC_SVBUS_ECC_TYPE,
20060  0u,
20061  NULL },
20062  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_ITAG_SPRAM_RAM0_ECC_SVBUS_RAM_ID,
20063  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_ITAG_SPRAM_RAM0_ECC_SVBUS_INJECT_TYPE,
20064  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_ITAG_SPRAM_RAM0_ECC_SVBUS_ECC_TYPE,
20065  0u,
20066  NULL },
20067  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_ITAG_SPRAM_RAM1_ECC_SVBUS_RAM_ID,
20068  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_ITAG_SPRAM_RAM1_ECC_SVBUS_INJECT_TYPE,
20069  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_ITAG_SPRAM_RAM1_ECC_SVBUS_ECC_TYPE,
20070  0u,
20071  NULL },
20072  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DDATA_SPRAM_BANK0_ECC_SVBUS_RAM_ID,
20073  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DDATA_SPRAM_BANK0_ECC_SVBUS_INJECT_TYPE,
20074  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DDATA_SPRAM_BANK0_ECC_SVBUS_ECC_TYPE,
20075  0u,
20076  NULL },
20077  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DDATA_SPRAM_BANK1_ECC_SVBUS_RAM_ID,
20078  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DDATA_SPRAM_BANK1_ECC_SVBUS_INJECT_TYPE,
20079  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DDATA_SPRAM_BANK1_ECC_SVBUS_ECC_TYPE,
20080  0u,
20081  NULL },
20082  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DDATA_SPRAM_BANK2_ECC_SVBUS_RAM_ID,
20083  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DDATA_SPRAM_BANK2_ECC_SVBUS_INJECT_TYPE,
20084  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DDATA_SPRAM_BANK2_ECC_SVBUS_ECC_TYPE,
20085  0u,
20086  NULL },
20087  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DDATA_SPRAM_BANK3_ECC_SVBUS_RAM_ID,
20088  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DDATA_SPRAM_BANK3_ECC_SVBUS_INJECT_TYPE,
20089  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DDATA_SPRAM_BANK3_ECC_SVBUS_ECC_TYPE,
20090  0u,
20091  NULL },
20092  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DDATA_SPRAM_BANK4_ECC_SVBUS_RAM_ID,
20093  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DDATA_SPRAM_BANK4_ECC_SVBUS_INJECT_TYPE,
20094  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DDATA_SPRAM_BANK4_ECC_SVBUS_ECC_TYPE,
20095  0u,
20096  NULL },
20097  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DDATA_SPRAM_BANK5_ECC_SVBUS_RAM_ID,
20098  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DDATA_SPRAM_BANK5_ECC_SVBUS_INJECT_TYPE,
20099  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DDATA_SPRAM_BANK5_ECC_SVBUS_ECC_TYPE,
20100  0u,
20101  NULL },
20102  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DDATA_SPRAM_BANK6_ECC_SVBUS_RAM_ID,
20103  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DDATA_SPRAM_BANK6_ECC_SVBUS_INJECT_TYPE,
20104  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DDATA_SPRAM_BANK6_ECC_SVBUS_ECC_TYPE,
20105  0u,
20106  NULL },
20107  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DDATA_SPRAM_BANK7_ECC_SVBUS_RAM_ID,
20108  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DDATA_SPRAM_BANK7_ECC_SVBUS_INJECT_TYPE,
20109  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DDATA_SPRAM_BANK7_ECC_SVBUS_ECC_TYPE,
20110  0u,
20111  NULL },
20112  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DTAG_SPRAM_BANK0_ECC_SVBUS_RAM_ID,
20113  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DTAG_SPRAM_BANK0_ECC_SVBUS_INJECT_TYPE,
20114  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DTAG_SPRAM_BANK0_ECC_SVBUS_ECC_TYPE,
20115  0u,
20116  NULL },
20117  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DTAG_SPRAM_BANK1_ECC_SVBUS_RAM_ID,
20118  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DTAG_SPRAM_BANK1_ECC_SVBUS_INJECT_TYPE,
20119  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DTAG_SPRAM_BANK1_ECC_SVBUS_ECC_TYPE,
20120  0u,
20121  NULL },
20122  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DTAG_SPRAM_BANK2_ECC_SVBUS_RAM_ID,
20123  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DTAG_SPRAM_BANK2_ECC_SVBUS_INJECT_TYPE,
20124  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DTAG_SPRAM_BANK2_ECC_SVBUS_ECC_TYPE,
20125  0u,
20126  NULL },
20127  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DTAG_SPRAM_BANK3_ECC_SVBUS_RAM_ID,
20128  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DTAG_SPRAM_BANK3_ECC_SVBUS_INJECT_TYPE,
20129  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DTAG_SPRAM_BANK3_ECC_SVBUS_ECC_TYPE,
20130  0u,
20131  NULL },
20132  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DDIRTY_SPRAM_ECC_SVBUS_RAM_ID,
20133  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DDIRTY_SPRAM_ECC_SVBUS_INJECT_TYPE,
20134  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DDIRTY_SPRAM_ECC_SVBUS_ECC_TYPE,
20135  0u,
20136  NULL },
20137  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_TLB_SPRAM_BANK0_ECC_SVBUS_RAM_ID,
20138  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_TLB_SPRAM_BANK0_ECC_SVBUS_INJECT_TYPE,
20139  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_TLB_SPRAM_BANK0_ECC_SVBUS_ECC_TYPE,
20140  0u,
20141  NULL },
20142  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_TLB_SPRAM_BANK1_ECC_SVBUS_RAM_ID,
20143  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_TLB_SPRAM_BANK1_ECC_SVBUS_INJECT_TYPE,
20144  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_TLB_SPRAM_BANK1_ECC_SVBUS_ECC_TYPE,
20145  0u,
20146  NULL },
20147  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_TLB_SPRAM_BANK2_ECC_SVBUS_RAM_ID,
20148  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_TLB_SPRAM_BANK2_ECC_SVBUS_INJECT_TYPE,
20149  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_TLB_SPRAM_BANK2_ECC_SVBUS_ECC_TYPE,
20150  0u,
20151  NULL },
20152  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_TLB_SPRAM_BANK3_ECC_SVBUS_RAM_ID,
20153  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_TLB_SPRAM_BANK3_ECC_SVBUS_INJECT_TYPE,
20154  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_TLB_SPRAM_BANK3_ECC_SVBUS_ECC_TYPE,
20155  0u,
20156  NULL },
20157  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY0_ECC_SVBUS_RAM_ID,
20158  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY0_ECC_SVBUS_INJECT_TYPE,
20159  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY0_ECC_SVBUS_ECC_TYPE,
20160  0u,
20161  NULL },
20162  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY1_ECC_SVBUS_RAM_ID,
20163  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY1_ECC_SVBUS_INJECT_TYPE,
20164  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY1_ECC_SVBUS_ECC_TYPE,
20165  0u,
20166  NULL },
20167  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY2_ECC_SVBUS_RAM_ID,
20168  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY2_ECC_SVBUS_INJECT_TYPE,
20169  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY2_ECC_SVBUS_ECC_TYPE,
20170  0u,
20171  NULL },
20172  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY3_ECC_SVBUS_RAM_ID,
20173  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY3_ECC_SVBUS_INJECT_TYPE,
20174  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY3_ECC_SVBUS_ECC_TYPE,
20175  0u,
20176  NULL },
20177 };
20178 
20183 static const SDL_RAMIdEntry_t SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_RamIdTable[SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_NUM_RAMS] =
20184 {
20185  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY0_ECC_SVBUS_RAM_ID,
20186  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY0_ECC_SVBUS_INJECT_TYPE,
20187  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY0_ECC_SVBUS_ECC_TYPE,
20188  0u,
20189  NULL },
20190  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY1_ECC_SVBUS_RAM_ID,
20191  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY1_ECC_SVBUS_INJECT_TYPE,
20192  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY1_ECC_SVBUS_ECC_TYPE,
20193  0u,
20194  NULL },
20195  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY2_ECC_SVBUS_RAM_ID,
20196  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY2_ECC_SVBUS_INJECT_TYPE,
20197  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY2_ECC_SVBUS_ECC_TYPE,
20198  0u,
20199  NULL },
20200  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY3_ECC_SVBUS_RAM_ID,
20201  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY3_ECC_SVBUS_INJECT_TYPE,
20202  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY3_ECC_SVBUS_ECC_TYPE,
20203  0u,
20204  NULL },
20205  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY4_ECC_SVBUS_RAM_ID,
20206  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY4_ECC_SVBUS_INJECT_TYPE,
20207  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY4_ECC_SVBUS_ECC_TYPE,
20208  0u,
20209  NULL },
20210  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY5_ECC_SVBUS_RAM_ID,
20211  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY5_ECC_SVBUS_INJECT_TYPE,
20212  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY5_ECC_SVBUS_ECC_TYPE,
20213  0u,
20214  NULL },
20215  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY6_ECC_SVBUS_RAM_ID,
20216  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY6_ECC_SVBUS_INJECT_TYPE,
20217  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY6_ECC_SVBUS_ECC_TYPE,
20218  0u,
20219  NULL },
20220  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY7_ECC_SVBUS_RAM_ID,
20221  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY7_ECC_SVBUS_INJECT_TYPE,
20222  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY7_ECC_SVBUS_ECC_TYPE,
20223  0u,
20224  NULL },
20225  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY8_ECC_SVBUS_RAM_ID,
20226  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY8_ECC_SVBUS_INJECT_TYPE,
20227  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY8_ECC_SVBUS_ECC_TYPE,
20228  0u,
20229  NULL },
20230  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY9_ECC_SVBUS_RAM_ID,
20231  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY9_ECC_SVBUS_INJECT_TYPE,
20232  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY9_ECC_SVBUS_ECC_TYPE,
20233  0u,
20234  NULL },
20235  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY10_ECC_SVBUS_RAM_ID,
20236  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY10_ECC_SVBUS_INJECT_TYPE,
20237  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY10_ECC_SVBUS_ECC_TYPE,
20238  0u,
20239  NULL },
20240  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY11_ECC_SVBUS_RAM_ID,
20241  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY11_ECC_SVBUS_INJECT_TYPE,
20242  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY11_ECC_SVBUS_ECC_TYPE,
20243  0u,
20244  NULL },
20245  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY12_ECC_SVBUS_RAM_ID,
20246  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY12_ECC_SVBUS_INJECT_TYPE,
20247  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY12_ECC_SVBUS_ECC_TYPE,
20248  0u,
20249  NULL },
20250  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY13_ECC_SVBUS_RAM_ID,
20251  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY13_ECC_SVBUS_INJECT_TYPE,
20252  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY13_ECC_SVBUS_ECC_TYPE,
20253  0u,
20254  NULL },
20255  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY14_ECC_SVBUS_RAM_ID,
20256  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY14_ECC_SVBUS_INJECT_TYPE,
20257  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY14_ECC_SVBUS_ECC_TYPE,
20258  0u,
20259  NULL },
20260  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY15_ECC_SVBUS_RAM_ID,
20261  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY15_ECC_SVBUS_INJECT_TYPE,
20262  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY15_ECC_SVBUS_ECC_TYPE,
20263  0u,
20264  NULL },
20265  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_DATARAM_SPRAM_0_ECC_SVBUS_RAM_ID,
20266  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_DATARAM_SPRAM_0_ECC_SVBUS_INJECT_TYPE,
20267  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_DATARAM_SPRAM_0_ECC_SVBUS_ECC_TYPE,
20268  0u,
20269  NULL },
20270  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_DATARAM_SPRAM_1_ECC_SVBUS_RAM_ID,
20271  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_DATARAM_SPRAM_1_ECC_SVBUS_INJECT_TYPE,
20272  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_DATARAM_SPRAM_1_ECC_SVBUS_ECC_TYPE,
20273  0u,
20274  NULL },
20275  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_DATARAM_SPRAM_2_ECC_SVBUS_RAM_ID,
20276  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_DATARAM_SPRAM_2_ECC_SVBUS_INJECT_TYPE,
20277  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_DATARAM_SPRAM_2_ECC_SVBUS_ECC_TYPE,
20278  0u,
20279  NULL },
20280  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_DATARAM_SPRAM_3_ECC_SVBUS_RAM_ID,
20281  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_DATARAM_SPRAM_3_ECC_SVBUS_INJECT_TYPE,
20282  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_DATARAM_SPRAM_3_ECC_SVBUS_ECC_TYPE,
20283  0u,
20284  NULL },
20285  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_DATARAM_SPRAM_4_ECC_SVBUS_RAM_ID,
20286  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_DATARAM_SPRAM_4_ECC_SVBUS_INJECT_TYPE,
20287  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_DATARAM_SPRAM_4_ECC_SVBUS_ECC_TYPE,
20288  0u,
20289  NULL },
20290  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_DATARAM_SPRAM_5_ECC_SVBUS_RAM_ID,
20291  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_DATARAM_SPRAM_5_ECC_SVBUS_INJECT_TYPE,
20292  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_DATARAM_SPRAM_5_ECC_SVBUS_ECC_TYPE,
20293  0u,
20294  NULL },
20295  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_DATARAM_SPRAM_6_ECC_SVBUS_RAM_ID,
20296  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_DATARAM_SPRAM_6_ECC_SVBUS_INJECT_TYPE,
20297  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_DATARAM_SPRAM_6_ECC_SVBUS_ECC_TYPE,
20298  0u,
20299  NULL },
20300  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_DATARAM_SPRAM_7_ECC_SVBUS_RAM_ID,
20301  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_DATARAM_SPRAM_7_ECC_SVBUS_INJECT_TYPE,
20302  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_DATARAM_SPRAM_7_ECC_SVBUS_ECC_TYPE,
20303  0u,
20304  NULL },
20305 };
20306 
20311 static const SDL_RAMIdEntry_t SDL_MCU_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_RamIdTable[SDL_MCU_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_NUM_RAMS] =
20312 {
20313  { SDL_MCU_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_ID,
20314  SDL_MCU_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_INJECT_TYPE,
20315  SDL_MCU_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_ECC_TYPE,
20316  0u,
20317  NULL },
20318  { SDL_MCU_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_RAM_ID,
20319  SDL_MCU_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_INJECT_TYPE,
20320  SDL_MCU_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_ECC_TYPE,
20321  SDL_MCU_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_MAX_NUM_CHECKERS,
20322  SDL_MCU_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_groupEntries },
20323 };
20324 
20325 
20326 
20331 static const SDL_EccAggrEntry_t SDL_ECC_aggrTable[SDL_ECC_MEMTYPE_MAX] =
20332 {
20333 
20334  /* Index: SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR (0u) */
20335  {
20336  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_NUM_RAMS,
20337  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_RamIdTable,
20338  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES,
20339  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_MemEntries,
20340  SDL_ESM_INST_MAIN_ESM0,
20341  SDLR_ESM0_ESM_LVL_EVENT_WKUP_R5FSS0_CORE0_ECC_CORRECTED_LEVEL_0,
20342  SDLR_ESM0_ESM_LVL_EVENT_WKUP_R5FSS0_CORE0_ECC_UNCORRECTED_LEVEL_0
20343  },
20344  /* SDL_DSS_DSI0_K3_DSS_DSI_DSI_TOP_ECC_AGGR_SYS (1) */
20345  {
20346  SDL_DSS_DSI0_K3_DSS_DSI_DSI_TOP_ECC_AGGR_SYS_NUM_RAMS,
20347  SDL_DSS_DSI0_K3_DSS_DSI_DSI_TOP_ECC_AGGR_SYS_RamIdTable,
20348  SDL_DSS_DSI0_K3_DSS_DSI_DSI_TOP_ECC_AGGR_SYS_RAM_IDS_TOTAL_ENTRIES,
20349  NULL,
20350  SDL_ESM_INST_MAIN_ESM0,
20351  SDLR_ESM0_ESM_LVL_EVENT_DSS_DSI0_DSI_0_SAFETY_ERROR_FATAL_INTR_0,
20352  SDLR_ESM0_ESM_LVL_EVENT_DSS_DSI0_ECC_INTR_UNCORR_LEVEL_SYS_0
20353  },
20354  /* SDL_PSRAMECC0_PSRAM256X32E_ECC_AGGR (2) */
20355  {
20356  SDL_PSRAMECC0_PSRAM256X32E_ECC_AGGR_NUM_RAMS,
20357  SDL_PSRAMECC0_PSRAM256X32E_ECC_AGGR_RamIdTable,
20358  SDL_PSRAMECC0_PSRAM256X32E_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES,
20359  SDL_PSRAMECC0_PSRAM256X32E_ECC_AGGR_MemEntries,
20360  SDL_ESM_INST_MAIN_ESM0,
20361  SDLR_ESM0_ESM_LVL_EVENT_PSRAMECC0_ECC_CORR_LEVEL_0,
20362  SDLR_ESM0_ESM_LVL_EVENT_PSRAMECC0_ECC_UNCORR_LEVEL_0
20363  },
20364  /* Index: SDL_PSRAMECC1_PSRAM256X32E_ECC_AGGR (3) */
20365  {
20366  SDL_PSRAMECC1_PSRAM256X32E_ECC_AGGR_NUM_RAMS,
20367  SDL_PSRAMECC1_PSRAM256X32E_ECC_AGGR_RamIdTable,
20368  SDL_PSRAMECC1_PSRAM256X32E_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES,
20369  SDL_PSRAMECC1_PSRAM256X32E_ECC_AGGR_MemEntries,
20370  SDL_ESM_INST_MAIN_ESM0,
20371  SDLR_ESM0_ESM_LVL_EVENT_PSRAMECC1_ECC_CORR_LEVEL_0,
20372  SDLR_ESM0_ESM_LVL_EVENT_PSRAMECC1_ECC_UNCORR_LEVEL_0
20373  },
20374  /* Index: SDL_MSRAM_64K0_MSRAM2KX256E_ECC_AGGR (4u) */
20375  {
20376  SDL_MSRAM_64K0_MSRAM2KX256E_ECC_AGGR_NUM_RAMS,
20377  SDL_MSRAM_64K0_MSRAM2KX256E_ECC_AGGR_RamIdTable,
20378  SDL_MSRAM_64K0_MSRAM2KX256E_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES,
20379  SDL_MSRAM_64K0_MSRAM2KX256E_ECC_AGGR_MemEntries,
20380  SDL_ESM_INST_MAIN_ESM0,
20381  SDLR_ESM0_ESM_LVL_EVENT_MSRAM_64K0_ECC_CORR_LEVEL_0,
20382  SDLR_ESM0_ESM_LVL_EVENT_MSRAM_64K0_ECC_UNCORR_LEVEL_0
20383  },
20384  /* Index: SDL_WKUP_ECC_AGGR2 (5u) */
20385  {
20386  SDL_WKUP_ECC_AGGR2_NUM_RAMS,
20387  SDL_WKUP_ECC_AGGR2_RamIdTable,
20388  SDL_WKUP_ECC_AGGR2_RAM_IDS_TOTAL_ENTRIES,
20389  NULL,
20390  SDL_ESM_INST_WKUP_ESM0,
20391  SDLR_WKUP_ESM0_ESM_LVL_EVENT_WKUP_ECC_AGGR2_CORR_LEVEL_0,
20392  SDLR_WKUP_ESM0_ESM_LVL_EVENT_WKUP_ECC_AGGR2_UNCORR_LEVEL_0
20393  },
20394 
20395  /* Index: SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR (6u) */
20396  {
20397  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_NUM_RAMS,
20398  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_RamIdTable,
20399  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES,
20400  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_MemEntries,
20401  SDL_ESM_INST_MAIN_ESM0,
20402  SDLR_ESM0_ESM_LVL_EVENT_ECC_AGGR0_CORR_LEVEL_0,
20403  SDLR_ESM0_ESM_LVL_EVENT_ECC_AGGR0_UNCORR_LEVEL_0
20404  },
20405  /* Index: SDL_DMASS1_DMSS_CSI_AM62A_ECCAGGR (7u) */
20406  {
20407  SDL_DMASS1_DMSS_CSI_AM62A_ECCAGGR_NUM_RAMS,
20408  SDL_DMASS1_DMSS_CSI_AM62A_ECCAGGR_RamIdTable,
20409  SDL_DMASS1_DMSS_CSI_AM62A_ECCAGGR_RAM_IDS_TOTAL_ENTRIES,
20410  SDL_DMASS1_DMSS_CSI_AM62A_ECCAGGR_MemEntries,
20411  SDL_ESM_INST_MAIN_ESM0,
20412  SDLR_ESM0_ESM_LVL_EVENT_DMASS1_ECC_AGGR_0_ECC_CORRECTED_ERR_LEVEL_0,
20413  SDLR_ESM0_ESM_LVL_EVENT_DMASS1_ECC_AGGR_0_ECC_UNCORRECTED_ERR_LEVEL_0
20414  },
20415  /* Index: SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR (8u) */
20416  {
20417  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_NUM_RAMS,
20418  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_RamIdTable,
20419  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES,
20420  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MemEntries,
20421  SDL_ESM_INST_WKUP_ESM0,
20422  SDLR_WKUP_ESM0_ESM_LVL_EVENT_MCU_MSRAM_256K1_ECC_CORR_LEVEL_0,
20423  SDLR_WKUP_ESM0_ESM_LVL_EVENT_MCU_MSRAM_256K1_ECC_UNCORR_LEVEL_0
20424  },
20425  /*Index: SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR (9u) */
20426  {
20427  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_NUM_RAMS,
20428  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_RamIdTable,
20429  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_RAM_IDS_TOTAL_ENTRIES,
20430  NULL,
20431  SDL_ESM_INST_MAIN_ESM0,
20432  SDLR_ESM0_ESM_LVL_EVENT_WKUP_VTM0_CORR_LEVEL_0,
20433  SDLR_ESM0_ESM_LVL_EVENT_WKUP_VTM0_UNCORR_LEVEL_0
20434  },
20435  /* Index: SDL_WKUP_ECC_AGGR1 (10u) */
20436  {
20437  SDL_WKUP_ECC_AGGR1_NUM_RAMS,
20438  SDL_WKUP_ECC_AGGR1_RamIdTable,
20439  SDL_WKUP_ECC_AGGR1_RAM_IDS_TOTAL_ENTRIES,
20440  NULL,
20441  SDL_ESM_INST_MAIN_ESM0,
20442  SDLR_ESM0_ESM_LVL_EVENT_WKUP_ECC_AGGR1_CORR_LEVEL_0,
20443  SDLR_ESM0_ESM_LVL_EVENT_WKUP_ECC_AGGR1_UNCORR_LEVEL_0
20444  },
20445 
20446  /* Index: SDL_FSS0_FSS_UL_OSPI0_OSPI_WRAP_ECC_AGGR (11) */
20447  {
20448  SDL_FSS0_FSS_UL_OSPI0_OSPI_WRAP_ECC_AGGR_NUM_RAMS,
20449  SDL_FSS0_FSS_UL_OSPI0_OSPI_WRAP_ECC_AGGR_RamIdTable,
20450  SDL_FSS0_FSS_UL_OSPI0_OSPI_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES,
20451  SDL_FSS0_FSS_UL_OSPI0_OSPI_WRAP_ECC_AGGR_MemEntries,
20452  SDL_ESM_INST_MAIN_ESM0,
20453  SDLR_ESM0_ESM_LVL_EVENT_FSS0_OSPI_0_OSPI_ECC_CORR_LVL_INTR_0,
20454  SDLR_ESM0_ESM_LVL_EVENT_FSS0_OSPI_0_OSPI_ECC_UNCORR_LVL_INTR_0
20455  },
20456  /* Index: SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR (12u) */
20457  {
20458  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_NUM_RAMS,
20459  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_RamIdTable,
20460  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES,
20461  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_MemEntries,
20462  SDL_ESM_INST_WKUP_ESM0,
20463  SDLR_WKUP_ESM0_ESM_LVL_EVENT_MCU_R5FSS0_CPU0_ECC_AGGR_0_CPU0_ECC_CORRECTED_LEVEL_0,
20464  SDLR_WKUP_ESM0_ESM_LVL_EVENT_MCU_R5FSS0_CPU0_ECC_AGGR_0_CPU0_ECC_UNCORRECTED_LEVEL_0
20465  },
20466  /* Index: SDL_GICSS0_GIC500SS_1_4_ECC_AGGR (13u) */
20467  {
20468  SDL_GICSS0_GIC500SS_1_4_ECC_AGGR_NUM_RAMS,
20469  SDL_GICSS0_GIC500SS_1_4_ECC_AGGR_RamIdTable,
20470  SDL_GICSS0_GIC500SS_1_4_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES,
20471  SDL_GICSS0_GIC500SS_1_4_ECC_AGGR_MemEntries,
20472  SDL_ESM_INST_MAIN_ESM0,
20473  SDLR_ESM0_ESM_LVL_EVENT_GICSS0_ECC_AGGR_CORR_LEVEL_0,
20474  SDLR_ESM0_ESM_LVL_EVENT_GICSS0_ECC_AGGR_UNCORR_LEVEL_0
20475  },
20476  /* Index: SDL_CPSW0_CPSW_3GUSS_AM67_CORE_ECC_CPSW_ECC_AGGR (14u) */
20477  {
20478  SDL_CPSW0_CPSW_3GUSS_AM67_CORE_ECC_CPSW_ECC_AGGR_NUM_RAMS,
20479  SDL_CPSW0_CPSW_3GUSS_AM67_CORE_ECC_CPSW_ECC_AGGR_RamIdTable,
20480  SDL_CPSW0_CPSW_3GUSS_AM67_CORE_ECC_CPSW_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES,
20481  SDL_CPSW0_CPSW_3GUSS_AM67_CORE_ECC_CPSW_ECC_AGGR_MemEntries,
20482  SDL_ESM_INST_MAIN_ESM0,
20483  SDLR_ESM0_ESM_LVL_EVENT_CPSW0_ECC_SEC_PEND_0,
20484  SDLR_ESM0_ESM_LVL_EVENT_CPSW0_ECC_DED_PEND_0
20485  },
20486  /* Index: SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR (15u) */
20487  {
20488  SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_NUM_RAMS,
20489  SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_RamIdTable,
20490  SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES,
20491  SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_MemEntries,
20492  SDL_ESM_INST_MAIN_ESM0,
20493  SDLR_ESM0_ESM_LVL_EVENT_CSI_RX_IF0_CORR_LEVEL_0,
20494  SDLR_ESM0_ESM_LVL_EVENT_CSI_RX_IF0_UNCORR_LEVEL_0
20495  },
20496  /* Index: SDL_PSCSS0_SAM67_MAIN_PSC_WRAP_ECC_AGGR (16u) */
20497  {
20498  SDL_PSCSS0_SAM67_MAIN_PSC_WRAP_ECC_AGGR_NUM_RAMS,
20499  SDL_PSCSS0_SAM67_MAIN_PSC_WRAP_ECC_AGGR_RamIdTable,
20500  SDL_PSCSS0_SAM67_MAIN_PSC_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES,
20501  SDL_PSCSS0_SAM67_MAIN_PSC_WRAP_ECC_AGGR_MemEntries,
20502  SDL_ESM_INST_MAIN_ESM0,
20503  SDLR_ESM0_ESM_LVL_EVENT_PSC0_ECC_AGGR_0_FW_CH_BR_ECC_AGGR_CORR_LEVEL_0,
20504  SDLR_ESM0_ESM_LVL_EVENT_PSC0_ECC_AGGR_0_FW_CH_BR_ECC_AGGR_UNCORR_LEVEL_0
20505  },
20506  /* Index: SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_RXMEM (17u) */
20507  {
20508  SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_RXMEM_NUM_RAMS,
20509  SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_RXMEM_RamIdTable,
20510  SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_RXMEM_RAM_IDS_TOTAL_ENTRIES,
20511  SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_RXMEM_MemEntries,
20512  SDL_ESM_INST_MAIN_ESM0,
20513  SDLR_ESM0_ESM_LVL_EVENT_MMCSD2_EMMCSDSS_RXMEM_CORR_ERR_LVL_0,
20514  SDLR_ESM0_ESM_LVL_EVENT_MMCSD2_EMMCSDSS_RXMEM_UNCORR_ERR_LVL_0
20515  },
20516  /* Index: SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_TXMEM (18u) */
20517  {
20518  SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_TXMEM_NUM_RAMS,
20519  SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_TXMEM_RamIdTable,
20520  SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_TXMEM_RAM_IDS_TOTAL_ENTRIES,
20521  SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_TXMEM_MemEntries,
20522  SDL_ESM_INST_MAIN_ESM0,
20523  SDLR_ESM0_ESM_LVL_EVENT_MMCSD2_EMMCSDSS_TXMEM_CORR_ERR_LVL_0,
20524  SDLR_ESM0_ESM_LVL_EVENT_MMCSD2_EMMCSDSS_TXMEM_UNCORR_ERR_LVL_0
20525  },
20526  /* Index: SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR (19u) */
20527  {
20528  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_NUM_RAMS,
20529  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_RamIdTable,
20530  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_RAM_IDS_TOTAL_ENTRIES,
20531  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_MemEntries,
20532  SDL_ESM_INST_MAIN_ESM0,
20533  SDLR_ESM0_ESM_LVL_EVENT_SA3_SS0_DMSS_ECCAGGR_0_DMSS_ECC_DED_PEND_0,
20534  SDLR_ESM0_ESM_LVL_EVENT_SA3_SS0_DMSS_ECCAGGR_0_DMSS_ECC_SEC_PEND_0
20535  },
20536  /* Index: SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR (20u) */
20537  {
20538  SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_NUM_RAMS,
20539  SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_RamIdTable,
20540  SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES,
20541  SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_MemEntries,
20542  SDL_ESM_INST_MAIN_ESM0,
20543  SDLR_ESM0_ESM_LVL_EVENT_SA3_SS0_SA_UL_0_SA_UL_ECC_CORR_LEVEL_0,
20544  SDLR_ESM0_ESM_LVL_EVENT_SA3_SS0_SA_UL_0_SA_UL_ECC_UNCORR_LEVEL_0
20545  },
20546  /* SDL_MCU_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR (21u) */
20547  {
20548  SDL_MCU_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_NUM_RAMS,
20549  SDL_MCU_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_RamIdTable,
20550  SDL_MCU_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES,
20551  SDL_MCU_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_MemEntries,
20552  SDL_ESM_INST_WKUP_ESM0,
20553  SDLR_WKUP_ESM0_ESM_LVL_EVENT_MCU_MCAN1_MCANSS_ECC_CORR_LVL_INT_0,
20554  SDLR_WKUP_ESM0_ESM_LVL_EVENT_MCU_MCAN1_MCANSS_ECC_UNCORR_LVL_INT_0
20555  },
20556  /* SDL_WKUP_ECC_AGGR0 (22u) */
20557  {
20558  SDL_WKUP_ECC_AGGR0_NUM_RAMS,
20559  SDL_WKUP_ECC_AGGR0_RamIdTable,
20560  SDL_WKUP_ECC_AGGR0_RAM_IDS_TOTAL_ENTRIES,
20561  NULL,
20562  SDL_ESM_INST_MAIN_ESM0,
20563  SDLR_ESM0_ESM_LVL_EVENT_WKUP_ECC_AGGR0_CORR_LEVEL_0,
20564  SDLR_ESM0_ESM_LVL_EVENT_WKUP_ECC_AGGR0_UNCORR_LEVEL_0
20565  },
20566  /* Index: SDL_DMASS0_ECC_AGGR_0 (23u) */
20567  {
20568  SDL_DMASS0_ECC_AGGR_0_NUM_RAMS,
20569  SDL_DMASS0_ECC_AGGR_0_RamIdTable,
20570  SDL_DMASS0_ECC_AGGR_0_RAM_IDS_TOTAL_ENTRIES,
20571  SDL_DMASS0_ECC_AGGR_0_MemEntries,
20572  SDL_ESM_INST_MAIN_ESM0,
20573  SDLR_ESM0_ESM_LVL_EVENT_DMASS0_ECC_AGGR_0_ECC_CORRECTED_ERR_LEVEL_0,
20574  SDLR_ESM0_ESM_LVL_EVENT_DMASS0_ECC_AGGR_0_ECC_UNCORRECTED_ERR_LEVEL_0
20575  },
20576  /* SDL_PDMA0_SAM67_PDMA_SPI_ECCAGGR (24u) */
20577  {
20578  SDL_PDMA0_SAM67_PDMA_SPI_ECCAGGR_NUM_RAMS,
20579  SDL_PDMA0_SAM67_PDMA_SPI_ECCAGGR_RamIdTable,
20580  SDL_PDMA0_SAM67_PDMA_SPI_ECCAGGR_RAM_IDS_TOTAL_ENTRIES,
20581  SDL_PDMA0_SAM67_PDMA_SPI_ECCAGGR_MemEntries,
20582  SDL_ESM_INST_MAIN_ESM0,
20583  SDLR_ESM0_ESM_LVL_EVENT_PDMA0_ECC_SEC_PEND_0,
20584  SDLR_ESM0_ESM_LVL_EVENT_PDMA0_ECC_DED_PEND_0
20585  },
20586 
20587  /* SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR (25u) */
20588  {
20589  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_NUM_RAMS,
20590  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_RamIdTable,
20591  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES,
20592  NULL,
20593  SDL_ESM_INST_WKUP_ESM0,
20594  SDLR_WKUP_ESM0_ESM_LVL_EVENT_MCU_ECC_AGGR1_CORR_LEVEL_0,
20595  SDLR_WKUP_ESM0_ESM_LVL_EVENT_MCU_ECC_AGGR1_UNCORR_LEVEL_0
20596  },
20597  /* SDL_USB1_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR (26u) */
20598  {
20599  SDL_USB1_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_NUM_RAMS,
20600  SDL_USB1_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_RamIdTable,
20601  SDL_USB1_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES,
20602  SDL_USB1_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_MemEntries,
20603  SDL_ESM_INST_MAIN_ESM0,
20604  SDLR_ESM0_ESM_LVL_EVENT_USB1_A_ECC_AGGR_CORRECTED_ERR_LEVEL_0,
20605  SDLR_ESM0_ESM_LVL_EVENT_USB1_A_ECC_AGGR_UNCORRECTED_ERR_LEVEL_0
20606  },
20607  /* SDL_USB0_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR (27u) */
20608  {
20609  SDL_USB0_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_NUM_RAMS,
20610  SDL_USB0_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_RamIdTable,
20611  SDL_USB0_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES,
20612  SDL_USB0_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_MemEntries,
20613  SDL_ESM_INST_MAIN_ESM0,
20614  SDLR_ESM0_ESM_LVL_EVENT_USB0_A_ECC_AGGR_CORRECTED_ERR_LEVEL_0,
20615  SDLR_ESM0_ESM_LVL_EVENT_USB0_A_ECC_AGGR_UNCORRECTED_ERR_LEVEL_0
20616  },
20617  /* Index: SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR (28u) */
20618  {
20619  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_NUM_RAMS,
20620  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_RamIdTable,
20621  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES,
20622  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MemEntries,
20623  SDL_ESM_INST_WKUP_ESM0,
20624  SDLR_WKUP_ESM0_ESM_LVL_EVENT_MCU_MSRAM_256K0_ECC_CORR_LEVEL_0,
20625  SDLR_WKUP_ESM0_ESM_LVL_EVENT_MCU_MSRAM_256K0_ECC_UNCORR_LEVEL_0
20626  },
20627  /* Index: SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_RXMEM (29u) */
20628  {
20629  SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_RXMEM_NUM_RAMS,
20630  SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_RXMEM_RamIdTable,
20631  SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_RXMEM_RAM_IDS_TOTAL_ENTRIES,
20632  SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_RXMEM_MemEntries,
20633  SDL_ESM_INST_MAIN_ESM0,
20634  SDLR_ESM0_ESM_LVL_EVENT_MMCSD1_EMMCSDSS_RXMEM_CORR_ERR_LVL_0,
20635  SDLR_ESM0_ESM_LVL_EVENT_MMCSD1_EMMCSDSS_RXMEM_UNCORR_ERR_LVL_0
20636  },
20637  /* Index: SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_TXMEM (30u) */
20638  {
20639  SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_TXMEM_NUM_RAMS,
20640  SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_TXMEM_RamIdTable,
20641  SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_TXMEM_RAM_IDS_TOTAL_ENTRIES,
20642  SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_TXMEM_MemEntries,
20643  SDL_ESM_INST_MAIN_ESM0,
20644  SDLR_ESM0_ESM_LVL_EVENT_MMCSD1_EMMCSDSS_TXMEM_CORR_ERR_LVL_0,
20645  SDLR_ESM0_ESM_LVL_EVENT_MMCSD1_EMMCSDSS_TXMEM_UNCORR_ERR_LVL_0
20646  },
20647  /* SDL_WKUP_PSRAMECC_8K0_PSRAM8KX32E_ECC_AGGR (31u) */
20648  {
20649  SDL_WKUP_PSRAMECC_8K0_PSRAM8KX32E_ECC_AGGR_NUM_RAMS,
20650  SDL_WKUP_PSRAMECC_8K0_PSRAM8KX32E_ECC_AGGR_RamIdTable,
20651  SDL_WKUP_PSRAMECC_8K0_PSRAM8KX32E_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES,
20652  SDL_WKUP_PSRAMECC_8K0_PSRAM8KX32E_ECC_AGGR_MemEntries,
20653  SDL_ESM_INST_MAIN_ESM0,
20654  SDLR_ESM0_ESM_LVL_EVENT_WKUP_PSRAMECC_8K0_ECC_CORR_LEVEL_0,
20655  SDLR_ESM0_ESM_LVL_EVENT_WKUP_PSRAMECC_8K0_ECC_UNCORR_LEVEL_0
20656  },
20657  /* SDL_PDMA1_SAM62_PDMA_UART_ECCAGGR (32u) */
20658  {
20659  SDL_PDMA1_SAM62_PDMA_UART_ECCAGGR_NUM_RAMS,
20660  SDL_PDMA1_SAM62_PDMA_UART_ECCAGGR_RamIdTable,
20661  SDL_PDMA1_SAM62_PDMA_UART_ECCAGGR_RAM_IDS_TOTAL_ENTRIES,
20662  SDL_PDMA1_SAM62_PDMA_UART_ECCAGGR_MemEntries,
20663  SDL_ESM_INST_MAIN_ESM0,
20664  SDLR_ESM0_ESM_LVL_EVENT_PDMA1_ECC_SEC_PEND_0,
20665  SDLR_ESM0_ESM_LVL_EVENT_PDMA1_ECC_DED_PEND_0
20666  },
20667  /* Index: SDL_MCU_ECC_AGGR0 (33u) */
20668  {
20669  SDL_MCU_ECC_AGGR0_NUM_RAMS,
20670  SDL_MCU_ECC_AGGR0_RamIdTable,
20671  SDL_MCU_ECC_AGGR0_RAM_IDS_TOTAL_ENTRIES,
20672  SDL_MCU_ECC_AGGR0_MemEntries,
20673  SDL_ESM_INST_WKUP_ESM0,
20674  SDLR_WKUP_ESM0_ESM_LVL_EVENT_MCU_ECC_AGGR0_CORR_LEVEL_0,
20675  SDLR_WKUP_ESM0_ESM_LVL_EVENT_MCU_ECC_AGGR0_UNCORR_LEVEL_0
20676  },
20677  /* Index: SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR (34u) */
20678  {
20679  SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_NUM_RAMS,
20680  SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_RamIdTable,
20681  SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES,
20682  SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_MemEntries,
20683  SDL_ESM_INST_MAIN_ESM0,
20684  SDLR_WKUP_ESM0_ESM_LVL_EVENT_MCU_MCAN1_MCANSS_ECC_CORR_LVL_INT_0,
20685  SDLR_WKUP_ESM0_ESM_LVL_EVENT_MCU_MCAN1_MCANSS_ECC_UNCORR_LVL_INT_0
20686  },
20687  /* Index: SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR (35u) */
20688  {
20689  SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_NUM_RAMS,
20690  SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_RamIdTable,
20691  SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES,
20692  SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_MemEntries,
20693  SDL_ESM_INST_MAIN_ESM0,
20694  SDLR_ESM0_ESM_LVL_EVENT_MCAN0_MCANSS_ECC_CORR_LVL_INT_0,
20695  SDLR_ESM0_ESM_LVL_EVENT_MCAN0_MCANSS_ECC_UNCORR_LVL_INT_0
20696  },
20697 
20698  /* Index: SDL_MMCSD0_EMMC8SS_16FFC_ECC_AGGR_TXMEM (36u) */
20699  {
20700  SDL_MMCSD0_EMMC8SS_16FFC_ECC_AGGR_TXMEM_NUM_RAMS,
20701  SDL_MMCSD0_EMMC8SS_16FFC_ECC_AGGR_TXMEM_RamIdTable,
20702  SDL_MMCSD0_EMMC8SS_16FFC_ECC_AGGR_TXMEM_RAM_IDS_TOTAL_ENTRIES,
20703  SDL_MMCSD0_EMMC8SS_16FFC_ECC_AGGR_TXMEM_MemEntries,
20704  SDL_ESM_INST_MAIN_ESM0,
20705  SDLR_ESM0_ESM_LVL_EVENT_MMCSD0_EMMCSS_TXMEM_CORR_ERR_LVL_0,
20706  SDLR_ESM0_ESM_LVL_EVENT_MMCSD0_EMMCSS_TXMEM_UNCORR_ERR_LVL_0
20707  },
20708 
20709  /* Index: SDL_MMCSD0_EMMC8SS_16FFC_ECC_AGGR_RXMEM (37u) */
20710  {
20711  SDL_MMCSD0_EMMC8SS_16FFC_ECC_AGGR_RXMEM_NUM_RAMS,
20712  SDL_MMCSD0_EMMC8SS_16FFC_ECC_AGGR_RXMEM_RamIdTable,
20713  SDL_MMCSD0_EMMC8SS_16FFC_ECC_AGGR_RXMEM_RAM_IDS_TOTAL_ENTRIES,
20714  SDL_MMCSD0_EMMC8SS_16FFC_ECC_AGGR_RXMEM_MemEntries,
20715  SDL_ESM_INST_MAIN_ESM0,
20716  SDLR_ESM0_ESM_LVL_EVENT_MMCSD0_EMMCSS_RXMEM_CORR_ERR_LVL_0,
20717  SDLR_ESM0_ESM_LVL_EVENT_MMCSD0_EMMCSS_RXMEM_UNCORR_ERR_LVL_0
20718  },
20719  /* SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0 (38u) */
20720  {
20721  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_NUM_RAMS,
20722  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_RamIdTable,
20723  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_RAM_IDS_TOTAL_ENTRIES,
20724  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_MemEntries,
20725  SDL_ESM_INST_MAIN_ESM0,
20726  SDLR_ESM0_ESM_LVL_EVENT_A53SS0_ECC_ECCAGGR0_CORRECTED_ERR_LEVEL_0,
20727  SDLR_ESM0_ESM_LVL_EVENT_A53SS0_ECC_ECCAGGR0_UNCORRECTED_ERR_LEVEL_0
20728  },
20729  /* SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1 (39u) */
20730  {
20731  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_NUM_RAMS,
20732  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_RamIdTable,
20733  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_RAM_IDS_TOTAL_ENTRIES,
20734  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_MemEntries,
20735  SDL_ESM_INST_MAIN_ESM0,
20736  SDLR_ESM0_ESM_LVL_EVENT_A53SS0_ECC_ECCAGGR1_CORRECTED_ERR_LEVEL_0,
20737  SDLR_ESM0_ESM_LVL_EVENT_A53SS0_ECC_ECCAGGR1_UNCORRECTED_ERR_LEVEL_0
20738  },
20739  /* SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2 (40u) */
20740  {
20741  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_NUM_RAMS,
20742  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_RamIdTable,
20743  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_RAM_IDS_TOTAL_ENTRIES,
20744  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_MemEntries,
20745  SDL_ESM_INST_MAIN_ESM0,
20746  SDLR_ESM0_ESM_LVL_EVENT_A53SS0_ECC_ECCAGGR2_CORRECTED_ERR_LEVEL_0,
20747  SDLR_ESM0_ESM_LVL_EVENT_A53SS0_ECC_ECCAGGR2_UNCORRECTED_ERR_LEVEL_0
20748  },
20749  /* SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3 (41u) */
20750  {
20751  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_NUM_RAMS,
20752  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_RamIdTable,
20753  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_RAM_IDS_TOTAL_ENTRIES,
20754  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_MemEntries,
20755  SDL_ESM_INST_MAIN_ESM0,
20756  SDLR_ESM0_ESM_LVL_EVENT_A53SS0_ECC_ECCAGGR3_CORRECTED_ERR_LEVEL_0,
20757  SDLR_ESM0_ESM_LVL_EVENT_A53SS0_ECC_ECCAGGR3_CORRECTED_ERR_LEVEL_0
20758  },
20759  /* SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC (42u) */
20760  {
20761  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_NUM_RAMS,
20762  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_RamIdTable,
20763  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_RAM_IDS_TOTAL_ENTRIES,
20764  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_MemEntries,
20765  SDL_ESM_INST_MAIN_ESM0,
20766  SDLR_ESM0_ESM_LVL_EVENT_A53SS0_ECC_ECCAGGR_COREPAC_CORRECTED_ERR_LEVEL_0,
20767  SDLR_ESM0_ESM_LVL_EVENT_A53SS0_ECC_ECCAGGR_COREPAC_UNCORRECTED_ERR_LEVEL_0
20768  },
20769  /* SDL_MCU_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR (43u) */
20770  {
20771  SDL_MCU_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_NUM_RAMS,
20772  SDL_MCU_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_RamIdTable,
20773  SDL_MCU_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES,
20774  SDL_MCU_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_MemEntries,
20775  SDL_ESM_INST_WKUP_ESM0,
20776  SDLR_WKUP_ESM0_ESM_LVL_EVENT_MCU_MCAN0_MCANSS_ECC_CORR_LVL_INT_0,
20777  SDLR_WKUP_ESM0_ESM_LVL_EVENT_MCU_MCAN0_MCANSS_ECC_UNCORR_LVL_INT_0
20778  },
20779 };
20780 
20781 #endif /* INCLUDE_SDL_ECC_SOC_H_ */
SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
#define SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:58
SDL_MMCSD0_EMMC8SS_16FFC_ECC_AGGR_RXMEM_RamIdTable
static const SDL_RAMIdEntry_t SDL_MMCSD0_EMMC8SS_16FFC_ECC_AGGR_RXMEM_RamIdTable[SDL_MMCSD0_EMMC8SS_16FFC_ECC_AGGR_RXMEM_NUM_RAMS]
Definition: sdl_ecc_soc.h:19598
SDL_PSCSS0_SAM67_MAIN_PSC_WRAP_ECC_AGGR_RamIdTable
static const SDL_RAMIdEntry_t SDL_PSCSS0_SAM67_MAIN_PSC_WRAP_ECC_AGGR_RamIdTable[SDL_PSCSS0_SAM67_MAIN_PSC_WRAP_ECC_AGGR_NUM_RAMS]
Definition: sdl_ecc_soc.h:18550
SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ISAM62A_MCU_PULSAR_UL_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM62A_MCU_PULSAR_UL_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ISAM62A_MCU_PULSAR_UL_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM62A_MCU_PULSAR_UL_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_groupEntries[SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ISAM62A_MCU_PULSAR_UL_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM62A_MCU_PULSAR_UL_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:13285
SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_CFG_P2P_BRIDGE_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_CFG_BRIDGE_DST_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_CFG_P2P_BRIDGE_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_CFG_BRIDGE_DST_BUSECC_groupEntries[SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_CFG_P2P_BRIDGE_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_CFG_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:13513
SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_MemEntries
static const SDL_MemConfig_t SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_MemEntries[SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
Definition: sdl_ecc_soc.h:5862
SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_groupEntries[SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:14564
SDL_WKUP_PSRAMECC_8K0_PSRAM8KX32E_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
#define SDL_WKUP_PSRAMECC_8K0_PSRAM8KX32E_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:89
SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
#define SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:83
SDL_ESM_INST_MAIN_ESM0
@ SDL_ESM_INST_MAIN_ESM0
Definition: sdl_esm_soc.h:65
SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_RamIdTable
static const SDL_RAMIdEntry_t SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_RamIdTable[SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_NUM_RAMS]
Definition: sdl_ecc_soc.h:20040
SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_RamIdTable
static const SDL_RAMIdEntry_t SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_RamIdTable[SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_NUM_RAMS]
Definition: sdl_ecc_soc.h:17722
SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISAM67_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM67_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_DST_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISAM67_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM67_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_DST_BUSECC_groupEntries[SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISAM67_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM67_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:10806
SDL_DMASS1_DMSS_CSI_AM62A_ECCAGGR_MemEntries
static const SDL_MemConfig_t SDL_DMASS1_DMSS_CSI_AM62A_ECCAGGR_MemEntries[SDL_DMASS1_DMSS_CSI_AM62A_ECCAGGR_RAM_IDS_TOTAL_ENTRIES]
Definition: sdl_ecc_soc.h:4712
SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_RXMEM_RAM_IDS_TOTAL_ENTRIES
#define SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_RXMEM_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:75
SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_groupEntries[SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:11123
SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_groupEntries[SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:12631
SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
#define SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:92
SDL_WKUP_ECC_AGGR2_SAM67_WKUP_SAFE_ECC_AGGR_EDC_CTRL_groupEntries
static const SDL_GrpChkConfig_t SDL_WKUP_ECC_AGGR2_SAM67_WKUP_SAFE_ECC_AGGR_EDC_CTRL_groupEntries[SDL_WKUP_ECC_AGGR2_SAM67_WKUP_SAFE_ECC_AGGR_EDC_CTRL_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:4216
SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_groupEntries[SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:6559
SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_INTAGGR_EVT_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_INTAGGR_EVT_EDC_CTRL_0_groupEntries[SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_INTAGGR_EVT_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:9067
SDL_ECC_aggrTable
static const SDL_EccAggrEntry_t SDL_ECC_aggrTable[SDL_ECC_MEMTYPE_MAX]
Definition: sdl_ecc_soc.h:20331
SDL_PDMA0_SAM67_PDMA_SPI_ECCAGGR_RAM_IDS_TOTAL_ENTRIES
#define SDL_PDMA0_SAM67_PDMA_SPI_ECCAGGR_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:82
SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_TXMEM_RamIdTable
static const SDL_RAMIdEntry_t SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_TXMEM_RamIdTable[SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_TXMEM_NUM_RAMS]
Definition: sdl_ecc_soc.h:19272
SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_P2M_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_BRIDGE_DST_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_P2M_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_BRIDGE_DST_BUSECC_groupEntries[SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_P2M_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:13104
SDL_PDMA0_SAM67_PDMA_SPI_ECCAGGR_MemEntries
static const SDL_MemConfig_t SDL_PDMA0_SAM67_PDMA_SPI_ECCAGGR_MemEntries[SDL_PDMA0_SAM67_PDMA_SPI_ECCAGGR_RAM_IDS_TOTAL_ENTRIES]
Definition: sdl_ecc_soc.h:11475
SDL_WKUP_ECC_AGGR2_RamIdTable
static const SDL_RAMIdEntry_t SDL_WKUP_ECC_AGGR2_RamIdTable[SDL_WKUP_ECC_AGGR2_NUM_RAMS]
Definition: sdl_ecc_soc.h:17927
SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_groupEntries[SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:11496
SDL_WKUP_ECC_AGGR1_AM67_MCU_FW_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_WKUP_ECC_AGGR1_AM67_MCU_FW_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_groupEntries[SDL_WKUP_ECC_AGGR1_AM67_MCU_FW_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:5800
SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_P2P_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_BRIDGE_SRC_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_P2P_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_BRIDGE_SRC_BUSECC_groupEntries[SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_P2P_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:12999
SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_RamIdTable
static const SDL_RAMIdEntry_t SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_RamIdTable[SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_NUM_RAMS]
Definition: sdl_ecc_soc.h:18141
SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
#define SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:73
SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_groupEntries[SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:12289
SDL_PDMA1_SAM62_PDMA_UART_ECCAGGR_MemEntries
static const SDL_MemConfig_t SDL_PDMA1_SAM62_PDMA_UART_ECCAGGR_MemEntries[SDL_PDMA1_SAM62_PDMA_UART_ECCAGGR_RAM_IDS_TOTAL_ENTRIES]
Definition: sdl_ecc_soc.h:12254
SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_TIFS_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_TIFS_VBUSP_S_BRIDGE_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_TIFS_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_TIFS_VBUSP_S_BRIDGE_BUSECC_groupEntries[SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_TIFS_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_TIFS_VBUSP_S_BRIDGE_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:4283
SDL_MCU_ECC_AGGR0_ISAM67_DM2MCU_VBUSM_GASKET_MCU_0_EDC_CTRL_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_ISAM67_DM2MCU_VBUSM_GASKET_MCU_0_EDC_CTRL_groupEntries[SDL_MCU_ECC_AGGR0_ISAM67_DM2MCU_VBUSM_GASKET_MCU_0_EDC_CTRL_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:12817
SDL_USB1_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
#define SDL_USB1_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:84
SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_groupEntries[SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:9636
SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_groupEntries[SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:2827
SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_groupEntries
static const SDL_GrpChkConfig_t SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_groupEntries[SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:2968
SDL_FSS0_FSS_UL_OSPI0_OSPI_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
#define SDL_FSS0_FSS_UL_OSPI0_OSPI_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:69
sdl_esm_soc.h
SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_RamIdTable
static const SDL_RAMIdEntry_t SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_RamIdTable[SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_NUM_RAMS]
Definition: sdl_ecc_soc.h:20183
SDL_PDMA1_SAM62_PDMA_UART_ECCAGGR_RamIdTable
static const SDL_RAMIdEntry_t SDL_PDMA1_SAM62_PDMA_UART_ECCAGGR_RamIdTable[SDL_PDMA1_SAM62_PDMA_UART_ECCAGGR_NUM_RAMS]
Definition: sdl_ecc_soc.h:19298
SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_groupEntries[SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:5587
SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_ECC_AGGR_EDC_CTRL_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_ECC_AGGR_EDC_CTRL_groupEntries[SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_ECC_AGGR_EDC_CTRL_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:12201
SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_RXMEM_RamIdTable
static const SDL_RAMIdEntry_t SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_RXMEM_RamIdTable[SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_RXMEM_NUM_RAMS]
Definition: sdl_ecc_soc.h:19259
SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_RAM_IDS_TOTAL_ENTRIES
#define SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:99
SDL_WKUP_ECC_AGGR2_ISAM67_DM2WS_VBUSM_GASKET_MCU_0_EDC_CTRL_groupEntries
static const SDL_GrpChkConfig_t SDL_WKUP_ECC_AGGR2_ISAM67_DM2WS_VBUSM_GASKET_MCU_0_EDC_CTRL_groupEntries[SDL_WKUP_ECC_AGGR2_ISAM67_DM2WS_VBUSM_GASKET_MCU_0_EDC_CTRL_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:2816
SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISAM67_DM_MCU_ECC_AGGR_WKUP_1_CFG_P2P_BRIDGE_ISAM67_DM_MCU_ECC_AGGR_WKUP_1_CFG_BRIDGE_SRC_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISAM67_DM_MCU_ECC_AGGR_WKUP_1_CFG_P2P_BRIDGE_ISAM67_DM_MCU_ECC_AGGR_WKUP_1_CFG_BRIDGE_SRC_BUSECC_groupEntries[SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISAM67_DM_MCU_ECC_AGGR_WKUP_1_CFG_P2P_BRIDGE_ISAM67_DM_MCU_ECC_AGGR_WKUP_1_CFG_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:10685
SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
#define SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:93
SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_TXMEM_RAM_IDS_TOTAL_ENTRIES
#define SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_TXMEM_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:76
SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_groupEntries[SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:16689
SDL_PSRAMECC0_PSRAM256X32E_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
#define SDL_PSRAMECC0_PSRAM256X32E_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:60
SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_groupEntries[SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:8619
SDL_ecc_aggrRegs
Definition: V0/sdlr_ecc.h:53
SDL_PSRAMECC0_PSRAM256X32E_ECC_AGGR_RamIdTable
static const SDL_RAMIdEntry_t SDL_PSRAMECC0_PSRAM256X32E_ECC_AGGR_RamIdTable[SDL_PSRAMECC0_PSRAM256X32E_ECC_AGGR_NUM_RAMS]
Definition: sdl_ecc_soc.h:17888
SDL_PSRAMECC0_PSRAM256X32E_ECC_AGGR_MemEntries
static const SDL_MemConfig_t SDL_PSRAMECC0_PSRAM256X32E_ECC_AGGR_MemEntries[SDL_PSRAMECC0_PSRAM256X32E_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
Definition: sdl_ecc_soc.h:266
NULL
#define NULL
Define NULL if not defined.
Definition: csl_types.h:100
SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_BRIDGE_SRC_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_BRIDGE_SRC_BUSECC_groupEntries[SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:13135
SDL_PDMA1_SAM62_PDMA_UART_ECCAGGR_RAM_IDS_TOTAL_ENTRIES
#define SDL_PDMA1_SAM62_PDMA_UART_ECCAGGR_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:90
SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_groupEntries[SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:6757
SDL_WKUP_ECC_AGGR1_RamIdTable
static const SDL_RAMIdEntry_t SDL_WKUP_ECC_AGGR1_RamIdTable[SDL_WKUP_ECC_AGGR1_NUM_RAMS]
Definition: sdl_ecc_soc.h:18192
SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_groupEntries[SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:4451
SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_RamIdTable
static const SDL_RAMIdEntry_t SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_RamIdTable[SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_NUM_RAMS]
Definition: sdl_ecc_soc.h:18020
SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_groupEntries
static const SDL_GrpChkConfig_t SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_groupEntries[SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:821
SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_groupEntries[SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:9421
SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_groupEntries
static const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_groupEntries[SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:7278
SDL_USB0_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_RamIdTable
static const SDL_RAMIdEntry_t SDL_USB0_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_RamIdTable[SDL_USB0_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_NUM_RAMS]
Definition: sdl_ecc_soc.h:19218
SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IAM67_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM67_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IAM67_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM67_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_groupEntries[SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IAM67_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM67_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:13536
SDL_MSRAM_64K0_MSRAM2KX256E_ECC_AGGR_RamIdTable
static const SDL_RAMIdEntry_t SDL_MSRAM_64K0_MSRAM2KX256E_ECC_AGGR_RamIdTable[SDL_MSRAM_64K0_MSRAM2KX256E_ECC_AGGR_NUM_RAMS]
Definition: sdl_ecc_soc.h:17914
SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_RXMEM_RamIdTable
static const SDL_RAMIdEntry_t SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_RXMEM_RamIdTable[SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_RXMEM_NUM_RAMS]
Definition: sdl_ecc_soc.h:18563
SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_EDC_CTRL_0_groupEntries[SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:6712
SDL_MMCSD0_EMMC8SS_16FFC_ECC_AGGR_TXMEM_MemEntries
static const SDL_MemConfig_t SDL_MMCSD0_EMMC8SS_16FFC_ECC_AGGR_TXMEM_MemEntries[SDL_MMCSD0_EMMC8SS_16FFC_ECC_AGGR_TXMEM_RAM_IDS_TOTAL_ENTRIES]
Definition: sdl_ecc_soc.h:17243
SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_groupEntries[SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:9959
SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_groupEntries[SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:7697
SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_CFG_P2P_BRIDGE_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_CFG_BRIDGE_SRC_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_CFG_P2P_BRIDGE_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_CFG_BRIDGE_SRC_BUSECC_groupEntries[SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_CFG_P2P_BRIDGE_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_CFG_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:13470
SDL_PSCSS0_SAM67_MAIN_PSC_WRAP_ECC_AGGR_MemEntries
static const SDL_MemConfig_t SDL_PSCSS0_SAM67_MAIN_PSC_WRAP_ECC_AGGR_MemEntries[SDL_PSCSS0_SAM67_MAIN_PSC_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
Definition: sdl_ecc_soc.h:6448
SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_groupEntries[SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:16378
SDL_PSRAMECC1_PSRAM256X32E_ECC_AGGR_MemEntries
static const SDL_MemConfig_t SDL_PSRAMECC1_PSRAM256X32E_ECC_AGGR_MemEntries[SDL_PSRAMECC1_PSRAM256X32E_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
Definition: sdl_ecc_soc.h:277
SDL_MCU_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_groupEntries[SDL_MCU_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:10338
SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_RamIdTable
static const SDL_RAMIdEntry_t SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_RamIdTable[SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_NUM_RAMS]
Definition: sdl_ecc_soc.h:18164
SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_CBASS_DEFAULT_MMRS_AM67_MCU_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_CBASS_DEFAULT_MMRS_AM67_MCU_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_groupEntries[SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_CBASS_DEFAULT_MMRS_AM67_MCU_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:16194
SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_groupEntries[SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:13602
SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_groupEntries[SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:6192
SDL_PDMA0_SAM67_PDMA_SPI_ECCAGGR_RamIdTable
static const SDL_RAMIdEntry_t SDL_PDMA0_SAM67_PDMA_SPI_ECCAGGR_RamIdTable[SDL_PDMA0_SAM67_PDMA_SPI_ECCAGGR_NUM_RAMS]
Definition: sdl_ecc_soc.h:19129
SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_groupEntries[SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:11288
SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_groupEntries[SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:16968
SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_MemEntries
static const SDL_MemConfig_t SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_MemEntries[SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
Definition: sdl_ecc_soc.h:17199
SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_EXPORT_AM67_MCU_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM67_MCU_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_SRC_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_EXPORT_AM67_MCU_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM67_MCU_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_SRC_BUSECC_groupEntries[SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_EXPORT_AM67_MCU_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM67_MCU_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:13355
SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IAM67_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM67_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IAM67_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM67_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_groupEntries[SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IAM67_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM67_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:13579
SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_SRC_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_SRC_BUSECC_groupEntries[SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:4512
SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_groupEntries
static const SDL_GrpChkConfig_t SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_groupEntries[SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:1942
SDL_MCU_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_RamIdTable
static const SDL_RAMIdEntry_t SDL_MCU_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_RamIdTable[SDL_MCU_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_NUM_RAMS]
Definition: sdl_ecc_soc.h:20311
SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_groupEntries[SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:9106
SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ERR_SCR_AM67_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ERR_SCR_AM67_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_groupEntries[SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ERR_SCR_AM67_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:16425
SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_MemEntries
static const SDL_MemConfig_t SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_MemEntries[SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
Definition: sdl_ecc_soc.h:17221
SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_0_groupEntries[SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:6122
SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_MemEntries
static const SDL_MemConfig_t SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_MemEntries[SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
Definition: sdl_ecc_soc.h:6406
SDL_DMASS0_ECC_AGGR_0_MemEntries
static const SDL_MemConfig_t SDL_DMASS0_ECC_AGGR_0_MemEntries[SDL_DMASS0_ECC_AGGR_0_RAM_IDS_TOTAL_ENTRIES]
Definition: sdl_ecc_soc.h:11383
SDL_WKUP_PSRAMECC_8K0_PSRAM8KX32E_ECC_AGGR_MemEntries
static const SDL_MemConfig_t SDL_WKUP_PSRAMECC_8K0_PSRAM8KX32E_ECC_AGGR_MemEntries[SDL_WKUP_PSRAMECC_8K0_PSRAM8KX32E_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
Definition: sdl_ecc_soc.h:12243
SDL_GICSS0_GIC500SS_1_4_ECC_AGGR_RamIdTable
static const SDL_RAMIdEntry_t SDL_GICSS0_GIC500SS_1_4_ECC_AGGR_RamIdTable[SDL_GICSS0_GIC500SS_1_4_ECC_AGGR_NUM_RAMS]
Definition: sdl_ecc_soc.h:18431
SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_groupEntries[SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:5438
SDL_ECC_aggrTransBaseAddressTable
SDL_ecc_aggrRegs * SDL_ECC_aggrTransBaseAddressTable[SDL_ECC_MEMTYPE_MAX]
Definition: sdl_ecc_soc.h:152
SDL_GICSS0_GIC500SS_1_4_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
#define SDL_GICSS0_GIC500SS_1_4_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:71
SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_RamIdTable
static const SDL_RAMIdEntry_t SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_RamIdTable[SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_NUM_RAMS]
Definition: sdl_ecc_soc.h:19611
SDL_DSS_DSI0_K3_DSS_DSI_DSI_TOP_ECC_AGGR_SYS_K3_DSS_DSI_DSI_TOP_DSI_EDC_CTRL_SYS_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_DSS_DSI0_K3_DSS_DSI_DSI_TOP_ECC_AGGR_SYS_K3_DSS_DSI_DSI_TOP_DSI_EDC_CTRL_SYS_EDC_CTRL_0_groupEntries[SDL_DSS_DSI0_K3_DSS_DSI_DSI_TOP_ECC_AGGR_SYS_K3_DSS_DSI_DSI_TOP_DSI_EDC_CTRL_SYS_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:254
SDL_WKUP_ECC_AGGR1_AM67_MCU_FW_CBASS_IAM67_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM67_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_WKUP_ECC_AGGR1_AM67_MCU_FW_CBASS_IAM67_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM67_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_groupEntries[SDL_WKUP_ECC_AGGR1_AM67_MCU_FW_CBASS_IAM67_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM67_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:5777
SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_FW_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_FW_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_groupEntries[SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_FW_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:4568
SDL_MMCSD0_EMMC8SS_16FFC_ECC_AGGR_RXMEM_MemEntries
static const SDL_MemConfig_t SDL_MMCSD0_EMMC8SS_16FFC_ECC_AGGR_RXMEM_MemEntries[SDL_MMCSD0_EMMC8SS_16FFC_ECC_AGGR_RXMEM_RAM_IDS_TOTAL_ENTRIES]
Definition: sdl_ecc_soc.h:17254
SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_MemEntries
static const SDL_MemConfig_t SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_MemEntries[SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_RAM_IDS_TOTAL_ENTRIES]
Definition: sdl_ecc_soc.h:17265
SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IPULSAR_ULS_MCU_0_CPU0_CFG_SLV_P2P_BRIDGE_IPULSAR_ULS_MCU_0_CPU0_CFG_SLV_BRIDGE_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IPULSAR_ULS_MCU_0_CPU0_CFG_SLV_P2P_BRIDGE_IPULSAR_ULS_MCU_0_CPU0_CFG_SLV_BRIDGE_BUSECC_groupEntries[SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IPULSAR_ULS_MCU_0_CPU0_CFG_SLV_P2P_BRIDGE_IPULSAR_ULS_MCU_0_CPU0_CFG_SLV_BRIDGE_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:13215
SDL_WKUP_ECC_AGGR2_RAM_IDS_TOTAL_ENTRIES
#define SDL_WKUP_ECC_AGGR2_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:63
SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_RAM_IDS_TOTAL_ENTRIES
#define SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:96
SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_groupEntries[SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:7985
SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
#define SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:70
SDL_USB1_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_RamIdTable
static const SDL_RAMIdEntry_t SDL_USB1_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_RamIdTable[SDL_USB1_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_NUM_RAMS]
Definition: sdl_ecc_soc.h:19200
SDL_USB0_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_MemEntries
static const SDL_MemConfig_t SDL_USB0_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_MemEntries[SDL_USB0_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
Definition: sdl_ecc_soc.h:12036
SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISAM67_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM67_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_SRC_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISAM67_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM67_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_SRC_BUSECC_groupEntries[SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISAM67_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM67_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:10763
SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_SCRP_EDC_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_SCRP_EDC_groupEntries[SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_SCRP_EDC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:6161
SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IMSRAM32KX64E_MCU_0_CFG_P2P_BRIDGE_IMSRAM32KX64E_MCU_0_CFG_BRIDGE_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IMSRAM32KX64E_MCU_0_CFG_P2P_BRIDGE_IMSRAM32KX64E_MCU_0_CFG_BRIDGE_BUSECC_groupEntries[SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IMSRAM32KX64E_MCU_0_CFG_P2P_BRIDGE_IMSRAM32KX64E_MCU_0_CFG_BRIDGE_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:13320
SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_RamIdTable
static const SDL_RAMIdEntry_t SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_RamIdTable[SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_NUM_RAMS]
Definition: sdl_ecc_soc.h:19157
SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_RAM_IDS_TOTAL_ENTRIES
#define SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:100
SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_MemEntries
static const SDL_MemConfig_t SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_MemEntries[SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
Definition: sdl_ecc_soc.h:158
SDL_WKUP_ECC_AGGR0_SAM67_DM_DM_ECC_AGGR_EDC_CTRL_groupEntries
static const SDL_GrpChkConfig_t SDL_WKUP_ECC_AGGR0_SAM67_DM_DM_ECC_AGGR_EDC_CTRL_groupEntries[SDL_WKUP_ECC_AGGR0_SAM67_DM_DM_ECC_AGGR_EDC_CTRL_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:11363
SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_groupEntries[SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:4759
SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_INTAGGR_CEVT_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_INTAGGR_CEVT_EDC_CTRL_0_groupEntries[SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_INTAGGR_CEVT_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:9080
SDL_WKUP_ECC_AGGR1_SAM67_DM_MCU_ECC_AGGR_EDC_CTRL_groupEntries
static const SDL_GrpChkConfig_t SDL_WKUP_ECC_AGGR1_SAM67_DM_MCU_ECC_AGGR_EDC_CTRL_groupEntries[SDL_WKUP_ECC_AGGR1_SAM67_DM_MCU_ECC_AGGR_EDC_CTRL_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:5831
SDL_CPSW0_CPSW_3GUSS_AM67_CORE_ECC_CPSW_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
#define SDL_CPSW0_CPSW_3GUSS_AM67_CORE_ECC_CPSW_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:72
SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_CFG_SLV_SRC_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_CFG_SLV_SRC_BUSECC_groupEntries[SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_CFG_SLV_SRC_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:12428
SDL_DMASS0_ECC_AGGR_0_RamIdTable
static const SDL_RAMIdEntry_t SDL_DMASS0_ECC_AGGR_0_RamIdTable[SDL_DMASS0_ECC_AGGR_0_NUM_RAMS]
Definition: sdl_ecc_soc.h:18981
SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_MemEntries
static const SDL_MemConfig_t SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_MemEntries[SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_RAM_IDS_TOTAL_ENTRIES]
Definition: sdl_ecc_soc.h:17354
SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_BRIDGE_DST_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_BRIDGE_DST_BUSECC_groupEntries[SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:13178
SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_RAM_IDS_TOTAL_ENTRIES
#define SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:97
SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_groupEntries
static const SDL_GrpChkConfig_t SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_groupEntries[SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:17211
SDL_CPSW0_CPSW_3GUSS_AM67_CORE_ECC_CPSW_ECC_AGGR_MemEntries
static const SDL_MemConfig_t SDL_CPSW0_CPSW_3GUSS_AM67_CORE_ECC_CPSW_ECC_AGGR_MemEntries[SDL_CPSW0_CPSW_3GUSS_AM67_CORE_ECC_CPSW_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
Definition: sdl_ecc_soc.h:6374
SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_RAM_IDS_TOTAL_ENTRIES
#define SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:98
SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries[SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:7544
SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_DMSS_CFG_P2P_BRIDGE_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_DMSS_CFG_P2P_BRIDGE_EDC_CTRL_0_groupEntries[SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_DMSS_CFG_P2P_BRIDGE_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:9936
SDL_GICSS0_GIC500SS_1_4_ECC_AGGR_MemEntries
static const SDL_MemConfig_t SDL_GICSS0_GIC500SS_1_4_ECC_AGGR_MemEntries[SDL_GICSS0_GIC500SS_1_4_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
Definition: sdl_ecc_soc.h:6357
SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_groupEntries[SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:8988
SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_SAM62A_MCU_PULSAR_UL_ECC_AGGR_EDC_CTRL_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_SAM62A_MCU_PULSAR_UL_ECC_AGGR_EDC_CTRL_groupEntries[SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_SAM62A_MCU_PULSAR_UL_ECC_AGGR_EDC_CTRL_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:12002
SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_ECCAGGR_EDC_CTRL_groupEntries
static const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_ECCAGGR_EDC_CTRL_groupEntries[SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_ECCAGGR_EDC_CTRL_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:6538
SDL_MemConfig_t
Definition: sdl_ecc_priv.h:71
SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_groupEntries
static const SDL_GrpChkConfig_t SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_groupEntries[SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:2463
SDL_WKUP_PSRAMECC_8K0_PSRAM8KX32E_ECC_AGGR_RamIdTable
static const SDL_RAMIdEntry_t SDL_WKUP_PSRAMECC_8K0_PSRAM8KX32E_ECC_AGGR_RamIdTable[SDL_WKUP_PSRAMECC_8K0_PSRAM8KX32E_ECC_AGGR_NUM_RAMS]
Definition: sdl_ecc_soc.h:19285
SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_MemEntries
static const SDL_MemConfig_t SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_MemEntries[SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_RAM_IDS_TOTAL_ENTRIES]
Definition: sdl_ecc_soc.h:6481
SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_MemEntries
static const SDL_MemConfig_t SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_MemEntries[SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_RAM_IDS_TOTAL_ENTRIES]
Definition: sdl_ecc_soc.h:17532
SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_TXMEM_RamIdTable
static const SDL_RAMIdEntry_t SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_TXMEM_RamIdTable[SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_TXMEM_NUM_RAMS]
Definition: sdl_ecc_soc.h:18576
SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_IK3VTM_N16FFC_WKUP_0_VBUSP_P2P_BRIDGE_IK3VTM_N16FFC_WKUP_0_VBUSP_BRIDGE_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_IK3VTM_N16FFC_WKUP_0_VBUSP_P2P_BRIDGE_IK3VTM_N16FFC_WKUP_0_VBUSP_BRIDGE_BUSECC_groupEntries[SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_IK3VTM_N16FFC_WKUP_0_VBUSP_P2P_BRIDGE_IK3VTM_N16FFC_WKUP_0_VBUSP_BRIDGE_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:10728
SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_RAM_IDS_TOTAL_ENTRIES
#define SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:77
SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_groupEntries[SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:14123
SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_groupEntries[SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:3825
SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__IECC_AGGR_CFG_SRC_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__IECC_AGGR_CFG_SRC_BUSECC_groupEntries[SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__IECC_AGGR_CFG_SRC_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:12778
SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_groupEntries[SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:15085
SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_groupEntries
static const SDL_GrpChkConfig_t SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_groupEntries[SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:300
SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ERR_SCR_AM67_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ERR_SCR_AM67_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_groupEntries[SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ERR_SCR_AM67_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:3872
SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_TXMEM_MemEntries
static const SDL_MemConfig_t SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_TXMEM_MemEntries[SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_TXMEM_RAM_IDS_TOTAL_ENTRIES]
Definition: sdl_ecc_soc.h:6470
SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_RXMEM_MemEntries
static const SDL_MemConfig_t SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_RXMEM_MemEntries[SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_RXMEM_RAM_IDS_TOTAL_ENTRIES]
Definition: sdl_ecc_soc.h:12221
SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
#define SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:86
SDL_PSCSS0_SAM67_MAIN_PSC_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
#define SDL_PSCSS0_SAM67_MAIN_PSC_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:74
SDL_DMASS1_DMSS_CSI_AM62A_ECCAGGR_RAM_IDS_TOTAL_ENTRIES
#define SDL_DMASS1_DMSS_CSI_AM62A_ECCAGGR_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:65
SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_groupEntries[SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:12828
SDL_FSS0_FSS_UL_OSPI0_OSPI_WRAP_ECC_AGGR_RamIdTable
static const SDL_RAMIdEntry_t SDL_FSS0_FSS_UL_OSPI0_OSPI_WRAP_ECC_AGGR_RamIdTable[SDL_FSS0_FSS_UL_OSPI0_OSPI_WRAP_ECC_AGGR_NUM_RAMS]
Definition: sdl_ecc_soc.h:18235
SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_groupEntries[SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:11782
sdl_ecc.h
Header file contains enumerations, structure definitions and function.
SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:10978
SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_RamIdTable
static const SDL_RAMIdEntry_t SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_RamIdTable[SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_NUM_RAMS]
Definition: sdl_ecc_soc.h:19549
SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_ECC_AGGR_EDC_CTRL_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_ECC_AGGR_EDC_CTRL_groupEntries[SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_ECC_AGGR_EDC_CTRL_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:4898
SDL_MCU_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
#define SDL_MCU_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:79
SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_CFG_SLV_DST_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_CFG_SLV_DST_BUSECC_groupEntries[SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_CFG_SLV_DST_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:11929
SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ISAM67_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM67_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_BRIDGE_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ISAM67_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM67_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_BRIDGE_BUSECC_groupEntries[SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ISAM67_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM67_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_BRIDGE_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:2898
SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_RamIdTable
static const SDL_RAMIdEntry_t SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_RamIdTable[SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_NUM_RAMS]
Definition: sdl_ecc_soc.h:18248
SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_TXMEM_RAM_IDS_TOTAL_ENTRIES
#define SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_TXMEM_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:88
SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MemEntries
static const SDL_MemConfig_t SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MemEntries[SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
Definition: sdl_ecc_soc.h:4747
SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_groupEntries[SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:16266
SDL_MCU_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_MemEntries
static const SDL_MemConfig_t SDL_MCU_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_MemEntries[SDL_MCU_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
Definition: sdl_ecc_soc.h:10326
SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_PMST_SRC_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_PMST_SRC_BUSECC_groupEntries[SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_PMST_SRC_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:11946
SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_EDC_CTRL_0_groupEntries[SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:6436
SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_groupEntries[SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:8339
SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_MemEntries
static const SDL_MemConfig_t SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_MemEntries[SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_RAM_IDS_TOTAL_ENTRIES]
Definition: sdl_ecc_soc.h:17621
SDL_MMCSD0_EMMC8SS_16FFC_ECC_AGGR_TXMEM_RAM_IDS_TOTAL_ENTRIES
#define SDL_MMCSD0_EMMC8SS_16FFC_ECC_AGGR_TXMEM_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:94
SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_DMSS_CFG_SRC_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_DMSS_CFG_SRC_BUSECC_groupEntries[SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_DMSS_CFG_SRC_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:4601
SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_groupEntries[SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:10514
SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_MemEntries
static const SDL_MemConfig_t SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_MemEntries[SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
Definition: sdl_ecc_soc.h:4236
SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_groupEntries[SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:8909
SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_TXMEM_MemEntries
static const SDL_MemConfig_t SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_TXMEM_MemEntries[SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_TXMEM_RAM_IDS_TOTAL_ENTRIES]
Definition: sdl_ecc_soc.h:12232
SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_RamIdTable
static const SDL_RAMIdEntry_t SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_RamIdTable[SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_NUM_RAMS]
Definition: sdl_ecc_soc.h:18502
SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_groupEntries[SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:8830
SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_PKTDMA_CRED_SRC_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_PKTDMA_CRED_SRC_BUSECC_groupEntries[SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_PKTDMA_CRED_SRC_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:4657
SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_groupEntries[SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:15883
SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_groupEntries
static const SDL_GrpChkConfig_t SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_groupEntries[SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:1421
SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_CBASS_DEFAULT_ERR_AM67_WKUP_SAFE_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_CBASS_DEFAULT_ERR_AM67_WKUP_SAFE_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_groupEntries[SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_CBASS_DEFAULT_ERR_AM67_WKUP_SAFE_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:3806
SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_groupEntries[SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:8270
SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_groupEntries[SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:10150
SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_DST_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_DST_BUSECC_groupEntries[SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:4551
SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MemEntries
static const SDL_MemConfig_t SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MemEntries[SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
Definition: sdl_ecc_soc.h:12050
SDL_ECC_aggrBaseAddressTable
static SDL_ecc_aggrRegs *const SDL_ECC_aggrBaseAddressTable[SDL_ECC_Base_Address_TOTAL_ENTRIES]
Definition: sdl_ecc_soc.h:104
SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_groupEntries[SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:3965
SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_groupEntries
static const SDL_GrpChkConfig_t SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_groupEntries[SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:17233
SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_RamIdTable
static const SDL_RAMIdEntry_t SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_RamIdTable[SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_NUM_RAMS]
Definition: sdl_ecc_soc.h:19897
SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ISAM67_MCU_MCU_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM67_MCU_MCU_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ISAM67_MCU_MCU_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM67_MCU_MCU_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_groupEntries[SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ISAM67_MCU_MCU_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM67_MCU_MCU_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:13435
SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_groupEntries[SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:8195
SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
#define SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:64
SDL_WKUP_ECC_AGGR2_AM67_MCU_PLL_MMR_EDC_CTRL_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_WKUP_ECC_AGGR2_AM67_MCU_PLL_MMR_EDC_CTRL_BUSECC_groupEntries[SDL_WKUP_ECC_AGGR2_AM67_MCU_PLL_MMR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:1306
SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_RamIdTable
static const SDL_RAMIdEntry_t SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_RamIdTable[SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_NUM_RAMS]
Definition: sdl_ecc_soc.h:19236
SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_MemEntries
static const SDL_MemConfig_t SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_MemEntries[SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
Definition: sdl_ecc_soc.h:10282
SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_IAM67_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM67_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_BRIDGE_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_IAM67_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM67_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_BRIDGE_BUSECC_groupEntries[SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_IAM67_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM67_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_BRIDGE_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:2933
SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__IECC_AGGR_CFG_DST_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__IECC_AGGR_CFG_DST_BUSECC_groupEntries[SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__IECC_AGGR_CFG_DST_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:11985
SDL_CPSW0_CPSW_3GUSS_AM67_CORE_ECC_CPSW_ECC_AGGR_RamIdTable
static const SDL_RAMIdEntry_t SDL_CPSW0_CPSW_3GUSS_AM67_CORE_ECC_CPSW_ECC_AGGR_RamIdTable[SDL_CPSW0_CPSW_3GUSS_AM67_CORE_ECC_CPSW_ECC_AGGR_NUM_RAMS]
Definition: sdl_ecc_soc.h:18454
SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_RXMEM_RAM_IDS_TOTAL_ENTRIES
#define SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_RXMEM_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:87
SDL_RAMIdEntry_t
Definition: sdl_ecc_priv.h:46
SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_RamIdTable
static const SDL_RAMIdEntry_t SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_RamIdTable[SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_NUM_RAMS]
Definition: sdl_ecc_soc.h:18589
SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_groupEntries
static const SDL_GrpChkConfig_t SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_groupEntries[SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:3489
SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_groupEntries[SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:16219
SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_VD2GCLK_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_VD2GCLK_EDC_CTRL_0_groupEntries[SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_VD2GCLK_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:7970
SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_groupEntries[SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:8120
SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_RAM_IDS_TOTAL_ENTRIES
#define SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:67
SDL_WKUP_ECC_AGGR1_AM67_MCU_FW_CBASS_IAM67_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM67_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_WKUP_ECC_AGGR1_AM67_MCU_FW_CBASS_IAM67_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM67_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_groupEntries[SDL_WKUP_ECC_AGGR1_AM67_MCU_FW_CBASS_IAM67_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM67_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:5734
SDL_MSRAM_64K0_MSRAM2KX256E_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
#define SDL_MSRAM_64K0_MSRAM2KX256E_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:62
SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_groupEntries[SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:4318
SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_RamIdTable
static const SDL_RAMIdEntry_t SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_RamIdTable[SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_NUM_RAMS]
Definition: sdl_ecc_soc.h:18832
SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_ECCAGGR_EDC_CTRL_groupEntries
static const SDL_GrpChkConfig_t SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_ECCAGGR_EDC_CTRL_groupEntries[SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_ECCAGGR_EDC_CTRL_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:4919
SDL_MCU_ECC_AGGR0_MemEntries
static const SDL_MemConfig_t SDL_MCU_ECC_AGGR0_MemEntries[SDL_MCU_ECC_AGGR0_RAM_IDS_TOTAL_ENTRIES]
Definition: sdl_ecc_soc.h:12274
SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_ISAM67_DM_MCU_ECC_AGGR_WKUP_1_CFG_P2P_BRIDGE_ISAM67_DM_MCU_ECC_AGGR_WKUP_1_CFG_BRIDGE_DST_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_ISAM67_DM_MCU_ECC_AGGR_WKUP_1_CFG_P2P_BRIDGE_ISAM67_DM_MCU_ECC_AGGR_WKUP_1_CFG_BRIDGE_DST_BUSECC_groupEntries[SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_ISAM67_DM_MCU_ECC_AGGR_WKUP_1_CFG_P2P_BRIDGE_ISAM67_DM_MCU_ECC_AGGR_WKUP_1_CFG_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:5415
SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
#define SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:78
SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:10829
SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_MemEntries
static const SDL_MemConfig_t SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_MemEntries[SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_RAM_IDS_TOTAL_ENTRIES]
Definition: sdl_ecc_soc.h:17443
SDL_MCU_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_groupEntries[SDL_MCU_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:17713
SDL_ECC_Base_Address_TOTAL_ENTRIES
#define SDL_ECC_Base_Address_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:102
SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_P2P_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_BRIDGE_DST_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_P2P_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_BRIDGE_DST_BUSECC_groupEntries[SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_P2P_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:13042
SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_groupEntries[SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:6039
SDL_MCU_ECC_AGGR0_RamIdTable
static const SDL_RAMIdEntry_t SDL_MCU_ECC_AGGR0_RamIdTable[SDL_MCU_ECC_AGGR0_NUM_RAMS]
Definition: sdl_ecc_soc.h:19326
SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_groupEntries[SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:7401
SDL_PSRAMECC1_PSRAM256X32E_ECC_AGGR_RamIdTable
static const SDL_RAMIdEntry_t SDL_PSRAMECC1_PSRAM256X32E_ECC_AGGR_RamIdTable[SDL_PSRAMECC1_PSRAM256X32E_ECC_AGGR_NUM_RAMS]
Definition: sdl_ecc_soc.h:17901
SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_groupEntries[SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:16518
SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_groupEntries[SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:11643
SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IMSRAM32KX64E_MCU_1_CFG_P2P_BRIDGE_IMSRAM32KX64E_MCU_1_CFG_BRIDGE_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IMSRAM32KX64E_MCU_1_CFG_P2P_BRIDGE_IMSRAM32KX64E_MCU_1_CFG_BRIDGE_BUSECC_groupEntries[SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IMSRAM32KX64E_MCU_1_CFG_P2P_BRIDGE_IMSRAM32KX64E_MCU_1_CFG_BRIDGE_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:13250
SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_groupEntries[SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:4940
SDL_PSRAMECC1_PSRAM256X32E_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
#define SDL_PSRAMECC1_PSRAM256X32E_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:61
SDL_DMASS1_DMSS_CSI_AM62A_ECCAGGR_RamIdTable
static const SDL_RAMIdEntry_t SDL_DMASS1_DMSS_CSI_AM62A_ECCAGGR_RamIdTable[SDL_DMASS1_DMSS_CSI_AM62A_ECCAGGR_NUM_RAMS]
Definition: sdl_ecc_soc.h:18088
SDL_MCU_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
#define SDL_MCU_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:101
SDL_MCU_ECC_AGGR0_SAM67_MCU_MCU_ECC_AGGR_EDC_CTRL_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_SAM67_MCU_MCU_ECC_AGGR_EDC_CTRL_groupEntries[SDL_MCU_ECC_AGGR0_SAM67_MCU_MCU_ECC_AGGR_EDC_CTRL_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:17179
SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_VD2GCLK_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_VD2GCLK_EDC_CTRL_0_groupEntries[SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_VD2GCLK_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:9907
SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_P2M_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_BRIDGE_SRC_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_P2M_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_BRIDGE_SRC_BUSECC_groupEntries[SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_P2M_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:13061
SDL_MCU_ECC_AGGR0_RAM_IDS_TOTAL_ENTRIES
#define SDL_MCU_ECC_AGGR0_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:91
SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_RamIdTable
static const SDL_RAMIdEntry_t SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_RamIdTable[SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_NUM_RAMS]
Definition: sdl_ecc_soc.h:19567
SDL_DSS_DSI0_K3_DSS_DSI_DSI_TOP_ECC_AGGR_SYS_RAM_IDS_TOTAL_ENTRIES
#define SDL_DSS_DSI0_K3_DSS_DSI_DSI_TOP_ECC_AGGR_SYS_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:59
SDL_EccAggrEntry_t
Definition: sdl_ecc_priv.h:87
SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_CBASS_DEFAULT_ERR_AM67_MCU_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_CBASS_DEFAULT_ERR_AM67_MCU_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_groupEntries[SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_CBASS_DEFAULT_ERR_AM67_MCU_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:16359
SDL_FSS0_FSS_UL_OSPI0_OSPI_WRAP_ECC_AGGR_MemEntries
static const SDL_MemConfig_t SDL_FSS0_FSS_UL_OSPI0_OSPI_WRAP_ECC_AGGR_MemEntries[SDL_FSS0_FSS_UL_OSPI0_OSPI_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
Definition: sdl_ecc_soc.h:5851
SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_groupEntries[SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:12484
SDL_MMCSD0_EMMC8SS_16FFC_ECC_AGGR_RXMEM_RAM_IDS_TOTAL_ENTRIES
#define SDL_MMCSD0_EMMC8SS_16FFC_ECC_AGGR_RXMEM_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:95
SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_RXMEM_MemEntries
static const SDL_MemConfig_t SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_RXMEM_MemEntries[SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_RXMEM_RAM_IDS_TOTAL_ENTRIES]
Definition: sdl_ecc_soc.h:6459
SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_groupEntries[SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:12062
SDL_USB1_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_MemEntries
static const SDL_MemConfig_t SDL_USB1_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_MemEntries[SDL_USB1_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
Definition: sdl_ecc_soc.h:12022
SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_VBUSM2AXI_EDC_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_VBUSM2AXI_EDC_groupEntries[SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_VBUSM2AXI_EDC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:5958
SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_INTAGGR_MEVT_IN_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_INTAGGR_MEVT_IN_EDC_CTRL_0_groupEntries[SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_INTAGGR_MEVT_IN_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:9093
SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_DMSS_CFG_DST_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_DMSS_CFG_DST_BUSECC_groupEntries[SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_DMSS_CFG_DST_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:4640
SDL_MSRAM_64K0_MSRAM2KX256E_ECC_AGGR_MemEntries
static const SDL_MemConfig_t SDL_MSRAM_64K0_MSRAM2KX256E_ECC_AGGR_MemEntries[SDL_MSRAM_64K0_MSRAM2KX256E_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
Definition: sdl_ecc_soc.h:288
SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:10349
SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_ECC_AGGR_EDC_CTRL_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_ECC_AGGR_EDC_CTRL_groupEntries[SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_ECC_AGGR_EDC_CTRL_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:6337
SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_RamIdTable
static const SDL_RAMIdEntry_t SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_RamIdTable[SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_NUM_RAMS]
Definition: sdl_ecc_soc.h:19754
SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_VBUSP_P2P_BRIDGE_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_VBUSP_P2P_BRIDGE_EDC_CTRL_0_groupEntries[SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_VBUSP_P2P_BRIDGE_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:5291
sdl_ecc_priv.h
SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_groupEntries[SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:15362
SDL_ESM_INST_WKUP_ESM0
@ SDL_ESM_INST_WKUP_ESM0
Definition: sdl_esm_soc.h:63
SDL_MMCSD0_EMMC8SS_16FFC_ECC_AGGR_TXMEM_RamIdTable
static const SDL_RAMIdEntry_t SDL_MMCSD0_EMMC8SS_16FFC_ECC_AGGR_TXMEM_RamIdTable[SDL_MMCSD0_EMMC8SS_16FFC_ECC_AGGR_TXMEM_NUM_RAMS]
Definition: sdl_ecc_soc.h:19585
SDL_WKUP_ECC_AGGR0_RAM_IDS_TOTAL_ENTRIES
#define SDL_WKUP_ECC_AGGR0_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:80
SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
#define SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:66
SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_PKTDMA_CRED_DST_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_PKTDMA_CRED_DST_BUSECC_groupEntries[SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_PKTDMA_CRED_DST_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:4696
SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_groupEntries[SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:9200
SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_HSM_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_HSM_VBUSP_S_BRIDGE_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_HSM_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_HSM_VBUSP_S_BRIDGE_BUSECC_groupEntries[SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_HSM_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_HSM_VBUSP_S_BRIDGE_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:4248
SDL_DSS_DSI0_K3_DSS_DSI_DSI_TOP_ECC_AGGR_SYS_RamIdTable
static const SDL_RAMIdEntry_t SDL_DSS_DSI0_K3_DSS_DSI_DSI_TOP_ECC_AGGR_SYS_RamIdTable[SDL_DSS_DSI0_K3_DSS_DSI_DSI_TOP_ECC_AGGR_SYS_NUM_RAMS]
Definition: sdl_ecc_soc.h:17875
SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_groupEntries[SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:5306
SDL_DMASS0_ECC_AGGR_0_RAM_IDS_TOTAL_ENTRIES
#define SDL_DMASS0_ECC_AGGR_0_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:81
SDL_WKUP_ECC_AGGR1_RAM_IDS_TOTAL_ENTRIES
#define SDL_WKUP_ECC_AGGR1_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:68
SDL_USB0_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
#define SDL_USB0_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:85
SDL_MCU_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_MemEntries
static const SDL_MemConfig_t SDL_MCU_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_MemEntries[SDL_MCU_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
Definition: sdl_ecc_soc.h:17701
SDL_MCU_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_RamIdTable
static const SDL_RAMIdEntry_t SDL_MCU_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_RamIdTable[SDL_MCU_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_NUM_RAMS]
Definition: sdl_ecc_soc.h:18900
SDL_WKUP_ECC_AGGR0_RamIdTable
static const SDL_RAMIdEntry_t SDL_WKUP_ECC_AGGR0_RamIdTable[SDL_WKUP_ECC_AGGR0_NUM_RAMS]
Definition: sdl_ecc_soc.h:18918
SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_groupEntries[SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:8408
SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_PMST_DST_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_PMST_DST_BUSECC_groupEntries[SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_PMST_DST_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:12467
SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CFG_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CFG_EDC_CTRL_0_groupEntries[SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CFG_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:9185
SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_EXPORT_AM67_MCU_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM67_MCU_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_DST_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_EXPORT_AM67_MCU_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM67_MCU_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_DST_BUSECC_groupEntries[SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_EXPORT_AM67_MCU_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM67_MCU_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:13398