Introduction

Asymmetric multiprocessing (AMP) with FreeRTOS is where each core of a multicore device runs its own independent instance of FreeRTOS. The cores do not all need to have the same architecture, but do need to share some memory if the FreeRTOS instances need to communicate with each other.

FreeRTOS-AMP support is added on all the a53 cores in AM62LX. Each a53 core in the device runs its own instance of FreeRTOS.

Running AMP application

Note

Only a few examples, such as hello_world, empty, dpl_demo and task_switch are added for both the a53 cores in am62lx. These examples are enough to start AMP application on a53 cores.

Attention

Currently bootloader support is not present on am62lx. Hence, booting/running an AMP application at this stage is not possible.

ATF

• Trusted Firmware-A (TF-A) is running a single instance on a53 core 0, and is used for clocking and power management using SCMI and PSCI.
• TF-A load address is 0x80000000 for a53 core 0.
• TF-A jumps to address 0x82000000 for a53 core 0 and to address 0x88000000 for a53 core 1.
• TF-A logs are printed to Main UART 0.
• The default log level for the release build is 20 and the debug build is 40. i.e., will see more logs from TF-A when examples run in the debug profile

Linker File update

• Separate linker.cmd file is used for each a53 core
• DDR Memory region is divided and allocated to each a53 core
  • From 0x82000000 to 0x84000000 is allocated to a53core0
  • From 0x88000000 to 0x8A000000 is allocated to a53core1
• Different TF-A jump address is used for each a53 core
• Shared Memory among all the a53 cores are defined

MMU and Cache configuration

• MMU configuration is done on each a53 core
• Memory region used in the spinlock is outer and inner write back cacheable and nontransient (MAIR7 in SysConfig)
• TF-A Region is read-only and non-shareable
• SMP enable bit is set to attain data coherency b/w cores, this is required in spinlock

GIC Configuration

• SGI(INT 0-15) and PPI (INT 16-31) interrupts are per core
• SPI interrupts can be routed to any core
• GIC initialization is done by the core, which runs first. Software spinlock is used to avoid the race condition that may occur among the 4 cores

Software Spinlock

• A spin lock can be used to protect shared data or resources from simultaneous access
• Software spinlock is implemented to avoid the race condition among the a53 cores when they try to access the same resource
• The memory region from 0x99000000 to 0x99004000 is used to store the buffer used in the spinlock. This is common for all the a53 cores
• This region should be marked as outer and inner write-back cacheable and nontransient (MAIR7 in SysConfig)