AM62D FreeRTOS SDK
11.01.00
tisci_devices.h
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/*
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* Copyright (C) 2017-2025 Texas Instruments Incorporated
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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*
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* Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the
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* distribution.
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*
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* Neither the name of Texas Instruments Incorporated nor the names of
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* its contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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*/
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#ifndef SOC_TISCI_DEVICES_H
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#define SOC_TISCI_DEVICES_H
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#ifdef __cplusplus
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extern
"C"
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{
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#endif
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#define TISCI_DEV_CMP_EVENT_INTROUTER0 1U
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#define TISCI_DEV_DBGSUSPENDROUTER0 2U
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#define TISCI_DEV_MAIN_GPIOMUX_INTROUTER0 3U
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#define TISCI_DEV_WKUP_MCU_GPIOMUX_INTROUTER0 5U
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#define TISCI_DEV_TIMESYNC_EVENT_ROUTER0 6U
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#define TISCI_DEV_MCU_R5FSS0 7U
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#define TISCI_DEV_MCU_R5FSS0_CORE0 9U
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#define TISCI_DEV_CPSW0 13U
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#define TISCI_DEV_STM0 15U
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#define TISCI_DEV_DCC0 16U
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#define TISCI_DEV_DCC1 17U
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#define TISCI_DEV_DCC2 18U
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#define TISCI_DEV_DCC3 19U
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#define TISCI_DEV_DCC4 20U
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#define TISCI_DEV_DCC5 21U
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#define TISCI_DEV_SMS0 22U
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#define TISCI_DEV_MCU_DCC0 23U
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#define TISCI_DEV_DEBUGSS_WRAP0 24U
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#define TISCI_DEV_DMASS0 25U
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#define TISCI_DEV_DMASS0_BCDMA_0 26U
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#define TISCI_DEV_DMASS0_CBASS_0 27U
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#define TISCI_DEV_DMASS0_INTAGGR_0 28U
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#define TISCI_DEV_DMASS0_IPCSS_0 29U
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#define TISCI_DEV_DMASS0_PKTDMA_0 30U
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#define TISCI_DEV_DMASS0_RINGACC_0 33U
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#define TISCI_DEV_MCU_TIMER0 35U
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#define TISCI_DEV_TIMER0 36U
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#define TISCI_DEV_TIMER1 37U
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#define TISCI_DEV_TIMER2 38U
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#define TISCI_DEV_TIMER3 39U
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#define TISCI_DEV_TIMER4 40U
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#define TISCI_DEV_TIMER5 41U
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#define TISCI_DEV_TIMER6 42U
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#define TISCI_DEV_TIMER7 43U
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#define TISCI_DEV_MCU_TIMER1 48U
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#define TISCI_DEV_MCU_TIMER2 49U
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#define TISCI_DEV_MCU_TIMER3 50U
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#define TISCI_DEV_ECAP0 51U
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#define TISCI_DEV_ECAP1 52U
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#define TISCI_DEV_ECAP2 53U
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#define TISCI_DEV_ELM0 54U
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#define TISCI_DEV_EMIF_DATA_ISO_VD 55U
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#define TISCI_DEV_MMCSD0 57U
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#define TISCI_DEV_MMCSD1 58U
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#define TISCI_DEV_EQEP0 59U
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#define TISCI_DEV_EQEP1 60U
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#define TISCI_DEV_WKUP_GTC0 61U
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#define TISCI_DEV_EQEP2 62U
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#define TISCI_DEV_ESM0 63U
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#define TISCI_DEV_WKUP_ESM0 64U
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#define TISCI_DEV_FSS0 73U
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#define TISCI_DEV_FSS0_FSAS_0 74U
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#define TISCI_DEV_FSS0_OSPI_0 75U
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#define TISCI_DEV_GICSS0 76U
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#define TISCI_DEV_GPIO0 77U
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#define TISCI_DEV_GPIO1 78U
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#define TISCI_DEV_MCU_GPIO0 79U
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#define TISCI_DEV_GPMC0 80U
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#define TISCI_DEV_LED0 83U
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#define TISCI_DEV_DDPA0 85U
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#define TISCI_DEV_EPWM0 86U
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#define TISCI_DEV_EPWM1 87U
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#define TISCI_DEV_EPWM2 88U
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#define TISCI_DEV_WKUP_VTM0 95U
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#define TISCI_DEV_MAILBOX0 96U
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#define TISCI_DEV_MAIN2MCU_VD 97U
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#define TISCI_DEV_MCAN0 98U
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#define TISCI_DEV_MCU_MCRC64_0 100U
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#define TISCI_DEV_I2C0 102U
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#define TISCI_DEV_I2C1 103U
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#define TISCI_DEV_I2C2 104U
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#define TISCI_DEV_I2C3 105U
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#define TISCI_DEV_MCU_I2C0 106U
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#define TISCI_DEV_WKUP_I2C0 107U
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#define TISCI_DEV_WKUP_TIMER0 110U
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#define TISCI_DEV_WKUP_TIMER1 111U
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#define TISCI_DEV_WKUP_UART0 114U
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#define TISCI_DEV_MCRC64_0 116U
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#define TISCI_DEV_WKUP_RTCSS0 117U
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#define TISCI_DEV_WKUP_R5FSS0_SS0 118U
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#define TISCI_DEV_WKUP_R5FSS0 119U
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#define TISCI_DEV_WKUP_R5FSS0_CORE0 121U
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#define TISCI_DEV_RTI0 125U
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#define TISCI_DEV_RTI1 126U
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#define TISCI_DEV_RTI2 127U
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#define TISCI_DEV_RTI3 128U
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#define TISCI_DEV_MCU_RTI0 131U
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#define TISCI_DEV_WKUP_RTI0 132U
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#define TISCI_DEV_COMPUTE_CLUSTER0 134U
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#define TISCI_DEV_A53SS0_CORE_0 135U
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#define TISCI_DEV_A53SS0_CORE_1 136U
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#define TISCI_DEV_A53SS0_CORE_2 137U
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#define TISCI_DEV_A53SS0_CORE_3 138U
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#define TISCI_DEV_PSCSS0 139U
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#define TISCI_DEV_WKUP_PSC0 140U
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#define TISCI_DEV_MCSPI0 141U
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#define TISCI_DEV_MCSPI1 142U
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#define TISCI_DEV_MCSPI2 143U
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#define TISCI_DEV_UART0 146U
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#define TISCI_DEV_MCU_MCSPI0 147U
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#define TISCI_DEV_MCU_MCSPI1 148U
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#define TISCI_DEV_MCU_UART0 149U
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#define TISCI_DEV_SPINLOCK0 150U
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#define TISCI_DEV_UART1 152U
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#define TISCI_DEV_UART2 153U
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#define TISCI_DEV_UART3 154U
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#define TISCI_DEV_UART4 155U
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#define TISCI_DEV_UART5 156U
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#define TISCI_DEV_BOARD0 157U
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#define TISCI_DEV_UART6 158U
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#define TISCI_DEV_USB0 161U
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#define TISCI_DEV_USB1 162U
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#define TISCI_DEV_PBIST0 163U
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#define TISCI_DEV_WKUP_PBIST0 165U
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#define TISCI_DEV_A53SS0 166U
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#define TISCI_DEV_COMPUTE_CLUSTER0_PBIST_0 167U
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#define TISCI_DEV_PSC0_FW_0 168U
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#define TISCI_DEV_PSC0 169U
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#define TISCI_DEV_DDR32SS0 170U
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#define TISCI_DEV_DEBUGSS0 171U
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#define TISCI_DEV_A53_RS_BW_LIMITER0 172U
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#define TISCI_DEV_A53_WS_BW_LIMITER1 173U
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#define TISCI_DEV_WKUP_DEEPSLEEP_SOURCES0 176U
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#define TISCI_DEV_EMIF_CFG_ISO_VD 177U
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#define TISCI_DEV_MAIN_USB0_ISO_VD 178U
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#define TISCI_DEV_MAIN_USB1_ISO_VD 179U
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#define TISCI_DEV_MCU_MCU_16FF0 180U
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#define TISCI_DEV_CSI_RX_IF0 182U
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#define TISCI_DEV_DCC6 183U
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#define TISCI_DEV_MMCSD2 184U
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#define TISCI_DEV_DPHY_RX0 185U
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#define TISCI_DEV_DSS0 186U
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#define TISCI_DEV_MCU_MCAN0 188U
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#define TISCI_DEV_MCU_MCAN1 189U
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#define TISCI_DEV_MCASP0 190U
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#define TISCI_DEV_MCASP1 191U
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#define TISCI_DEV_MCASP2 192U
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#define TISCI_DEV_CLK_32K_RC_SEL_DEV_VD 193U
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#define TISCI_DEV_CPT2_AGGR1 194U
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#define TISCI_DEV_CPT2_AGGR0 195U
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#define TISCI_DEV_MCU_CPT2_AGGR0 196U
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#define TISCI_DEV_MCU_DCC1 197U
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#define TISCI_DEV_DMASS1 198U
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#define TISCI_DEV_DMASS1_BCDMA_0 199U
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#define TISCI_DEV_DMASS1_INTAGGR_0 200U
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#define TISCI_DEV_JPGENC0 201U
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#define TISCI_DEV_WKUP_PBIST1 202U
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#define TISCI_DEV_MCU_PBIST0 203U
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#define TISCI_DEV_CODEC0 204U
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#define TISCI_DEV_RTI4 205U
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#define TISCI_DEV_C7XV_RSWS_BS_LIMITER6 206U
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#define TISCI_DEV_C7X256V0 207U
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#define TISCI_DEV_C7X256V0_C7XV_CORE_0 208U
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#define TISCI_DEV_C7X256V0_CORE0 209U
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#define TISCI_DEV_C7X256V0_CLEC 210U
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#define TISCI_DEV_C7X256V0_CLK 211U
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#define TISCI_DEV_C7X256V0_DEBUG 212U
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#define TISCI_DEV_C7X256V0_GICSS 213U
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#define TISCI_DEV_C7X256V0_PBIST 214U
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#define TISCI_DEV_JPGENC_RS_BW_LIMITER4 215U
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#define TISCI_DEV_JPGENC_WS_BW_LIMITER5 216U
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#define TISCI_DEV_VPAC_RSWS_BW_LIMITER8 217U
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#define TISCI_DEV_VPAC_RSWS_BW_LIMITER7 218U
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#define TISCI_DEV_VPAC0 219U
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#define TISCI_DEV_PBIST3 220U
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#define TISCI_DEV_CODEC_RS_BW_LIMITER2 221U
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#define TISCI_DEV_CODEC_WS_BW_LIMITER3 222U
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#define TISCI_DEV_HSM0 225U
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#define TISCI_DEV_WKUP_CLKOUT_SEL_DEV_VD 226U
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#define TISCI_DEV_MCU_OBSCLK_MUX_SEL_DEV_VD 227U
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#define TISCI_DEV_OBSCLK0_MUX_SEL_DEV_VD 228U
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#ifdef __cplusplus
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}
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#endif
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#endif
/* SOC_TISCI_DEVICES_H */
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source
drivers
sciclient
include
tisci
am62dx
tisci_devices.h
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