AM62D FreeRTOS SDK  11.02.00
sdl_ecc_soc.h
Go to the documentation of this file.
1 /*
2  * Copyright (C) 2024-25 Texas Instruments Incorporated
3  *
4  * Redistribution and use in source and binary forms, with or without
5  * modification, are permitted provided that the following conditions
6  * are met:
7  *
8  * Redistributions of source code must retain the above copyright
9  * notice, this list of conditions and the following disclaimer.
10  *
11  * Redistributions in binary form must reproduce the above copyright
12  * notice, this list of conditions and the following disclaimer in the
13  * documentation and/or other materials provided with the
14  * distribution.
15  *
16  * Neither the name of Texas Instruments Incorporated nor the names of
17  * its contributors may be used to endorse or promote products derived
18  * from this software without specific prior written permission.
19  *
20  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
21  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
22  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
23  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
24  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
25  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
26  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
27  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
28  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
29  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
30  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31  */
41 #ifndef INCLUDE_SDL_ECC_SOC_H_
42 #define INCLUDE_SDL_ECC_SOC_H_
43 
44 #include <stdint.h>
45 #include <sdl/sdl_ecc.h>
46 #include <sdl/ecc/sdl_ip_ecc.h>
47 #include <sdl/include/sdl_types.h>
48 #include <sdl/esm/soc/am62dx/sdl_esm_core.h>
49 #include <sdl/esm/soc/am62dx/sdl_esm_soc.h>
50 #include <sdl/ecc/sdl_ecc_priv.h>
51 #include <sdl/include/am62dx/sdlr_soc_ecc_aggr.h>
52 #include <sdl/include/am62dx/sdlr_intr_esm0.h>
53 #include <sdl/include/am62dx/sdlr_intr_wkup_esm0.h>
54 #include <sdl/include/am62dx/sdlr_soc_baseaddress.h>
55 
56 
57 
58 /* define Max memEntries for each aggregator (i.e. the number of RAM ID's with * Wrapper type) */
59 #define SDL_PSCSS0_SAM62A_MAIN_PSC_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (1U)
60 #define SDL_PSRAMECC0_PSRAM256X32E_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (1U)
61 #define SDL_PSRAMECC1_PSRAM256X32E_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (1U)
62 #define SDL_MSRAM_64K0_MSRAM2KX256E_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (1U)
63 #define SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (0U)
64 #define SDL_DMASS1_DMSS_CSI_AM62A_ECCAGGR_RAM_IDS_TOTAL_ENTRIES (9U)
65 #define SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (1U)
66 #define SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_RAM_IDS_TOTAL_ENTRIES (0U)
67 #define SDL_FSS0_FSS_UL_OSPI0_OSPI_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (1U)
68 #define SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (29U)
69 #define SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (8U)
70 #define SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (1U)
71 #define SDL_GICSS0_GIC500SS_1_4_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (3U)
72 #define SDL_ECC_AGGR1_SAM62A_SEC_MCU_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (0U)
73 #define SDL_DMASS0_DMSS_AM62A_ECCAGGR_RAM_IDS_TOTAL_ENTRIES (28U)
74 #define SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_RXMEM_RAM_IDS_TOTAL_ENTRIES (1U)
75 #define SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_TXMEM_RAM_IDS_TOTAL_ENTRIES (1U)
76 #define SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_RXMEM_RAM_IDS_TOTAL_ENTRIES (1U)
77 #define SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_TXMEM_RAM_IDS_TOTAL_ENTRIES (1U)
78 #define SDL_MMCSD0_EMMCSD8SS_ECC_AGGR_TXMEM_RAM_IDS_TOTAL_ENTRIES (1U)
79 #define SDL_MMCSD0_EMMCSD8SS_ECC_AGGR_RXMEM_RAM_IDS_TOTAL_ENTRIES (1U)
80 #define SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (2U)
81 #define SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_RAM_IDS_TOTAL_ENTRIES (16U)
82 #define SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (12U)
83 #define SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (0U)
84 #define SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (29U)
85 #define SDL_SMS0_SMS_HSM_ECC_RAM_IDS_TOTAL_ENTRIES (2U)
86 #define SDL_SMS0_SMS_TIFS_ECC_RAM_IDS_TOTAL_ENTRIES (2U)
87 #define SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (0U)
88 #define SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (1U)
89 #define SDL_USB1_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (2U)
90 #define SDL_USB0_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (2U)
91 #define SDL_WKUP_PSRAMECC_8K0_PSRAM8KX32E_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (1U)
92 #define SDL_PDMA0_SAM62_PDMA_SPI_ECCAGGR_RAM_IDS_TOTAL_ENTRIES (4U)
93 #define SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (0U)
94 #define SDL_PDMA1_SAM62_PDMA_UART_ECCAGGR_RAM_IDS_TOTAL_ENTRIES (4U)
95 #define SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (1U)
96 #define SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_RAM_IDS_TOTAL_ENTRIES (27U)
97 #define SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_RAM_IDS_TOTAL_ENTRIES (27U)
98 #define SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_RAM_IDS_TOTAL_ENTRIES (27U)
99 #define SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_RAM_IDS_TOTAL_ENTRIES (27U)
100 #define SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_RAM_IDS_TOTAL_ENTRIES (24U)
101 #define SDL_MCU_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (1U)
102 #define SDL_MCU_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (1U)
103 #define SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (1U)
104 #define SDL_ECC_BASE_ADDRESS_TOTAL_ENTRIES (45U)
105 
110 static const SDL_MemConfig_t SDL_PSCSS0_SAM62A_MAIN_PSC_WRAP_ECC_AGGR_MemEntries[SDL_PSCSS0_SAM62A_MAIN_PSC_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES] =
111 {
112  { SDL_PSCSS0_SAM62A_MAIN_PSC_WRAP_ECC_AGGR_AM62A_PSC_CHFW_CBASS_DST_FW_CH_VBUSP_TABLE_RAM_ID, 0u,
113  SDL_PSCSS0_SAM62A_MAIN_PSC_WRAP_ECC_AGGR_AM62A_PSC_CHFW_CBASS_DST_FW_CH_VBUSP_TABLE_RAM_SIZE, 10u,
114  SDL_PSCSS0_SAM62A_MAIN_PSC_WRAP_ECC_AGGR_AM62A_PSC_CHFW_CBASS_DST_FW_CH_VBUSP_TABLE_ROW_WIDTH, ((bool)false) },
115 };
116 
121 static const SDL_MemConfig_t SDL_PSRAMECC0_PSRAM256X32E_ECC_AGGR_MemEntries[SDL_PSRAMECC0_PSRAM256X32E_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES] =
122 {
123  { SDL_PSRAMECC0_PSRAM256X32E_ECC_AGGR_PSRAM256X32E_PSRAM0_ECC_RAM_ID, 0x0000000000u,
124  SDL_PSRAMECC0_PSRAM256X32E_ECC_AGGR_PSRAM256X32E_PSRAM0_ECC_RAM_SIZE, 4u,
125  SDL_PSRAMECC0_PSRAM256X32E_ECC_AGGR_PSRAM256X32E_PSRAM0_ECC_ROW_WIDTH, ((bool)true) },
126 };
127 
132 static const SDL_MemConfig_t SDL_PSRAMECC1_PSRAM256X32E_ECC_AGGR_MemEntries[SDL_PSRAMECC1_PSRAM256X32E_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES] =
133 {
134  { SDL_PSRAMECC1_PSRAM256X32E_ECC_AGGR_PSRAM256X32E_PSRAM0_ECC_RAM_ID, 0x0000900000u,
135  SDL_PSRAMECC1_PSRAM256X32E_ECC_AGGR_PSRAM256X32E_PSRAM0_ECC_RAM_SIZE, 4u,
136  SDL_PSRAMECC1_PSRAM256X32E_ECC_AGGR_PSRAM256X32E_PSRAM0_ECC_ROW_WIDTH, ((bool)true) },
137 };
138 
143 static const SDL_MemConfig_t SDL_MSRAM_64K0_MSRAM2KX256E_ECC_AGGR_MemEntries[SDL_MSRAM_64K0_MSRAM2KX256E_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES] =
144 {
145  { SDL_MSRAM_64K0_MSRAM2KX256E_ECC_AGGR_MSRAM2KX256E_MSRAM0_ECC0_RAM_ID, 0x0043C40000u,
146  SDL_MSRAM_64K0_MSRAM2KX256E_ECC_AGGR_MSRAM2KX256E_MSRAM0_ECC0_RAM_SIZE, 32u,
147  SDL_MSRAM_64K0_MSRAM2KX256E_ECC_AGGR_MSRAM2KX256E_MSRAM0_ECC0_ROW_WIDTH, ((bool)true) },
148 };
149 
155 static const SDL_GrpChkConfig_t SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISAM62A_DM_MCU_ECC_AGGR_WKUP_1_CFG_P2P_BRIDGE_ISAM62A_DM_MCU_ECC_AGGR_WKUP_1_CFG_BRIDGE_DST_BUSECC_groupEntries[SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISAM62A_DM_MCU_ECC_AGGR_WKUP_1_CFG_P2P_BRIDGE_ISAM62A_DM_MCU_ECC_AGGR_WKUP_1_CFG_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS] =
156 {
157  { SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISAM62A_DM_MCU_ECC_AGGR_WKUP_1_CFG_P2P_BRIDGE_ISAM62A_DM_MCU_ECC_AGGR_WKUP_1_CFG_BRIDGE_DST_BUSECC_GROUP_0_CHECKER_TYPE,
158  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISAM62A_DM_MCU_ECC_AGGR_WKUP_1_CFG_P2P_BRIDGE_ISAM62A_DM_MCU_ECC_AGGR_WKUP_1_CFG_BRIDGE_DST_BUSECC_GROUP_0_WIDTH },
159  { SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISAM62A_DM_MCU_ECC_AGGR_WKUP_1_CFG_P2P_BRIDGE_ISAM62A_DM_MCU_ECC_AGGR_WKUP_1_CFG_BRIDGE_DST_BUSECC_GROUP_1_CHECKER_TYPE,
160  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISAM62A_DM_MCU_ECC_AGGR_WKUP_1_CFG_P2P_BRIDGE_ISAM62A_DM_MCU_ECC_AGGR_WKUP_1_CFG_BRIDGE_DST_BUSECC_GROUP_1_WIDTH },
161  { SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISAM62A_DM_MCU_ECC_AGGR_WKUP_1_CFG_P2P_BRIDGE_ISAM62A_DM_MCU_ECC_AGGR_WKUP_1_CFG_BRIDGE_DST_BUSECC_GROUP_2_CHECKER_TYPE,
162  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISAM62A_DM_MCU_ECC_AGGR_WKUP_1_CFG_P2P_BRIDGE_ISAM62A_DM_MCU_ECC_AGGR_WKUP_1_CFG_BRIDGE_DST_BUSECC_GROUP_2_WIDTH },
163  { SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISAM62A_DM_MCU_ECC_AGGR_WKUP_1_CFG_P2P_BRIDGE_ISAM62A_DM_MCU_ECC_AGGR_WKUP_1_CFG_BRIDGE_DST_BUSECC_GROUP_3_CHECKER_TYPE,
164  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISAM62A_DM_MCU_ECC_AGGR_WKUP_1_CFG_P2P_BRIDGE_ISAM62A_DM_MCU_ECC_AGGR_WKUP_1_CFG_BRIDGE_DST_BUSECC_GROUP_3_WIDTH },
165  { SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISAM62A_DM_MCU_ECC_AGGR_WKUP_1_CFG_P2P_BRIDGE_ISAM62A_DM_MCU_ECC_AGGR_WKUP_1_CFG_BRIDGE_DST_BUSECC_GROUP_4_CHECKER_TYPE,
166  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISAM62A_DM_MCU_ECC_AGGR_WKUP_1_CFG_P2P_BRIDGE_ISAM62A_DM_MCU_ECC_AGGR_WKUP_1_CFG_BRIDGE_DST_BUSECC_GROUP_4_WIDTH },
167  { SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISAM62A_DM_MCU_ECC_AGGR_WKUP_1_CFG_P2P_BRIDGE_ISAM62A_DM_MCU_ECC_AGGR_WKUP_1_CFG_BRIDGE_DST_BUSECC_GROUP_5_CHECKER_TYPE,
168  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISAM62A_DM_MCU_ECC_AGGR_WKUP_1_CFG_P2P_BRIDGE_ISAM62A_DM_MCU_ECC_AGGR_WKUP_1_CFG_BRIDGE_DST_BUSECC_GROUP_5_WIDTH },
169  { SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISAM62A_DM_MCU_ECC_AGGR_WKUP_1_CFG_P2P_BRIDGE_ISAM62A_DM_MCU_ECC_AGGR_WKUP_1_CFG_BRIDGE_DST_BUSECC_GROUP_6_CHECKER_TYPE,
170  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISAM62A_DM_MCU_ECC_AGGR_WKUP_1_CFG_P2P_BRIDGE_ISAM62A_DM_MCU_ECC_AGGR_WKUP_1_CFG_BRIDGE_DST_BUSECC_GROUP_6_WIDTH },
171 };
172 
178 static const SDL_GrpChkConfig_t SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_groupEntries[SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS] =
179 {
180  { SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
181  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
182  { SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
183  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
184  { SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
185  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
186  { SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
187  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
188  { SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
189  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
190  { SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_5_CHECKER_TYPE,
191  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_5_WIDTH },
192  { SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_6_CHECKER_TYPE,
193  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_6_WIDTH },
194  { SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_7_CHECKER_TYPE,
195  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_7_WIDTH },
196  { SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_8_CHECKER_TYPE,
197  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_8_WIDTH },
198  { SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_9_CHECKER_TYPE,
199  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_9_WIDTH },
200  { SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_10_CHECKER_TYPE,
201  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_10_WIDTH },
202  { SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_11_CHECKER_TYPE,
203  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_11_WIDTH },
204  { SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_12_CHECKER_TYPE,
205  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_12_WIDTH },
206  { SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_13_CHECKER_TYPE,
207  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_13_WIDTH },
208  { SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_14_CHECKER_TYPE,
209  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_14_WIDTH },
210  { SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_15_CHECKER_TYPE,
211  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_15_WIDTH },
212  { SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_16_CHECKER_TYPE,
213  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_16_WIDTH },
214  { SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_17_CHECKER_TYPE,
215  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_17_WIDTH },
216  { SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_18_CHECKER_TYPE,
217  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_18_WIDTH },
218  { SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_19_CHECKER_TYPE,
219  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_19_WIDTH },
220  { SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_20_CHECKER_TYPE,
221  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_20_WIDTH },
222  { SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_21_CHECKER_TYPE,
223  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_21_WIDTH },
224  { SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_22_CHECKER_TYPE,
225  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_22_WIDTH },
226  { SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_23_CHECKER_TYPE,
227  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_23_WIDTH },
228  { SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_24_CHECKER_TYPE,
229  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_24_WIDTH },
230  { SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_25_CHECKER_TYPE,
231  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_25_WIDTH },
232  { SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_26_CHECKER_TYPE,
233  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_26_WIDTH },
234  { SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_27_CHECKER_TYPE,
235  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_27_WIDTH },
236  { SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_28_CHECKER_TYPE,
237  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_28_WIDTH },
238  { SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_29_CHECKER_TYPE,
239  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_29_WIDTH },
240  { SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_30_CHECKER_TYPE,
241  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_30_WIDTH },
242  { SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_31_CHECKER_TYPE,
243  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_31_WIDTH },
244  { SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_32_CHECKER_TYPE,
245  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_32_WIDTH },
246  { SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_33_CHECKER_TYPE,
247  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_33_WIDTH },
248  { SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_34_CHECKER_TYPE,
249  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_34_WIDTH },
250  { SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_35_CHECKER_TYPE,
251  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_35_WIDTH },
252  { SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_36_CHECKER_TYPE,
253  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_36_WIDTH },
254  { SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_37_CHECKER_TYPE,
255  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_37_WIDTH },
256  { SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_38_CHECKER_TYPE,
257  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_38_WIDTH },
258  { SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_39_CHECKER_TYPE,
259  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_39_WIDTH },
260  { SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_40_CHECKER_TYPE,
261  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_40_WIDTH },
262  { SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_41_CHECKER_TYPE,
263  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_41_WIDTH },
264  { SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_42_CHECKER_TYPE,
265  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_42_WIDTH },
266  { SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_43_CHECKER_TYPE,
267  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_43_WIDTH },
268  { SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_44_CHECKER_TYPE,
269  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_44_WIDTH },
270  { SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_45_CHECKER_TYPE,
271  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_45_WIDTH },
272  { SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_46_CHECKER_TYPE,
273  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_46_WIDTH },
274  { SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_47_CHECKER_TYPE,
275  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_47_WIDTH },
276  { SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_48_CHECKER_TYPE,
277  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_48_WIDTH },
278  { SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_49_CHECKER_TYPE,
279  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_49_WIDTH },
280  { SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_50_CHECKER_TYPE,
281  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_50_WIDTH },
282  { SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_51_CHECKER_TYPE,
283  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_51_WIDTH },
284  { SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_52_CHECKER_TYPE,
285  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_52_WIDTH },
286  { SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_53_CHECKER_TYPE,
287  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_53_WIDTH },
288  { SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_54_CHECKER_TYPE,
289  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_54_WIDTH },
290  { SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_55_CHECKER_TYPE,
291  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_55_WIDTH },
292  { SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_56_CHECKER_TYPE,
293  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_56_WIDTH },
294  { SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_57_CHECKER_TYPE,
295  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_57_WIDTH },
296  { SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_58_CHECKER_TYPE,
297  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_58_WIDTH },
298  { SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_59_CHECKER_TYPE,
299  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_59_WIDTH },
300  { SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_60_CHECKER_TYPE,
301  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_60_WIDTH },
302  { SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_61_CHECKER_TYPE,
303  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_61_WIDTH },
304  { SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_62_CHECKER_TYPE,
305  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_62_WIDTH },
306  { SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_63_CHECKER_TYPE,
307  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_63_WIDTH },
308  { SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_64_CHECKER_TYPE,
309  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_64_WIDTH },
310  { SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_65_CHECKER_TYPE,
311  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_65_WIDTH },
312  { SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_66_CHECKER_TYPE,
313  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_66_WIDTH },
314  { SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_67_CHECKER_TYPE,
315  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_67_WIDTH },
316  { SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_68_CHECKER_TYPE,
317  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_68_WIDTH },
318 };
319 
325 static const SDL_GrpChkConfig_t SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_groupEntries[SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS] =
326 {
327  { SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
328  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
329  { SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
330  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
331  { SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
332  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
333  { SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
334  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
335  { SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
336  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
337  { SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_5_CHECKER_TYPE,
338  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_5_WIDTH },
339  { SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_6_CHECKER_TYPE,
340  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_6_WIDTH },
341  { SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_7_CHECKER_TYPE,
342  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_7_WIDTH },
343  { SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_8_CHECKER_TYPE,
344  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_8_WIDTH },
345  { SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_9_CHECKER_TYPE,
346  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_9_WIDTH },
347  { SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_10_CHECKER_TYPE,
348  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_10_WIDTH },
349  { SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_11_CHECKER_TYPE,
350  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_11_WIDTH },
351  { SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_12_CHECKER_TYPE,
352  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_12_WIDTH },
353  { SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_13_CHECKER_TYPE,
354  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_13_WIDTH },
355  { SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_14_CHECKER_TYPE,
356  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_14_WIDTH },
357  { SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_15_CHECKER_TYPE,
358  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_15_WIDTH },
359  { SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_16_CHECKER_TYPE,
360  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_16_WIDTH },
361  { SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_17_CHECKER_TYPE,
362  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_17_WIDTH },
363  { SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_18_CHECKER_TYPE,
364  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_18_WIDTH },
365  { SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_19_CHECKER_TYPE,
366  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_19_WIDTH },
367  { SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_20_CHECKER_TYPE,
368  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_20_WIDTH },
369  { SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_21_CHECKER_TYPE,
370  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_21_WIDTH },
371  { SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_22_CHECKER_TYPE,
372  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_22_WIDTH },
373  { SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_23_CHECKER_TYPE,
374  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_23_WIDTH },
375  { SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_24_CHECKER_TYPE,
376  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_24_WIDTH },
377  { SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_25_CHECKER_TYPE,
378  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_25_WIDTH },
379  { SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_26_CHECKER_TYPE,
380  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_26_WIDTH },
381  { SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_27_CHECKER_TYPE,
382  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_27_WIDTH },
383  { SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_28_CHECKER_TYPE,
384  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_28_WIDTH },
385  { SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_29_CHECKER_TYPE,
386  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_29_WIDTH },
387  { SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_30_CHECKER_TYPE,
388  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_30_WIDTH },
389  { SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_31_CHECKER_TYPE,
390  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_31_WIDTH },
391  { SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_32_CHECKER_TYPE,
392  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_32_WIDTH },
393  { SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_33_CHECKER_TYPE,
394  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_33_WIDTH },
395  { SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_34_CHECKER_TYPE,
396  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_34_WIDTH },
397  { SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_35_CHECKER_TYPE,
398  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_35_WIDTH },
399  { SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_36_CHECKER_TYPE,
400  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_36_WIDTH },
401  { SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_37_CHECKER_TYPE,
402  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_37_WIDTH },
403  { SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_38_CHECKER_TYPE,
404  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_38_WIDTH },
405  { SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_39_CHECKER_TYPE,
406  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_39_WIDTH },
407  { SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_40_CHECKER_TYPE,
408  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_40_WIDTH },
409  { SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_41_CHECKER_TYPE,
410  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_41_WIDTH },
411  { SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_42_CHECKER_TYPE,
412  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_42_WIDTH },
413  { SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_43_CHECKER_TYPE,
414  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_43_WIDTH },
415  { SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_44_CHECKER_TYPE,
416  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_44_WIDTH },
417  { SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_45_CHECKER_TYPE,
418  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_45_WIDTH },
419  { SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_46_CHECKER_TYPE,
420  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_46_WIDTH },
421  { SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_47_CHECKER_TYPE,
422  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_47_WIDTH },
423  { SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_48_CHECKER_TYPE,
424  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_48_WIDTH },
425  { SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_49_CHECKER_TYPE,
426  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_49_WIDTH },
427  { SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_50_CHECKER_TYPE,
428  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_50_WIDTH },
429  { SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_51_CHECKER_TYPE,
430  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_51_WIDTH },
431  { SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_52_CHECKER_TYPE,
432  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_52_WIDTH },
433  { SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_53_CHECKER_TYPE,
434  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_53_WIDTH },
435  { SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_54_CHECKER_TYPE,
436  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_54_WIDTH },
437  { SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_55_CHECKER_TYPE,
438  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_55_WIDTH },
439  { SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_56_CHECKER_TYPE,
440  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_56_WIDTH },
441  { SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_57_CHECKER_TYPE,
442  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_57_WIDTH },
443  { SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_58_CHECKER_TYPE,
444  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_58_WIDTH },
445  { SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_59_CHECKER_TYPE,
446  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_59_WIDTH },
447  { SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_60_CHECKER_TYPE,
448  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_60_WIDTH },
449  { SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_61_CHECKER_TYPE,
450  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_61_WIDTH },
451  { SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_62_CHECKER_TYPE,
452  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_62_WIDTH },
453  { SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_63_CHECKER_TYPE,
454  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_63_WIDTH },
455  { SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_64_CHECKER_TYPE,
456  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_64_WIDTH },
457  { SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_65_CHECKER_TYPE,
458  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_65_WIDTH },
459  { SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_66_CHECKER_TYPE,
460  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_66_WIDTH },
461  { SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_67_CHECKER_TYPE,
462  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_67_WIDTH },
463  { SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_68_CHECKER_TYPE,
464  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_68_WIDTH },
465 };
466 
472 static const SDL_GrpChkConfig_t SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_SAM62A_DM_MCU_ECC_AGGR_EDC_CTRL_groupEntries[SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_SAM62A_DM_MCU_ECC_AGGR_EDC_CTRL_MAX_NUM_CHECKERS] =
473 {
474  { SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_SAM62A_DM_MCU_ECC_AGGR_EDC_CTRL_GROUP_0_CHECKER_TYPE,
475  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_SAM62A_DM_MCU_ECC_AGGR_EDC_CTRL_GROUP_0_WIDTH },
476  { SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_SAM62A_DM_MCU_ECC_AGGR_EDC_CTRL_GROUP_1_CHECKER_TYPE,
477  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_SAM62A_DM_MCU_ECC_AGGR_EDC_CTRL_GROUP_1_WIDTH },
478  { SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_SAM62A_DM_MCU_ECC_AGGR_EDC_CTRL_GROUP_2_CHECKER_TYPE,
479  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_SAM62A_DM_MCU_ECC_AGGR_EDC_CTRL_GROUP_2_WIDTH },
480  { SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_SAM62A_DM_MCU_ECC_AGGR_EDC_CTRL_GROUP_3_CHECKER_TYPE,
481  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_SAM62A_DM_MCU_ECC_AGGR_EDC_CTRL_GROUP_3_WIDTH },
482  { SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_SAM62A_DM_MCU_ECC_AGGR_EDC_CTRL_GROUP_4_CHECKER_TYPE,
483  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_SAM62A_DM_MCU_ECC_AGGR_EDC_CTRL_GROUP_4_WIDTH },
484  { SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_SAM62A_DM_MCU_ECC_AGGR_EDC_CTRL_GROUP_5_CHECKER_TYPE,
485  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_SAM62A_DM_MCU_ECC_AGGR_EDC_CTRL_GROUP_5_WIDTH },
486 };
487 
492 static const SDL_MemConfig_t SDL_DMASS1_DMSS_CSI_AM62A_ECCAGGR_MemEntries[SDL_DMASS1_DMSS_CSI_AM62A_ECCAGGR_RAM_IDS_TOTAL_ENTRIES] =
493 {
494  { SDL_DMASS1_DMSS_CSI_AM62A_ECCAGGR_DMSS_CSI_AM62A_BCDMA_CFG_CONFIG_RAM_ID, 0u,
495  SDL_DMASS1_DMSS_CSI_AM62A_ECCAGGR_DMSS_CSI_AM62A_BCDMA_CFG_CONFIG_RAM_SIZE, 11u,
496  SDL_DMASS1_DMSS_CSI_AM62A_ECCAGGR_DMSS_CSI_AM62A_BCDMA_CFG_CONFIG_ROW_WIDTH, ((bool)false) },
497  { SDL_DMASS1_DMSS_CSI_AM62A_ECCAGGR_DMSS_CSI_AM62A_BCDMA_CFG_STATE_RAM_ID, 0u,
498  SDL_DMASS1_DMSS_CSI_AM62A_ECCAGGR_DMSS_CSI_AM62A_BCDMA_CFG_STATE_RAM_SIZE, 50u,
499  SDL_DMASS1_DMSS_CSI_AM62A_ECCAGGR_DMSS_CSI_AM62A_BCDMA_CFG_STATE_ROW_WIDTH, ((bool)false) },
500  { SDL_DMASS1_DMSS_CSI_AM62A_ECCAGGR_DMSS_CSI_AM62A_BCDMA_RPCFIFO_F0_RAM_ID, 0u,
501  SDL_DMASS1_DMSS_CSI_AM62A_ECCAGGR_DMSS_CSI_AM62A_BCDMA_RPCFIFO_F0_RAM_SIZE, 16u,
502  SDL_DMASS1_DMSS_CSI_AM62A_ECCAGGR_DMSS_CSI_AM62A_BCDMA_RPCFIFO_F0_ROW_WIDTH, ((bool)false) },
503  { SDL_DMASS1_DMSS_CSI_AM62A_ECCAGGR_DMSS_CSI_AM62A_BCDMA_RPCFIFO_F1_RAM_ID, 0u,
504  SDL_DMASS1_DMSS_CSI_AM62A_ECCAGGR_DMSS_CSI_AM62A_BCDMA_RPCFIFO_F1_RAM_SIZE, 16u,
505  SDL_DMASS1_DMSS_CSI_AM62A_ECCAGGR_DMSS_CSI_AM62A_BCDMA_RPCFIFO_F1_ROW_WIDTH, ((bool)false) },
506  { SDL_DMASS1_DMSS_CSI_AM62A_ECCAGGR_DMSS_CSI_AM62A_BCDMA_RPCFIFO_WC_RAM_ID, 0u,
507  SDL_DMASS1_DMSS_CSI_AM62A_ECCAGGR_DMSS_CSI_AM62A_BCDMA_RPCFIFO_WC_RAM_SIZE, 4u,
508  SDL_DMASS1_DMSS_CSI_AM62A_ECCAGGR_DMSS_CSI_AM62A_BCDMA_RPCFIFO_WC_ROW_WIDTH, ((bool)false) },
509  { SDL_DMASS1_DMSS_CSI_AM62A_ECCAGGR_DMSS_CSI_AM62A_BCDMA_STATS_STSR0_RAM_ID, 0u,
510  SDL_DMASS1_DMSS_CSI_AM62A_ECCAGGR_DMSS_CSI_AM62A_BCDMA_STATS_STSR0_RAM_SIZE, 12u,
511  SDL_DMASS1_DMSS_CSI_AM62A_ECCAGGR_DMSS_CSI_AM62A_BCDMA_STATS_STSR0_ROW_WIDTH, ((bool)false) },
512  { SDL_DMASS1_DMSS_CSI_AM62A_ECCAGGR_DMSS_CSI_AM62A_BCDMA_RINGOCC_CNTR_RAM_ID, 0u,
513  SDL_DMASS1_DMSS_CSI_AM62A_ECCAGGR_DMSS_CSI_AM62A_BCDMA_RINGOCC_CNTR_RAM_SIZE, 4u,
514  SDL_DMASS1_DMSS_CSI_AM62A_ECCAGGR_DMSS_CSI_AM62A_BCDMA_RINGOCC_CNTR_ROW_WIDTH, ((bool)false) },
515  { SDL_DMASS1_DMSS_CSI_AM62A_ECCAGGR_DMSS_CSI_AM62A_INTAGGR_STATREG_SR_SPRAM_8X128_SWW_SR_RAM_ID, 0u,
516  SDL_DMASS1_DMSS_CSI_AM62A_ECCAGGR_DMSS_CSI_AM62A_INTAGGR_STATREG_SR_SPRAM_8X128_SWW_SR_RAM_SIZE, 16u,
517  SDL_DMASS1_DMSS_CSI_AM62A_ECCAGGR_DMSS_CSI_AM62A_INTAGGR_STATREG_SR_SPRAM_8X128_SWW_SR_ROW_WIDTH, ((bool)false) },
518  { SDL_DMASS1_DMSS_CSI_AM62A_ECCAGGR_DMSS_CSI_AM62A_INTAGGR_COMMON_IM_TPRAM_153X34_SWW_SR_RAM_ID, 0u,
519  SDL_DMASS1_DMSS_CSI_AM62A_ECCAGGR_DMSS_CSI_AM62A_INTAGGR_COMMON_IM_TPRAM_153X34_SWW_SR_RAM_SIZE, 5u,
520  SDL_DMASS1_DMSS_CSI_AM62A_ECCAGGR_DMSS_CSI_AM62A_INTAGGR_COMMON_IM_TPRAM_153X34_SWW_SR_ROW_WIDTH, ((bool)false) },
521 };
522 
527 static const SDL_MemConfig_t SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MemEntries[SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES] =
528 {
529  { SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_ECC0_RAM_ID, 0x79140000u,
530  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_ECC0_RAM_SIZE, 4u,
531  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_ECC0_ROW_WIDTH, ((bool)true) },
532 };
533 
539 static const SDL_GrpChkConfig_t SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_groupEntries[SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_MAX_NUM_CHECKERS] =
540 {
541  { SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
542  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_0_WIDTH },
543  { SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
544  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_1_WIDTH },
545  { SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
546  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_2_WIDTH },
547  { SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
548  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_3_WIDTH },
549  { SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
550  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_4_WIDTH },
551  { SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
552  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_5_WIDTH },
553  { SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
554  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_6_WIDTH },
555  { SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
556  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_7_WIDTH },
557  { SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
558  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_8_WIDTH },
559  { SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
560  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_9_WIDTH },
561  { SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
562  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_10_WIDTH },
563  { SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
564  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_11_WIDTH },
565  { SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
566  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_12_WIDTH },
567  { SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
568  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_13_WIDTH },
569  { SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
570  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_14_WIDTH },
571  { SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
572  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_15_WIDTH },
573  { SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
574  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_16_WIDTH },
575  { SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
576  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_17_WIDTH },
577  { SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
578  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_18_WIDTH },
579  { SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
580  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_19_WIDTH },
581  { SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
582  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_20_WIDTH },
583  { SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
584  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_21_WIDTH },
585  { SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
586  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_22_WIDTH },
587  { SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
588  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_23_WIDTH },
589  { SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
590  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_24_WIDTH },
591  { SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
592  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_25_WIDTH },
593  { SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
594  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_26_WIDTH },
595  { SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
596  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_27_WIDTH },
597  { SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
598  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_28_WIDTH },
599  { SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
600  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_29_WIDTH },
601  { SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
602  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_30_WIDTH },
603  { SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
604  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_31_WIDTH },
605  { SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
606  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_32_WIDTH },
607  { SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_33_CHECKER_TYPE,
608  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_33_WIDTH },
609  { SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_34_CHECKER_TYPE,
610  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_34_WIDTH },
611  { SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_35_CHECKER_TYPE,
612  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_35_WIDTH },
613  { SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_36_CHECKER_TYPE,
614  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_36_WIDTH },
615  { SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_37_CHECKER_TYPE,
616  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_37_WIDTH },
617  { SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_38_CHECKER_TYPE,
618  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_38_WIDTH },
619  { SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_39_CHECKER_TYPE,
620  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_39_WIDTH },
621  { SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_40_CHECKER_TYPE,
622  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_40_WIDTH },
623  { SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_41_CHECKER_TYPE,
624  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_41_WIDTH },
625  { SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_42_CHECKER_TYPE,
626  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_42_WIDTH },
627  { SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_43_CHECKER_TYPE,
628  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_43_WIDTH },
629  { SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_44_CHECKER_TYPE,
630  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_44_WIDTH },
631  { SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_45_CHECKER_TYPE,
632  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_45_WIDTH },
633  { SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_46_CHECKER_TYPE,
634  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_46_WIDTH },
635  { SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_47_CHECKER_TYPE,
636  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_47_WIDTH },
637  { SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_48_CHECKER_TYPE,
638  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_48_WIDTH },
639  { SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_49_CHECKER_TYPE,
640  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_49_WIDTH },
641  { SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_50_CHECKER_TYPE,
642  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_50_WIDTH },
643  { SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_51_CHECKER_TYPE,
644  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_51_WIDTH },
645  { SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_52_CHECKER_TYPE,
646  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_52_WIDTH },
647  { SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_53_CHECKER_TYPE,
648  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_53_WIDTH },
649  { SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_54_CHECKER_TYPE,
650  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_54_WIDTH },
651  { SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_55_CHECKER_TYPE,
652  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_55_WIDTH },
653  { SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_56_CHECKER_TYPE,
654  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_56_WIDTH },
655  { SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_57_CHECKER_TYPE,
656  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_57_WIDTH },
657  { SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_58_CHECKER_TYPE,
658  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_58_WIDTH },
659  { SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_59_CHECKER_TYPE,
660  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_59_WIDTH },
661  { SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_60_CHECKER_TYPE,
662  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_60_WIDTH },
663  { SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_61_CHECKER_TYPE,
664  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_61_WIDTH },
665  { SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_62_CHECKER_TYPE,
666  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_62_WIDTH },
667  { SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_63_CHECKER_TYPE,
668  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_63_WIDTH },
669  { SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_64_CHECKER_TYPE,
670  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_64_WIDTH },
671 };
672 
678 static const SDL_GrpChkConfig_t SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_ECC_AGGR_EDC_CTRL_groupEntries[SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_ECC_AGGR_EDC_CTRL_MAX_NUM_CHECKERS] =
679 {
680  { SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_ECC_AGGR_EDC_CTRL_GROUP_0_CHECKER_TYPE,
681  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_ECC_AGGR_EDC_CTRL_GROUP_0_WIDTH },
682  { SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_ECC_AGGR_EDC_CTRL_GROUP_1_CHECKER_TYPE,
683  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_ECC_AGGR_EDC_CTRL_GROUP_1_WIDTH },
684  { SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_ECC_AGGR_EDC_CTRL_GROUP_2_CHECKER_TYPE,
685  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_ECC_AGGR_EDC_CTRL_GROUP_2_WIDTH },
686  { SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_ECC_AGGR_EDC_CTRL_GROUP_3_CHECKER_TYPE,
687  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_ECC_AGGR_EDC_CTRL_GROUP_3_WIDTH },
688  { SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_ECC_AGGR_EDC_CTRL_GROUP_4_CHECKER_TYPE,
689  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_ECC_AGGR_EDC_CTRL_GROUP_4_WIDTH },
690  { SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_ECC_AGGR_EDC_CTRL_GROUP_5_CHECKER_TYPE,
691  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_ECC_AGGR_EDC_CTRL_GROUP_5_WIDTH },
692 };
693 
699 static const SDL_GrpChkConfig_t SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_ECCAGGR_EDC_CTRL_groupEntries[SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_ECCAGGR_EDC_CTRL_MAX_NUM_CHECKERS] =
700 {
701  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_ECCAGGR_EDC_CTRL_GROUP_0_CHECKER_TYPE,
702  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_ECCAGGR_EDC_CTRL_GROUP_0_WIDTH },
703  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_ECCAGGR_EDC_CTRL_GROUP_1_CHECKER_TYPE,
704  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_ECCAGGR_EDC_CTRL_GROUP_1_WIDTH },
705  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_ECCAGGR_EDC_CTRL_GROUP_2_CHECKER_TYPE,
706  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_ECCAGGR_EDC_CTRL_GROUP_2_WIDTH },
707  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_ECCAGGR_EDC_CTRL_GROUP_3_CHECKER_TYPE,
708  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_ECCAGGR_EDC_CTRL_GROUP_3_WIDTH },
709  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_ECCAGGR_EDC_CTRL_GROUP_4_CHECKER_TYPE,
710  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_ECCAGGR_EDC_CTRL_GROUP_4_WIDTH },
711  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_ECCAGGR_EDC_CTRL_GROUP_5_CHECKER_TYPE,
712  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_ECCAGGR_EDC_CTRL_GROUP_5_WIDTH },
713 };
714 
720 static const SDL_GrpChkConfig_t SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_groupEntries[SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_MAX_NUM_CHECKERS] =
721 {
722  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
723  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_0_WIDTH },
724  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
725  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_1_WIDTH },
726  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
727  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_2_WIDTH },
728  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
729  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_3_WIDTH },
730  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
731  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_4_WIDTH },
732  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
733  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_5_WIDTH },
734  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
735  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_6_WIDTH },
736  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
737  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_7_WIDTH },
738  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
739  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_8_WIDTH },
740  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
741  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_9_WIDTH },
742  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
743  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_10_WIDTH },
744  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
745  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_11_WIDTH },
746  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
747  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_12_WIDTH },
748  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
749  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_13_WIDTH },
750  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
751  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_14_WIDTH },
752  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
753  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_15_WIDTH },
754  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
755  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_16_WIDTH },
756  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
757  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_17_WIDTH },
758  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
759  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_18_WIDTH },
760  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
761  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_19_WIDTH },
762  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
763  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_20_WIDTH },
764  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
765  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_21_WIDTH },
766  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
767  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_22_WIDTH },
768  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
769  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_23_WIDTH },
770  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
771  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_24_WIDTH },
772  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
773  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_25_WIDTH },
774  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
775  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_26_WIDTH },
776  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
777  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_27_WIDTH },
778  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
779  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_28_WIDTH },
780  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
781  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_29_WIDTH },
782  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
783  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_30_WIDTH },
784  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
785  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_31_WIDTH },
786  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
787  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_32_WIDTH },
788  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_33_CHECKER_TYPE,
789  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_33_WIDTH },
790  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_34_CHECKER_TYPE,
791  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_34_WIDTH },
792  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_35_CHECKER_TYPE,
793  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_35_WIDTH },
794  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_36_CHECKER_TYPE,
795  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_36_WIDTH },
796  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_37_CHECKER_TYPE,
797  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_37_WIDTH },
798  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_38_CHECKER_TYPE,
799  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_38_WIDTH },
800  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_39_CHECKER_TYPE,
801  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_39_WIDTH },
802  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_40_CHECKER_TYPE,
803  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_40_WIDTH },
804  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_41_CHECKER_TYPE,
805  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_41_WIDTH },
806  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_42_CHECKER_TYPE,
807  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_42_WIDTH },
808  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_43_CHECKER_TYPE,
809  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_43_WIDTH },
810  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_44_CHECKER_TYPE,
811  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_44_WIDTH },
812  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_45_CHECKER_TYPE,
813  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_45_WIDTH },
814  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_46_CHECKER_TYPE,
815  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_46_WIDTH },
816  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_47_CHECKER_TYPE,
817  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_47_WIDTH },
818  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_48_CHECKER_TYPE,
819  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_48_WIDTH },
820  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_49_CHECKER_TYPE,
821  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_49_WIDTH },
822  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_50_CHECKER_TYPE,
823  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_50_WIDTH },
824  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_51_CHECKER_TYPE,
825  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_51_WIDTH },
826  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_52_CHECKER_TYPE,
827  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_52_WIDTH },
828  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_53_CHECKER_TYPE,
829  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_53_WIDTH },
830  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_54_CHECKER_TYPE,
831  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_54_WIDTH },
832  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_55_CHECKER_TYPE,
833  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_55_WIDTH },
834  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_56_CHECKER_TYPE,
835  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_56_WIDTH },
836  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_57_CHECKER_TYPE,
837  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_57_WIDTH },
838  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_58_CHECKER_TYPE,
839  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_58_WIDTH },
840  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_59_CHECKER_TYPE,
841  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_59_WIDTH },
842  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_60_CHECKER_TYPE,
843  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_60_WIDTH },
844  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_61_CHECKER_TYPE,
845  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_61_WIDTH },
846  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_62_CHECKER_TYPE,
847  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_62_WIDTH },
848  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_63_CHECKER_TYPE,
849  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_63_WIDTH },
850  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_64_CHECKER_TYPE,
851  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_64_WIDTH },
852  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_65_CHECKER_TYPE,
853  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_65_WIDTH },
854  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_66_CHECKER_TYPE,
855  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_66_WIDTH },
856  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_67_CHECKER_TYPE,
857  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_67_WIDTH },
858  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_68_CHECKER_TYPE,
859  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_68_WIDTH },
860  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_69_CHECKER_TYPE,
861  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_69_WIDTH },
862  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_70_CHECKER_TYPE,
863  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_70_WIDTH },
864  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_71_CHECKER_TYPE,
865  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_71_WIDTH },
866  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_72_CHECKER_TYPE,
867  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_72_WIDTH },
868  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_73_CHECKER_TYPE,
869  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_73_WIDTH },
870  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_74_CHECKER_TYPE,
871  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_74_WIDTH },
872  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_75_CHECKER_TYPE,
873  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_75_WIDTH },
874  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_76_CHECKER_TYPE,
875  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_76_WIDTH },
876  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_77_CHECKER_TYPE,
877  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_77_WIDTH },
878  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_78_CHECKER_TYPE,
879  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_78_WIDTH },
880  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_79_CHECKER_TYPE,
881  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_79_WIDTH },
882  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_80_CHECKER_TYPE,
883  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_80_WIDTH },
884  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_81_CHECKER_TYPE,
885  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_81_WIDTH },
886  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_82_CHECKER_TYPE,
887  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_82_WIDTH },
888  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_83_CHECKER_TYPE,
889  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_83_WIDTH },
890  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_84_CHECKER_TYPE,
891  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_84_WIDTH },
892  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_85_CHECKER_TYPE,
893  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_85_WIDTH },
894  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_86_CHECKER_TYPE,
895  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_86_WIDTH },
896  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_87_CHECKER_TYPE,
897  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_87_WIDTH },
898  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_88_CHECKER_TYPE,
899  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_88_WIDTH },
900  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_89_CHECKER_TYPE,
901  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_89_WIDTH },
902  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_90_CHECKER_TYPE,
903  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_90_WIDTH },
904  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_91_CHECKER_TYPE,
905  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_91_WIDTH },
906  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_92_CHECKER_TYPE,
907  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_92_WIDTH },
908  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_93_CHECKER_TYPE,
909  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_93_WIDTH },
910  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_94_CHECKER_TYPE,
911  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_94_WIDTH },
912  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_95_CHECKER_TYPE,
913  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_95_WIDTH },
914  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_96_CHECKER_TYPE,
915  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_96_WIDTH },
916  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_97_CHECKER_TYPE,
917  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_97_WIDTH },
918  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_98_CHECKER_TYPE,
919  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_98_WIDTH },
920  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_99_CHECKER_TYPE,
921  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_99_WIDTH },
922  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_100_CHECKER_TYPE,
923  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_100_WIDTH },
924  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_101_CHECKER_TYPE,
925  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_101_WIDTH },
926  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_102_CHECKER_TYPE,
927  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_102_WIDTH },
928  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_103_CHECKER_TYPE,
929  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_103_WIDTH },
930  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_104_CHECKER_TYPE,
931  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_104_WIDTH },
932  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_105_CHECKER_TYPE,
933  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_105_WIDTH },
934  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_106_CHECKER_TYPE,
935  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_106_WIDTH },
936  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_107_CHECKER_TYPE,
937  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_107_WIDTH },
938  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_108_CHECKER_TYPE,
939  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_108_WIDTH },
940  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_109_CHECKER_TYPE,
941  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_109_WIDTH },
942  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_110_CHECKER_TYPE,
943  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_110_WIDTH },
944  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_111_CHECKER_TYPE,
945  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_111_WIDTH },
946  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_112_CHECKER_TYPE,
947  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_112_WIDTH },
948  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_113_CHECKER_TYPE,
949  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_113_WIDTH },
950  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_114_CHECKER_TYPE,
951  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_114_WIDTH },
952  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_115_CHECKER_TYPE,
953  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_115_WIDTH },
954  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_116_CHECKER_TYPE,
955  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_116_WIDTH },
956  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_117_CHECKER_TYPE,
957  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_117_WIDTH },
958  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_118_CHECKER_TYPE,
959  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_118_WIDTH },
960  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_119_CHECKER_TYPE,
961  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_119_WIDTH },
962  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_120_CHECKER_TYPE,
963  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_120_WIDTH },
964  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_121_CHECKER_TYPE,
965  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_121_WIDTH },
966  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_122_CHECKER_TYPE,
967  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_122_WIDTH },
968  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_123_CHECKER_TYPE,
969  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_123_WIDTH },
970  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_124_CHECKER_TYPE,
971  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_124_WIDTH },
972  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_125_CHECKER_TYPE,
973  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_125_WIDTH },
974  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_126_CHECKER_TYPE,
975  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_126_WIDTH },
976  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_127_CHECKER_TYPE,
977  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_127_WIDTH },
978  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_128_CHECKER_TYPE,
979  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_128_WIDTH },
980  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_129_CHECKER_TYPE,
981  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_129_WIDTH },
982  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_130_CHECKER_TYPE,
983  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_130_WIDTH },
984  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_131_CHECKER_TYPE,
985  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_131_WIDTH },
986  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_132_CHECKER_TYPE,
987  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_132_WIDTH },
988  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_133_CHECKER_TYPE,
989  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_133_WIDTH },
990  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_134_CHECKER_TYPE,
991  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_134_WIDTH },
992  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_135_CHECKER_TYPE,
993  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_135_WIDTH },
994  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_136_CHECKER_TYPE,
995  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_136_WIDTH },
996  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_137_CHECKER_TYPE,
997  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_137_WIDTH },
998  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_138_CHECKER_TYPE,
999  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_138_WIDTH },
1000  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_139_CHECKER_TYPE,
1001  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_139_WIDTH },
1002  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_140_CHECKER_TYPE,
1003  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_140_WIDTH },
1004  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_141_CHECKER_TYPE,
1005  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_141_WIDTH },
1006  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_142_CHECKER_TYPE,
1007  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_142_WIDTH },
1008  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_143_CHECKER_TYPE,
1009  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_143_WIDTH },
1010  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_144_CHECKER_TYPE,
1011  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_144_WIDTH },
1012  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_145_CHECKER_TYPE,
1013  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_145_WIDTH },
1014  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_146_CHECKER_TYPE,
1015  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_146_WIDTH },
1016  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_147_CHECKER_TYPE,
1017  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_147_WIDTH },
1018  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_148_CHECKER_TYPE,
1019  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_148_WIDTH },
1020  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_149_CHECKER_TYPE,
1021  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_149_WIDTH },
1022  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_150_CHECKER_TYPE,
1023  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_150_WIDTH },
1024  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_151_CHECKER_TYPE,
1025  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_151_WIDTH },
1026  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_152_CHECKER_TYPE,
1027  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_152_WIDTH },
1028  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_153_CHECKER_TYPE,
1029  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_153_WIDTH },
1030  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_154_CHECKER_TYPE,
1031  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_154_WIDTH },
1032  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_155_CHECKER_TYPE,
1033  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_155_WIDTH },
1034  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_156_CHECKER_TYPE,
1035  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_156_WIDTH },
1036  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_157_CHECKER_TYPE,
1037  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_157_WIDTH },
1038  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_158_CHECKER_TYPE,
1039  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_158_WIDTH },
1040  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_159_CHECKER_TYPE,
1041  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_159_WIDTH },
1042  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_160_CHECKER_TYPE,
1043  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_160_WIDTH },
1044  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_161_CHECKER_TYPE,
1045  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_161_WIDTH },
1046  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_162_CHECKER_TYPE,
1047  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_162_WIDTH },
1048  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_163_CHECKER_TYPE,
1049  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_163_WIDTH },
1050  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_164_CHECKER_TYPE,
1051  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_164_WIDTH },
1052  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_165_CHECKER_TYPE,
1053  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_165_WIDTH },
1054  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_166_CHECKER_TYPE,
1055  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_166_WIDTH },
1056  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_167_CHECKER_TYPE,
1057  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_167_WIDTH },
1058  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_168_CHECKER_TYPE,
1059  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_168_WIDTH },
1060  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_169_CHECKER_TYPE,
1061  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_169_WIDTH },
1062  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_170_CHECKER_TYPE,
1063  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_170_WIDTH },
1064 };
1065 
1071 static const SDL_GrpChkConfig_t SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_VBUSP_P2P_BRIDGE_EDC_CTRL_0_groupEntries[SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_VBUSP_P2P_BRIDGE_EDC_CTRL_0_MAX_NUM_CHECKERS] =
1072 {
1073  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_VBUSP_P2P_BRIDGE_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
1074  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_VBUSP_P2P_BRIDGE_EDC_CTRL_0_GROUP_0_WIDTH },
1075  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_VBUSP_P2P_BRIDGE_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
1076  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_VBUSP_P2P_BRIDGE_EDC_CTRL_0_GROUP_1_WIDTH },
1077  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_VBUSP_P2P_BRIDGE_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
1078  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_VBUSP_P2P_BRIDGE_EDC_CTRL_0_GROUP_2_WIDTH },
1079 };
1080 
1086 static const SDL_GrpChkConfig_t SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_groupEntries[SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_MAX_NUM_CHECKERS] =
1087 {
1088  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
1089  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_0_WIDTH },
1090  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
1091  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_1_WIDTH },
1092  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
1093  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_2_WIDTH },
1094  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
1095  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_3_WIDTH },
1096  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
1097  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_4_WIDTH },
1098  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
1099  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_5_WIDTH },
1100  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
1101  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_6_WIDTH },
1102  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
1103  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_7_WIDTH },
1104  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
1105  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_8_WIDTH },
1106  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
1107  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_9_WIDTH },
1108  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
1109  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_10_WIDTH },
1110  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
1111  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_11_WIDTH },
1112  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
1113  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_12_WIDTH },
1114  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
1115  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_13_WIDTH },
1116  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
1117  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_14_WIDTH },
1118  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
1119  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_15_WIDTH },
1120  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
1121  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_16_WIDTH },
1122  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
1123  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_17_WIDTH },
1124  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
1125  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_18_WIDTH },
1126  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
1127  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_19_WIDTH },
1128  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
1129  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_20_WIDTH },
1130  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
1131  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_21_WIDTH },
1132  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
1133  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_22_WIDTH },
1134  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
1135  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_23_WIDTH },
1136  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
1137  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_24_WIDTH },
1138  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
1139  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_25_WIDTH },
1140  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
1141  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_26_WIDTH },
1142  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
1143  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_27_WIDTH },
1144  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
1145  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_28_WIDTH },
1146  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
1147  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_29_WIDTH },
1148  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
1149  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_30_WIDTH },
1150  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
1151  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_31_WIDTH },
1152  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
1153  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_32_WIDTH },
1154  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_33_CHECKER_TYPE,
1155  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_33_WIDTH },
1156  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_34_CHECKER_TYPE,
1157  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_34_WIDTH },
1158  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_35_CHECKER_TYPE,
1159  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_35_WIDTH },
1160  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_36_CHECKER_TYPE,
1161  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_36_WIDTH },
1162  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_37_CHECKER_TYPE,
1163  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_37_WIDTH },
1164  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_38_CHECKER_TYPE,
1165  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_38_WIDTH },
1166  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_39_CHECKER_TYPE,
1167  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_39_WIDTH },
1168  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_40_CHECKER_TYPE,
1169  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_40_WIDTH },
1170  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_41_CHECKER_TYPE,
1171  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_41_WIDTH },
1172  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_42_CHECKER_TYPE,
1173  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_42_WIDTH },
1174  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_43_CHECKER_TYPE,
1175  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_43_WIDTH },
1176  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_44_CHECKER_TYPE,
1177  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_44_WIDTH },
1178  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_45_CHECKER_TYPE,
1179  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_45_WIDTH },
1180  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_46_CHECKER_TYPE,
1181  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_46_WIDTH },
1182  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_47_CHECKER_TYPE,
1183  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_47_WIDTH },
1184  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_48_CHECKER_TYPE,
1185  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_48_WIDTH },
1186  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_49_CHECKER_TYPE,
1187  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_49_WIDTH },
1188 };
1189 
1194 static const SDL_MemConfig_t SDL_FSS0_FSS_UL_OSPI0_OSPI_WRAP_ECC_AGGR_MemEntries[SDL_FSS0_FSS_UL_OSPI0_OSPI_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES] =
1195 {
1196  { SDL_FSS0_FSS_UL_OSPI0_OSPI_WRAP_ECC_AGGR_OSPI_OSPI_WRAP_SRAM_RAM_ID, 0u,
1197  SDL_FSS0_FSS_UL_OSPI0_OSPI_WRAP_ECC_AGGR_OSPI_OSPI_WRAP_SRAM_RAM_SIZE, 4u,
1198  SDL_FSS0_FSS_UL_OSPI0_OSPI_WRAP_ECC_AGGR_OSPI_OSPI_WRAP_SRAM_ROW_WIDTH, ((bool)false) },
1199 };
1200 
1205 static const SDL_MemConfig_t SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_MemEntries[SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES] =
1206 {
1207  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_ITAG_RAM0_RAM_ID, 0u,
1208  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_ITAG_RAM0_RAM_SIZE, 4u,
1209  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_ITAG_RAM0_ROW_WIDTH, ((bool)false) },
1210  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_ITAG_RAM1_RAM_ID, 0u,
1211  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_ITAG_RAM1_RAM_SIZE, 4u,
1212  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_ITAG_RAM1_ROW_WIDTH, ((bool)false) },
1213  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_ITAG_RAM2_RAM_ID, 0u,
1214  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_ITAG_RAM2_RAM_SIZE, 4u,
1215  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_ITAG_RAM2_ROW_WIDTH, ((bool)false) },
1216  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_ITAG_RAM3_RAM_ID, 0u,
1217  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_ITAG_RAM3_RAM_SIZE, 4u,
1218  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_ITAG_RAM3_ROW_WIDTH, ((bool)false) },
1219  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_IDATA_BANK0_RAM_ID, 0u,
1220  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_IDATA_BANK0_RAM_SIZE, 8u,
1221  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_IDATA_BANK0_ROW_WIDTH, ((bool)true) },
1222  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_IDATA_BANK1_RAM_ID, 0u,
1223  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_IDATA_BANK1_RAM_SIZE, 8u,
1224  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_IDATA_BANK1_ROW_WIDTH, ((bool)true) },
1225  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_IDATA_BANK2_RAM_ID, 0u,
1226  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_IDATA_BANK2_RAM_SIZE, 8u,
1227  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_IDATA_BANK2_ROW_WIDTH, ((bool)true) },
1228  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_IDATA_BANK3_RAM_ID, 0u,
1229  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_IDATA_BANK3_RAM_SIZE, 8u,
1230  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_IDATA_BANK3_ROW_WIDTH, ((bool)true) },
1231  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_DTAG_RAM0_RAM_ID, 0u,
1232  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_DTAG_RAM0_RAM_SIZE, 4u,
1233  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_DTAG_RAM0_ROW_WIDTH, ((bool)false) },
1234  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_DTAG_RAM1_RAM_ID, 0u,
1235  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_DTAG_RAM1_RAM_SIZE, 4u,
1236  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_DTAG_RAM1_ROW_WIDTH, ((bool)false) },
1237  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_DTAG_RAM2_RAM_ID, 0u,
1238  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_DTAG_RAM2_RAM_SIZE, 4u,
1239  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_DTAG_RAM2_ROW_WIDTH, ((bool)false) },
1240  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_DTAG_RAM3_RAM_ID, 0u,
1241  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_DTAG_RAM3_RAM_SIZE, 4u,
1242  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_DTAG_RAM3_ROW_WIDTH, ((bool)false) },
1243  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_DDIRTY_RAM_RAM_ID, 0u,
1244  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_DDIRTY_RAM_RAM_SIZE, 4u,
1245  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_DDIRTY_RAM_ROW_WIDTH, ((bool)false) },
1246  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_DDATA_RAM0_RAM_ID, 0u,
1247  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_DDATA_RAM0_RAM_SIZE, 4u,
1248  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_DDATA_RAM0_ROW_WIDTH, ((bool)true) },
1249  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_DDATA_RAM1_RAM_ID, 0u,
1250  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_DDATA_RAM1_RAM_SIZE, 4u,
1251  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_DDATA_RAM1_ROW_WIDTH, ((bool)true) },
1252  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_DDATA_RAM2_RAM_ID, 0u,
1253  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_DDATA_RAM2_RAM_SIZE, 4u,
1254  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_DDATA_RAM2_ROW_WIDTH, ((bool)true) },
1255  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_DDATA_RAM3_RAM_ID, 0u,
1256  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_DDATA_RAM3_RAM_SIZE, 4u,
1257  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_DDATA_RAM3_ROW_WIDTH, ((bool)true) },
1258  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_DDATA_RAM4_RAM_ID, 0u,
1259  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_DDATA_RAM4_RAM_SIZE, 4u,
1260  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_DDATA_RAM4_ROW_WIDTH, ((bool)true) },
1261  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_DDATA_RAM5_RAM_ID, 0u,
1262  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_DDATA_RAM5_RAM_SIZE, 4u,
1263  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_DDATA_RAM5_ROW_WIDTH, ((bool)true) },
1264  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_DDATA_RAM6_RAM_ID, 0u,
1265  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_DDATA_RAM6_RAM_SIZE, 4u,
1266  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_DDATA_RAM6_ROW_WIDTH, ((bool)true) },
1267  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_DDATA_RAM7_RAM_ID, 0u,
1268  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_DDATA_RAM7_RAM_SIZE, 4u,
1269  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_DDATA_RAM7_ROW_WIDTH, ((bool)true) },
1270  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_ATCM0_BANK0_RAM_ID, 0x00u,
1271  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_ATCM0_BANK0_RAM_SIZE, 4u,
1272  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_ATCM0_BANK0_ROW_WIDTH, ((bool)true) },
1273  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_ATCM0_BANK1_RAM_ID, 0x00u,
1274  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_ATCM0_BANK1_RAM_SIZE, 4u,
1275  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_ATCM0_BANK1_ROW_WIDTH, ((bool)true) },
1276  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_B0TCM0_BANK0_RAM_ID, 0x41010000u,
1277  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_B0TCM0_BANK0_RAM_SIZE, 4u,
1278  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_B0TCM0_BANK0_ROW_WIDTH, ((bool)true) },
1279  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_B0TCM0_BANK1_RAM_ID, 0x41010000u,
1280  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_B0TCM0_BANK1_RAM_SIZE, 4u,
1281  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_B0TCM0_BANK1_ROW_WIDTH, ((bool)true) },
1282  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_B1TCM0_BANK0_RAM_ID, 0x41010000u,
1283  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_B1TCM0_BANK0_RAM_SIZE, 4u,
1284  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_B1TCM0_BANK0_ROW_WIDTH, ((bool)true) },
1285  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_B1TCM0_BANK1_RAM_ID, 0x41010000u,
1286  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_B1TCM0_BANK1_RAM_SIZE, 4u,
1287  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_B1TCM0_BANK1_ROW_WIDTH, ((bool)true) },
1288  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_KS_VIM_RAMECC_RAM_ID, 0u,
1289  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_KS_VIM_RAMECC_RAM_SIZE, 4u,
1290  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_KS_VIM_RAMECC_ROW_WIDTH, ((bool)false) },
1291  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_AXI2VBUSM_MEM_MST_RAMECC_RAM_ID, 0u,
1292  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_AXI2VBUSM_MEM_MST_RAMECC_RAM_SIZE, 8u,
1293  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_AXI2VBUSM_MEM_MST_RAMECC_ROW_WIDTH, ((bool)false) },
1294 };
1295 
1301 static const SDL_GrpChkConfig_t SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_VBUSM2AXI_EDC_groupEntries[SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_VBUSM2AXI_EDC_MAX_NUM_CHECKERS] =
1302 {
1303  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_VBUSM2AXI_EDC_GROUP_0_CHECKER_TYPE,
1304  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_VBUSM2AXI_EDC_GROUP_0_WIDTH },
1305  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_VBUSM2AXI_EDC_GROUP_1_CHECKER_TYPE,
1306  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_VBUSM2AXI_EDC_GROUP_1_WIDTH },
1307  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_VBUSM2AXI_EDC_GROUP_2_CHECKER_TYPE,
1308  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_VBUSM2AXI_EDC_GROUP_2_WIDTH },
1309  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_VBUSM2AXI_EDC_GROUP_3_CHECKER_TYPE,
1310  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_VBUSM2AXI_EDC_GROUP_3_WIDTH },
1311  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_VBUSM2AXI_EDC_GROUP_4_CHECKER_TYPE,
1312  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_VBUSM2AXI_EDC_GROUP_4_WIDTH },
1313  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_VBUSM2AXI_EDC_GROUP_5_CHECKER_TYPE,
1314  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_VBUSM2AXI_EDC_GROUP_5_WIDTH },
1315  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_VBUSM2AXI_EDC_GROUP_6_CHECKER_TYPE,
1316  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_VBUSM2AXI_EDC_GROUP_6_WIDTH },
1317  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_VBUSM2AXI_EDC_GROUP_7_CHECKER_TYPE,
1318  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_VBUSM2AXI_EDC_GROUP_7_WIDTH },
1319  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_VBUSM2AXI_EDC_GROUP_8_CHECKER_TYPE,
1320  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_VBUSM2AXI_EDC_GROUP_8_WIDTH },
1321  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_VBUSM2AXI_EDC_GROUP_9_CHECKER_TYPE,
1322  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_VBUSM2AXI_EDC_GROUP_9_WIDTH },
1323  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_VBUSM2AXI_EDC_GROUP_10_CHECKER_TYPE,
1324  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_VBUSM2AXI_EDC_GROUP_10_WIDTH },
1325  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_VBUSM2AXI_EDC_GROUP_11_CHECKER_TYPE,
1326  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_VBUSM2AXI_EDC_GROUP_11_WIDTH },
1327  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_VBUSM2AXI_EDC_GROUP_12_CHECKER_TYPE,
1328  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_VBUSM2AXI_EDC_GROUP_12_WIDTH },
1329  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_VBUSM2AXI_EDC_GROUP_13_CHECKER_TYPE,
1330  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_VBUSM2AXI_EDC_GROUP_13_WIDTH },
1331  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_VBUSM2AXI_EDC_GROUP_14_CHECKER_TYPE,
1332  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_VBUSM2AXI_EDC_GROUP_14_WIDTH },
1333  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_VBUSM2AXI_EDC_GROUP_15_CHECKER_TYPE,
1334  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_VBUSM2AXI_EDC_GROUP_15_WIDTH },
1335  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_VBUSM2AXI_EDC_GROUP_16_CHECKER_TYPE,
1336  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_VBUSM2AXI_EDC_GROUP_16_WIDTH },
1337  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_VBUSM2AXI_EDC_GROUP_17_CHECKER_TYPE,
1338  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_VBUSM2AXI_EDC_GROUP_17_WIDTH },
1339  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_VBUSM2AXI_EDC_GROUP_18_CHECKER_TYPE,
1340  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_VBUSM2AXI_EDC_GROUP_18_WIDTH },
1341  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_VBUSM2AXI_EDC_GROUP_19_CHECKER_TYPE,
1342  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_VBUSM2AXI_EDC_GROUP_19_WIDTH },
1343  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_VBUSM2AXI_EDC_GROUP_20_CHECKER_TYPE,
1344  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_VBUSM2AXI_EDC_GROUP_20_WIDTH },
1345  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_VBUSM2AXI_EDC_GROUP_21_CHECKER_TYPE,
1346  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_VBUSM2AXI_EDC_GROUP_21_WIDTH },
1347  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_VBUSM2AXI_EDC_GROUP_22_CHECKER_TYPE,
1348  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_VBUSM2AXI_EDC_GROUP_22_WIDTH },
1349  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_VBUSM2AXI_EDC_GROUP_23_CHECKER_TYPE,
1350  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_VBUSM2AXI_EDC_GROUP_23_WIDTH },
1351  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_VBUSM2AXI_EDC_GROUP_24_CHECKER_TYPE,
1352  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_VBUSM2AXI_EDC_GROUP_24_WIDTH },
1353  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_VBUSM2AXI_EDC_GROUP_25_CHECKER_TYPE,
1354  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_VBUSM2AXI_EDC_GROUP_25_WIDTH },
1355  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_VBUSM2AXI_EDC_GROUP_26_CHECKER_TYPE,
1356  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_VBUSM2AXI_EDC_GROUP_26_WIDTH },
1357  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_VBUSM2AXI_EDC_GROUP_27_CHECKER_TYPE,
1358  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_VBUSM2AXI_EDC_GROUP_27_WIDTH },
1359  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_VBUSM2AXI_EDC_GROUP_28_CHECKER_TYPE,
1360  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_VBUSM2AXI_EDC_GROUP_28_WIDTH },
1361  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_VBUSM2AXI_EDC_GROUP_29_CHECKER_TYPE,
1362  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_VBUSM2AXI_EDC_GROUP_29_WIDTH },
1363  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_VBUSM2AXI_EDC_GROUP_30_CHECKER_TYPE,
1364  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_VBUSM2AXI_EDC_GROUP_30_WIDTH },
1365  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_VBUSM2AXI_EDC_GROUP_31_CHECKER_TYPE,
1366  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_VBUSM2AXI_EDC_GROUP_31_WIDTH },
1367  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_VBUSM2AXI_EDC_GROUP_32_CHECKER_TYPE,
1368  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_VBUSM2AXI_EDC_GROUP_32_WIDTH },
1369  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_VBUSM2AXI_EDC_GROUP_33_CHECKER_TYPE,
1370  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_VBUSM2AXI_EDC_GROUP_33_WIDTH },
1371  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_VBUSM2AXI_EDC_GROUP_34_CHECKER_TYPE,
1372  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_VBUSM2AXI_EDC_GROUP_34_WIDTH },
1373  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_VBUSM2AXI_EDC_GROUP_35_CHECKER_TYPE,
1374  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_VBUSM2AXI_EDC_GROUP_35_WIDTH },
1375 };
1376 
1382 static const SDL_GrpChkConfig_t SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_groupEntries[SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_MAX_NUM_CHECKERS] =
1383 {
1384  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
1385  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_GROUP_0_WIDTH },
1386  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
1387  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_GROUP_1_WIDTH },
1388  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
1389  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_GROUP_2_WIDTH },
1390  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
1391  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_GROUP_3_WIDTH },
1392  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
1393  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_GROUP_4_WIDTH },
1394  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
1395  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_GROUP_5_WIDTH },
1396  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
1397  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_GROUP_6_WIDTH },
1398  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
1399  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_GROUP_7_WIDTH },
1400  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
1401  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_GROUP_8_WIDTH },
1402  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
1403  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_GROUP_9_WIDTH },
1404  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
1405  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_GROUP_10_WIDTH },
1406  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
1407  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_GROUP_11_WIDTH },
1408  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
1409  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_GROUP_12_WIDTH },
1410  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
1411  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_GROUP_13_WIDTH },
1412  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
1413  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_GROUP_14_WIDTH },
1414  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
1415  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_GROUP_15_WIDTH },
1416  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
1417  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_GROUP_16_WIDTH },
1418  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
1419  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_GROUP_17_WIDTH },
1420  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
1421  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_GROUP_18_WIDTH },
1422  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
1423  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_GROUP_19_WIDTH },
1424  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
1425  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_GROUP_20_WIDTH },
1426  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
1427  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_GROUP_21_WIDTH },
1428  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
1429  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_GROUP_22_WIDTH },
1430  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
1431  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_GROUP_23_WIDTH },
1432  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
1433  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_GROUP_24_WIDTH },
1434  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
1435  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_GROUP_25_WIDTH },
1436  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
1437  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_GROUP_26_WIDTH },
1438  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
1439  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_GROUP_27_WIDTH },
1440  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
1441  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_GROUP_28_WIDTH },
1442  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
1443  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_GROUP_29_WIDTH },
1444  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
1445  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_GROUP_30_WIDTH },
1446  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
1447  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_GROUP_31_WIDTH },
1448  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
1449  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_GROUP_32_WIDTH },
1450  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_GROUP_33_CHECKER_TYPE,
1451  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_GROUP_33_WIDTH },
1452  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_GROUP_34_CHECKER_TYPE,
1453  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_GROUP_34_WIDTH },
1454  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_GROUP_35_CHECKER_TYPE,
1455  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_GROUP_35_WIDTH },
1456  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_GROUP_36_CHECKER_TYPE,
1457  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_GROUP_36_WIDTH },
1458 };
1459 
1465 static const SDL_GrpChkConfig_t SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_0_groupEntries[SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_0_MAX_NUM_CHECKERS] =
1466 {
1467  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
1468  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_0_GROUP_0_WIDTH },
1469  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
1470  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_0_GROUP_1_WIDTH },
1471  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
1472  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_0_GROUP_2_WIDTH },
1473  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
1474  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_0_GROUP_3_WIDTH },
1475  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
1476  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_0_GROUP_4_WIDTH },
1477  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
1478  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_0_GROUP_5_WIDTH },
1479  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
1480  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_0_GROUP_6_WIDTH },
1481  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
1482  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_0_GROUP_7_WIDTH },
1483  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
1484  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_0_GROUP_8_WIDTH },
1485  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
1486  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_0_GROUP_9_WIDTH },
1487  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
1488  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_0_GROUP_10_WIDTH },
1489  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
1490  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_0_GROUP_11_WIDTH },
1491  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
1492  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_0_GROUP_12_WIDTH },
1493  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
1494  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_0_GROUP_13_WIDTH },
1495  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
1496  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_0_GROUP_14_WIDTH },
1497 };
1498 
1504 static const SDL_GrpChkConfig_t SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_SCRP_EDC_groupEntries[SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_SCRP_EDC_MAX_NUM_CHECKERS] =
1505 {
1506  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_SCRP_EDC_GROUP_0_CHECKER_TYPE,
1507  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_SCRP_EDC_GROUP_0_WIDTH },
1508  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_SCRP_EDC_GROUP_1_CHECKER_TYPE,
1509  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_SCRP_EDC_GROUP_1_WIDTH },
1510  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_SCRP_EDC_GROUP_2_CHECKER_TYPE,
1511  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_SCRP_EDC_GROUP_2_WIDTH },
1512  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_SCRP_EDC_GROUP_3_CHECKER_TYPE,
1513  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_SCRP_EDC_GROUP_3_WIDTH },
1514  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_SCRP_EDC_GROUP_4_CHECKER_TYPE,
1515  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_SCRP_EDC_GROUP_4_WIDTH },
1516  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_SCRP_EDC_GROUP_5_CHECKER_TYPE,
1517  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_SCRP_EDC_GROUP_5_WIDTH },
1518  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_SCRP_EDC_GROUP_6_CHECKER_TYPE,
1519  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_SCRP_EDC_GROUP_6_WIDTH },
1520  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_SCRP_EDC_GROUP_7_CHECKER_TYPE,
1521  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_SCRP_EDC_GROUP_7_WIDTH },
1522  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_SCRP_EDC_GROUP_8_CHECKER_TYPE,
1523  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_SCRP_EDC_GROUP_8_WIDTH },
1524  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_SCRP_EDC_GROUP_9_CHECKER_TYPE,
1525  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_SCRP_EDC_GROUP_9_WIDTH },
1526  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_SCRP_EDC_GROUP_10_CHECKER_TYPE,
1527  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_SCRP_EDC_GROUP_10_WIDTH },
1528 };
1529 
1535 static const SDL_GrpChkConfig_t SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_groupEntries[SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS] =
1536 {
1537  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
1538  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
1539  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
1540  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
1541  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
1542  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
1543  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
1544  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
1545  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
1546  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
1547  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_5_CHECKER_TYPE,
1548  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_5_WIDTH },
1549  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_6_CHECKER_TYPE,
1550  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_6_WIDTH },
1551  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_7_CHECKER_TYPE,
1552  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_7_WIDTH },
1553  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_8_CHECKER_TYPE,
1554  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_8_WIDTH },
1555  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_9_CHECKER_TYPE,
1556  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_9_WIDTH },
1557  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_10_CHECKER_TYPE,
1558  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_10_WIDTH },
1559  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_11_CHECKER_TYPE,
1560  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_11_WIDTH },
1561  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_12_CHECKER_TYPE,
1562  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_12_WIDTH },
1563  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_13_CHECKER_TYPE,
1564  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_13_WIDTH },
1565  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_14_CHECKER_TYPE,
1566  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_14_WIDTH },
1567  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_15_CHECKER_TYPE,
1568  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_15_WIDTH },
1569  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_16_CHECKER_TYPE,
1570  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_16_WIDTH },
1571  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_17_CHECKER_TYPE,
1572  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_17_WIDTH },
1573  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_18_CHECKER_TYPE,
1574  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_18_WIDTH },
1575  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_19_CHECKER_TYPE,
1576  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_19_WIDTH },
1577  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_20_CHECKER_TYPE,
1578  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_20_WIDTH },
1579  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_21_CHECKER_TYPE,
1580  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_21_WIDTH },
1581  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_22_CHECKER_TYPE,
1582  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_22_WIDTH },
1583  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_23_CHECKER_TYPE,
1584  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_23_WIDTH },
1585  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_24_CHECKER_TYPE,
1586  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_24_WIDTH },
1587  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_25_CHECKER_TYPE,
1588  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_25_WIDTH },
1589  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_26_CHECKER_TYPE,
1590  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_26_WIDTH },
1591  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_27_CHECKER_TYPE,
1592  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_27_WIDTH },
1593  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_28_CHECKER_TYPE,
1594  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_28_WIDTH },
1595  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_29_CHECKER_TYPE,
1596  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_29_WIDTH },
1597  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_30_CHECKER_TYPE,
1598  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_30_WIDTH },
1599  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_31_CHECKER_TYPE,
1600  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_31_WIDTH },
1601  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_32_CHECKER_TYPE,
1602  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_32_WIDTH },
1603  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_33_CHECKER_TYPE,
1604  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_33_WIDTH },
1605  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_34_CHECKER_TYPE,
1606  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_34_WIDTH },
1607  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_35_CHECKER_TYPE,
1608  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_35_WIDTH },
1609  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_36_CHECKER_TYPE,
1610  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_36_WIDTH },
1611  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_37_CHECKER_TYPE,
1612  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_37_WIDTH },
1613  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_38_CHECKER_TYPE,
1614  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_38_WIDTH },
1615  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_39_CHECKER_TYPE,
1616  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_39_WIDTH },
1617  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_40_CHECKER_TYPE,
1618  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_40_WIDTH },
1619  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_41_CHECKER_TYPE,
1620  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_41_WIDTH },
1621  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_42_CHECKER_TYPE,
1622  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_42_WIDTH },
1623  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_43_CHECKER_TYPE,
1624  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_43_WIDTH },
1625  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_44_CHECKER_TYPE,
1626  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_44_WIDTH },
1627  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_45_CHECKER_TYPE,
1628  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_45_WIDTH },
1629  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_46_CHECKER_TYPE,
1630  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_46_WIDTH },
1631  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_47_CHECKER_TYPE,
1632  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_47_WIDTH },
1633  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_48_CHECKER_TYPE,
1634  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_48_WIDTH },
1635  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_49_CHECKER_TYPE,
1636  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_49_WIDTH },
1637  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_50_CHECKER_TYPE,
1638  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_50_WIDTH },
1639  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_51_CHECKER_TYPE,
1640  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_51_WIDTH },
1641  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_52_CHECKER_TYPE,
1642  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_52_WIDTH },
1643  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_53_CHECKER_TYPE,
1644  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_53_WIDTH },
1645  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_54_CHECKER_TYPE,
1646  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_54_WIDTH },
1647  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_55_CHECKER_TYPE,
1648  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_55_WIDTH },
1649  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_56_CHECKER_TYPE,
1650  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_56_WIDTH },
1651  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_57_CHECKER_TYPE,
1652  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_57_WIDTH },
1653  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_58_CHECKER_TYPE,
1654  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_58_WIDTH },
1655  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_59_CHECKER_TYPE,
1656  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_59_WIDTH },
1657  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_60_CHECKER_TYPE,
1658  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_60_WIDTH },
1659  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_61_CHECKER_TYPE,
1660  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_61_WIDTH },
1661  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_62_CHECKER_TYPE,
1662  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_62_WIDTH },
1663  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_63_CHECKER_TYPE,
1664  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_63_WIDTH },
1665  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_64_CHECKER_TYPE,
1666  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_64_WIDTH },
1667  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_65_CHECKER_TYPE,
1668  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_65_WIDTH },
1669  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_66_CHECKER_TYPE,
1670  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_66_WIDTH },
1671  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_67_CHECKER_TYPE,
1672  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_67_WIDTH },
1673 };
1674 
1680 static const SDL_GrpChkConfig_t SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_ECC_AGGR_EDC_CTRL_groupEntries[SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_ECC_AGGR_EDC_CTRL_MAX_NUM_CHECKERS] =
1681 {
1682  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_ECC_AGGR_EDC_CTRL_GROUP_0_CHECKER_TYPE,
1683  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_ECC_AGGR_EDC_CTRL_GROUP_0_WIDTH },
1684  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_ECC_AGGR_EDC_CTRL_GROUP_1_CHECKER_TYPE,
1685  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_ECC_AGGR_EDC_CTRL_GROUP_1_WIDTH },
1686  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_ECC_AGGR_EDC_CTRL_GROUP_2_CHECKER_TYPE,
1687  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_ECC_AGGR_EDC_CTRL_GROUP_2_WIDTH },
1688  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_ECC_AGGR_EDC_CTRL_GROUP_3_CHECKER_TYPE,
1689  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_ECC_AGGR_EDC_CTRL_GROUP_3_WIDTH },
1690  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_ECC_AGGR_EDC_CTRL_GROUP_4_CHECKER_TYPE,
1691  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_ECC_AGGR_EDC_CTRL_GROUP_4_WIDTH },
1692  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_ECC_AGGR_EDC_CTRL_GROUP_5_CHECKER_TYPE,
1693  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_ECC_AGGR_EDC_CTRL_GROUP_5_WIDTH },
1694 };
1695 
1700 static const SDL_MemConfig_t SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR_MemEntries[SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES] =
1701 {
1702  { SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR_ALE_RAM_RAM_ID, 0u,
1703  SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR_ALE_RAM_RAM_SIZE, 71u,
1704  SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR_ALE_RAM_ROW_WIDTH, ((bool)false) },
1705  { SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR_CPSW_3GU_CORE_ECC_ECC_CTRL1_RAM_ID, 0u,
1706  SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR_CPSW_3GU_CORE_ECC_ECC_CTRL1_RAM_SIZE, 32u,
1707  SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR_CPSW_3GU_CORE_ECC_ECC_CTRL1_ROW_WIDTH, ((bool)false) },
1708  { SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR_CPSW_3GU_CORE_ECC_ECC_CTRL2_RAM_ID, 0u,
1709  SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR_CPSW_3GU_CORE_ECC_ECC_CTRL2_RAM_SIZE, 32u,
1710  SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR_CPSW_3GU_CORE_ECC_ECC_CTRL2_ROW_WIDTH, ((bool)false) },
1711  { SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR_CPSW_3GU_CORE_ECC_ECC_CTRL3_RAM_ID, 0u,
1712  SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR_CPSW_3GU_CORE_ECC_ECC_CTRL3_RAM_SIZE, 32u,
1713  SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR_CPSW_3GU_CORE_ECC_ECC_CTRL3_ROW_WIDTH, ((bool)false) },
1714  { SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR_CPSW_3GU_CORE_ECC_ECC_CTRL4_RAM_ID, 0u,
1715  SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR_CPSW_3GU_CORE_ECC_ECC_CTRL4_RAM_SIZE, 32u,
1716  SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR_CPSW_3GU_CORE_ECC_ECC_CTRL4_ROW_WIDTH, ((bool)false) },
1717  { SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR_CPSW_3GU_CORE_ECC_ECC_CTRL5_RAM_ID, 0u,
1718  SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR_CPSW_3GU_CORE_ECC_ECC_CTRL5_RAM_SIZE, 32u,
1719  SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR_CPSW_3GU_CORE_ECC_ECC_CTRL5_ROW_WIDTH, ((bool)false) },
1720  { SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR_CPSW_3GU_CORE_ECC_ECC_CTRL6_RAM_ID, 0u,
1721  SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR_CPSW_3GU_CORE_ECC_ECC_CTRL6_RAM_SIZE, 32u,
1722  SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR_CPSW_3GU_CORE_ECC_ECC_CTRL6_ROW_WIDTH, ((bool)false) },
1723  { SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR_EST_RAM_RAM_ID, 0u,
1724  SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR_EST_RAM_RAM_SIZE, 4u,
1725  SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR_EST_RAM_ROW_WIDTH, ((bool)false) },
1726 };
1727 
1732 static const SDL_MemConfig_t SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MemEntries[SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES] =
1733 {
1734  { SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_ECC0_RAM_ID, 0x79100000u,
1735  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_ECC0_RAM_SIZE, 4u,
1736  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_ECC0_ROW_WIDTH, ((bool)true) },
1737 };
1738 
1744 static const SDL_GrpChkConfig_t SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_groupEntries[SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_MAX_NUM_CHECKERS] =
1745 {
1746  { SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
1747  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_0_WIDTH },
1748  { SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
1749  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_1_WIDTH },
1750  { SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
1751  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_2_WIDTH },
1752  { SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
1753  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_3_WIDTH },
1754  { SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
1755  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_4_WIDTH },
1756  { SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
1757  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_5_WIDTH },
1758  { SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
1759  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_6_WIDTH },
1760  { SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
1761  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_7_WIDTH },
1762  { SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
1763  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_8_WIDTH },
1764  { SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
1765  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_9_WIDTH },
1766  { SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
1767  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_10_WIDTH },
1768  { SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
1769  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_11_WIDTH },
1770  { SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
1771  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_12_WIDTH },
1772  { SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
1773  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_13_WIDTH },
1774  { SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
1775  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_14_WIDTH },
1776  { SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
1777  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_15_WIDTH },
1778  { SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
1779  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_16_WIDTH },
1780  { SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
1781  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_17_WIDTH },
1782  { SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
1783  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_18_WIDTH },
1784  { SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
1785  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_19_WIDTH },
1786  { SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
1787  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_20_WIDTH },
1788  { SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
1789  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_21_WIDTH },
1790  { SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
1791  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_22_WIDTH },
1792  { SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
1793  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_23_WIDTH },
1794  { SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
1795  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_24_WIDTH },
1796  { SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
1797  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_25_WIDTH },
1798  { SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
1799  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_26_WIDTH },
1800  { SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
1801  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_27_WIDTH },
1802  { SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
1803  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_28_WIDTH },
1804  { SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
1805  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_29_WIDTH },
1806  { SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
1807  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_30_WIDTH },
1808  { SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
1809  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_31_WIDTH },
1810  { SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
1811  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_32_WIDTH },
1812  { SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_33_CHECKER_TYPE,
1813  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_33_WIDTH },
1814  { SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_34_CHECKER_TYPE,
1815  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_34_WIDTH },
1816  { SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_35_CHECKER_TYPE,
1817  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_35_WIDTH },
1818  { SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_36_CHECKER_TYPE,
1819  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_36_WIDTH },
1820  { SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_37_CHECKER_TYPE,
1821  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_37_WIDTH },
1822  { SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_38_CHECKER_TYPE,
1823  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_38_WIDTH },
1824  { SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_39_CHECKER_TYPE,
1825  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_39_WIDTH },
1826  { SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_40_CHECKER_TYPE,
1827  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_40_WIDTH },
1828  { SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_41_CHECKER_TYPE,
1829  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_41_WIDTH },
1830  { SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_42_CHECKER_TYPE,
1831  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_42_WIDTH },
1832  { SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_43_CHECKER_TYPE,
1833  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_43_WIDTH },
1834  { SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_44_CHECKER_TYPE,
1835  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_44_WIDTH },
1836  { SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_45_CHECKER_TYPE,
1837  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_45_WIDTH },
1838  { SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_46_CHECKER_TYPE,
1839  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_46_WIDTH },
1840  { SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_47_CHECKER_TYPE,
1841  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_47_WIDTH },
1842  { SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_48_CHECKER_TYPE,
1843  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_48_WIDTH },
1844  { SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_49_CHECKER_TYPE,
1845  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_49_WIDTH },
1846  { SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_50_CHECKER_TYPE,
1847  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_50_WIDTH },
1848  { SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_51_CHECKER_TYPE,
1849  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_51_WIDTH },
1850  { SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_52_CHECKER_TYPE,
1851  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_52_WIDTH },
1852  { SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_53_CHECKER_TYPE,
1853  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_53_WIDTH },
1854  { SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_54_CHECKER_TYPE,
1855  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_54_WIDTH },
1856  { SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_55_CHECKER_TYPE,
1857  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_55_WIDTH },
1858  { SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_56_CHECKER_TYPE,
1859  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_56_WIDTH },
1860  { SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_57_CHECKER_TYPE,
1861  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_57_WIDTH },
1862  { SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_58_CHECKER_TYPE,
1863  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_58_WIDTH },
1864  { SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_59_CHECKER_TYPE,
1865  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_59_WIDTH },
1866  { SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_60_CHECKER_TYPE,
1867  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_60_WIDTH },
1868  { SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_61_CHECKER_TYPE,
1869  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_61_WIDTH },
1870  { SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_62_CHECKER_TYPE,
1871  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_62_WIDTH },
1872  { SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_63_CHECKER_TYPE,
1873  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_63_WIDTH },
1874  { SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_64_CHECKER_TYPE,
1875  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_64_WIDTH },
1876 };
1877 
1883 static const SDL_GrpChkConfig_t SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_ECC_AGGR_EDC_CTRL_groupEntries[SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_ECC_AGGR_EDC_CTRL_MAX_NUM_CHECKERS] =
1884 {
1885  { SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_ECC_AGGR_EDC_CTRL_GROUP_0_CHECKER_TYPE,
1886  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_ECC_AGGR_EDC_CTRL_GROUP_0_WIDTH },
1887  { SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_ECC_AGGR_EDC_CTRL_GROUP_1_CHECKER_TYPE,
1888  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_ECC_AGGR_EDC_CTRL_GROUP_1_WIDTH },
1889  { SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_ECC_AGGR_EDC_CTRL_GROUP_2_CHECKER_TYPE,
1890  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_ECC_AGGR_EDC_CTRL_GROUP_2_WIDTH },
1891  { SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_ECC_AGGR_EDC_CTRL_GROUP_3_CHECKER_TYPE,
1892  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_ECC_AGGR_EDC_CTRL_GROUP_3_WIDTH },
1893  { SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_ECC_AGGR_EDC_CTRL_GROUP_4_CHECKER_TYPE,
1894  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_ECC_AGGR_EDC_CTRL_GROUP_4_WIDTH },
1895  { SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_ECC_AGGR_EDC_CTRL_GROUP_5_CHECKER_TYPE,
1896  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_ECC_AGGR_EDC_CTRL_GROUP_5_WIDTH },
1897 };
1898 
1903 static const SDL_MemConfig_t SDL_GICSS0_GIC500SS_1_4_ECC_AGGR_MemEntries[SDL_GICSS0_GIC500SS_1_4_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES] =
1904 {
1905  { SDL_GICSS0_GIC500SS_1_4_ECC_AGGR_ICB_RAMECC_RAM_ID, 0u,
1906  SDL_GICSS0_GIC500SS_1_4_ECC_AGGR_ICB_RAMECC_RAM_SIZE, 4u,
1907  SDL_GICSS0_GIC500SS_1_4_ECC_AGGR_ICB_RAMECC_ROW_WIDTH, ((bool)true) },
1908  { SDL_GICSS0_GIC500SS_1_4_ECC_AGGR_ITE_RAMECC_RAM_ID, 0u,
1909  SDL_GICSS0_GIC500SS_1_4_ECC_AGGR_ITE_RAMECC_RAM_SIZE, 8u,
1910  SDL_GICSS0_GIC500SS_1_4_ECC_AGGR_ITE_RAMECC_ROW_WIDTH, ((bool)true) },
1911  { SDL_GICSS0_GIC500SS_1_4_ECC_AGGR_LPI_RAMECC_RAM_ID, 0u,
1912  SDL_GICSS0_GIC500SS_1_4_ECC_AGGR_LPI_RAMECC_RAM_SIZE, 4u,
1913  SDL_GICSS0_GIC500SS_1_4_ECC_AGGR_LPI_RAMECC_ROW_WIDTH, ((bool)true) },
1914 };
1915 
1921 static const SDL_GrpChkConfig_t SDL_ECC_AGGR1_SAM62A_SEC_MCU_ECC_AGGR_AM62A_MAIN_FW_CBASS_IAM62A_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM62A_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_groupEntries[SDL_ECC_AGGR1_SAM62A_SEC_MCU_ECC_AGGR_AM62A_MAIN_FW_CBASS_IAM62A_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM62A_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS] =
1922 {
1923  { SDL_ECC_AGGR1_SAM62A_SEC_MCU_ECC_AGGR_AM62A_MAIN_FW_CBASS_IAM62A_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM62A_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_GROUP_0_CHECKER_TYPE,
1924  SDL_ECC_AGGR1_SAM62A_SEC_MCU_ECC_AGGR_AM62A_MAIN_FW_CBASS_IAM62A_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM62A_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_GROUP_0_WIDTH },
1925  { SDL_ECC_AGGR1_SAM62A_SEC_MCU_ECC_AGGR_AM62A_MAIN_FW_CBASS_IAM62A_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM62A_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_GROUP_1_CHECKER_TYPE,
1926  SDL_ECC_AGGR1_SAM62A_SEC_MCU_ECC_AGGR_AM62A_MAIN_FW_CBASS_IAM62A_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM62A_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_GROUP_1_WIDTH },
1927  { SDL_ECC_AGGR1_SAM62A_SEC_MCU_ECC_AGGR_AM62A_MAIN_FW_CBASS_IAM62A_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM62A_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_GROUP_2_CHECKER_TYPE,
1928  SDL_ECC_AGGR1_SAM62A_SEC_MCU_ECC_AGGR_AM62A_MAIN_FW_CBASS_IAM62A_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM62A_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_GROUP_2_WIDTH },
1929  { SDL_ECC_AGGR1_SAM62A_SEC_MCU_ECC_AGGR_AM62A_MAIN_FW_CBASS_IAM62A_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM62A_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_GROUP_3_CHECKER_TYPE,
1930  SDL_ECC_AGGR1_SAM62A_SEC_MCU_ECC_AGGR_AM62A_MAIN_FW_CBASS_IAM62A_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM62A_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_GROUP_3_WIDTH },
1931 };
1932 
1937 static const SDL_MemConfig_t SDL_DMASS0_DMSS_AM62A_ECCAGGR_MemEntries[SDL_DMASS0_DMSS_AM62A_ECCAGGR_RAM_IDS_TOTAL_ENTRIES] =
1938 {
1939  { SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_PKTDMA_CFG_CONFIG_RAM_ID, 0u,
1940  SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_PKTDMA_CFG_CONFIG_RAM_SIZE, 12u,
1941  SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_PKTDMA_CFG_CONFIG_ROW_WIDTH, ((bool)false) },
1942  { SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_PKTDMA_CFG_STATE_RAM_ID, 0u,
1943  SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_PKTDMA_CFG_STATE_RAM_SIZE, 28u,
1944  SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_PKTDMA_CFG_STATE_ROW_WIDTH, ((bool)false) },
1945  { SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_PKTDMA_TPCFIFO_F0_RAM_ID, 0u,
1946  SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_PKTDMA_TPCFIFO_F0_RAM_SIZE, 18u,
1947  SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_PKTDMA_TPCFIFO_F0_ROW_WIDTH, ((bool)false) },
1948  { SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_PKTDMA_TPCFIFO_F1_RAM_ID, 0u,
1949  SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_PKTDMA_TPCFIFO_F1_RAM_SIZE, 18u,
1950  SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_PKTDMA_TPCFIFO_F1_ROW_WIDTH, ((bool)false) },
1951  { SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_PKTDMA_RPCFIFO_F0_RAM_ID, 0u,
1952  SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_PKTDMA_RPCFIFO_F0_RAM_SIZE, 16u,
1953  SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_PKTDMA_RPCFIFO_F0_ROW_WIDTH, ((bool)false) },
1954  { SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_PKTDMA_RPCFIFO_F1_RAM_ID, 0u,
1955  SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_PKTDMA_RPCFIFO_F1_RAM_SIZE, 16u,
1956  SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_PKTDMA_RPCFIFO_F1_ROW_WIDTH, ((bool)false) },
1957  { SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_PKTDMA_RPCFIFO_WC_RAM_ID, 0u,
1958  SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_PKTDMA_RPCFIFO_WC_RAM_SIZE, 4u,
1959  SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_PKTDMA_RPCFIFO_WC_ROW_WIDTH, ((bool)false) },
1960  { SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_PKTDMA_STATS_STST0_RAM_ID, 0u,
1961  SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_PKTDMA_STATS_STST0_RAM_SIZE, 12u,
1962  SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_PKTDMA_STATS_STST0_ROW_WIDTH, ((bool)false) },
1963  { SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_PKTDMA_STATS_STSR0_RAM_ID, 0u,
1964  SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_PKTDMA_STATS_STSR0_RAM_SIZE, 16u,
1965  SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_PKTDMA_STATS_STSR0_ROW_WIDTH, ((bool)false) },
1966  { SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_PKTDMA_RINGOCC_CNTR_RAM_ID, 0u,
1967  SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_PKTDMA_RINGOCC_CNTR_RAM_SIZE, 4u,
1968  SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_PKTDMA_RINGOCC_CNTR_ROW_WIDTH, ((bool)false) },
1969  { SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_BCDMA_CFG_CONFIG_RAM_ID, 0u,
1970  SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_BCDMA_CFG_CONFIG_RAM_SIZE, 11u,
1971  SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_BCDMA_CFG_CONFIG_ROW_WIDTH, ((bool)false) },
1972  { SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_BCDMA_CFG_STATE_RAM_ID, 0u,
1973  SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_BCDMA_CFG_STATE_RAM_SIZE, 50u,
1974  SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_BCDMA_CFG_STATE_ROW_WIDTH, ((bool)false) },
1975  { SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_BCDMA_PCFIFO_DFIFO_F0_RAM_ID, 0u,
1976  SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_BCDMA_PCFIFO_DFIFO_F0_RAM_SIZE, 16u,
1977  SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_BCDMA_PCFIFO_DFIFO_F0_ROW_WIDTH, ((bool)false) },
1978  { SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_BCDMA_PCFIFO_DFIFO_F1_RAM_ID, 0u,
1979  SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_BCDMA_PCFIFO_DFIFO_F1_RAM_SIZE, 16u,
1980  SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_BCDMA_PCFIFO_DFIFO_F1_ROW_WIDTH, ((bool)false) },
1981  { SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_BCDMA_TPCFIFO_F0_RAM_ID, 0u,
1982  SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_BCDMA_TPCFIFO_F0_RAM_SIZE, 18u,
1983  SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_BCDMA_TPCFIFO_F0_ROW_WIDTH, ((bool)false) },
1984  { SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_BCDMA_TPCFIFO_F1_RAM_ID, 0u,
1985  SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_BCDMA_TPCFIFO_F1_RAM_SIZE, 18u,
1986  SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_BCDMA_TPCFIFO_F1_ROW_WIDTH, ((bool)false) },
1987  { SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_BCDMA_RPCFIFO_F0_RAM_ID, 0u,
1988  SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_BCDMA_RPCFIFO_F0_RAM_SIZE, 16u,
1989  SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_BCDMA_RPCFIFO_F0_ROW_WIDTH, ((bool)false) },
1990  { SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_BCDMA_RPCFIFO_F1_RAM_ID, 0u,
1991  SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_BCDMA_RPCFIFO_F1_RAM_SIZE, 16u,
1992  SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_BCDMA_RPCFIFO_F1_ROW_WIDTH, ((bool)false) },
1993  { SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_BCDMA_RPCFIFO_WC_RAM_ID, 0u,
1994  SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_BCDMA_RPCFIFO_WC_RAM_SIZE, 4u,
1995  SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_BCDMA_RPCFIFO_WC_ROW_WIDTH, ((bool)false) },
1996  { SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_BCDMA_STATS_STST0_RAM_ID, 0u,
1997  SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_BCDMA_STATS_STST0_RAM_SIZE, 12u,
1998  SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_BCDMA_STATS_STST0_ROW_WIDTH, ((bool)false) },
1999  { SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_BCDMA_STATS_STSR0_RAM_ID, 0u,
2000  SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_BCDMA_STATS_STSR0_RAM_SIZE, 12u,
2001  SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_BCDMA_STATS_STSR0_ROW_WIDTH, ((bool)false) },
2002  { SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_BCDMA_RINGOCC_CNTR_RAM_ID, 0u,
2003  SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_BCDMA_RINGOCC_CNTR_RAM_SIZE, 4u,
2004  SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_BCDMA_RINGOCC_CNTR_ROW_WIDTH, ((bool)false) },
2005  { SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_INTAGGR_STATREG_SR_SPRAM_184X128_SWW_SR_RAM_ID, 0u,
2006  SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_INTAGGR_STATREG_SR_SPRAM_184X128_SWW_SR_RAM_SIZE, 16u,
2007  SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_INTAGGR_STATREG_SR_SPRAM_184X128_SWW_SR_ROW_WIDTH, ((bool)false) },
2008  { SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_INTAGGR_COMMON_IM_TPRAM_1531X34_SWW_SR_RAM_ID, 0u,
2009  SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_INTAGGR_COMMON_IM_TPRAM_1531X34_SWW_SR_RAM_SIZE, 5u,
2010  SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_INTAGGR_COMMON_IM_TPRAM_1531X34_SWW_SR_ROW_WIDTH, ((bool)false) },
2011  { SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_IPCSS_RINGACC_STRAM_RAM_ID, 0u,
2012  SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_IPCSS_RINGACC_STRAM_RAM_SIZE, 27u,
2013  SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_IPCSS_RINGACC_STRAM_ROW_WIDTH, ((bool)false) },
2014  { SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_IPCSS_SEC_PROXY_BUF_STRAM_RAM_ID, 0u,
2015  SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_IPCSS_SEC_PROXY_BUF_STRAM_RAM_SIZE, 12u,
2016  SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_IPCSS_SEC_PROXY_BUF_STRAM_ROW_WIDTH, ((bool)false) },
2017  { SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_IPCSS_SEC_PROXY_BUF_BUFRAM_RAM_ID, 0u,
2018  SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_IPCSS_SEC_PROXY_BUF_BUFRAM_RAM_SIZE, 8u,
2019  SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_IPCSS_SEC_PROXY_BUF_BUFRAM_ROW_WIDTH, ((bool)false) },
2020  { SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_IPCSS_MSRAM_ECC0_RAM_ID, 0u,
2021  SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_IPCSS_MSRAM_ECC0_RAM_SIZE, 8u,
2022  SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_IPCSS_MSRAM_ECC0_ROW_WIDTH, ((bool)false) },
2023 };
2024 
2029 static const SDL_MemConfig_t SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_RXMEM_MemEntries[SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_RXMEM_RAM_IDS_TOTAL_ENTRIES] =
2030 {
2031  { SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_RXMEM_EMMCSD4SS_SDHC_WRAP_RXMEM_RAM_ID, 0u,
2032  SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_RXMEM_EMMCSD4SS_SDHC_WRAP_RXMEM_RAM_SIZE, 8u,
2033  SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_RXMEM_EMMCSD4SS_SDHC_WRAP_RXMEM_ROW_WIDTH, ((bool)false) },
2034 };
2035 
2040 static const SDL_MemConfig_t SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_TXMEM_MemEntries[SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_TXMEM_RAM_IDS_TOTAL_ENTRIES] =
2041 {
2042  { SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_TXMEM_EMMCSD4SS_SDHC_WRAP_TXMEM_RAM_ID, 0u,
2043  SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_TXMEM_EMMCSD4SS_SDHC_WRAP_TXMEM_RAM_SIZE, 8u,
2044  SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_TXMEM_EMMCSD4SS_SDHC_WRAP_TXMEM_ROW_WIDTH, ((bool)false) },
2045 };
2046 
2051 static const SDL_MemConfig_t SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_RXMEM_MemEntries[SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_RXMEM_RAM_IDS_TOTAL_ENTRIES] =
2052 {
2053  { SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_RXMEM_EMMCSD4SS_SDHC_WRAP_RXMEM_RAM_ID, 0u,
2054  SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_RXMEM_EMMCSD4SS_SDHC_WRAP_RXMEM_RAM_SIZE, 8u,
2055  SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_RXMEM_EMMCSD4SS_SDHC_WRAP_RXMEM_ROW_WIDTH, ((bool)false) },
2056 };
2057 
2062 static const SDL_MemConfig_t SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_TXMEM_MemEntries[SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_TXMEM_RAM_IDS_TOTAL_ENTRIES] =
2063 {
2064  { SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_TXMEM_EMMCSD4SS_SDHC_WRAP_TXMEM_RAM_ID, 0u,
2065  SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_TXMEM_EMMCSD4SS_SDHC_WRAP_TXMEM_RAM_SIZE, 8u,
2066  SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_TXMEM_EMMCSD4SS_SDHC_WRAP_TXMEM_ROW_WIDTH, ((bool)false) },
2067 };
2068 
2073 static const SDL_MemConfig_t SDL_MMCSD0_EMMCSD8SS_ECC_AGGR_TXMEM_MemEntries[SDL_MMCSD0_EMMCSD8SS_ECC_AGGR_TXMEM_RAM_IDS_TOTAL_ENTRIES] =
2074 {
2075  { SDL_MMCSD0_EMMCSD8SS_ECC_AGGR_TXMEM_EMMCSD8SS_SDHC_WRAP_TXMEM_RAM_ID, 0u,
2076  SDL_MMCSD0_EMMCSD8SS_ECC_AGGR_TXMEM_EMMCSD8SS_SDHC_WRAP_TXMEM_RAM_SIZE, 8u,
2077  SDL_MMCSD0_EMMCSD8SS_ECC_AGGR_TXMEM_EMMCSD8SS_SDHC_WRAP_TXMEM_ROW_WIDTH, ((bool)false) },
2078 };
2079 
2084 static const SDL_MemConfig_t SDL_MMCSD0_EMMCSD8SS_ECC_AGGR_RXMEM_MemEntries[SDL_MMCSD0_EMMCSD8SS_ECC_AGGR_RXMEM_RAM_IDS_TOTAL_ENTRIES] =
2085 {
2086  { SDL_MMCSD0_EMMCSD8SS_ECC_AGGR_RXMEM_EMMCSD8SS_SDHC_WRAP_RXMEM_RAM_ID, 0u,
2087  SDL_MMCSD0_EMMCSD8SS_ECC_AGGR_RXMEM_EMMCSD8SS_SDHC_WRAP_RXMEM_RAM_SIZE, 8u,
2088  SDL_MMCSD0_EMMCSD8SS_ECC_AGGR_RXMEM_EMMCSD8SS_SDHC_WRAP_RXMEM_ROW_WIDTH, ((bool)false) },
2089 };
2090 
2095 static const SDL_MemConfig_t SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_MemEntries[SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES] =
2096 {
2097  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_RD_RAMECC_RAM_ID, 0u,
2098  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_RD_RAMECC_RAM_SIZE, 10u,
2099  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_RD_RAMECC_ROW_WIDTH, ((bool)false) },
2100  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_WR_RAMECC_RAM_ID, 0u,
2101  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_WR_RAMECC_RAM_SIZE, 10u,
2102  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_WR_RAMECC_ROW_WIDTH, ((bool)false) },
2103 };
2104 
2110 static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_groupEntries[SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_MAX_NUM_CHECKERS] =
2111 {
2112  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_0_CHECKER_TYPE,
2113  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_0_WIDTH },
2114  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_1_CHECKER_TYPE,
2115  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_1_WIDTH },
2116  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_2_CHECKER_TYPE,
2117  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_2_WIDTH },
2118  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_3_CHECKER_TYPE,
2119  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_3_WIDTH },
2120  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_4_CHECKER_TYPE,
2121  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_4_WIDTH },
2122  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_5_CHECKER_TYPE,
2123  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_5_WIDTH },
2124  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_6_CHECKER_TYPE,
2125  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_6_WIDTH },
2126  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_7_CHECKER_TYPE,
2127  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_7_WIDTH },
2128  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_8_CHECKER_TYPE,
2129  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_8_WIDTH },
2130  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_9_CHECKER_TYPE,
2131  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_9_WIDTH },
2132  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_10_CHECKER_TYPE,
2133  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_10_WIDTH },
2134  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_11_CHECKER_TYPE,
2135  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_11_WIDTH },
2136  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_12_CHECKER_TYPE,
2137  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_12_WIDTH },
2138  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_13_CHECKER_TYPE,
2139  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_13_WIDTH },
2140  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_14_CHECKER_TYPE,
2141  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_14_WIDTH },
2142  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_15_CHECKER_TYPE,
2143  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_15_WIDTH },
2144  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_16_CHECKER_TYPE,
2145  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_16_WIDTH },
2146  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_17_CHECKER_TYPE,
2147  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_17_WIDTH },
2148  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_18_CHECKER_TYPE,
2149  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_18_WIDTH },
2150  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_19_CHECKER_TYPE,
2151  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_19_WIDTH },
2152  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_20_CHECKER_TYPE,
2153  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_20_WIDTH },
2154  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_21_CHECKER_TYPE,
2155  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_21_WIDTH },
2156  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_22_CHECKER_TYPE,
2157  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_22_WIDTH },
2158  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_23_CHECKER_TYPE,
2159  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_23_WIDTH },
2160  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_24_CHECKER_TYPE,
2161  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_24_WIDTH },
2162  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_25_CHECKER_TYPE,
2163  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_25_WIDTH },
2164  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_26_CHECKER_TYPE,
2165  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_26_WIDTH },
2166  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_27_CHECKER_TYPE,
2167  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_27_WIDTH },
2168  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_28_CHECKER_TYPE,
2169  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_28_WIDTH },
2170  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_29_CHECKER_TYPE,
2171  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_29_WIDTH },
2172  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_30_CHECKER_TYPE,
2173  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_30_WIDTH },
2174  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_31_CHECKER_TYPE,
2175  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_31_WIDTH },
2176  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_32_CHECKER_TYPE,
2177  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_32_WIDTH },
2178  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_33_CHECKER_TYPE,
2179  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_33_WIDTH },
2180  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_34_CHECKER_TYPE,
2181  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_34_WIDTH },
2182  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_35_CHECKER_TYPE,
2183  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_35_WIDTH },
2184  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_36_CHECKER_TYPE,
2185  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_36_WIDTH },
2186  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_37_CHECKER_TYPE,
2187  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_37_WIDTH },
2188  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_38_CHECKER_TYPE,
2189  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_38_WIDTH },
2190  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_39_CHECKER_TYPE,
2191  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_39_WIDTH },
2192  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_40_CHECKER_TYPE,
2193  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_40_WIDTH },
2194  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_41_CHECKER_TYPE,
2195  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_41_WIDTH },
2196  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_42_CHECKER_TYPE,
2197  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_42_WIDTH },
2198  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_43_CHECKER_TYPE,
2199  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_43_WIDTH },
2200  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_44_CHECKER_TYPE,
2201  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_44_WIDTH },
2202  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_45_CHECKER_TYPE,
2203  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_45_WIDTH },
2204  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_46_CHECKER_TYPE,
2205  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_46_WIDTH },
2206  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_47_CHECKER_TYPE,
2207  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_47_WIDTH },
2208  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_48_CHECKER_TYPE,
2209  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_48_WIDTH },
2210  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_49_CHECKER_TYPE,
2211  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_49_WIDTH },
2212  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_50_CHECKER_TYPE,
2213  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_50_WIDTH },
2214  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_51_CHECKER_TYPE,
2215  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_51_WIDTH },
2216  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_52_CHECKER_TYPE,
2217  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_52_WIDTH },
2218  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_53_CHECKER_TYPE,
2219  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_53_WIDTH },
2220  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_54_CHECKER_TYPE,
2221  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_54_WIDTH },
2222  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_55_CHECKER_TYPE,
2223  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_55_WIDTH },
2224  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_56_CHECKER_TYPE,
2225  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_56_WIDTH },
2226  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_57_CHECKER_TYPE,
2227  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_57_WIDTH },
2228  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_58_CHECKER_TYPE,
2229  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_58_WIDTH },
2230  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_59_CHECKER_TYPE,
2231  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_59_WIDTH },
2232  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_60_CHECKER_TYPE,
2233  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_60_WIDTH },
2234  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_61_CHECKER_TYPE,
2235  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_61_WIDTH },
2236  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_62_CHECKER_TYPE,
2237  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_62_WIDTH },
2238  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_63_CHECKER_TYPE,
2239  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_63_WIDTH },
2240  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_64_CHECKER_TYPE,
2241  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_64_WIDTH },
2242  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_65_CHECKER_TYPE,
2243  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_65_WIDTH },
2244  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_66_CHECKER_TYPE,
2245  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_66_WIDTH },
2246  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_67_CHECKER_TYPE,
2247  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_67_WIDTH },
2248  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_68_CHECKER_TYPE,
2249  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_68_WIDTH },
2250 };
2251 
2257 static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_groupEntries[SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_MAX_NUM_CHECKERS] =
2258 {
2259  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_0_CHECKER_TYPE,
2260  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_0_WIDTH },
2261  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_1_CHECKER_TYPE,
2262  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_1_WIDTH },
2263  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_2_CHECKER_TYPE,
2264  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_2_WIDTH },
2265  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_3_CHECKER_TYPE,
2266  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_3_WIDTH },
2267  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_4_CHECKER_TYPE,
2268  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_4_WIDTH },
2269  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_5_CHECKER_TYPE,
2270  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_5_WIDTH },
2271  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_6_CHECKER_TYPE,
2272  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_6_WIDTH },
2273  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_7_CHECKER_TYPE,
2274  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_7_WIDTH },
2275  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_8_CHECKER_TYPE,
2276  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_8_WIDTH },
2277  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_9_CHECKER_TYPE,
2278  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_9_WIDTH },
2279  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_10_CHECKER_TYPE,
2280  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_10_WIDTH },
2281  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_11_CHECKER_TYPE,
2282  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_11_WIDTH },
2283  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_12_CHECKER_TYPE,
2284  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_12_WIDTH },
2285  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_13_CHECKER_TYPE,
2286  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_13_WIDTH },
2287  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_14_CHECKER_TYPE,
2288  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_14_WIDTH },
2289  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_15_CHECKER_TYPE,
2290  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_15_WIDTH },
2291  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_16_CHECKER_TYPE,
2292  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_16_WIDTH },
2293  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_17_CHECKER_TYPE,
2294  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_17_WIDTH },
2295  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_18_CHECKER_TYPE,
2296  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_18_WIDTH },
2297  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_19_CHECKER_TYPE,
2298  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_19_WIDTH },
2299  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_20_CHECKER_TYPE,
2300  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_20_WIDTH },
2301  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_21_CHECKER_TYPE,
2302  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_21_WIDTH },
2303  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_22_CHECKER_TYPE,
2304  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_22_WIDTH },
2305  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_23_CHECKER_TYPE,
2306  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_23_WIDTH },
2307  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_24_CHECKER_TYPE,
2308  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_24_WIDTH },
2309  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_25_CHECKER_TYPE,
2310  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_25_WIDTH },
2311  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_26_CHECKER_TYPE,
2312  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_26_WIDTH },
2313  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_27_CHECKER_TYPE,
2314  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_27_WIDTH },
2315  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_28_CHECKER_TYPE,
2316  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_28_WIDTH },
2317  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_29_CHECKER_TYPE,
2318  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_29_WIDTH },
2319  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_30_CHECKER_TYPE,
2320  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_30_WIDTH },
2321  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_31_CHECKER_TYPE,
2322  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_31_WIDTH },
2323  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_32_CHECKER_TYPE,
2324  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_32_WIDTH },
2325  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_33_CHECKER_TYPE,
2326  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_33_WIDTH },
2327  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_34_CHECKER_TYPE,
2328  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_34_WIDTH },
2329  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_35_CHECKER_TYPE,
2330  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_35_WIDTH },
2331  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_36_CHECKER_TYPE,
2332  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_36_WIDTH },
2333  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_37_CHECKER_TYPE,
2334  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_37_WIDTH },
2335  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_38_CHECKER_TYPE,
2336  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_38_WIDTH },
2337  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_39_CHECKER_TYPE,
2338  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_39_WIDTH },
2339  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_40_CHECKER_TYPE,
2340  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_40_WIDTH },
2341  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_41_CHECKER_TYPE,
2342  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_41_WIDTH },
2343  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_42_CHECKER_TYPE,
2344  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_42_WIDTH },
2345  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_43_CHECKER_TYPE,
2346  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_43_WIDTH },
2347  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_44_CHECKER_TYPE,
2348  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_44_WIDTH },
2349  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_45_CHECKER_TYPE,
2350  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_45_WIDTH },
2351  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_46_CHECKER_TYPE,
2352  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_46_WIDTH },
2353  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_47_CHECKER_TYPE,
2354  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_47_WIDTH },
2355  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_48_CHECKER_TYPE,
2356  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_48_WIDTH },
2357  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_49_CHECKER_TYPE,
2358  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_49_WIDTH },
2359  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_50_CHECKER_TYPE,
2360  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_50_WIDTH },
2361  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_51_CHECKER_TYPE,
2362  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_51_WIDTH },
2363  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_52_CHECKER_TYPE,
2364  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_52_WIDTH },
2365  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_53_CHECKER_TYPE,
2366  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_53_WIDTH },
2367  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_54_CHECKER_TYPE,
2368  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_54_WIDTH },
2369  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_55_CHECKER_TYPE,
2370  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_55_WIDTH },
2371  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_56_CHECKER_TYPE,
2372  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_56_WIDTH },
2373  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_57_CHECKER_TYPE,
2374  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_57_WIDTH },
2375  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_58_CHECKER_TYPE,
2376  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_58_WIDTH },
2377  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_59_CHECKER_TYPE,
2378  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_59_WIDTH },
2379  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_60_CHECKER_TYPE,
2380  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_60_WIDTH },
2381  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_61_CHECKER_TYPE,
2382  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_61_WIDTH },
2383  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_62_CHECKER_TYPE,
2384  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_62_WIDTH },
2385  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_63_CHECKER_TYPE,
2386  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_63_WIDTH },
2387  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_64_CHECKER_TYPE,
2388  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_64_WIDTH },
2389 };
2390 
2396 static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_groupEntries[SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_MAX_NUM_CHECKERS] =
2397 {
2398  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_0_CHECKER_TYPE,
2399  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_0_WIDTH },
2400  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_1_CHECKER_TYPE,
2401  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_1_WIDTH },
2402  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_2_CHECKER_TYPE,
2403  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_2_WIDTH },
2404  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_3_CHECKER_TYPE,
2405  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_3_WIDTH },
2406  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_4_CHECKER_TYPE,
2407  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_4_WIDTH },
2408  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_5_CHECKER_TYPE,
2409  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_5_WIDTH },
2410  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_6_CHECKER_TYPE,
2411  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_6_WIDTH },
2412  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_7_CHECKER_TYPE,
2413  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_7_WIDTH },
2414  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_8_CHECKER_TYPE,
2415  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_8_WIDTH },
2416  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_9_CHECKER_TYPE,
2417  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_9_WIDTH },
2418  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_10_CHECKER_TYPE,
2419  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_10_WIDTH },
2420  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_11_CHECKER_TYPE,
2421  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_11_WIDTH },
2422  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_12_CHECKER_TYPE,
2423  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_12_WIDTH },
2424  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_13_CHECKER_TYPE,
2425  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_13_WIDTH },
2426  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_14_CHECKER_TYPE,
2427  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_14_WIDTH },
2428  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_15_CHECKER_TYPE,
2429  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_15_WIDTH },
2430  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_16_CHECKER_TYPE,
2431  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_16_WIDTH },
2432  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_17_CHECKER_TYPE,
2433  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_17_WIDTH },
2434  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_18_CHECKER_TYPE,
2435  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_18_WIDTH },
2436  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_19_CHECKER_TYPE,
2437  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_19_WIDTH },
2438  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_20_CHECKER_TYPE,
2439  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_20_WIDTH },
2440  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_21_CHECKER_TYPE,
2441  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_21_WIDTH },
2442  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_22_CHECKER_TYPE,
2443  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_22_WIDTH },
2444  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_23_CHECKER_TYPE,
2445  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_23_WIDTH },
2446  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_24_CHECKER_TYPE,
2447  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_24_WIDTH },
2448  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_25_CHECKER_TYPE,
2449  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_25_WIDTH },
2450  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_26_CHECKER_TYPE,
2451  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_26_WIDTH },
2452  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_27_CHECKER_TYPE,
2453  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_27_WIDTH },
2454  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_28_CHECKER_TYPE,
2455  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_28_WIDTH },
2456  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_29_CHECKER_TYPE,
2457  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_29_WIDTH },
2458  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_30_CHECKER_TYPE,
2459  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_30_WIDTH },
2460  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_31_CHECKER_TYPE,
2461  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_31_WIDTH },
2462  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_32_CHECKER_TYPE,
2463  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_32_WIDTH },
2464  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_33_CHECKER_TYPE,
2465  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_33_WIDTH },
2466  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_34_CHECKER_TYPE,
2467  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_34_WIDTH },
2468  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_35_CHECKER_TYPE,
2469  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_35_WIDTH },
2470  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_36_CHECKER_TYPE,
2471  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_36_WIDTH },
2472  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_37_CHECKER_TYPE,
2473  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_37_WIDTH },
2474  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_38_CHECKER_TYPE,
2475  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_38_WIDTH },
2476  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_39_CHECKER_TYPE,
2477  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_39_WIDTH },
2478  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_40_CHECKER_TYPE,
2479  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_40_WIDTH },
2480  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_41_CHECKER_TYPE,
2481  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_41_WIDTH },
2482  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_42_CHECKER_TYPE,
2483  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_42_WIDTH },
2484  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_43_CHECKER_TYPE,
2485  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_43_WIDTH },
2486  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_44_CHECKER_TYPE,
2487  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_44_WIDTH },
2488  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_45_CHECKER_TYPE,
2489  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_45_WIDTH },
2490  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_46_CHECKER_TYPE,
2491  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_46_WIDTH },
2492  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_47_CHECKER_TYPE,
2493  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_47_WIDTH },
2494  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_48_CHECKER_TYPE,
2495  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_48_WIDTH },
2496  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_49_CHECKER_TYPE,
2497  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_49_WIDTH },
2498  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_50_CHECKER_TYPE,
2499  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_50_WIDTH },
2500  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_51_CHECKER_TYPE,
2501  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_51_WIDTH },
2502  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_52_CHECKER_TYPE,
2503  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_52_WIDTH },
2504  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_53_CHECKER_TYPE,
2505  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_53_WIDTH },
2506  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_54_CHECKER_TYPE,
2507  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_54_WIDTH },
2508  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_55_CHECKER_TYPE,
2509  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_55_WIDTH },
2510  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_56_CHECKER_TYPE,
2511  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_56_WIDTH },
2512  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_57_CHECKER_TYPE,
2513  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_57_WIDTH },
2514  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_58_CHECKER_TYPE,
2515  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_58_WIDTH },
2516  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_59_CHECKER_TYPE,
2517  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_59_WIDTH },
2518  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_60_CHECKER_TYPE,
2519  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_60_WIDTH },
2520  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_61_CHECKER_TYPE,
2521  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_61_WIDTH },
2522  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_62_CHECKER_TYPE,
2523  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_62_WIDTH },
2524  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_63_CHECKER_TYPE,
2525  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_63_WIDTH },
2526  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_64_CHECKER_TYPE,
2527  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_64_WIDTH },
2528  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_65_CHECKER_TYPE,
2529  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_65_WIDTH },
2530  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_66_CHECKER_TYPE,
2531  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_66_WIDTH },
2532  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_67_CHECKER_TYPE,
2533  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_67_WIDTH },
2534  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_68_CHECKER_TYPE,
2535  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_68_WIDTH },
2536 };
2537 
2543 static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_CFG_SLV_SRC_BUSECC_groupEntries[SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_CFG_SLV_SRC_BUSECC_MAX_NUM_CHECKERS] =
2544 {
2545  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_CFG_SLV_SRC_BUSECC_GROUP_0_CHECKER_TYPE,
2546  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_CFG_SLV_SRC_BUSECC_GROUP_0_WIDTH },
2547  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_CFG_SLV_SRC_BUSECC_GROUP_1_CHECKER_TYPE,
2548  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_CFG_SLV_SRC_BUSECC_GROUP_1_WIDTH },
2549  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_CFG_SLV_SRC_BUSECC_GROUP_2_CHECKER_TYPE,
2550  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_CFG_SLV_SRC_BUSECC_GROUP_2_WIDTH },
2551  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_CFG_SLV_SRC_BUSECC_GROUP_3_CHECKER_TYPE,
2552  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_CFG_SLV_SRC_BUSECC_GROUP_3_WIDTH },
2553  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_CFG_SLV_SRC_BUSECC_GROUP_4_CHECKER_TYPE,
2554  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_CFG_SLV_SRC_BUSECC_GROUP_4_WIDTH },
2555  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_CFG_SLV_SRC_BUSECC_GROUP_5_CHECKER_TYPE,
2556  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_CFG_SLV_SRC_BUSECC_GROUP_5_WIDTH },
2557  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_CFG_SLV_SRC_BUSECC_GROUP_6_CHECKER_TYPE,
2558  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_CFG_SLV_SRC_BUSECC_GROUP_6_WIDTH },
2559  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_CFG_SLV_SRC_BUSECC_GROUP_7_CHECKER_TYPE,
2560  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_CFG_SLV_SRC_BUSECC_GROUP_7_WIDTH },
2561  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_CFG_SLV_SRC_BUSECC_GROUP_8_CHECKER_TYPE,
2562  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_CFG_SLV_SRC_BUSECC_GROUP_8_WIDTH },
2563  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_CFG_SLV_SRC_BUSECC_GROUP_9_CHECKER_TYPE,
2564  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_CFG_SLV_SRC_BUSECC_GROUP_9_WIDTH },
2565  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_CFG_SLV_SRC_BUSECC_GROUP_10_CHECKER_TYPE,
2566  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_CFG_SLV_SRC_BUSECC_GROUP_10_WIDTH },
2567  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_CFG_SLV_SRC_BUSECC_GROUP_11_CHECKER_TYPE,
2568  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_CFG_SLV_SRC_BUSECC_GROUP_11_WIDTH },
2569  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_CFG_SLV_SRC_BUSECC_GROUP_12_CHECKER_TYPE,
2570  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_CFG_SLV_SRC_BUSECC_GROUP_12_WIDTH },
2571  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_CFG_SLV_SRC_BUSECC_GROUP_13_CHECKER_TYPE,
2572  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_CFG_SLV_SRC_BUSECC_GROUP_13_WIDTH },
2573  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_CFG_SLV_SRC_BUSECC_GROUP_14_CHECKER_TYPE,
2574  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_CFG_SLV_SRC_BUSECC_GROUP_14_WIDTH },
2575 };
2576 
2582 static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_PMST_DST_BUSECC_groupEntries[SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_PMST_DST_BUSECC_MAX_NUM_CHECKERS] =
2583 {
2584  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_PMST_DST_BUSECC_GROUP_0_CHECKER_TYPE,
2585  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_PMST_DST_BUSECC_GROUP_0_WIDTH },
2586  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_PMST_DST_BUSECC_GROUP_1_CHECKER_TYPE,
2587  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_PMST_DST_BUSECC_GROUP_1_WIDTH },
2588  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_PMST_DST_BUSECC_GROUP_2_CHECKER_TYPE,
2589  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_PMST_DST_BUSECC_GROUP_2_WIDTH },
2590  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_PMST_DST_BUSECC_GROUP_3_CHECKER_TYPE,
2591  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_PMST_DST_BUSECC_GROUP_3_WIDTH },
2592 };
2593 
2599 static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__IECC_AGGR_CFG_SRC_BUSECC_groupEntries[SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__IECC_AGGR_CFG_SRC_BUSECC_MAX_NUM_CHECKERS] =
2600 {
2601  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__IECC_AGGR_CFG_SRC_BUSECC_GROUP_0_CHECKER_TYPE,
2602  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__IECC_AGGR_CFG_SRC_BUSECC_GROUP_0_WIDTH },
2603  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__IECC_AGGR_CFG_SRC_BUSECC_GROUP_1_CHECKER_TYPE,
2604  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__IECC_AGGR_CFG_SRC_BUSECC_GROUP_1_WIDTH },
2605  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__IECC_AGGR_CFG_SRC_BUSECC_GROUP_2_CHECKER_TYPE,
2606  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__IECC_AGGR_CFG_SRC_BUSECC_GROUP_2_WIDTH },
2607  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__IECC_AGGR_CFG_SRC_BUSECC_GROUP_3_CHECKER_TYPE,
2608  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__IECC_AGGR_CFG_SRC_BUSECC_GROUP_3_WIDTH },
2609  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__IECC_AGGR_CFG_SRC_BUSECC_GROUP_4_CHECKER_TYPE,
2610  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__IECC_AGGR_CFG_SRC_BUSECC_GROUP_4_WIDTH },
2611  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__IECC_AGGR_CFG_SRC_BUSECC_GROUP_5_CHECKER_TYPE,
2612  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__IECC_AGGR_CFG_SRC_BUSECC_GROUP_5_WIDTH },
2613  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__IECC_AGGR_CFG_SRC_BUSECC_GROUP_6_CHECKER_TYPE,
2614  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__IECC_AGGR_CFG_SRC_BUSECC_GROUP_6_WIDTH },
2615  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__IECC_AGGR_CFG_SRC_BUSECC_GROUP_7_CHECKER_TYPE,
2616  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__IECC_AGGR_CFG_SRC_BUSECC_GROUP_7_WIDTH },
2617  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__IECC_AGGR_CFG_SRC_BUSECC_GROUP_8_CHECKER_TYPE,
2618  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__IECC_AGGR_CFG_SRC_BUSECC_GROUP_8_WIDTH },
2619  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__IECC_AGGR_CFG_SRC_BUSECC_GROUP_9_CHECKER_TYPE,
2620  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__IECC_AGGR_CFG_SRC_BUSECC_GROUP_9_WIDTH },
2621  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__IECC_AGGR_CFG_SRC_BUSECC_GROUP_10_CHECKER_TYPE,
2622  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__IECC_AGGR_CFG_SRC_BUSECC_GROUP_10_WIDTH },
2623  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__IECC_AGGR_CFG_SRC_BUSECC_GROUP_11_CHECKER_TYPE,
2624  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__IECC_AGGR_CFG_SRC_BUSECC_GROUP_11_WIDTH },
2625  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__IECC_AGGR_CFG_SRC_BUSECC_GROUP_12_CHECKER_TYPE,
2626  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__IECC_AGGR_CFG_SRC_BUSECC_GROUP_12_WIDTH },
2627  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__IECC_AGGR_CFG_SRC_BUSECC_GROUP_13_CHECKER_TYPE,
2628  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__IECC_AGGR_CFG_SRC_BUSECC_GROUP_13_WIDTH },
2629  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__IECC_AGGR_CFG_SRC_BUSECC_GROUP_14_CHECKER_TYPE,
2630  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__IECC_AGGR_CFG_SRC_BUSECC_GROUP_14_WIDTH },
2631 };
2632 
2638 static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_DM2MCU_VBUSM_GASKET_MCU_0_EDC_CTRL_groupEntries[SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_DM2MCU_VBUSM_GASKET_MCU_0_EDC_CTRL_MAX_NUM_CHECKERS] =
2639 {
2640  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_DM2MCU_VBUSM_GASKET_MCU_0_EDC_CTRL_GROUP_0_CHECKER_TYPE,
2641  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_DM2MCU_VBUSM_GASKET_MCU_0_EDC_CTRL_GROUP_0_WIDTH },
2642 };
2643 
2649 static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_groupEntries[SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_MAX_NUM_CHECKERS] =
2650 {
2651  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_0_CHECKER_TYPE,
2652  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_0_WIDTH },
2653  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_1_CHECKER_TYPE,
2654  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_1_WIDTH },
2655  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_2_CHECKER_TYPE,
2656  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_2_WIDTH },
2657  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_3_CHECKER_TYPE,
2658  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_3_WIDTH },
2659  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_4_CHECKER_TYPE,
2660  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_4_WIDTH },
2661  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_5_CHECKER_TYPE,
2662  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_5_WIDTH },
2663  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_6_CHECKER_TYPE,
2664  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_6_WIDTH },
2665  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_7_CHECKER_TYPE,
2666  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_7_WIDTH },
2667  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_8_CHECKER_TYPE,
2668  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_8_WIDTH },
2669  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_9_CHECKER_TYPE,
2670  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_9_WIDTH },
2671  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_10_CHECKER_TYPE,
2672  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_10_WIDTH },
2673  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_11_CHECKER_TYPE,
2674  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_11_WIDTH },
2675  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_12_CHECKER_TYPE,
2676  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_12_WIDTH },
2677  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_13_CHECKER_TYPE,
2678  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_13_WIDTH },
2679  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_14_CHECKER_TYPE,
2680  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_14_WIDTH },
2681  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_15_CHECKER_TYPE,
2682  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_15_WIDTH },
2683  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_16_CHECKER_TYPE,
2684  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_16_WIDTH },
2685  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_17_CHECKER_TYPE,
2686  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_17_WIDTH },
2687  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_18_CHECKER_TYPE,
2688  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_18_WIDTH },
2689  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_19_CHECKER_TYPE,
2690  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_19_WIDTH },
2691  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_20_CHECKER_TYPE,
2692  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_20_WIDTH },
2693  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_21_CHECKER_TYPE,
2694  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_21_WIDTH },
2695  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_22_CHECKER_TYPE,
2696  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_22_WIDTH },
2697  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_23_CHECKER_TYPE,
2698  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_23_WIDTH },
2699  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_24_CHECKER_TYPE,
2700  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_24_WIDTH },
2701  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_25_CHECKER_TYPE,
2702  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_25_WIDTH },
2703  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_26_CHECKER_TYPE,
2704  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_26_WIDTH },
2705  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_27_CHECKER_TYPE,
2706  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_27_WIDTH },
2707  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_28_CHECKER_TYPE,
2708  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_28_WIDTH },
2709  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_29_CHECKER_TYPE,
2710  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_29_WIDTH },
2711  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_30_CHECKER_TYPE,
2712  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_30_WIDTH },
2713  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_31_CHECKER_TYPE,
2714  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_31_WIDTH },
2715  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_32_CHECKER_TYPE,
2716  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_32_WIDTH },
2717  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_33_CHECKER_TYPE,
2718  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_33_WIDTH },
2719  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_34_CHECKER_TYPE,
2720  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_34_WIDTH },
2721  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_35_CHECKER_TYPE,
2722  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_35_WIDTH },
2723  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_36_CHECKER_TYPE,
2724  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_36_WIDTH },
2725  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_37_CHECKER_TYPE,
2726  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_37_WIDTH },
2727  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_38_CHECKER_TYPE,
2728  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_38_WIDTH },
2729  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_39_CHECKER_TYPE,
2730  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_39_WIDTH },
2731  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_40_CHECKER_TYPE,
2732  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_40_WIDTH },
2733  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_41_CHECKER_TYPE,
2734  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_41_WIDTH },
2735  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_42_CHECKER_TYPE,
2736  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_42_WIDTH },
2737  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_43_CHECKER_TYPE,
2738  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_43_WIDTH },
2739  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_44_CHECKER_TYPE,
2740  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_44_WIDTH },
2741  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_45_CHECKER_TYPE,
2742  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_45_WIDTH },
2743  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_46_CHECKER_TYPE,
2744  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_46_WIDTH },
2745  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_47_CHECKER_TYPE,
2746  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_47_WIDTH },
2747  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_48_CHECKER_TYPE,
2748  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_48_WIDTH },
2749  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_49_CHECKER_TYPE,
2750  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_49_WIDTH },
2751  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_50_CHECKER_TYPE,
2752  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_50_WIDTH },
2753  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_51_CHECKER_TYPE,
2754  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_51_WIDTH },
2755  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_52_CHECKER_TYPE,
2756  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_52_WIDTH },
2757  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_53_CHECKER_TYPE,
2758  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_53_WIDTH },
2759  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_54_CHECKER_TYPE,
2760  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_54_WIDTH },
2761  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_55_CHECKER_TYPE,
2762  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_55_WIDTH },
2763  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_56_CHECKER_TYPE,
2764  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_56_WIDTH },
2765  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_57_CHECKER_TYPE,
2766  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_57_WIDTH },
2767  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_58_CHECKER_TYPE,
2768  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_58_WIDTH },
2769  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_59_CHECKER_TYPE,
2770  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_59_WIDTH },
2771  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_60_CHECKER_TYPE,
2772  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_60_WIDTH },
2773  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_61_CHECKER_TYPE,
2774  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_61_WIDTH },
2775  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_62_CHECKER_TYPE,
2776  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_62_WIDTH },
2777  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_63_CHECKER_TYPE,
2778  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_63_WIDTH },
2779  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_64_CHECKER_TYPE,
2780  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_64_WIDTH },
2781  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_65_CHECKER_TYPE,
2782  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_65_WIDTH },
2783  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_66_CHECKER_TYPE,
2784  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_66_WIDTH },
2785  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_67_CHECKER_TYPE,
2786  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_67_WIDTH },
2787  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_68_CHECKER_TYPE,
2788  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_68_WIDTH },
2789 };
2790 
2796 static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IAM62A_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM62A_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_groupEntries[SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IAM62A_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM62A_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS] =
2797 {
2798  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IAM62A_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM62A_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_GROUP_0_CHECKER_TYPE,
2799  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IAM62A_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM62A_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_GROUP_0_WIDTH },
2800  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IAM62A_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM62A_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_GROUP_1_CHECKER_TYPE,
2801  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IAM62A_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM62A_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_GROUP_1_WIDTH },
2802  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IAM62A_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM62A_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_GROUP_2_CHECKER_TYPE,
2803  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IAM62A_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM62A_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_GROUP_2_WIDTH },
2804  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IAM62A_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM62A_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_GROUP_3_CHECKER_TYPE,
2805  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IAM62A_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM62A_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_GROUP_3_WIDTH },
2806  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IAM62A_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM62A_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_GROUP_4_CHECKER_TYPE,
2807  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IAM62A_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM62A_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_GROUP_4_WIDTH },
2808  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IAM62A_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM62A_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_GROUP_5_CHECKER_TYPE,
2809  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IAM62A_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM62A_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_GROUP_5_WIDTH },
2810  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IAM62A_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM62A_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_GROUP_6_CHECKER_TYPE,
2811  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IAM62A_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM62A_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_GROUP_6_WIDTH },
2812 };
2813 
2819 static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IAM62A_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM62A_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_groupEntries[SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IAM62A_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM62A_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS] =
2820 {
2821  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IAM62A_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM62A_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_0_CHECKER_TYPE,
2822  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IAM62A_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM62A_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_0_WIDTH },
2823  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IAM62A_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM62A_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_1_CHECKER_TYPE,
2824  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IAM62A_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM62A_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_1_WIDTH },
2825  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IAM62A_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM62A_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_2_CHECKER_TYPE,
2826  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IAM62A_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM62A_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_2_WIDTH },
2827  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IAM62A_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM62A_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_3_CHECKER_TYPE,
2828  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IAM62A_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM62A_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_3_WIDTH },
2829  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IAM62A_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM62A_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_4_CHECKER_TYPE,
2830  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IAM62A_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM62A_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_4_WIDTH },
2831  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IAM62A_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM62A_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_5_CHECKER_TYPE,
2832  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IAM62A_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM62A_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_5_WIDTH },
2833  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IAM62A_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM62A_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_6_CHECKER_TYPE,
2834  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IAM62A_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM62A_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_6_WIDTH },
2835  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IAM62A_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM62A_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_7_CHECKER_TYPE,
2836  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IAM62A_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM62A_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_7_WIDTH },
2837  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IAM62A_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM62A_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_8_CHECKER_TYPE,
2838  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IAM62A_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM62A_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_8_WIDTH },
2839  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IAM62A_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM62A_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_9_CHECKER_TYPE,
2840  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IAM62A_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM62A_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_9_WIDTH },
2841  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IAM62A_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM62A_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_10_CHECKER_TYPE,
2842  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IAM62A_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM62A_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_10_WIDTH },
2843  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IAM62A_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM62A_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_11_CHECKER_TYPE,
2844  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IAM62A_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM62A_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_11_WIDTH },
2845  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IAM62A_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM62A_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_12_CHECKER_TYPE,
2846  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IAM62A_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM62A_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_12_WIDTH },
2847  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IAM62A_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM62A_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_13_CHECKER_TYPE,
2848  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IAM62A_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM62A_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_13_WIDTH },
2849  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IAM62A_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM62A_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_14_CHECKER_TYPE,
2850  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IAM62A_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM62A_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_14_WIDTH },
2851  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IAM62A_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM62A_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_15_CHECKER_TYPE,
2852  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IAM62A_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM62A_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_15_WIDTH },
2853  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IAM62A_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM62A_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_16_CHECKER_TYPE,
2854  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IAM62A_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM62A_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_16_WIDTH },
2855 };
2856 
2862 static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IMSRAM32KX64E_MCU_0_CFG_P2P_BRIDGE_IMSRAM32KX64E_MCU_0_CFG_BRIDGE_BUSECC_groupEntries[SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IMSRAM32KX64E_MCU_0_CFG_P2P_BRIDGE_IMSRAM32KX64E_MCU_0_CFG_BRIDGE_BUSECC_MAX_NUM_CHECKERS] =
2863 {
2864  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IMSRAM32KX64E_MCU_0_CFG_P2P_BRIDGE_IMSRAM32KX64E_MCU_0_CFG_BRIDGE_BUSECC_GROUP_0_CHECKER_TYPE,
2865  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IMSRAM32KX64E_MCU_0_CFG_P2P_BRIDGE_IMSRAM32KX64E_MCU_0_CFG_BRIDGE_BUSECC_GROUP_0_WIDTH },
2866  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IMSRAM32KX64E_MCU_0_CFG_P2P_BRIDGE_IMSRAM32KX64E_MCU_0_CFG_BRIDGE_BUSECC_GROUP_1_CHECKER_TYPE,
2867  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IMSRAM32KX64E_MCU_0_CFG_P2P_BRIDGE_IMSRAM32KX64E_MCU_0_CFG_BRIDGE_BUSECC_GROUP_1_WIDTH },
2868  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IMSRAM32KX64E_MCU_0_CFG_P2P_BRIDGE_IMSRAM32KX64E_MCU_0_CFG_BRIDGE_BUSECC_GROUP_2_CHECKER_TYPE,
2869  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IMSRAM32KX64E_MCU_0_CFG_P2P_BRIDGE_IMSRAM32KX64E_MCU_0_CFG_BRIDGE_BUSECC_GROUP_2_WIDTH },
2870  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IMSRAM32KX64E_MCU_0_CFG_P2P_BRIDGE_IMSRAM32KX64E_MCU_0_CFG_BRIDGE_BUSECC_GROUP_3_CHECKER_TYPE,
2871  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IMSRAM32KX64E_MCU_0_CFG_P2P_BRIDGE_IMSRAM32KX64E_MCU_0_CFG_BRIDGE_BUSECC_GROUP_3_WIDTH },
2872  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IMSRAM32KX64E_MCU_0_CFG_P2P_BRIDGE_IMSRAM32KX64E_MCU_0_CFG_BRIDGE_BUSECC_GROUP_4_CHECKER_TYPE,
2873  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IMSRAM32KX64E_MCU_0_CFG_P2P_BRIDGE_IMSRAM32KX64E_MCU_0_CFG_BRIDGE_BUSECC_GROUP_4_WIDTH },
2874  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IMSRAM32KX64E_MCU_0_CFG_P2P_BRIDGE_IMSRAM32KX64E_MCU_0_CFG_BRIDGE_BUSECC_GROUP_5_CHECKER_TYPE,
2875  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IMSRAM32KX64E_MCU_0_CFG_P2P_BRIDGE_IMSRAM32KX64E_MCU_0_CFG_BRIDGE_BUSECC_GROUP_5_WIDTH },
2876  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IMSRAM32KX64E_MCU_0_CFG_P2P_BRIDGE_IMSRAM32KX64E_MCU_0_CFG_BRIDGE_BUSECC_GROUP_6_CHECKER_TYPE,
2877  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IMSRAM32KX64E_MCU_0_CFG_P2P_BRIDGE_IMSRAM32KX64E_MCU_0_CFG_BRIDGE_BUSECC_GROUP_6_WIDTH },
2878  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IMSRAM32KX64E_MCU_0_CFG_P2P_BRIDGE_IMSRAM32KX64E_MCU_0_CFG_BRIDGE_BUSECC_GROUP_7_CHECKER_TYPE,
2879  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IMSRAM32KX64E_MCU_0_CFG_P2P_BRIDGE_IMSRAM32KX64E_MCU_0_CFG_BRIDGE_BUSECC_GROUP_7_WIDTH },
2880  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IMSRAM32KX64E_MCU_0_CFG_P2P_BRIDGE_IMSRAM32KX64E_MCU_0_CFG_BRIDGE_BUSECC_GROUP_8_CHECKER_TYPE,
2881  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IMSRAM32KX64E_MCU_0_CFG_P2P_BRIDGE_IMSRAM32KX64E_MCU_0_CFG_BRIDGE_BUSECC_GROUP_8_WIDTH },
2882  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IMSRAM32KX64E_MCU_0_CFG_P2P_BRIDGE_IMSRAM32KX64E_MCU_0_CFG_BRIDGE_BUSECC_GROUP_9_CHECKER_TYPE,
2883  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IMSRAM32KX64E_MCU_0_CFG_P2P_BRIDGE_IMSRAM32KX64E_MCU_0_CFG_BRIDGE_BUSECC_GROUP_9_WIDTH },
2884  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IMSRAM32KX64E_MCU_0_CFG_P2P_BRIDGE_IMSRAM32KX64E_MCU_0_CFG_BRIDGE_BUSECC_GROUP_10_CHECKER_TYPE,
2885  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IMSRAM32KX64E_MCU_0_CFG_P2P_BRIDGE_IMSRAM32KX64E_MCU_0_CFG_BRIDGE_BUSECC_GROUP_10_WIDTH },
2886  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IMSRAM32KX64E_MCU_0_CFG_P2P_BRIDGE_IMSRAM32KX64E_MCU_0_CFG_BRIDGE_BUSECC_GROUP_11_CHECKER_TYPE,
2887  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IMSRAM32KX64E_MCU_0_CFG_P2P_BRIDGE_IMSRAM32KX64E_MCU_0_CFG_BRIDGE_BUSECC_GROUP_11_WIDTH },
2888  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IMSRAM32KX64E_MCU_0_CFG_P2P_BRIDGE_IMSRAM32KX64E_MCU_0_CFG_BRIDGE_BUSECC_GROUP_12_CHECKER_TYPE,
2889  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IMSRAM32KX64E_MCU_0_CFG_P2P_BRIDGE_IMSRAM32KX64E_MCU_0_CFG_BRIDGE_BUSECC_GROUP_12_WIDTH },
2890 };
2891 
2897 static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IMSRAM32KX64E_MCU_1_CFG_P2P_BRIDGE_IMSRAM32KX64E_MCU_1_CFG_BRIDGE_BUSECC_groupEntries[SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IMSRAM32KX64E_MCU_1_CFG_P2P_BRIDGE_IMSRAM32KX64E_MCU_1_CFG_BRIDGE_BUSECC_MAX_NUM_CHECKERS] =
2898 {
2899  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IMSRAM32KX64E_MCU_1_CFG_P2P_BRIDGE_IMSRAM32KX64E_MCU_1_CFG_BRIDGE_BUSECC_GROUP_0_CHECKER_TYPE,
2900  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IMSRAM32KX64E_MCU_1_CFG_P2P_BRIDGE_IMSRAM32KX64E_MCU_1_CFG_BRIDGE_BUSECC_GROUP_0_WIDTH },
2901  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IMSRAM32KX64E_MCU_1_CFG_P2P_BRIDGE_IMSRAM32KX64E_MCU_1_CFG_BRIDGE_BUSECC_GROUP_1_CHECKER_TYPE,
2902  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IMSRAM32KX64E_MCU_1_CFG_P2P_BRIDGE_IMSRAM32KX64E_MCU_1_CFG_BRIDGE_BUSECC_GROUP_1_WIDTH },
2903  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IMSRAM32KX64E_MCU_1_CFG_P2P_BRIDGE_IMSRAM32KX64E_MCU_1_CFG_BRIDGE_BUSECC_GROUP_2_CHECKER_TYPE,
2904  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IMSRAM32KX64E_MCU_1_CFG_P2P_BRIDGE_IMSRAM32KX64E_MCU_1_CFG_BRIDGE_BUSECC_GROUP_2_WIDTH },
2905  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IMSRAM32KX64E_MCU_1_CFG_P2P_BRIDGE_IMSRAM32KX64E_MCU_1_CFG_BRIDGE_BUSECC_GROUP_3_CHECKER_TYPE,
2906  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IMSRAM32KX64E_MCU_1_CFG_P2P_BRIDGE_IMSRAM32KX64E_MCU_1_CFG_BRIDGE_BUSECC_GROUP_3_WIDTH },
2907  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IMSRAM32KX64E_MCU_1_CFG_P2P_BRIDGE_IMSRAM32KX64E_MCU_1_CFG_BRIDGE_BUSECC_GROUP_4_CHECKER_TYPE,
2908  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IMSRAM32KX64E_MCU_1_CFG_P2P_BRIDGE_IMSRAM32KX64E_MCU_1_CFG_BRIDGE_BUSECC_GROUP_4_WIDTH },
2909  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IMSRAM32KX64E_MCU_1_CFG_P2P_BRIDGE_IMSRAM32KX64E_MCU_1_CFG_BRIDGE_BUSECC_GROUP_5_CHECKER_TYPE,
2910  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IMSRAM32KX64E_MCU_1_CFG_P2P_BRIDGE_IMSRAM32KX64E_MCU_1_CFG_BRIDGE_BUSECC_GROUP_5_WIDTH },
2911  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IMSRAM32KX64E_MCU_1_CFG_P2P_BRIDGE_IMSRAM32KX64E_MCU_1_CFG_BRIDGE_BUSECC_GROUP_6_CHECKER_TYPE,
2912  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IMSRAM32KX64E_MCU_1_CFG_P2P_BRIDGE_IMSRAM32KX64E_MCU_1_CFG_BRIDGE_BUSECC_GROUP_6_WIDTH },
2913  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IMSRAM32KX64E_MCU_1_CFG_P2P_BRIDGE_IMSRAM32KX64E_MCU_1_CFG_BRIDGE_BUSECC_GROUP_7_CHECKER_TYPE,
2914  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IMSRAM32KX64E_MCU_1_CFG_P2P_BRIDGE_IMSRAM32KX64E_MCU_1_CFG_BRIDGE_BUSECC_GROUP_7_WIDTH },
2915  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IMSRAM32KX64E_MCU_1_CFG_P2P_BRIDGE_IMSRAM32KX64E_MCU_1_CFG_BRIDGE_BUSECC_GROUP_8_CHECKER_TYPE,
2916  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IMSRAM32KX64E_MCU_1_CFG_P2P_BRIDGE_IMSRAM32KX64E_MCU_1_CFG_BRIDGE_BUSECC_GROUP_8_WIDTH },
2917  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IMSRAM32KX64E_MCU_1_CFG_P2P_BRIDGE_IMSRAM32KX64E_MCU_1_CFG_BRIDGE_BUSECC_GROUP_9_CHECKER_TYPE,
2918  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IMSRAM32KX64E_MCU_1_CFG_P2P_BRIDGE_IMSRAM32KX64E_MCU_1_CFG_BRIDGE_BUSECC_GROUP_9_WIDTH },
2919  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IMSRAM32KX64E_MCU_1_CFG_P2P_BRIDGE_IMSRAM32KX64E_MCU_1_CFG_BRIDGE_BUSECC_GROUP_10_CHECKER_TYPE,
2920  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IMSRAM32KX64E_MCU_1_CFG_P2P_BRIDGE_IMSRAM32KX64E_MCU_1_CFG_BRIDGE_BUSECC_GROUP_10_WIDTH },
2921  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IMSRAM32KX64E_MCU_1_CFG_P2P_BRIDGE_IMSRAM32KX64E_MCU_1_CFG_BRIDGE_BUSECC_GROUP_11_CHECKER_TYPE,
2922  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IMSRAM32KX64E_MCU_1_CFG_P2P_BRIDGE_IMSRAM32KX64E_MCU_1_CFG_BRIDGE_BUSECC_GROUP_11_WIDTH },
2923  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IMSRAM32KX64E_MCU_1_CFG_P2P_BRIDGE_IMSRAM32KX64E_MCU_1_CFG_BRIDGE_BUSECC_GROUP_12_CHECKER_TYPE,
2924  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IMSRAM32KX64E_MCU_1_CFG_P2P_BRIDGE_IMSRAM32KX64E_MCU_1_CFG_BRIDGE_BUSECC_GROUP_12_WIDTH },
2925 };
2926 
2932 static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IPULSAR_ULS_MCU_0_CPU0_CFG_SLV_P2P_BRIDGE_IPULSAR_ULS_MCU_0_CPU0_CFG_SLV_BRIDGE_BUSECC_groupEntries[SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IPULSAR_ULS_MCU_0_CPU0_CFG_SLV_P2P_BRIDGE_IPULSAR_ULS_MCU_0_CPU0_CFG_SLV_BRIDGE_BUSECC_MAX_NUM_CHECKERS] =
2933 {
2934  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IPULSAR_ULS_MCU_0_CPU0_CFG_SLV_P2P_BRIDGE_IPULSAR_ULS_MCU_0_CPU0_CFG_SLV_BRIDGE_BUSECC_GROUP_0_CHECKER_TYPE,
2935  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IPULSAR_ULS_MCU_0_CPU0_CFG_SLV_P2P_BRIDGE_IPULSAR_ULS_MCU_0_CPU0_CFG_SLV_BRIDGE_BUSECC_GROUP_0_WIDTH },
2936  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IPULSAR_ULS_MCU_0_CPU0_CFG_SLV_P2P_BRIDGE_IPULSAR_ULS_MCU_0_CPU0_CFG_SLV_BRIDGE_BUSECC_GROUP_1_CHECKER_TYPE,
2937  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IPULSAR_ULS_MCU_0_CPU0_CFG_SLV_P2P_BRIDGE_IPULSAR_ULS_MCU_0_CPU0_CFG_SLV_BRIDGE_BUSECC_GROUP_1_WIDTH },
2938  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IPULSAR_ULS_MCU_0_CPU0_CFG_SLV_P2P_BRIDGE_IPULSAR_ULS_MCU_0_CPU0_CFG_SLV_BRIDGE_BUSECC_GROUP_2_CHECKER_TYPE,
2939  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IPULSAR_ULS_MCU_0_CPU0_CFG_SLV_P2P_BRIDGE_IPULSAR_ULS_MCU_0_CPU0_CFG_SLV_BRIDGE_BUSECC_GROUP_2_WIDTH },
2940  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IPULSAR_ULS_MCU_0_CPU0_CFG_SLV_P2P_BRIDGE_IPULSAR_ULS_MCU_0_CPU0_CFG_SLV_BRIDGE_BUSECC_GROUP_3_CHECKER_TYPE,
2941  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IPULSAR_ULS_MCU_0_CPU0_CFG_SLV_P2P_BRIDGE_IPULSAR_ULS_MCU_0_CPU0_CFG_SLV_BRIDGE_BUSECC_GROUP_3_WIDTH },
2942  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IPULSAR_ULS_MCU_0_CPU0_CFG_SLV_P2P_BRIDGE_IPULSAR_ULS_MCU_0_CPU0_CFG_SLV_BRIDGE_BUSECC_GROUP_4_CHECKER_TYPE,
2943  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IPULSAR_ULS_MCU_0_CPU0_CFG_SLV_P2P_BRIDGE_IPULSAR_ULS_MCU_0_CPU0_CFG_SLV_BRIDGE_BUSECC_GROUP_4_WIDTH },
2944  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IPULSAR_ULS_MCU_0_CPU0_CFG_SLV_P2P_BRIDGE_IPULSAR_ULS_MCU_0_CPU0_CFG_SLV_BRIDGE_BUSECC_GROUP_5_CHECKER_TYPE,
2945  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IPULSAR_ULS_MCU_0_CPU0_CFG_SLV_P2P_BRIDGE_IPULSAR_ULS_MCU_0_CPU0_CFG_SLV_BRIDGE_BUSECC_GROUP_5_WIDTH },
2946  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IPULSAR_ULS_MCU_0_CPU0_CFG_SLV_P2P_BRIDGE_IPULSAR_ULS_MCU_0_CPU0_CFG_SLV_BRIDGE_BUSECC_GROUP_6_CHECKER_TYPE,
2947  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IPULSAR_ULS_MCU_0_CPU0_CFG_SLV_P2P_BRIDGE_IPULSAR_ULS_MCU_0_CPU0_CFG_SLV_BRIDGE_BUSECC_GROUP_6_WIDTH },
2948  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IPULSAR_ULS_MCU_0_CPU0_CFG_SLV_P2P_BRIDGE_IPULSAR_ULS_MCU_0_CPU0_CFG_SLV_BRIDGE_BUSECC_GROUP_7_CHECKER_TYPE,
2949  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IPULSAR_ULS_MCU_0_CPU0_CFG_SLV_P2P_BRIDGE_IPULSAR_ULS_MCU_0_CPU0_CFG_SLV_BRIDGE_BUSECC_GROUP_7_WIDTH },
2950  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IPULSAR_ULS_MCU_0_CPU0_CFG_SLV_P2P_BRIDGE_IPULSAR_ULS_MCU_0_CPU0_CFG_SLV_BRIDGE_BUSECC_GROUP_8_CHECKER_TYPE,
2951  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IPULSAR_ULS_MCU_0_CPU0_CFG_SLV_P2P_BRIDGE_IPULSAR_ULS_MCU_0_CPU0_CFG_SLV_BRIDGE_BUSECC_GROUP_8_WIDTH },
2952  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IPULSAR_ULS_MCU_0_CPU0_CFG_SLV_P2P_BRIDGE_IPULSAR_ULS_MCU_0_CPU0_CFG_SLV_BRIDGE_BUSECC_GROUP_9_CHECKER_TYPE,
2953  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IPULSAR_ULS_MCU_0_CPU0_CFG_SLV_P2P_BRIDGE_IPULSAR_ULS_MCU_0_CPU0_CFG_SLV_BRIDGE_BUSECC_GROUP_9_WIDTH },
2954  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IPULSAR_ULS_MCU_0_CPU0_CFG_SLV_P2P_BRIDGE_IPULSAR_ULS_MCU_0_CPU0_CFG_SLV_BRIDGE_BUSECC_GROUP_10_CHECKER_TYPE,
2955  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IPULSAR_ULS_MCU_0_CPU0_CFG_SLV_P2P_BRIDGE_IPULSAR_ULS_MCU_0_CPU0_CFG_SLV_BRIDGE_BUSECC_GROUP_10_WIDTH },
2956  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IPULSAR_ULS_MCU_0_CPU0_CFG_SLV_P2P_BRIDGE_IPULSAR_ULS_MCU_0_CPU0_CFG_SLV_BRIDGE_BUSECC_GROUP_11_CHECKER_TYPE,
2957  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IPULSAR_ULS_MCU_0_CPU0_CFG_SLV_P2P_BRIDGE_IPULSAR_ULS_MCU_0_CPU0_CFG_SLV_BRIDGE_BUSECC_GROUP_11_WIDTH },
2958  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IPULSAR_ULS_MCU_0_CPU0_CFG_SLV_P2P_BRIDGE_IPULSAR_ULS_MCU_0_CPU0_CFG_SLV_BRIDGE_BUSECC_GROUP_12_CHECKER_TYPE,
2959  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IPULSAR_ULS_MCU_0_CPU0_CFG_SLV_P2P_BRIDGE_IPULSAR_ULS_MCU_0_CPU0_CFG_SLV_BRIDGE_BUSECC_GROUP_12_WIDTH },
2960 };
2961 
2967 static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_CFG_P2P_BRIDGE_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_CFG_BRIDGE_DST_BUSECC_groupEntries[SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_CFG_P2P_BRIDGE_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_CFG_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS] =
2968 {
2969  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_CFG_P2P_BRIDGE_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_CFG_BRIDGE_DST_BUSECC_GROUP_0_CHECKER_TYPE,
2970  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_CFG_P2P_BRIDGE_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_CFG_BRIDGE_DST_BUSECC_GROUP_0_WIDTH },
2971  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_CFG_P2P_BRIDGE_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_CFG_BRIDGE_DST_BUSECC_GROUP_1_CHECKER_TYPE,
2972  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_CFG_P2P_BRIDGE_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_CFG_BRIDGE_DST_BUSECC_GROUP_1_WIDTH },
2973  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_CFG_P2P_BRIDGE_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_CFG_BRIDGE_DST_BUSECC_GROUP_2_CHECKER_TYPE,
2974  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_CFG_P2P_BRIDGE_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_CFG_BRIDGE_DST_BUSECC_GROUP_2_WIDTH },
2975  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_CFG_P2P_BRIDGE_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_CFG_BRIDGE_DST_BUSECC_GROUP_3_CHECKER_TYPE,
2976  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_CFG_P2P_BRIDGE_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_CFG_BRIDGE_DST_BUSECC_GROUP_3_WIDTH },
2977  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_CFG_P2P_BRIDGE_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_CFG_BRIDGE_DST_BUSECC_GROUP_4_CHECKER_TYPE,
2978  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_CFG_P2P_BRIDGE_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_CFG_BRIDGE_DST_BUSECC_GROUP_4_WIDTH },
2979  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_CFG_P2P_BRIDGE_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_CFG_BRIDGE_DST_BUSECC_GROUP_5_CHECKER_TYPE,
2980  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_CFG_P2P_BRIDGE_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_CFG_BRIDGE_DST_BUSECC_GROUP_5_WIDTH },
2981  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_CFG_P2P_BRIDGE_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_CFG_BRIDGE_DST_BUSECC_GROUP_6_CHECKER_TYPE,
2982  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_CFG_P2P_BRIDGE_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_CFG_BRIDGE_DST_BUSECC_GROUP_6_WIDTH },
2983 };
2984 
2990 static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_CFG_P2P_BRIDGE_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_CFG_BRIDGE_SRC_BUSECC_groupEntries[SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_CFG_P2P_BRIDGE_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_CFG_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS] =
2991 {
2992  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_CFG_P2P_BRIDGE_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_CFG_BRIDGE_SRC_BUSECC_GROUP_0_CHECKER_TYPE,
2993  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_CFG_P2P_BRIDGE_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_CFG_BRIDGE_SRC_BUSECC_GROUP_0_WIDTH },
2994  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_CFG_P2P_BRIDGE_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_CFG_BRIDGE_SRC_BUSECC_GROUP_1_CHECKER_TYPE,
2995  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_CFG_P2P_BRIDGE_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_CFG_BRIDGE_SRC_BUSECC_GROUP_1_WIDTH },
2996  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_CFG_P2P_BRIDGE_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_CFG_BRIDGE_SRC_BUSECC_GROUP_2_CHECKER_TYPE,
2997  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_CFG_P2P_BRIDGE_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_CFG_BRIDGE_SRC_BUSECC_GROUP_2_WIDTH },
2998  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_CFG_P2P_BRIDGE_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_CFG_BRIDGE_SRC_BUSECC_GROUP_3_CHECKER_TYPE,
2999  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_CFG_P2P_BRIDGE_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_CFG_BRIDGE_SRC_BUSECC_GROUP_3_WIDTH },
3000  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_CFG_P2P_BRIDGE_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_CFG_BRIDGE_SRC_BUSECC_GROUP_4_CHECKER_TYPE,
3001  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_CFG_P2P_BRIDGE_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_CFG_BRIDGE_SRC_BUSECC_GROUP_4_WIDTH },
3002  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_CFG_P2P_BRIDGE_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_CFG_BRIDGE_SRC_BUSECC_GROUP_5_CHECKER_TYPE,
3003  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_CFG_P2P_BRIDGE_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_CFG_BRIDGE_SRC_BUSECC_GROUP_5_WIDTH },
3004  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_CFG_P2P_BRIDGE_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_CFG_BRIDGE_SRC_BUSECC_GROUP_6_CHECKER_TYPE,
3005  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_CFG_P2P_BRIDGE_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_CFG_BRIDGE_SRC_BUSECC_GROUP_6_WIDTH },
3006  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_CFG_P2P_BRIDGE_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_CFG_BRIDGE_SRC_BUSECC_GROUP_7_CHECKER_TYPE,
3007  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_CFG_P2P_BRIDGE_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_CFG_BRIDGE_SRC_BUSECC_GROUP_7_WIDTH },
3008  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_CFG_P2P_BRIDGE_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_CFG_BRIDGE_SRC_BUSECC_GROUP_8_CHECKER_TYPE,
3009  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_CFG_P2P_BRIDGE_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_CFG_BRIDGE_SRC_BUSECC_GROUP_8_WIDTH },
3010  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_CFG_P2P_BRIDGE_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_CFG_BRIDGE_SRC_BUSECC_GROUP_9_CHECKER_TYPE,
3011  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_CFG_P2P_BRIDGE_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_CFG_BRIDGE_SRC_BUSECC_GROUP_9_WIDTH },
3012  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_CFG_P2P_BRIDGE_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_CFG_BRIDGE_SRC_BUSECC_GROUP_10_CHECKER_TYPE,
3013  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_CFG_P2P_BRIDGE_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_CFG_BRIDGE_SRC_BUSECC_GROUP_10_WIDTH },
3014  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_CFG_P2P_BRIDGE_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_CFG_BRIDGE_SRC_BUSECC_GROUP_11_CHECKER_TYPE,
3015  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_CFG_P2P_BRIDGE_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_CFG_BRIDGE_SRC_BUSECC_GROUP_11_WIDTH },
3016  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_CFG_P2P_BRIDGE_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_CFG_BRIDGE_SRC_BUSECC_GROUP_12_CHECKER_TYPE,
3017  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_CFG_P2P_BRIDGE_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_CFG_BRIDGE_SRC_BUSECC_GROUP_12_WIDTH },
3018  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_CFG_P2P_BRIDGE_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_CFG_BRIDGE_SRC_BUSECC_GROUP_13_CHECKER_TYPE,
3019  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_CFG_P2P_BRIDGE_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_CFG_BRIDGE_SRC_BUSECC_GROUP_13_WIDTH },
3020  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_CFG_P2P_BRIDGE_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_CFG_BRIDGE_SRC_BUSECC_GROUP_14_CHECKER_TYPE,
3021  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_CFG_P2P_BRIDGE_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_CFG_BRIDGE_SRC_BUSECC_GROUP_14_WIDTH },
3022  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_CFG_P2P_BRIDGE_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_CFG_BRIDGE_SRC_BUSECC_GROUP_15_CHECKER_TYPE,
3023  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_CFG_P2P_BRIDGE_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_CFG_BRIDGE_SRC_BUSECC_GROUP_15_WIDTH },
3024  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_CFG_P2P_BRIDGE_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_CFG_BRIDGE_SRC_BUSECC_GROUP_16_CHECKER_TYPE,
3025  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_CFG_P2P_BRIDGE_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_CFG_BRIDGE_SRC_BUSECC_GROUP_16_WIDTH },
3026 };
3027 
3033 static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ISAM62A_MCU_MCU_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM62A_MCU_MCU_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_groupEntries[SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ISAM62A_MCU_MCU_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM62A_MCU_MCU_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_MAX_NUM_CHECKERS] =
3034 {
3035  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ISAM62A_MCU_MCU_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM62A_MCU_MCU_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_GROUP_0_CHECKER_TYPE,
3036  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ISAM62A_MCU_MCU_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM62A_MCU_MCU_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_GROUP_0_WIDTH },
3037  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ISAM62A_MCU_MCU_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM62A_MCU_MCU_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_GROUP_1_CHECKER_TYPE,
3038  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ISAM62A_MCU_MCU_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM62A_MCU_MCU_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_GROUP_1_WIDTH },
3039  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ISAM62A_MCU_MCU_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM62A_MCU_MCU_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_GROUP_2_CHECKER_TYPE,
3040  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ISAM62A_MCU_MCU_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM62A_MCU_MCU_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_GROUP_2_WIDTH },
3041  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ISAM62A_MCU_MCU_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM62A_MCU_MCU_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_GROUP_3_CHECKER_TYPE,
3042  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ISAM62A_MCU_MCU_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM62A_MCU_MCU_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_GROUP_3_WIDTH },
3043  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ISAM62A_MCU_MCU_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM62A_MCU_MCU_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_GROUP_4_CHECKER_TYPE,
3044  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ISAM62A_MCU_MCU_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM62A_MCU_MCU_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_GROUP_4_WIDTH },
3045  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ISAM62A_MCU_MCU_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM62A_MCU_MCU_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_GROUP_5_CHECKER_TYPE,
3046  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ISAM62A_MCU_MCU_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM62A_MCU_MCU_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_GROUP_5_WIDTH },
3047  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ISAM62A_MCU_MCU_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM62A_MCU_MCU_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_GROUP_6_CHECKER_TYPE,
3048  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ISAM62A_MCU_MCU_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM62A_MCU_MCU_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_GROUP_6_WIDTH },
3049  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ISAM62A_MCU_MCU_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM62A_MCU_MCU_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_GROUP_7_CHECKER_TYPE,
3050  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ISAM62A_MCU_MCU_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM62A_MCU_MCU_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_GROUP_7_WIDTH },
3051  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ISAM62A_MCU_MCU_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM62A_MCU_MCU_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_GROUP_8_CHECKER_TYPE,
3052  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ISAM62A_MCU_MCU_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM62A_MCU_MCU_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_GROUP_8_WIDTH },
3053  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ISAM62A_MCU_MCU_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM62A_MCU_MCU_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_GROUP_9_CHECKER_TYPE,
3054  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ISAM62A_MCU_MCU_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM62A_MCU_MCU_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_GROUP_9_WIDTH },
3055  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ISAM62A_MCU_MCU_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM62A_MCU_MCU_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_GROUP_10_CHECKER_TYPE,
3056  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ISAM62A_MCU_MCU_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM62A_MCU_MCU_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_GROUP_10_WIDTH },
3057  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ISAM62A_MCU_MCU_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM62A_MCU_MCU_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_GROUP_11_CHECKER_TYPE,
3058  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ISAM62A_MCU_MCU_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM62A_MCU_MCU_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_GROUP_11_WIDTH },
3059  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ISAM62A_MCU_MCU_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM62A_MCU_MCU_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_GROUP_12_CHECKER_TYPE,
3060  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ISAM62A_MCU_MCU_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM62A_MCU_MCU_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_GROUP_12_WIDTH },
3061 };
3062 
3068 static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ISAM62A_MCU_PULSAR_UL_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM62A_MCU_PULSAR_UL_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_groupEntries[SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ISAM62A_MCU_PULSAR_UL_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM62A_MCU_PULSAR_UL_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_MAX_NUM_CHECKERS] =
3069 {
3070  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ISAM62A_MCU_PULSAR_UL_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM62A_MCU_PULSAR_UL_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_GROUP_0_CHECKER_TYPE,
3071  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ISAM62A_MCU_PULSAR_UL_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM62A_MCU_PULSAR_UL_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_GROUP_0_WIDTH },
3072  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ISAM62A_MCU_PULSAR_UL_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM62A_MCU_PULSAR_UL_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_GROUP_1_CHECKER_TYPE,
3073  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ISAM62A_MCU_PULSAR_UL_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM62A_MCU_PULSAR_UL_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_GROUP_1_WIDTH },
3074  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ISAM62A_MCU_PULSAR_UL_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM62A_MCU_PULSAR_UL_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_GROUP_2_CHECKER_TYPE,
3075  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ISAM62A_MCU_PULSAR_UL_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM62A_MCU_PULSAR_UL_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_GROUP_2_WIDTH },
3076  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ISAM62A_MCU_PULSAR_UL_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM62A_MCU_PULSAR_UL_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_GROUP_3_CHECKER_TYPE,
3077  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ISAM62A_MCU_PULSAR_UL_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM62A_MCU_PULSAR_UL_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_GROUP_3_WIDTH },
3078  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ISAM62A_MCU_PULSAR_UL_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM62A_MCU_PULSAR_UL_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_GROUP_4_CHECKER_TYPE,
3079  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ISAM62A_MCU_PULSAR_UL_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM62A_MCU_PULSAR_UL_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_GROUP_4_WIDTH },
3080  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ISAM62A_MCU_PULSAR_UL_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM62A_MCU_PULSAR_UL_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_GROUP_5_CHECKER_TYPE,
3081  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ISAM62A_MCU_PULSAR_UL_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM62A_MCU_PULSAR_UL_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_GROUP_5_WIDTH },
3082  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ISAM62A_MCU_PULSAR_UL_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM62A_MCU_PULSAR_UL_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_GROUP_6_CHECKER_TYPE,
3083  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ISAM62A_MCU_PULSAR_UL_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM62A_MCU_PULSAR_UL_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_GROUP_6_WIDTH },
3084  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ISAM62A_MCU_PULSAR_UL_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM62A_MCU_PULSAR_UL_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_GROUP_7_CHECKER_TYPE,
3085  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ISAM62A_MCU_PULSAR_UL_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM62A_MCU_PULSAR_UL_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_GROUP_7_WIDTH },
3086  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ISAM62A_MCU_PULSAR_UL_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM62A_MCU_PULSAR_UL_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_GROUP_8_CHECKER_TYPE,
3087  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ISAM62A_MCU_PULSAR_UL_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM62A_MCU_PULSAR_UL_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_GROUP_8_WIDTH },
3088  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ISAM62A_MCU_PULSAR_UL_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM62A_MCU_PULSAR_UL_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_GROUP_9_CHECKER_TYPE,
3089  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ISAM62A_MCU_PULSAR_UL_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM62A_MCU_PULSAR_UL_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_GROUP_9_WIDTH },
3090  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ISAM62A_MCU_PULSAR_UL_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM62A_MCU_PULSAR_UL_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_GROUP_10_CHECKER_TYPE,
3091  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ISAM62A_MCU_PULSAR_UL_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM62A_MCU_PULSAR_UL_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_GROUP_10_WIDTH },
3092  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ISAM62A_MCU_PULSAR_UL_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM62A_MCU_PULSAR_UL_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_GROUP_11_CHECKER_TYPE,
3093  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ISAM62A_MCU_PULSAR_UL_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM62A_MCU_PULSAR_UL_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_GROUP_11_WIDTH },
3094  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ISAM62A_MCU_PULSAR_UL_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM62A_MCU_PULSAR_UL_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_GROUP_12_CHECKER_TYPE,
3095  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ISAM62A_MCU_PULSAR_UL_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM62A_MCU_PULSAR_UL_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_GROUP_12_WIDTH },
3096 };
3097 
3103 static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_groupEntries[SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_MAX_NUM_CHECKERS] =
3104 {
3105  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_0_CHECKER_TYPE,
3106  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_0_WIDTH },
3107  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_1_CHECKER_TYPE,
3108  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_1_WIDTH },
3109  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_2_CHECKER_TYPE,
3110  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_2_WIDTH },
3111  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_3_CHECKER_TYPE,
3112  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_3_WIDTH },
3113  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_4_CHECKER_TYPE,
3114  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_4_WIDTH },
3115  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_5_CHECKER_TYPE,
3116  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_5_WIDTH },
3117  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_6_CHECKER_TYPE,
3118  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_6_WIDTH },
3119  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_7_CHECKER_TYPE,
3120  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_7_WIDTH },
3121  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_8_CHECKER_TYPE,
3122  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_8_WIDTH },
3123  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_9_CHECKER_TYPE,
3124  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_9_WIDTH },
3125  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_10_CHECKER_TYPE,
3126  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_10_WIDTH },
3127  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_11_CHECKER_TYPE,
3128  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_11_WIDTH },
3129  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_12_CHECKER_TYPE,
3130  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_12_WIDTH },
3131  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_13_CHECKER_TYPE,
3132  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_13_WIDTH },
3133  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_14_CHECKER_TYPE,
3134  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_14_WIDTH },
3135  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_15_CHECKER_TYPE,
3136  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_15_WIDTH },
3137  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_16_CHECKER_TYPE,
3138  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_16_WIDTH },
3139  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_17_CHECKER_TYPE,
3140  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_17_WIDTH },
3141  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_18_CHECKER_TYPE,
3142  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_18_WIDTH },
3143  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_19_CHECKER_TYPE,
3144  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_19_WIDTH },
3145  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_20_CHECKER_TYPE,
3146  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_20_WIDTH },
3147  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_21_CHECKER_TYPE,
3148  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_21_WIDTH },
3149  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_22_CHECKER_TYPE,
3150  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_22_WIDTH },
3151  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_23_CHECKER_TYPE,
3152  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_23_WIDTH },
3153  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_24_CHECKER_TYPE,
3154  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_24_WIDTH },
3155  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_25_CHECKER_TYPE,
3156  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_25_WIDTH },
3157  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_26_CHECKER_TYPE,
3158  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_26_WIDTH },
3159  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_27_CHECKER_TYPE,
3160  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_27_WIDTH },
3161  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_28_CHECKER_TYPE,
3162  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_28_WIDTH },
3163  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_29_CHECKER_TYPE,
3164  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_29_WIDTH },
3165  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_30_CHECKER_TYPE,
3166  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_30_WIDTH },
3167  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_31_CHECKER_TYPE,
3168  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_31_WIDTH },
3169  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_32_CHECKER_TYPE,
3170  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_32_WIDTH },
3171  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_33_CHECKER_TYPE,
3172  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_33_WIDTH },
3173  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_34_CHECKER_TYPE,
3174  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_34_WIDTH },
3175  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_35_CHECKER_TYPE,
3176  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_35_WIDTH },
3177  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_36_CHECKER_TYPE,
3178  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_36_WIDTH },
3179  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_37_CHECKER_TYPE,
3180  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_37_WIDTH },
3181  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_38_CHECKER_TYPE,
3182  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_38_WIDTH },
3183  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_39_CHECKER_TYPE,
3184  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_39_WIDTH },
3185  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_40_CHECKER_TYPE,
3186  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_40_WIDTH },
3187  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_41_CHECKER_TYPE,
3188  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_41_WIDTH },
3189  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_42_CHECKER_TYPE,
3190  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_42_WIDTH },
3191  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_43_CHECKER_TYPE,
3192  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_43_WIDTH },
3193  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_44_CHECKER_TYPE,
3194  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_44_WIDTH },
3195  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_45_CHECKER_TYPE,
3196  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_45_WIDTH },
3197  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_46_CHECKER_TYPE,
3198  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_46_WIDTH },
3199  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_47_CHECKER_TYPE,
3200  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_47_WIDTH },
3201  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_48_CHECKER_TYPE,
3202  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_48_WIDTH },
3203  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_49_CHECKER_TYPE,
3204  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_49_WIDTH },
3205  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_50_CHECKER_TYPE,
3206  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_50_WIDTH },
3207  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_51_CHECKER_TYPE,
3208  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_51_WIDTH },
3209  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_52_CHECKER_TYPE,
3210  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_52_WIDTH },
3211  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_53_CHECKER_TYPE,
3212  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_53_WIDTH },
3213  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_54_CHECKER_TYPE,
3214  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_54_WIDTH },
3215  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_55_CHECKER_TYPE,
3216  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_55_WIDTH },
3217  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_56_CHECKER_TYPE,
3218  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_56_WIDTH },
3219  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_57_CHECKER_TYPE,
3220  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_57_WIDTH },
3221  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_58_CHECKER_TYPE,
3222  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_58_WIDTH },
3223  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_59_CHECKER_TYPE,
3224  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_59_WIDTH },
3225  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_60_CHECKER_TYPE,
3226  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_60_WIDTH },
3227  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_61_CHECKER_TYPE,
3228  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_61_WIDTH },
3229  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_62_CHECKER_TYPE,
3230  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_62_WIDTH },
3231  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_63_CHECKER_TYPE,
3232  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_63_WIDTH },
3233  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_64_CHECKER_TYPE,
3234  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_64_WIDTH },
3235  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_65_CHECKER_TYPE,
3236  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_65_WIDTH },
3237  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_66_CHECKER_TYPE,
3238  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_66_WIDTH },
3239  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_67_CHECKER_TYPE,
3240  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_67_WIDTH },
3241  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_68_CHECKER_TYPE,
3242  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_68_WIDTH },
3243  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_69_CHECKER_TYPE,
3244  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_69_WIDTH },
3245  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_70_CHECKER_TYPE,
3246  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_70_WIDTH },
3247  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_71_CHECKER_TYPE,
3248  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_71_WIDTH },
3249  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_72_CHECKER_TYPE,
3250  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_72_WIDTH },
3251  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_73_CHECKER_TYPE,
3252  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_73_WIDTH },
3253  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_74_CHECKER_TYPE,
3254  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_74_WIDTH },
3255  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_75_CHECKER_TYPE,
3256  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_75_WIDTH },
3257  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_76_CHECKER_TYPE,
3258  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_76_WIDTH },
3259  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_77_CHECKER_TYPE,
3260  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_77_WIDTH },
3261  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_78_CHECKER_TYPE,
3262  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_78_WIDTH },
3263  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_79_CHECKER_TYPE,
3264  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_79_WIDTH },
3265  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_80_CHECKER_TYPE,
3266  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_80_WIDTH },
3267 };
3268 
3274 static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_groupEntries[SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_MAX_NUM_CHECKERS] =
3275 {
3276  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_0_CHECKER_TYPE,
3277  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_0_WIDTH },
3278  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_1_CHECKER_TYPE,
3279  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_1_WIDTH },
3280  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_2_CHECKER_TYPE,
3281  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_2_WIDTH },
3282  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_3_CHECKER_TYPE,
3283  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_3_WIDTH },
3284  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_4_CHECKER_TYPE,
3285  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_4_WIDTH },
3286  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_5_CHECKER_TYPE,
3287  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_5_WIDTH },
3288  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_6_CHECKER_TYPE,
3289  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_6_WIDTH },
3290  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_7_CHECKER_TYPE,
3291  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_7_WIDTH },
3292  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_8_CHECKER_TYPE,
3293  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_8_WIDTH },
3294  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_9_CHECKER_TYPE,
3295  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_9_WIDTH },
3296  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_10_CHECKER_TYPE,
3297  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_10_WIDTH },
3298  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_11_CHECKER_TYPE,
3299  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_11_WIDTH },
3300  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_12_CHECKER_TYPE,
3301  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_12_WIDTH },
3302  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_13_CHECKER_TYPE,
3303  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_13_WIDTH },
3304  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_14_CHECKER_TYPE,
3305  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_14_WIDTH },
3306  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_15_CHECKER_TYPE,
3307  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_15_WIDTH },
3308  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_16_CHECKER_TYPE,
3309  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_16_WIDTH },
3310  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_17_CHECKER_TYPE,
3311  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_17_WIDTH },
3312  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_18_CHECKER_TYPE,
3313  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_18_WIDTH },
3314  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_19_CHECKER_TYPE,
3315  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_19_WIDTH },
3316  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_20_CHECKER_TYPE,
3317  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_20_WIDTH },
3318  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_21_CHECKER_TYPE,
3319  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_21_WIDTH },
3320  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_22_CHECKER_TYPE,
3321  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_22_WIDTH },
3322  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_23_CHECKER_TYPE,
3323  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_23_WIDTH },
3324  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_24_CHECKER_TYPE,
3325  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_24_WIDTH },
3326  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_25_CHECKER_TYPE,
3327  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_25_WIDTH },
3328  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_26_CHECKER_TYPE,
3329  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_26_WIDTH },
3330  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_27_CHECKER_TYPE,
3331  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_27_WIDTH },
3332  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_28_CHECKER_TYPE,
3333  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_28_WIDTH },
3334  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_29_CHECKER_TYPE,
3335  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_29_WIDTH },
3336  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_30_CHECKER_TYPE,
3337  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_30_WIDTH },
3338  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_31_CHECKER_TYPE,
3339  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_31_WIDTH },
3340  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_32_CHECKER_TYPE,
3341  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_32_WIDTH },
3342  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_33_CHECKER_TYPE,
3343  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_33_WIDTH },
3344  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_34_CHECKER_TYPE,
3345  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_34_WIDTH },
3346  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_35_CHECKER_TYPE,
3347  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_35_WIDTH },
3348  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_36_CHECKER_TYPE,
3349  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_36_WIDTH },
3350  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_37_CHECKER_TYPE,
3351  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_37_WIDTH },
3352  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_38_CHECKER_TYPE,
3353  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_38_WIDTH },
3354  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_39_CHECKER_TYPE,
3355  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_39_WIDTH },
3356  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_40_CHECKER_TYPE,
3357  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_40_WIDTH },
3358  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_41_CHECKER_TYPE,
3359  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_41_WIDTH },
3360  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_42_CHECKER_TYPE,
3361  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_42_WIDTH },
3362  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_43_CHECKER_TYPE,
3363  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_43_WIDTH },
3364  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_44_CHECKER_TYPE,
3365  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_44_WIDTH },
3366  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_45_CHECKER_TYPE,
3367  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_45_WIDTH },
3368  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_46_CHECKER_TYPE,
3369  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_46_WIDTH },
3370  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_47_CHECKER_TYPE,
3371  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_47_WIDTH },
3372  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_48_CHECKER_TYPE,
3373  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_48_WIDTH },
3374  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_49_CHECKER_TYPE,
3375  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_49_WIDTH },
3376  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_50_CHECKER_TYPE,
3377  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_50_WIDTH },
3378  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_51_CHECKER_TYPE,
3379  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_51_WIDTH },
3380  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_52_CHECKER_TYPE,
3381  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_52_WIDTH },
3382  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_53_CHECKER_TYPE,
3383  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_53_WIDTH },
3384  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_54_CHECKER_TYPE,
3385  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_54_WIDTH },
3386  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_55_CHECKER_TYPE,
3387  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_55_WIDTH },
3388  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_56_CHECKER_TYPE,
3389  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_56_WIDTH },
3390  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_57_CHECKER_TYPE,
3391  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_57_WIDTH },
3392  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_58_CHECKER_TYPE,
3393  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_58_WIDTH },
3394  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_59_CHECKER_TYPE,
3395  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_59_WIDTH },
3396  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_60_CHECKER_TYPE,
3397  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_60_WIDTH },
3398  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_61_CHECKER_TYPE,
3399  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_61_WIDTH },
3400  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_62_CHECKER_TYPE,
3401  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_62_WIDTH },
3402  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_63_CHECKER_TYPE,
3403  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_63_WIDTH },
3404  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_64_CHECKER_TYPE,
3405  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_64_WIDTH },
3406  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_65_CHECKER_TYPE,
3407  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_65_WIDTH },
3408  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_66_CHECKER_TYPE,
3409  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_66_WIDTH },
3410  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_67_CHECKER_TYPE,
3411  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_67_WIDTH },
3412  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_68_CHECKER_TYPE,
3413  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_68_WIDTH },
3414  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_69_CHECKER_TYPE,
3415  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_69_WIDTH },
3416  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_70_CHECKER_TYPE,
3417  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_70_WIDTH },
3418  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_71_CHECKER_TYPE,
3419  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_71_WIDTH },
3420  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_72_CHECKER_TYPE,
3421  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_72_WIDTH },
3422  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_73_CHECKER_TYPE,
3423  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_73_WIDTH },
3424  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_74_CHECKER_TYPE,
3425  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_74_WIDTH },
3426  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_75_CHECKER_TYPE,
3427  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_75_WIDTH },
3428  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_76_CHECKER_TYPE,
3429  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_76_WIDTH },
3430  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_77_CHECKER_TYPE,
3431  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_77_WIDTH },
3432  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_78_CHECKER_TYPE,
3433  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_78_WIDTH },
3434  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_79_CHECKER_TYPE,
3435  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_79_WIDTH },
3436  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_80_CHECKER_TYPE,
3437  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_80_WIDTH },
3438  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_81_CHECKER_TYPE,
3439  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_81_WIDTH },
3440  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_82_CHECKER_TYPE,
3441  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_82_WIDTH },
3442  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_83_CHECKER_TYPE,
3443  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_83_WIDTH },
3444  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_84_CHECKER_TYPE,
3445  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_84_WIDTH },
3446  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_85_CHECKER_TYPE,
3447  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_85_WIDTH },
3448  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_86_CHECKER_TYPE,
3449  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_86_WIDTH },
3450  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_87_CHECKER_TYPE,
3451  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_87_WIDTH },
3452  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_88_CHECKER_TYPE,
3453  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_88_WIDTH },
3454  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_89_CHECKER_TYPE,
3455  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_89_WIDTH },
3456  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_90_CHECKER_TYPE,
3457  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_90_WIDTH },
3458  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_91_CHECKER_TYPE,
3459  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_91_WIDTH },
3460  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_92_CHECKER_TYPE,
3461  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_92_WIDTH },
3462  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_93_CHECKER_TYPE,
3463  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_93_WIDTH },
3464  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_94_CHECKER_TYPE,
3465  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_94_WIDTH },
3466  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_95_CHECKER_TYPE,
3467  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_95_WIDTH },
3468  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_96_CHECKER_TYPE,
3469  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_96_WIDTH },
3470  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_97_CHECKER_TYPE,
3471  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_97_WIDTH },
3472  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_98_CHECKER_TYPE,
3473  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_98_WIDTH },
3474  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_99_CHECKER_TYPE,
3475  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_99_WIDTH },
3476  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_100_CHECKER_TYPE,
3477  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_100_WIDTH },
3478 };
3479 
3485 static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_groupEntries[SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_MAX_NUM_CHECKERS] =
3486 {
3487  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_0_CHECKER_TYPE,
3488  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_0_WIDTH },
3489  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_1_CHECKER_TYPE,
3490  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_1_WIDTH },
3491  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_2_CHECKER_TYPE,
3492  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_2_WIDTH },
3493  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_3_CHECKER_TYPE,
3494  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_3_WIDTH },
3495  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_4_CHECKER_TYPE,
3496  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_4_WIDTH },
3497  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_5_CHECKER_TYPE,
3498  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_5_WIDTH },
3499  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_6_CHECKER_TYPE,
3500  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_6_WIDTH },
3501  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_7_CHECKER_TYPE,
3502  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_7_WIDTH },
3503  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_8_CHECKER_TYPE,
3504  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_8_WIDTH },
3505  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_9_CHECKER_TYPE,
3506  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_9_WIDTH },
3507  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_10_CHECKER_TYPE,
3508  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_10_WIDTH },
3509  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_11_CHECKER_TYPE,
3510  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_11_WIDTH },
3511  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_12_CHECKER_TYPE,
3512  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_12_WIDTH },
3513  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_13_CHECKER_TYPE,
3514  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_13_WIDTH },
3515  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_14_CHECKER_TYPE,
3516  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_14_WIDTH },
3517  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_15_CHECKER_TYPE,
3518  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_15_WIDTH },
3519  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_16_CHECKER_TYPE,
3520  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_16_WIDTH },
3521  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_17_CHECKER_TYPE,
3522  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_17_WIDTH },
3523  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_18_CHECKER_TYPE,
3524  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_18_WIDTH },
3525  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_19_CHECKER_TYPE,
3526  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_19_WIDTH },
3527  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_20_CHECKER_TYPE,
3528  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_20_WIDTH },
3529  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_21_CHECKER_TYPE,
3530  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_21_WIDTH },
3531  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_22_CHECKER_TYPE,
3532  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_22_WIDTH },
3533  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_23_CHECKER_TYPE,
3534  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_23_WIDTH },
3535  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_24_CHECKER_TYPE,
3536  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_24_WIDTH },
3537  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_25_CHECKER_TYPE,
3538  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_25_WIDTH },
3539  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_26_CHECKER_TYPE,
3540  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_26_WIDTH },
3541  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_27_CHECKER_TYPE,
3542  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_27_WIDTH },
3543  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_28_CHECKER_TYPE,
3544  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_28_WIDTH },
3545  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_29_CHECKER_TYPE,
3546  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_29_WIDTH },
3547  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_30_CHECKER_TYPE,
3548  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_30_WIDTH },
3549  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_31_CHECKER_TYPE,
3550  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_31_WIDTH },
3551  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_32_CHECKER_TYPE,
3552  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_32_WIDTH },
3553  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_33_CHECKER_TYPE,
3554  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_33_WIDTH },
3555  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_34_CHECKER_TYPE,
3556  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_34_WIDTH },
3557  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_35_CHECKER_TYPE,
3558  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_35_WIDTH },
3559  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_36_CHECKER_TYPE,
3560  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_36_WIDTH },
3561  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_37_CHECKER_TYPE,
3562  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_37_WIDTH },
3563  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_38_CHECKER_TYPE,
3564  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_38_WIDTH },
3565  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_39_CHECKER_TYPE,
3566  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_39_WIDTH },
3567  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_40_CHECKER_TYPE,
3568  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_40_WIDTH },
3569  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_41_CHECKER_TYPE,
3570  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_41_WIDTH },
3571  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_42_CHECKER_TYPE,
3572  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_42_WIDTH },
3573  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_43_CHECKER_TYPE,
3574  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_43_WIDTH },
3575  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_44_CHECKER_TYPE,
3576  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_44_WIDTH },
3577  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_45_CHECKER_TYPE,
3578  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_45_WIDTH },
3579  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_46_CHECKER_TYPE,
3580  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_46_WIDTH },
3581  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_47_CHECKER_TYPE,
3582  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_47_WIDTH },
3583  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_48_CHECKER_TYPE,
3584  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_48_WIDTH },
3585  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_49_CHECKER_TYPE,
3586  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_49_WIDTH },
3587  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_50_CHECKER_TYPE,
3588  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_50_WIDTH },
3589  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_51_CHECKER_TYPE,
3590  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_51_WIDTH },
3591  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_52_CHECKER_TYPE,
3592  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_52_WIDTH },
3593  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_53_CHECKER_TYPE,
3594  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_53_WIDTH },
3595  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_54_CHECKER_TYPE,
3596  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_54_WIDTH },
3597  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_55_CHECKER_TYPE,
3598  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_55_WIDTH },
3599  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_56_CHECKER_TYPE,
3600  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_56_WIDTH },
3601  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_57_CHECKER_TYPE,
3602  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_57_WIDTH },
3603  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_58_CHECKER_TYPE,
3604  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_58_WIDTH },
3605  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_59_CHECKER_TYPE,
3606  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_59_WIDTH },
3607  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_60_CHECKER_TYPE,
3608  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_60_WIDTH },
3609  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_61_CHECKER_TYPE,
3610  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_61_WIDTH },
3611  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_62_CHECKER_TYPE,
3612  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_62_WIDTH },
3613  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_63_CHECKER_TYPE,
3614  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_63_WIDTH },
3615  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_64_CHECKER_TYPE,
3616  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_64_WIDTH },
3617  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_65_CHECKER_TYPE,
3618  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_65_WIDTH },
3619  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_66_CHECKER_TYPE,
3620  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_66_WIDTH },
3621  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_67_CHECKER_TYPE,
3622  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_67_WIDTH },
3623  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_68_CHECKER_TYPE,
3624  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_68_WIDTH },
3625  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_69_CHECKER_TYPE,
3626  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_69_WIDTH },
3627  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_70_CHECKER_TYPE,
3628  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_70_WIDTH },
3629  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_71_CHECKER_TYPE,
3630  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_71_WIDTH },
3631  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_72_CHECKER_TYPE,
3632  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_72_WIDTH },
3633  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_73_CHECKER_TYPE,
3634  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_73_WIDTH },
3635  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_74_CHECKER_TYPE,
3636  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_74_WIDTH },
3637  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_75_CHECKER_TYPE,
3638  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_75_WIDTH },
3639  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_76_CHECKER_TYPE,
3640  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_76_WIDTH },
3641  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_77_CHECKER_TYPE,
3642  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_77_WIDTH },
3643  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_78_CHECKER_TYPE,
3644  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_78_WIDTH },
3645  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_79_CHECKER_TYPE,
3646  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_79_WIDTH },
3647  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_80_CHECKER_TYPE,
3648  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_80_WIDTH },
3649  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_81_CHECKER_TYPE,
3650  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_81_WIDTH },
3651  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_82_CHECKER_TYPE,
3652  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_82_WIDTH },
3653  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_83_CHECKER_TYPE,
3654  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_83_WIDTH },
3655  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_84_CHECKER_TYPE,
3656  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_84_WIDTH },
3657  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_85_CHECKER_TYPE,
3658  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_85_WIDTH },
3659  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_86_CHECKER_TYPE,
3660  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_86_WIDTH },
3661  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_87_CHECKER_TYPE,
3662  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_87_WIDTH },
3663  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_88_CHECKER_TYPE,
3664  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_88_WIDTH },
3665  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_89_CHECKER_TYPE,
3666  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_89_WIDTH },
3667  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_90_CHECKER_TYPE,
3668  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_90_WIDTH },
3669  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_91_CHECKER_TYPE,
3670  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_91_WIDTH },
3671  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_92_CHECKER_TYPE,
3672  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_92_WIDTH },
3673  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_93_CHECKER_TYPE,
3674  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_93_WIDTH },
3675  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_94_CHECKER_TYPE,
3676  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_94_WIDTH },
3677  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_95_CHECKER_TYPE,
3678  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_95_WIDTH },
3679  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_96_CHECKER_TYPE,
3680  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_96_WIDTH },
3681  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_97_CHECKER_TYPE,
3682  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_97_WIDTH },
3683  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_98_CHECKER_TYPE,
3684  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_98_WIDTH },
3685  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_99_CHECKER_TYPE,
3686  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_99_WIDTH },
3687  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_100_CHECKER_TYPE,
3688  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_100_WIDTH },
3689  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_101_CHECKER_TYPE,
3690  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_101_WIDTH },
3691  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_102_CHECKER_TYPE,
3692  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_102_WIDTH },
3693  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_103_CHECKER_TYPE,
3694  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_103_WIDTH },
3695  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_104_CHECKER_TYPE,
3696  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_104_WIDTH },
3697  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_105_CHECKER_TYPE,
3698  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_105_WIDTH },
3699  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_106_CHECKER_TYPE,
3700  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_106_WIDTH },
3701  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_107_CHECKER_TYPE,
3702  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_107_WIDTH },
3703  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_108_CHECKER_TYPE,
3704  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_108_WIDTH },
3705  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_109_CHECKER_TYPE,
3706  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_109_WIDTH },
3707  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_110_CHECKER_TYPE,
3708  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_110_WIDTH },
3709  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_111_CHECKER_TYPE,
3710  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_111_WIDTH },
3711  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_112_CHECKER_TYPE,
3712  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_112_WIDTH },
3713  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_113_CHECKER_TYPE,
3714  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_113_WIDTH },
3715  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_114_CHECKER_TYPE,
3716  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_114_WIDTH },
3717  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_115_CHECKER_TYPE,
3718  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_115_WIDTH },
3719  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_116_CHECKER_TYPE,
3720  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_116_WIDTH },
3721  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_117_CHECKER_TYPE,
3722  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_117_WIDTH },
3723  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_118_CHECKER_TYPE,
3724  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_118_WIDTH },
3725  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_119_CHECKER_TYPE,
3726  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_119_WIDTH },
3727  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_120_CHECKER_TYPE,
3728  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_120_WIDTH },
3729  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_121_CHECKER_TYPE,
3730  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_121_WIDTH },
3731  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_122_CHECKER_TYPE,
3732  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_122_WIDTH },
3733  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_123_CHECKER_TYPE,
3734  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_123_WIDTH },
3735  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_124_CHECKER_TYPE,
3736  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_124_WIDTH },
3737  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_125_CHECKER_TYPE,
3738  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_125_WIDTH },
3739  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_126_CHECKER_TYPE,
3740  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_126_WIDTH },
3741  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_127_CHECKER_TYPE,
3742  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_127_WIDTH },
3743  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_128_CHECKER_TYPE,
3744  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_128_WIDTH },
3745  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_129_CHECKER_TYPE,
3746  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_129_WIDTH },
3747  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_130_CHECKER_TYPE,
3748  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_130_WIDTH },
3749  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_131_CHECKER_TYPE,
3750  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_131_WIDTH },
3751  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_132_CHECKER_TYPE,
3752  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_132_WIDTH },
3753  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_133_CHECKER_TYPE,
3754  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_133_WIDTH },
3755  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_134_CHECKER_TYPE,
3756  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_134_WIDTH },
3757 };
3758 
3764 static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_groupEntries[SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_MAX_NUM_CHECKERS] =
3765 {
3766  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_0_CHECKER_TYPE,
3767  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_0_WIDTH },
3768  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_1_CHECKER_TYPE,
3769  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_1_WIDTH },
3770  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_2_CHECKER_TYPE,
3771  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_2_WIDTH },
3772  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_3_CHECKER_TYPE,
3773  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_3_WIDTH },
3774  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_4_CHECKER_TYPE,
3775  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_4_WIDTH },
3776  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_5_CHECKER_TYPE,
3777  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_5_WIDTH },
3778  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_6_CHECKER_TYPE,
3779  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_6_WIDTH },
3780  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_7_CHECKER_TYPE,
3781  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_7_WIDTH },
3782  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_8_CHECKER_TYPE,
3783  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_8_WIDTH },
3784  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_9_CHECKER_TYPE,
3785  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_9_WIDTH },
3786  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_10_CHECKER_TYPE,
3787  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_10_WIDTH },
3788  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_11_CHECKER_TYPE,
3789  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_11_WIDTH },
3790  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_12_CHECKER_TYPE,
3791  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_12_WIDTH },
3792  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_13_CHECKER_TYPE,
3793  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_13_WIDTH },
3794  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_14_CHECKER_TYPE,
3795  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_14_WIDTH },
3796  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_15_CHECKER_TYPE,
3797  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_15_WIDTH },
3798  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_16_CHECKER_TYPE,
3799  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_16_WIDTH },
3800  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_17_CHECKER_TYPE,
3801  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_17_WIDTH },
3802  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_18_CHECKER_TYPE,
3803  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_18_WIDTH },
3804  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_19_CHECKER_TYPE,
3805  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_19_WIDTH },
3806  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_20_CHECKER_TYPE,
3807  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_20_WIDTH },
3808  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_21_CHECKER_TYPE,
3809  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_21_WIDTH },
3810  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_22_CHECKER_TYPE,
3811  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_22_WIDTH },
3812  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_23_CHECKER_TYPE,
3813  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_23_WIDTH },
3814  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_24_CHECKER_TYPE,
3815  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_24_WIDTH },
3816  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_25_CHECKER_TYPE,
3817  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_25_WIDTH },
3818  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_26_CHECKER_TYPE,
3819  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_26_WIDTH },
3820  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_27_CHECKER_TYPE,
3821  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_27_WIDTH },
3822  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_28_CHECKER_TYPE,
3823  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_28_WIDTH },
3824  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_29_CHECKER_TYPE,
3825  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_29_WIDTH },
3826  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_30_CHECKER_TYPE,
3827  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_30_WIDTH },
3828  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_31_CHECKER_TYPE,
3829  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_31_WIDTH },
3830  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_32_CHECKER_TYPE,
3831  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_32_WIDTH },
3832  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_33_CHECKER_TYPE,
3833  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_33_WIDTH },
3834  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_34_CHECKER_TYPE,
3835  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_34_WIDTH },
3836  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_35_CHECKER_TYPE,
3837  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_35_WIDTH },
3838  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_36_CHECKER_TYPE,
3839  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_36_WIDTH },
3840  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_37_CHECKER_TYPE,
3841  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_37_WIDTH },
3842  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_38_CHECKER_TYPE,
3843  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_38_WIDTH },
3844  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_39_CHECKER_TYPE,
3845  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_39_WIDTH },
3846  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_40_CHECKER_TYPE,
3847  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_40_WIDTH },
3848  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_41_CHECKER_TYPE,
3849  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_41_WIDTH },
3850  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_42_CHECKER_TYPE,
3851  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_42_WIDTH },
3852  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_43_CHECKER_TYPE,
3853  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_43_WIDTH },
3854  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_44_CHECKER_TYPE,
3855  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_44_WIDTH },
3856  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_45_CHECKER_TYPE,
3857  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_45_WIDTH },
3858  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_46_CHECKER_TYPE,
3859  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_46_WIDTH },
3860  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_47_CHECKER_TYPE,
3861  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_47_WIDTH },
3862  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_48_CHECKER_TYPE,
3863  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_48_WIDTH },
3864  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_49_CHECKER_TYPE,
3865  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_49_WIDTH },
3866  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_50_CHECKER_TYPE,
3867  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_50_WIDTH },
3868  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_51_CHECKER_TYPE,
3869  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_51_WIDTH },
3870  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_52_CHECKER_TYPE,
3871  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_52_WIDTH },
3872  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_53_CHECKER_TYPE,
3873  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_53_WIDTH },
3874  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_54_CHECKER_TYPE,
3875  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_54_WIDTH },
3876  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_55_CHECKER_TYPE,
3877  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_55_WIDTH },
3878  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_56_CHECKER_TYPE,
3879  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_56_WIDTH },
3880  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_57_CHECKER_TYPE,
3881  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_57_WIDTH },
3882  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_58_CHECKER_TYPE,
3883  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_58_WIDTH },
3884  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_59_CHECKER_TYPE,
3885  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_59_WIDTH },
3886  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_60_CHECKER_TYPE,
3887  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_60_WIDTH },
3888  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_61_CHECKER_TYPE,
3889  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_61_WIDTH },
3890  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_62_CHECKER_TYPE,
3891  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_62_WIDTH },
3892  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_63_CHECKER_TYPE,
3893  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_63_WIDTH },
3894  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_64_CHECKER_TYPE,
3895  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_64_WIDTH },
3896  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_65_CHECKER_TYPE,
3897  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_65_WIDTH },
3898  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_66_CHECKER_TYPE,
3899  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_66_WIDTH },
3900  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_67_CHECKER_TYPE,
3901  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_67_WIDTH },
3902  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_68_CHECKER_TYPE,
3903  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_68_WIDTH },
3904  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_69_CHECKER_TYPE,
3905  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_69_WIDTH },
3906  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_70_CHECKER_TYPE,
3907  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_70_WIDTH },
3908  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_71_CHECKER_TYPE,
3909  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_71_WIDTH },
3910  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_72_CHECKER_TYPE,
3911  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_72_WIDTH },
3912  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_73_CHECKER_TYPE,
3913  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_73_WIDTH },
3914  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_74_CHECKER_TYPE,
3915  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_74_WIDTH },
3916  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_75_CHECKER_TYPE,
3917  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_75_WIDTH },
3918  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_76_CHECKER_TYPE,
3919  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_76_WIDTH },
3920  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_77_CHECKER_TYPE,
3921  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_77_WIDTH },
3922  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_78_CHECKER_TYPE,
3923  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_78_WIDTH },
3924  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_79_CHECKER_TYPE,
3925  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_79_WIDTH },
3926  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_80_CHECKER_TYPE,
3927  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_80_WIDTH },
3928  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_81_CHECKER_TYPE,
3929  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_81_WIDTH },
3930  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_82_CHECKER_TYPE,
3931  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_82_WIDTH },
3932  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_83_CHECKER_TYPE,
3933  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_83_WIDTH },
3934  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_84_CHECKER_TYPE,
3935  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_84_WIDTH },
3936  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_85_CHECKER_TYPE,
3937  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_85_WIDTH },
3938  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_86_CHECKER_TYPE,
3939  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_86_WIDTH },
3940  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_87_CHECKER_TYPE,
3941  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_87_WIDTH },
3942  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_88_CHECKER_TYPE,
3943  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_88_WIDTH },
3944  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_89_CHECKER_TYPE,
3945  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_89_WIDTH },
3946  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_90_CHECKER_TYPE,
3947  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_90_WIDTH },
3948  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_91_CHECKER_TYPE,
3949  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_91_WIDTH },
3950  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_92_CHECKER_TYPE,
3951  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_92_WIDTH },
3952  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_93_CHECKER_TYPE,
3953  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_93_WIDTH },
3954  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_94_CHECKER_TYPE,
3955  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_94_WIDTH },
3956  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_95_CHECKER_TYPE,
3957  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_95_WIDTH },
3958  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_96_CHECKER_TYPE,
3959  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_96_WIDTH },
3960  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_97_CHECKER_TYPE,
3961  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_97_WIDTH },
3962  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_98_CHECKER_TYPE,
3963  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_98_WIDTH },
3964  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_99_CHECKER_TYPE,
3965  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_99_WIDTH },
3966  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_100_CHECKER_TYPE,
3967  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_100_WIDTH },
3968  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_101_CHECKER_TYPE,
3969  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_101_WIDTH },
3970  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_102_CHECKER_TYPE,
3971  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_102_WIDTH },
3972  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_103_CHECKER_TYPE,
3973  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_103_WIDTH },
3974  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_104_CHECKER_TYPE,
3975  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_104_WIDTH },
3976  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_105_CHECKER_TYPE,
3977  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_105_WIDTH },
3978  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_106_CHECKER_TYPE,
3979  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_106_WIDTH },
3980  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_107_CHECKER_TYPE,
3981  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_107_WIDTH },
3982  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_108_CHECKER_TYPE,
3983  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_108_WIDTH },
3984  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_109_CHECKER_TYPE,
3985  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_109_WIDTH },
3986  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_110_CHECKER_TYPE,
3987  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_110_WIDTH },
3988  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_111_CHECKER_TYPE,
3989  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_111_WIDTH },
3990  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_112_CHECKER_TYPE,
3991  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_112_WIDTH },
3992  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_113_CHECKER_TYPE,
3993  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_113_WIDTH },
3994  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_114_CHECKER_TYPE,
3995  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_114_WIDTH },
3996  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_115_CHECKER_TYPE,
3997  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_115_WIDTH },
3998  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_116_CHECKER_TYPE,
3999  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_116_WIDTH },
4000  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_117_CHECKER_TYPE,
4001  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_117_WIDTH },
4002  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_118_CHECKER_TYPE,
4003  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_118_WIDTH },
4004  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_119_CHECKER_TYPE,
4005  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_119_WIDTH },
4006  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_120_CHECKER_TYPE,
4007  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_120_WIDTH },
4008  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_121_CHECKER_TYPE,
4009  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_121_WIDTH },
4010  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_122_CHECKER_TYPE,
4011  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_122_WIDTH },
4012  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_123_CHECKER_TYPE,
4013  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_123_WIDTH },
4014  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_124_CHECKER_TYPE,
4015  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_124_WIDTH },
4016  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_125_CHECKER_TYPE,
4017  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_125_WIDTH },
4018  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_126_CHECKER_TYPE,
4019  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_126_WIDTH },
4020  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_127_CHECKER_TYPE,
4021  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_127_WIDTH },
4022  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_128_CHECKER_TYPE,
4023  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_128_WIDTH },
4024  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_129_CHECKER_TYPE,
4025  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_129_WIDTH },
4026  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_130_CHECKER_TYPE,
4027  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_130_WIDTH },
4028  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_131_CHECKER_TYPE,
4029  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_131_WIDTH },
4030  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_132_CHECKER_TYPE,
4031  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_132_WIDTH },
4032  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_133_CHECKER_TYPE,
4033  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_133_WIDTH },
4034  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_134_CHECKER_TYPE,
4035  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_134_WIDTH },
4036  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_135_CHECKER_TYPE,
4037  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_135_WIDTH },
4038  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_136_CHECKER_TYPE,
4039  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_136_WIDTH },
4040  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_137_CHECKER_TYPE,
4041  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_137_WIDTH },
4042  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_138_CHECKER_TYPE,
4043  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_138_WIDTH },
4044  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_139_CHECKER_TYPE,
4045  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_139_WIDTH },
4046  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_140_CHECKER_TYPE,
4047  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_140_WIDTH },
4048  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_141_CHECKER_TYPE,
4049  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_141_WIDTH },
4050  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_142_CHECKER_TYPE,
4051  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_142_WIDTH },
4052  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_143_CHECKER_TYPE,
4053  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_143_WIDTH },
4054  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_144_CHECKER_TYPE,
4055  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_144_WIDTH },
4056  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_145_CHECKER_TYPE,
4057  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_145_WIDTH },
4058  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_146_CHECKER_TYPE,
4059  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_146_WIDTH },
4060  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_147_CHECKER_TYPE,
4061  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_147_WIDTH },
4062  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_148_CHECKER_TYPE,
4063  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_148_WIDTH },
4064  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_149_CHECKER_TYPE,
4065  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_149_WIDTH },
4066  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_150_CHECKER_TYPE,
4067  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_150_WIDTH },
4068  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_151_CHECKER_TYPE,
4069  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_151_WIDTH },
4070  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_152_CHECKER_TYPE,
4071  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_152_WIDTH },
4072  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_153_CHECKER_TYPE,
4073  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_153_WIDTH },
4074  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_154_CHECKER_TYPE,
4075  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_154_WIDTH },
4076  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_155_CHECKER_TYPE,
4077  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_155_WIDTH },
4078  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_156_CHECKER_TYPE,
4079  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_156_WIDTH },
4080  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_157_CHECKER_TYPE,
4081  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_157_WIDTH },
4082  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_158_CHECKER_TYPE,
4083  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_158_WIDTH },
4084  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_159_CHECKER_TYPE,
4085  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_159_WIDTH },
4086  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_160_CHECKER_TYPE,
4087  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_160_WIDTH },
4088  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_161_CHECKER_TYPE,
4089  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_161_WIDTH },
4090  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_162_CHECKER_TYPE,
4091  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_162_WIDTH },
4092  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_163_CHECKER_TYPE,
4093  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_163_WIDTH },
4094  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_164_CHECKER_TYPE,
4095  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_164_WIDTH },
4096  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_165_CHECKER_TYPE,
4097  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_165_WIDTH },
4098  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_166_CHECKER_TYPE,
4099  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_166_WIDTH },
4100  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_167_CHECKER_TYPE,
4101  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_167_WIDTH },
4102  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_168_CHECKER_TYPE,
4103  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_168_WIDTH },
4104  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_169_CHECKER_TYPE,
4105  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_169_WIDTH },
4106  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_170_CHECKER_TYPE,
4107  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_170_WIDTH },
4108  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_171_CHECKER_TYPE,
4109  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_171_WIDTH },
4110  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_172_CHECKER_TYPE,
4111  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_172_WIDTH },
4112  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_173_CHECKER_TYPE,
4113  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_173_WIDTH },
4114  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_174_CHECKER_TYPE,
4115  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_174_WIDTH },
4116  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_175_CHECKER_TYPE,
4117  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_175_WIDTH },
4118  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_176_CHECKER_TYPE,
4119  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_176_WIDTH },
4120  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_177_CHECKER_TYPE,
4121  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_177_WIDTH },
4122  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_178_CHECKER_TYPE,
4123  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_178_WIDTH },
4124  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_179_CHECKER_TYPE,
4125  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_179_WIDTH },
4126  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_180_CHECKER_TYPE,
4127  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_180_WIDTH },
4128  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_181_CHECKER_TYPE,
4129  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_181_WIDTH },
4130  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_182_CHECKER_TYPE,
4131  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_182_WIDTH },
4132  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_183_CHECKER_TYPE,
4133  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_183_WIDTH },
4134  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_184_CHECKER_TYPE,
4135  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_184_WIDTH },
4136  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_185_CHECKER_TYPE,
4137  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_185_WIDTH },
4138  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_186_CHECKER_TYPE,
4139  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_186_WIDTH },
4140  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_187_CHECKER_TYPE,
4141  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_187_WIDTH },
4142  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_188_CHECKER_TYPE,
4143  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_188_WIDTH },
4144  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_189_CHECKER_TYPE,
4145  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_189_WIDTH },
4146  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_190_CHECKER_TYPE,
4147  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_190_WIDTH },
4148  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_191_CHECKER_TYPE,
4149  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_191_WIDTH },
4150  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_192_CHECKER_TYPE,
4151  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_192_WIDTH },
4152  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_193_CHECKER_TYPE,
4153  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_193_WIDTH },
4154  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_194_CHECKER_TYPE,
4155  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_194_WIDTH },
4156  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_195_CHECKER_TYPE,
4157  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_195_WIDTH },
4158  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_196_CHECKER_TYPE,
4159  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_196_WIDTH },
4160  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_197_CHECKER_TYPE,
4161  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_197_WIDTH },
4162  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_198_CHECKER_TYPE,
4163  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_198_WIDTH },
4164  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_199_CHECKER_TYPE,
4165  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_199_WIDTH },
4166  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_200_CHECKER_TYPE,
4167  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_200_WIDTH },
4168  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_201_CHECKER_TYPE,
4169  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_201_WIDTH },
4170  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_202_CHECKER_TYPE,
4171  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_202_WIDTH },
4172  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_203_CHECKER_TYPE,
4173  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_203_WIDTH },
4174  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_204_CHECKER_TYPE,
4175  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_204_WIDTH },
4176  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_205_CHECKER_TYPE,
4177  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_205_WIDTH },
4178  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_206_CHECKER_TYPE,
4179  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_206_WIDTH },
4180  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_207_CHECKER_TYPE,
4181  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_207_WIDTH },
4182  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_208_CHECKER_TYPE,
4183  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_208_WIDTH },
4184  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_209_CHECKER_TYPE,
4185  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_209_WIDTH },
4186  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_210_CHECKER_TYPE,
4187  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_210_WIDTH },
4188  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_211_CHECKER_TYPE,
4189  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_211_WIDTH },
4190  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_212_CHECKER_TYPE,
4191  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_212_WIDTH },
4192  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_213_CHECKER_TYPE,
4193  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_213_WIDTH },
4194  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_214_CHECKER_TYPE,
4195  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_214_WIDTH },
4196  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_215_CHECKER_TYPE,
4197  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_215_WIDTH },
4198  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_216_CHECKER_TYPE,
4199  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_216_WIDTH },
4200  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_217_CHECKER_TYPE,
4201  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_217_WIDTH },
4202  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_218_CHECKER_TYPE,
4203  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_218_WIDTH },
4204  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_219_CHECKER_TYPE,
4205  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_219_WIDTH },
4206  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_220_CHECKER_TYPE,
4207  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_220_WIDTH },
4208  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_221_CHECKER_TYPE,
4209  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_221_WIDTH },
4210  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_222_CHECKER_TYPE,
4211  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_222_WIDTH },
4212  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_223_CHECKER_TYPE,
4213  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_223_WIDTH },
4214  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_224_CHECKER_TYPE,
4215  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_224_WIDTH },
4216  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_225_CHECKER_TYPE,
4217  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_225_WIDTH },
4218  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_226_CHECKER_TYPE,
4219  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_226_WIDTH },
4220  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_227_CHECKER_TYPE,
4221  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_227_WIDTH },
4222  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_228_CHECKER_TYPE,
4223  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_228_WIDTH },
4224  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_229_CHECKER_TYPE,
4225  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_229_WIDTH },
4226  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_230_CHECKER_TYPE,
4227  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_230_WIDTH },
4228  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_231_CHECKER_TYPE,
4229  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_231_WIDTH },
4230  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_232_CHECKER_TYPE,
4231  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_232_WIDTH },
4232  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_233_CHECKER_TYPE,
4233  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_233_WIDTH },
4234  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_234_CHECKER_TYPE,
4235  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_234_WIDTH },
4236  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_235_CHECKER_TYPE,
4237  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_235_WIDTH },
4238  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_236_CHECKER_TYPE,
4239  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_236_WIDTH },
4240  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_237_CHECKER_TYPE,
4241  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_237_WIDTH },
4242  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_238_CHECKER_TYPE,
4243  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_238_WIDTH },
4244  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_239_CHECKER_TYPE,
4245  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_239_WIDTH },
4246  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_240_CHECKER_TYPE,
4247  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_240_WIDTH },
4248  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_241_CHECKER_TYPE,
4249  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_241_WIDTH },
4250  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_242_CHECKER_TYPE,
4251  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_242_WIDTH },
4252  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_243_CHECKER_TYPE,
4253  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_243_WIDTH },
4254  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_244_CHECKER_TYPE,
4255  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_244_WIDTH },
4256  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_245_CHECKER_TYPE,
4257  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_245_WIDTH },
4258  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_246_CHECKER_TYPE,
4259  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_246_WIDTH },
4260  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_247_CHECKER_TYPE,
4261  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_247_WIDTH },
4262  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_248_CHECKER_TYPE,
4263  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_248_WIDTH },
4264  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_249_CHECKER_TYPE,
4265  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_249_WIDTH },
4266  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_250_CHECKER_TYPE,
4267  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_250_WIDTH },
4268  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_251_CHECKER_TYPE,
4269  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_251_WIDTH },
4270  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_252_CHECKER_TYPE,
4271  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_252_WIDTH },
4272  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_253_CHECKER_TYPE,
4273  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_253_WIDTH },
4274  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_254_CHECKER_TYPE,
4275  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_254_WIDTH },
4276  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_255_CHECKER_TYPE,
4277  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_255_WIDTH },
4278 };
4279 
4285 static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_groupEntries[SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_MAX_NUM_CHECKERS] =
4286 {
4287  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_0_CHECKER_TYPE,
4288  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_0_WIDTH },
4289  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_1_CHECKER_TYPE,
4290  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_1_WIDTH },
4291  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_2_CHECKER_TYPE,
4292  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_2_WIDTH },
4293  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_3_CHECKER_TYPE,
4294  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_3_WIDTH },
4295  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_4_CHECKER_TYPE,
4296  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_4_WIDTH },
4297  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_5_CHECKER_TYPE,
4298  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_5_WIDTH },
4299  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_6_CHECKER_TYPE,
4300  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_6_WIDTH },
4301  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_7_CHECKER_TYPE,
4302  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_7_WIDTH },
4303  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_8_CHECKER_TYPE,
4304  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_8_WIDTH },
4305  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_9_CHECKER_TYPE,
4306  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_9_WIDTH },
4307  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_10_CHECKER_TYPE,
4308  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_10_WIDTH },
4309  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_11_CHECKER_TYPE,
4310  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_11_WIDTH },
4311  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_12_CHECKER_TYPE,
4312  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_12_WIDTH },
4313  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_13_CHECKER_TYPE,
4314  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_13_WIDTH },
4315  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_14_CHECKER_TYPE,
4316  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_14_WIDTH },
4317  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_15_CHECKER_TYPE,
4318  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_15_WIDTH },
4319  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_16_CHECKER_TYPE,
4320  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_16_WIDTH },
4321  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_17_CHECKER_TYPE,
4322  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_17_WIDTH },
4323  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_18_CHECKER_TYPE,
4324  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_18_WIDTH },
4325  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_19_CHECKER_TYPE,
4326  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_19_WIDTH },
4327  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_20_CHECKER_TYPE,
4328  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_20_WIDTH },
4329  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_21_CHECKER_TYPE,
4330  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_21_WIDTH },
4331  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_22_CHECKER_TYPE,
4332  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_22_WIDTH },
4333  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_23_CHECKER_TYPE,
4334  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_23_WIDTH },
4335  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_24_CHECKER_TYPE,
4336  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_24_WIDTH },
4337  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_25_CHECKER_TYPE,
4338  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_25_WIDTH },
4339  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_26_CHECKER_TYPE,
4340  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_26_WIDTH },
4341  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_27_CHECKER_TYPE,
4342  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_27_WIDTH },
4343  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_28_CHECKER_TYPE,
4344  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_28_WIDTH },
4345  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_29_CHECKER_TYPE,
4346  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_29_WIDTH },
4347  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_30_CHECKER_TYPE,
4348  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_30_WIDTH },
4349  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_31_CHECKER_TYPE,
4350  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_31_WIDTH },
4351  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_32_CHECKER_TYPE,
4352  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_32_WIDTH },
4353  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_33_CHECKER_TYPE,
4354  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_33_WIDTH },
4355  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_34_CHECKER_TYPE,
4356  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_34_WIDTH },
4357  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_35_CHECKER_TYPE,
4358  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_35_WIDTH },
4359  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_36_CHECKER_TYPE,
4360  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_36_WIDTH },
4361  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_37_CHECKER_TYPE,
4362  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_37_WIDTH },
4363  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_38_CHECKER_TYPE,
4364  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_38_WIDTH },
4365  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_39_CHECKER_TYPE,
4366  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_39_WIDTH },
4367  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_40_CHECKER_TYPE,
4368  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_40_WIDTH },
4369  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_41_CHECKER_TYPE,
4370  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_41_WIDTH },
4371  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_42_CHECKER_TYPE,
4372  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_42_WIDTH },
4373  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_43_CHECKER_TYPE,
4374  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_43_WIDTH },
4375  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_44_CHECKER_TYPE,
4376  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_44_WIDTH },
4377  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_45_CHECKER_TYPE,
4378  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_45_WIDTH },
4379  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_46_CHECKER_TYPE,
4380  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_46_WIDTH },
4381  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_47_CHECKER_TYPE,
4382  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_47_WIDTH },
4383  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_48_CHECKER_TYPE,
4384  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_48_WIDTH },
4385  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_49_CHECKER_TYPE,
4386  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_49_WIDTH },
4387  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_50_CHECKER_TYPE,
4388  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_50_WIDTH },
4389  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_51_CHECKER_TYPE,
4390  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_51_WIDTH },
4391  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_52_CHECKER_TYPE,
4392  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_52_WIDTH },
4393  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_53_CHECKER_TYPE,
4394  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_53_WIDTH },
4395  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_54_CHECKER_TYPE,
4396  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_54_WIDTH },
4397  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_55_CHECKER_TYPE,
4398  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_55_WIDTH },
4399  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_56_CHECKER_TYPE,
4400  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_56_WIDTH },
4401  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_57_CHECKER_TYPE,
4402  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_57_WIDTH },
4403  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_58_CHECKER_TYPE,
4404  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_58_WIDTH },
4405  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_59_CHECKER_TYPE,
4406  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_59_WIDTH },
4407  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_60_CHECKER_TYPE,
4408  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_60_WIDTH },
4409  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_61_CHECKER_TYPE,
4410  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_61_WIDTH },
4411  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_62_CHECKER_TYPE,
4412  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_62_WIDTH },
4413  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_63_CHECKER_TYPE,
4414  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_63_WIDTH },
4415  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_64_CHECKER_TYPE,
4416  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_64_WIDTH },
4417  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_65_CHECKER_TYPE,
4418  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_65_WIDTH },
4419  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_66_CHECKER_TYPE,
4420  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_66_WIDTH },
4421  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_67_CHECKER_TYPE,
4422  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_67_WIDTH },
4423  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_68_CHECKER_TYPE,
4424  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_68_WIDTH },
4425  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_69_CHECKER_TYPE,
4426  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_69_WIDTH },
4427  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_70_CHECKER_TYPE,
4428  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_70_WIDTH },
4429  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_71_CHECKER_TYPE,
4430  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_71_WIDTH },
4431  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_72_CHECKER_TYPE,
4432  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_72_WIDTH },
4433  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_73_CHECKER_TYPE,
4434  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_73_WIDTH },
4435  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_74_CHECKER_TYPE,
4436  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_74_WIDTH },
4437  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_75_CHECKER_TYPE,
4438  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_75_WIDTH },
4439  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_76_CHECKER_TYPE,
4440  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_76_WIDTH },
4441  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_77_CHECKER_TYPE,
4442  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_77_WIDTH },
4443  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_78_CHECKER_TYPE,
4444  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_78_WIDTH },
4445  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_79_CHECKER_TYPE,
4446  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_79_WIDTH },
4447  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_80_CHECKER_TYPE,
4448  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_80_WIDTH },
4449  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_81_CHECKER_TYPE,
4450  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_81_WIDTH },
4451  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_82_CHECKER_TYPE,
4452  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_82_WIDTH },
4453  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_83_CHECKER_TYPE,
4454  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_83_WIDTH },
4455  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_84_CHECKER_TYPE,
4456  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_84_WIDTH },
4457  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_85_CHECKER_TYPE,
4458  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_85_WIDTH },
4459  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_86_CHECKER_TYPE,
4460  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_86_WIDTH },
4461  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_87_CHECKER_TYPE,
4462  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_87_WIDTH },
4463  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_88_CHECKER_TYPE,
4464  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_88_WIDTH },
4465  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_89_CHECKER_TYPE,
4466  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_89_WIDTH },
4467  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_90_CHECKER_TYPE,
4468  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_90_WIDTH },
4469  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_91_CHECKER_TYPE,
4470  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_91_WIDTH },
4471  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_92_CHECKER_TYPE,
4472  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_92_WIDTH },
4473  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_93_CHECKER_TYPE,
4474  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_93_WIDTH },
4475  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_94_CHECKER_TYPE,
4476  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_94_WIDTH },
4477  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_95_CHECKER_TYPE,
4478  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_95_WIDTH },
4479  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_96_CHECKER_TYPE,
4480  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_96_WIDTH },
4481  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_97_CHECKER_TYPE,
4482  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_97_WIDTH },
4483  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_98_CHECKER_TYPE,
4484  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_98_WIDTH },
4485  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_99_CHECKER_TYPE,
4486  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_99_WIDTH },
4487  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_100_CHECKER_TYPE,
4488  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_100_WIDTH },
4489  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_101_CHECKER_TYPE,
4490  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_101_WIDTH },
4491  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_102_CHECKER_TYPE,
4492  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_102_WIDTH },
4493  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_103_CHECKER_TYPE,
4494  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_103_WIDTH },
4495  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_104_CHECKER_TYPE,
4496  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_104_WIDTH },
4497  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_105_CHECKER_TYPE,
4498  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_105_WIDTH },
4499  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_106_CHECKER_TYPE,
4500  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_106_WIDTH },
4501  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_107_CHECKER_TYPE,
4502  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_107_WIDTH },
4503  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_108_CHECKER_TYPE,
4504  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_108_WIDTH },
4505  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_109_CHECKER_TYPE,
4506  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_109_WIDTH },
4507  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_110_CHECKER_TYPE,
4508  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_110_WIDTH },
4509  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_111_CHECKER_TYPE,
4510  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_111_WIDTH },
4511  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_112_CHECKER_TYPE,
4512  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_112_WIDTH },
4513  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_113_CHECKER_TYPE,
4514  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_113_WIDTH },
4515  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_114_CHECKER_TYPE,
4516  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_114_WIDTH },
4517  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_115_CHECKER_TYPE,
4518  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_115_WIDTH },
4519  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_116_CHECKER_TYPE,
4520  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_116_WIDTH },
4521  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_117_CHECKER_TYPE,
4522  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_117_WIDTH },
4523  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_118_CHECKER_TYPE,
4524  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_118_WIDTH },
4525  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_119_CHECKER_TYPE,
4526  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_119_WIDTH },
4527  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_120_CHECKER_TYPE,
4528  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_120_WIDTH },
4529  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_121_CHECKER_TYPE,
4530  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_121_WIDTH },
4531  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_122_CHECKER_TYPE,
4532  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_122_WIDTH },
4533  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_123_CHECKER_TYPE,
4534  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_123_WIDTH },
4535  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_124_CHECKER_TYPE,
4536  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_124_WIDTH },
4537  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_125_CHECKER_TYPE,
4538  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_125_WIDTH },
4539  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_126_CHECKER_TYPE,
4540  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_126_WIDTH },
4541  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_127_CHECKER_TYPE,
4542  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_127_WIDTH },
4543  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_128_CHECKER_TYPE,
4544  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_128_WIDTH },
4545  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_129_CHECKER_TYPE,
4546  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_129_WIDTH },
4547  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_130_CHECKER_TYPE,
4548  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_130_WIDTH },
4549  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_131_CHECKER_TYPE,
4550  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_131_WIDTH },
4551  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_132_CHECKER_TYPE,
4552  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_132_WIDTH },
4553  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_133_CHECKER_TYPE,
4554  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_133_WIDTH },
4555 };
4556 
4562 static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_groupEntries[SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_MAX_NUM_CHECKERS] =
4563 {
4564  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_0_CHECKER_TYPE,
4565  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_0_WIDTH },
4566  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_1_CHECKER_TYPE,
4567  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_1_WIDTH },
4568  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_2_CHECKER_TYPE,
4569  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_2_WIDTH },
4570  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_3_CHECKER_TYPE,
4571  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_3_WIDTH },
4572  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_4_CHECKER_TYPE,
4573  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_4_WIDTH },
4574  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_5_CHECKER_TYPE,
4575  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_5_WIDTH },
4576  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_6_CHECKER_TYPE,
4577  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_6_WIDTH },
4578  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_7_CHECKER_TYPE,
4579  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_7_WIDTH },
4580  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_8_CHECKER_TYPE,
4581  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_8_WIDTH },
4582  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_9_CHECKER_TYPE,
4583  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_9_WIDTH },
4584  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_10_CHECKER_TYPE,
4585  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_10_WIDTH },
4586  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_11_CHECKER_TYPE,
4587  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_11_WIDTH },
4588  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_12_CHECKER_TYPE,
4589  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_12_WIDTH },
4590  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_13_CHECKER_TYPE,
4591  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_13_WIDTH },
4592  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_14_CHECKER_TYPE,
4593  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_14_WIDTH },
4594  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_15_CHECKER_TYPE,
4595  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_15_WIDTH },
4596  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_16_CHECKER_TYPE,
4597  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_16_WIDTH },
4598  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_17_CHECKER_TYPE,
4599  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_17_WIDTH },
4600  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_18_CHECKER_TYPE,
4601  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_18_WIDTH },
4602  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_19_CHECKER_TYPE,
4603  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_19_WIDTH },
4604  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_20_CHECKER_TYPE,
4605  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_20_WIDTH },
4606  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_21_CHECKER_TYPE,
4607  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_21_WIDTH },
4608  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_22_CHECKER_TYPE,
4609  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_22_WIDTH },
4610  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_23_CHECKER_TYPE,
4611  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_23_WIDTH },
4612  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_24_CHECKER_TYPE,
4613  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_24_WIDTH },
4614  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_25_CHECKER_TYPE,
4615  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_25_WIDTH },
4616  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_26_CHECKER_TYPE,
4617  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_26_WIDTH },
4618  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_27_CHECKER_TYPE,
4619  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_27_WIDTH },
4620  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_28_CHECKER_TYPE,
4621  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_28_WIDTH },
4622  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_29_CHECKER_TYPE,
4623  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_29_WIDTH },
4624  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_30_CHECKER_TYPE,
4625  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_30_WIDTH },
4626  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_31_CHECKER_TYPE,
4627  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_31_WIDTH },
4628  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_32_CHECKER_TYPE,
4629  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_32_WIDTH },
4630  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_33_CHECKER_TYPE,
4631  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_33_WIDTH },
4632  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_34_CHECKER_TYPE,
4633  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_34_WIDTH },
4634  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_35_CHECKER_TYPE,
4635  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_35_WIDTH },
4636  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_36_CHECKER_TYPE,
4637  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_36_WIDTH },
4638  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_37_CHECKER_TYPE,
4639  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_37_WIDTH },
4640  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_38_CHECKER_TYPE,
4641  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_38_WIDTH },
4642  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_39_CHECKER_TYPE,
4643  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_39_WIDTH },
4644  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_40_CHECKER_TYPE,
4645  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_40_WIDTH },
4646  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_41_CHECKER_TYPE,
4647  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_41_WIDTH },
4648  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_42_CHECKER_TYPE,
4649  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_42_WIDTH },
4650  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_43_CHECKER_TYPE,
4651  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_43_WIDTH },
4652  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_44_CHECKER_TYPE,
4653  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_44_WIDTH },
4654  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_45_CHECKER_TYPE,
4655  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_45_WIDTH },
4656  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_46_CHECKER_TYPE,
4657  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_46_WIDTH },
4658  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_47_CHECKER_TYPE,
4659  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_47_WIDTH },
4660  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_48_CHECKER_TYPE,
4661  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_48_WIDTH },
4662  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_49_CHECKER_TYPE,
4663  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_49_WIDTH },
4664  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_50_CHECKER_TYPE,
4665  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_50_WIDTH },
4666  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_51_CHECKER_TYPE,
4667  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_51_WIDTH },
4668  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_52_CHECKER_TYPE,
4669  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_52_WIDTH },
4670  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_53_CHECKER_TYPE,
4671  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_53_WIDTH },
4672  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_54_CHECKER_TYPE,
4673  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_54_WIDTH },
4674  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_55_CHECKER_TYPE,
4675  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_55_WIDTH },
4676  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_56_CHECKER_TYPE,
4677  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_56_WIDTH },
4678  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_57_CHECKER_TYPE,
4679  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_57_WIDTH },
4680  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_58_CHECKER_TYPE,
4681  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_58_WIDTH },
4682  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_59_CHECKER_TYPE,
4683  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_59_WIDTH },
4684  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_60_CHECKER_TYPE,
4685  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_60_WIDTH },
4686  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_61_CHECKER_TYPE,
4687  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_61_WIDTH },
4688  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_62_CHECKER_TYPE,
4689  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_62_WIDTH },
4690  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_63_CHECKER_TYPE,
4691  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_63_WIDTH },
4692  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_64_CHECKER_TYPE,
4693  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_64_WIDTH },
4694  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_65_CHECKER_TYPE,
4695  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_65_WIDTH },
4696  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_66_CHECKER_TYPE,
4697  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_66_WIDTH },
4698  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_67_CHECKER_TYPE,
4699  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_67_WIDTH },
4700  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_68_CHECKER_TYPE,
4701  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_68_WIDTH },
4702  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_69_CHECKER_TYPE,
4703  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_69_WIDTH },
4704  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_70_CHECKER_TYPE,
4705  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_70_WIDTH },
4706  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_71_CHECKER_TYPE,
4707  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_71_WIDTH },
4708  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_72_CHECKER_TYPE,
4709  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_72_WIDTH },
4710  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_73_CHECKER_TYPE,
4711  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_73_WIDTH },
4712  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_74_CHECKER_TYPE,
4713  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_74_WIDTH },
4714  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_75_CHECKER_TYPE,
4715  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_75_WIDTH },
4716  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_76_CHECKER_TYPE,
4717  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_76_WIDTH },
4718  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_77_CHECKER_TYPE,
4719  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_77_WIDTH },
4720  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_78_CHECKER_TYPE,
4721  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_78_WIDTH },
4722  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_79_CHECKER_TYPE,
4723  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_79_WIDTH },
4724  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_80_CHECKER_TYPE,
4725  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_80_WIDTH },
4726  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_81_CHECKER_TYPE,
4727  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_81_WIDTH },
4728  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_82_CHECKER_TYPE,
4729  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_82_WIDTH },
4730  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_83_CHECKER_TYPE,
4731  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_83_WIDTH },
4732  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_84_CHECKER_TYPE,
4733  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_84_WIDTH },
4734  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_85_CHECKER_TYPE,
4735  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_85_WIDTH },
4736  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_86_CHECKER_TYPE,
4737  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_86_WIDTH },
4738  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_87_CHECKER_TYPE,
4739  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_87_WIDTH },
4740  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_88_CHECKER_TYPE,
4741  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_88_WIDTH },
4742  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_89_CHECKER_TYPE,
4743  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_89_WIDTH },
4744  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_90_CHECKER_TYPE,
4745  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_90_WIDTH },
4746  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_91_CHECKER_TYPE,
4747  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_91_WIDTH },
4748  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_92_CHECKER_TYPE,
4749  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_92_WIDTH },
4750  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_93_CHECKER_TYPE,
4751  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_93_WIDTH },
4752  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_94_CHECKER_TYPE,
4753  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_94_WIDTH },
4754  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_95_CHECKER_TYPE,
4755  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_95_WIDTH },
4756  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_96_CHECKER_TYPE,
4757  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_96_WIDTH },
4758  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_97_CHECKER_TYPE,
4759  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_97_WIDTH },
4760  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_98_CHECKER_TYPE,
4761  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_98_WIDTH },
4762  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_99_CHECKER_TYPE,
4763  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_99_WIDTH },
4764  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_100_CHECKER_TYPE,
4765  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_100_WIDTH },
4766  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_101_CHECKER_TYPE,
4767  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_101_WIDTH },
4768  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_102_CHECKER_TYPE,
4769  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_102_WIDTH },
4770  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_103_CHECKER_TYPE,
4771  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_103_WIDTH },
4772  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_104_CHECKER_TYPE,
4773  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_104_WIDTH },
4774  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_105_CHECKER_TYPE,
4775  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_105_WIDTH },
4776  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_106_CHECKER_TYPE,
4777  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_106_WIDTH },
4778  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_107_CHECKER_TYPE,
4779  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_107_WIDTH },
4780  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_108_CHECKER_TYPE,
4781  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_108_WIDTH },
4782  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_109_CHECKER_TYPE,
4783  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_109_WIDTH },
4784  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_110_CHECKER_TYPE,
4785  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_110_WIDTH },
4786  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_111_CHECKER_TYPE,
4787  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_111_WIDTH },
4788  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_112_CHECKER_TYPE,
4789  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_112_WIDTH },
4790  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_113_CHECKER_TYPE,
4791  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_113_WIDTH },
4792  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_114_CHECKER_TYPE,
4793  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_114_WIDTH },
4794  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_115_CHECKER_TYPE,
4795  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_115_WIDTH },
4796  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_116_CHECKER_TYPE,
4797  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_116_WIDTH },
4798  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_117_CHECKER_TYPE,
4799  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_117_WIDTH },
4800  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_118_CHECKER_TYPE,
4801  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_118_WIDTH },
4802  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_119_CHECKER_TYPE,
4803  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_119_WIDTH },
4804  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_120_CHECKER_TYPE,
4805  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_120_WIDTH },
4806  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_121_CHECKER_TYPE,
4807  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_121_WIDTH },
4808  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_122_CHECKER_TYPE,
4809  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_122_WIDTH },
4810  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_123_CHECKER_TYPE,
4811  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_123_WIDTH },
4812  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_124_CHECKER_TYPE,
4813  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_124_WIDTH },
4814  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_125_CHECKER_TYPE,
4815  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_125_WIDTH },
4816  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_126_CHECKER_TYPE,
4817  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_126_WIDTH },
4818  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_127_CHECKER_TYPE,
4819  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_127_WIDTH },
4820  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_128_CHECKER_TYPE,
4821  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_128_WIDTH },
4822  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_129_CHECKER_TYPE,
4823  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_129_WIDTH },
4824  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_130_CHECKER_TYPE,
4825  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_130_WIDTH },
4826  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_131_CHECKER_TYPE,
4827  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_131_WIDTH },
4828  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_132_CHECKER_TYPE,
4829  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_132_WIDTH },
4830  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_133_CHECKER_TYPE,
4831  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_133_WIDTH },
4832  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_134_CHECKER_TYPE,
4833  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_134_WIDTH },
4834  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_135_CHECKER_TYPE,
4835  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_135_WIDTH },
4836  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_136_CHECKER_TYPE,
4837  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_136_WIDTH },
4838  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_137_CHECKER_TYPE,
4839  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_137_WIDTH },
4840  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_138_CHECKER_TYPE,
4841  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_138_WIDTH },
4842  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_139_CHECKER_TYPE,
4843  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_139_WIDTH },
4844  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_140_CHECKER_TYPE,
4845  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_140_WIDTH },
4846  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_141_CHECKER_TYPE,
4847  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_141_WIDTH },
4848  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_142_CHECKER_TYPE,
4849  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_142_WIDTH },
4850  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_143_CHECKER_TYPE,
4851  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_143_WIDTH },
4852  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_144_CHECKER_TYPE,
4853  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_144_WIDTH },
4854  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_145_CHECKER_TYPE,
4855  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_145_WIDTH },
4856  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_146_CHECKER_TYPE,
4857  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_146_WIDTH },
4858  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_147_CHECKER_TYPE,
4859  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_147_WIDTH },
4860  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_148_CHECKER_TYPE,
4861  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_148_WIDTH },
4862  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_149_CHECKER_TYPE,
4863  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_149_WIDTH },
4864  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_150_CHECKER_TYPE,
4865  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_150_WIDTH },
4866  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_151_CHECKER_TYPE,
4867  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_151_WIDTH },
4868  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_152_CHECKER_TYPE,
4869  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_152_WIDTH },
4870  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_153_CHECKER_TYPE,
4871  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_153_WIDTH },
4872  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_154_CHECKER_TYPE,
4873  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_154_WIDTH },
4874  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_155_CHECKER_TYPE,
4875  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_155_WIDTH },
4876  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_156_CHECKER_TYPE,
4877  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_156_WIDTH },
4878  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_157_CHECKER_TYPE,
4879  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_157_WIDTH },
4880  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_158_CHECKER_TYPE,
4881  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_158_WIDTH },
4882  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_159_CHECKER_TYPE,
4883  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_159_WIDTH },
4884  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_160_CHECKER_TYPE,
4885  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_160_WIDTH },
4886  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_161_CHECKER_TYPE,
4887  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_161_WIDTH },
4888  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_162_CHECKER_TYPE,
4889  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_162_WIDTH },
4890  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_163_CHECKER_TYPE,
4891  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_163_WIDTH },
4892  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_164_CHECKER_TYPE,
4893  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_164_WIDTH },
4894  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_165_CHECKER_TYPE,
4895  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_165_WIDTH },
4896  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_166_CHECKER_TYPE,
4897  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_166_WIDTH },
4898  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_167_CHECKER_TYPE,
4899  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_167_WIDTH },
4900  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_168_CHECKER_TYPE,
4901  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_168_WIDTH },
4902  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_169_CHECKER_TYPE,
4903  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_169_WIDTH },
4904  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_170_CHECKER_TYPE,
4905  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_170_WIDTH },
4906  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_171_CHECKER_TYPE,
4907  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_171_WIDTH },
4908  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_172_CHECKER_TYPE,
4909  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_172_WIDTH },
4910  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_173_CHECKER_TYPE,
4911  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_173_WIDTH },
4912  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_174_CHECKER_TYPE,
4913  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_174_WIDTH },
4914  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_175_CHECKER_TYPE,
4915  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_175_WIDTH },
4916  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_176_CHECKER_TYPE,
4917  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_176_WIDTH },
4918  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_177_CHECKER_TYPE,
4919  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_177_WIDTH },
4920  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_178_CHECKER_TYPE,
4921  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_178_WIDTH },
4922  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_179_CHECKER_TYPE,
4923  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_179_WIDTH },
4924  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_180_CHECKER_TYPE,
4925  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_180_WIDTH },
4926  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_181_CHECKER_TYPE,
4927  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_181_WIDTH },
4928  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_182_CHECKER_TYPE,
4929  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_182_WIDTH },
4930  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_183_CHECKER_TYPE,
4931  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_183_WIDTH },
4932  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_184_CHECKER_TYPE,
4933  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_184_WIDTH },
4934  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_185_CHECKER_TYPE,
4935  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_185_WIDTH },
4936  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_186_CHECKER_TYPE,
4937  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_186_WIDTH },
4938  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_187_CHECKER_TYPE,
4939  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_187_WIDTH },
4940  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_188_CHECKER_TYPE,
4941  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_188_WIDTH },
4942  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_189_CHECKER_TYPE,
4943  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_189_WIDTH },
4944  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_190_CHECKER_TYPE,
4945  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_190_WIDTH },
4946  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_191_CHECKER_TYPE,
4947  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_191_WIDTH },
4948  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_192_CHECKER_TYPE,
4949  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_192_WIDTH },
4950  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_193_CHECKER_TYPE,
4951  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_193_WIDTH },
4952  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_194_CHECKER_TYPE,
4953  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_194_WIDTH },
4954  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_195_CHECKER_TYPE,
4955  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_195_WIDTH },
4956  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_196_CHECKER_TYPE,
4957  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_196_WIDTH },
4958  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_197_CHECKER_TYPE,
4959  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_197_WIDTH },
4960  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_198_CHECKER_TYPE,
4961  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_198_WIDTH },
4962  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_199_CHECKER_TYPE,
4963  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_199_WIDTH },
4964  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_200_CHECKER_TYPE,
4965  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_200_WIDTH },
4966  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_201_CHECKER_TYPE,
4967  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_201_WIDTH },
4968  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_202_CHECKER_TYPE,
4969  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_202_WIDTH },
4970  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_203_CHECKER_TYPE,
4971  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_203_WIDTH },
4972  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_204_CHECKER_TYPE,
4973  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_204_WIDTH },
4974  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_205_CHECKER_TYPE,
4975  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_205_WIDTH },
4976  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_206_CHECKER_TYPE,
4977  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_206_WIDTH },
4978  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_207_CHECKER_TYPE,
4979  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_207_WIDTH },
4980  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_208_CHECKER_TYPE,
4981  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_208_WIDTH },
4982  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_209_CHECKER_TYPE,
4983  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_209_WIDTH },
4984  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_210_CHECKER_TYPE,
4985  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_210_WIDTH },
4986  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_211_CHECKER_TYPE,
4987  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_211_WIDTH },
4988  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_212_CHECKER_TYPE,
4989  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_212_WIDTH },
4990  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_213_CHECKER_TYPE,
4991  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_213_WIDTH },
4992  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_214_CHECKER_TYPE,
4993  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_214_WIDTH },
4994  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_215_CHECKER_TYPE,
4995  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_215_WIDTH },
4996  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_216_CHECKER_TYPE,
4997  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_216_WIDTH },
4998  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_217_CHECKER_TYPE,
4999  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_217_WIDTH },
5000  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_218_CHECKER_TYPE,
5001  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_218_WIDTH },
5002  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_219_CHECKER_TYPE,
5003  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_219_WIDTH },
5004  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_220_CHECKER_TYPE,
5005  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_220_WIDTH },
5006  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_221_CHECKER_TYPE,
5007  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_221_WIDTH },
5008  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_222_CHECKER_TYPE,
5009  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_222_WIDTH },
5010  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_223_CHECKER_TYPE,
5011  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_223_WIDTH },
5012  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_224_CHECKER_TYPE,
5013  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_224_WIDTH },
5014  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_225_CHECKER_TYPE,
5015  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_225_WIDTH },
5016  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_226_CHECKER_TYPE,
5017  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_226_WIDTH },
5018  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_227_CHECKER_TYPE,
5019  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_227_WIDTH },
5020  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_228_CHECKER_TYPE,
5021  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_228_WIDTH },
5022  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_229_CHECKER_TYPE,
5023  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_229_WIDTH },
5024  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_230_CHECKER_TYPE,
5025  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_230_WIDTH },
5026  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_231_CHECKER_TYPE,
5027  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_231_WIDTH },
5028  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_232_CHECKER_TYPE,
5029  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_232_WIDTH },
5030  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_233_CHECKER_TYPE,
5031  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_233_WIDTH },
5032  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_234_CHECKER_TYPE,
5033  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_234_WIDTH },
5034  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_235_CHECKER_TYPE,
5035  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_235_WIDTH },
5036  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_236_CHECKER_TYPE,
5037  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_236_WIDTH },
5038  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_237_CHECKER_TYPE,
5039  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_237_WIDTH },
5040  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_238_CHECKER_TYPE,
5041  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_238_WIDTH },
5042  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_239_CHECKER_TYPE,
5043  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_239_WIDTH },
5044  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_240_CHECKER_TYPE,
5045  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_240_WIDTH },
5046  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_241_CHECKER_TYPE,
5047  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_241_WIDTH },
5048  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_242_CHECKER_TYPE,
5049  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_242_WIDTH },
5050  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_243_CHECKER_TYPE,
5051  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_243_WIDTH },
5052  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_244_CHECKER_TYPE,
5053  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_244_WIDTH },
5054  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_245_CHECKER_TYPE,
5055  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_245_WIDTH },
5056  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_246_CHECKER_TYPE,
5057  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_246_WIDTH },
5058  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_247_CHECKER_TYPE,
5059  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_247_WIDTH },
5060  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_248_CHECKER_TYPE,
5061  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_248_WIDTH },
5062  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_249_CHECKER_TYPE,
5063  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_249_WIDTH },
5064  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_250_CHECKER_TYPE,
5065  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_250_WIDTH },
5066  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_251_CHECKER_TYPE,
5067  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_251_WIDTH },
5068  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_252_CHECKER_TYPE,
5069  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_252_WIDTH },
5070  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_253_CHECKER_TYPE,
5071  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_253_WIDTH },
5072  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_254_CHECKER_TYPE,
5073  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_254_WIDTH },
5074  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_255_CHECKER_TYPE,
5075  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_255_WIDTH },
5076 };
5077 
5083 static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_groupEntries[SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_MAX_NUM_CHECKERS] =
5084 {
5085  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_0_CHECKER_TYPE,
5086  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_0_WIDTH },
5087  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_1_CHECKER_TYPE,
5088  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_1_WIDTH },
5089  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_2_CHECKER_TYPE,
5090  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_2_WIDTH },
5091  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_3_CHECKER_TYPE,
5092  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_3_WIDTH },
5093  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_4_CHECKER_TYPE,
5094  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_4_WIDTH },
5095  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_5_CHECKER_TYPE,
5096  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_5_WIDTH },
5097  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_6_CHECKER_TYPE,
5098  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_6_WIDTH },
5099  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_7_CHECKER_TYPE,
5100  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_7_WIDTH },
5101  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_8_CHECKER_TYPE,
5102  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_8_WIDTH },
5103  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_9_CHECKER_TYPE,
5104  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_9_WIDTH },
5105  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_10_CHECKER_TYPE,
5106  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_10_WIDTH },
5107  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_11_CHECKER_TYPE,
5108  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_11_WIDTH },
5109  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_12_CHECKER_TYPE,
5110  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_12_WIDTH },
5111  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_13_CHECKER_TYPE,
5112  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_13_WIDTH },
5113  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_14_CHECKER_TYPE,
5114  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_14_WIDTH },
5115  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_15_CHECKER_TYPE,
5116  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_15_WIDTH },
5117  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_16_CHECKER_TYPE,
5118  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_16_WIDTH },
5119  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_17_CHECKER_TYPE,
5120  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_17_WIDTH },
5121  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_18_CHECKER_TYPE,
5122  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_18_WIDTH },
5123  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_19_CHECKER_TYPE,
5124  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_19_WIDTH },
5125  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_20_CHECKER_TYPE,
5126  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_20_WIDTH },
5127  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_21_CHECKER_TYPE,
5128  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_21_WIDTH },
5129  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_22_CHECKER_TYPE,
5130  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_22_WIDTH },
5131  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_23_CHECKER_TYPE,
5132  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_23_WIDTH },
5133  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_24_CHECKER_TYPE,
5134  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_24_WIDTH },
5135  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_25_CHECKER_TYPE,
5136  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_25_WIDTH },
5137  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_26_CHECKER_TYPE,
5138  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_26_WIDTH },
5139  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_27_CHECKER_TYPE,
5140  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_27_WIDTH },
5141  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_28_CHECKER_TYPE,
5142  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_28_WIDTH },
5143  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_29_CHECKER_TYPE,
5144  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_29_WIDTH },
5145  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_30_CHECKER_TYPE,
5146  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_30_WIDTH },
5147  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_31_CHECKER_TYPE,
5148  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_31_WIDTH },
5149  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_32_CHECKER_TYPE,
5150  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_32_WIDTH },
5151  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_33_CHECKER_TYPE,
5152  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_33_WIDTH },
5153  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_34_CHECKER_TYPE,
5154  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_34_WIDTH },
5155  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_35_CHECKER_TYPE,
5156  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_35_WIDTH },
5157  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_36_CHECKER_TYPE,
5158  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_36_WIDTH },
5159  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_37_CHECKER_TYPE,
5160  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_37_WIDTH },
5161  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_38_CHECKER_TYPE,
5162  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_38_WIDTH },
5163  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_39_CHECKER_TYPE,
5164  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_39_WIDTH },
5165  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_40_CHECKER_TYPE,
5166  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_40_WIDTH },
5167  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_41_CHECKER_TYPE,
5168  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_41_WIDTH },
5169  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_42_CHECKER_TYPE,
5170  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_42_WIDTH },
5171  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_43_CHECKER_TYPE,
5172  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_43_WIDTH },
5173  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_44_CHECKER_TYPE,
5174  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_44_WIDTH },
5175  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_45_CHECKER_TYPE,
5176  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_45_WIDTH },
5177  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_46_CHECKER_TYPE,
5178  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_46_WIDTH },
5179  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_47_CHECKER_TYPE,
5180  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_47_WIDTH },
5181  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_48_CHECKER_TYPE,
5182  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_48_WIDTH },
5183  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_49_CHECKER_TYPE,
5184  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_49_WIDTH },
5185  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_50_CHECKER_TYPE,
5186  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_50_WIDTH },
5187  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_51_CHECKER_TYPE,
5188  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_51_WIDTH },
5189  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_52_CHECKER_TYPE,
5190  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_52_WIDTH },
5191  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_53_CHECKER_TYPE,
5192  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_53_WIDTH },
5193  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_54_CHECKER_TYPE,
5194  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_54_WIDTH },
5195  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_55_CHECKER_TYPE,
5196  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_55_WIDTH },
5197  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_56_CHECKER_TYPE,
5198  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_56_WIDTH },
5199  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_57_CHECKER_TYPE,
5200  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_57_WIDTH },
5201  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_58_CHECKER_TYPE,
5202  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_58_WIDTH },
5203  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_59_CHECKER_TYPE,
5204  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_59_WIDTH },
5205  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_60_CHECKER_TYPE,
5206  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_60_WIDTH },
5207  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_61_CHECKER_TYPE,
5208  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_61_WIDTH },
5209  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_62_CHECKER_TYPE,
5210  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_62_WIDTH },
5211  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_63_CHECKER_TYPE,
5212  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_63_WIDTH },
5213  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_64_CHECKER_TYPE,
5214  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_64_WIDTH },
5215  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_65_CHECKER_TYPE,
5216  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_65_WIDTH },
5217  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_66_CHECKER_TYPE,
5218  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_66_WIDTH },
5219  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_67_CHECKER_TYPE,
5220  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_67_WIDTH },
5221  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_68_CHECKER_TYPE,
5222  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_68_WIDTH },
5223  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_69_CHECKER_TYPE,
5224  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_69_WIDTH },
5225  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_70_CHECKER_TYPE,
5226  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_70_WIDTH },
5227  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_71_CHECKER_TYPE,
5228  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_71_WIDTH },
5229  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_72_CHECKER_TYPE,
5230  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_72_WIDTH },
5231  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_73_CHECKER_TYPE,
5232  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_73_WIDTH },
5233  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_74_CHECKER_TYPE,
5234  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_74_WIDTH },
5235  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_75_CHECKER_TYPE,
5236  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_75_WIDTH },
5237  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_76_CHECKER_TYPE,
5238  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_76_WIDTH },
5239  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_77_CHECKER_TYPE,
5240  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_77_WIDTH },
5241  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_78_CHECKER_TYPE,
5242  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_78_WIDTH },
5243  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_79_CHECKER_TYPE,
5244  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_79_WIDTH },
5245  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_80_CHECKER_TYPE,
5246  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_80_WIDTH },
5247  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_81_CHECKER_TYPE,
5248  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_81_WIDTH },
5249  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_82_CHECKER_TYPE,
5250  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_82_WIDTH },
5251  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_83_CHECKER_TYPE,
5252  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_83_WIDTH },
5253  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_84_CHECKER_TYPE,
5254  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_84_WIDTH },
5255  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_85_CHECKER_TYPE,
5256  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_85_WIDTH },
5257  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_86_CHECKER_TYPE,
5258  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_86_WIDTH },
5259  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_87_CHECKER_TYPE,
5260  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_87_WIDTH },
5261  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_88_CHECKER_TYPE,
5262  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_88_WIDTH },
5263  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_89_CHECKER_TYPE,
5264  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_89_WIDTH },
5265  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_90_CHECKER_TYPE,
5266  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_90_WIDTH },
5267  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_91_CHECKER_TYPE,
5268  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_91_WIDTH },
5269  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_92_CHECKER_TYPE,
5270  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_92_WIDTH },
5271  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_93_CHECKER_TYPE,
5272  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_93_WIDTH },
5273  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_94_CHECKER_TYPE,
5274  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_94_WIDTH },
5275  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_95_CHECKER_TYPE,
5276  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_95_WIDTH },
5277  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_96_CHECKER_TYPE,
5278  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_96_WIDTH },
5279  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_97_CHECKER_TYPE,
5280  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_97_WIDTH },
5281  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_98_CHECKER_TYPE,
5282  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_98_WIDTH },
5283  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_99_CHECKER_TYPE,
5284  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_99_WIDTH },
5285  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_100_CHECKER_TYPE,
5286  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_100_WIDTH },
5287  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_101_CHECKER_TYPE,
5288  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_101_WIDTH },
5289  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_102_CHECKER_TYPE,
5290  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_102_WIDTH },
5291  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_103_CHECKER_TYPE,
5292  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_103_WIDTH },
5293  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_104_CHECKER_TYPE,
5294  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_104_WIDTH },
5295  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_105_CHECKER_TYPE,
5296  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_105_WIDTH },
5297  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_106_CHECKER_TYPE,
5298  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_106_WIDTH },
5299  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_107_CHECKER_TYPE,
5300  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_107_WIDTH },
5301  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_108_CHECKER_TYPE,
5302  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_108_WIDTH },
5303  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_109_CHECKER_TYPE,
5304  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_109_WIDTH },
5305  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_110_CHECKER_TYPE,
5306  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_110_WIDTH },
5307  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_111_CHECKER_TYPE,
5308  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_111_WIDTH },
5309  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_112_CHECKER_TYPE,
5310  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_112_WIDTH },
5311  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_113_CHECKER_TYPE,
5312  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_113_WIDTH },
5313  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_114_CHECKER_TYPE,
5314  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_114_WIDTH },
5315  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_115_CHECKER_TYPE,
5316  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_115_WIDTH },
5317  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_116_CHECKER_TYPE,
5318  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_116_WIDTH },
5319  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_117_CHECKER_TYPE,
5320  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_117_WIDTH },
5321  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_118_CHECKER_TYPE,
5322  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_118_WIDTH },
5323  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_119_CHECKER_TYPE,
5324  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_119_WIDTH },
5325  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_120_CHECKER_TYPE,
5326  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_120_WIDTH },
5327  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_121_CHECKER_TYPE,
5328  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_121_WIDTH },
5329  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_122_CHECKER_TYPE,
5330  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_122_WIDTH },
5331  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_123_CHECKER_TYPE,
5332  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_123_WIDTH },
5333  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_124_CHECKER_TYPE,
5334  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_124_WIDTH },
5335  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_125_CHECKER_TYPE,
5336  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_125_WIDTH },
5337  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_126_CHECKER_TYPE,
5338  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_126_WIDTH },
5339  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_127_CHECKER_TYPE,
5340  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_127_WIDTH },
5341  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_128_CHECKER_TYPE,
5342  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_128_WIDTH },
5343  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_129_CHECKER_TYPE,
5344  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_129_WIDTH },
5345  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_130_CHECKER_TYPE,
5346  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_130_WIDTH },
5347  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_131_CHECKER_TYPE,
5348  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_131_WIDTH },
5349  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_132_CHECKER_TYPE,
5350  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_132_WIDTH },
5351  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_133_CHECKER_TYPE,
5352  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_133_WIDTH },
5353  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_134_CHECKER_TYPE,
5354  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_134_WIDTH },
5355  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_135_CHECKER_TYPE,
5356  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_135_WIDTH },
5357  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_136_CHECKER_TYPE,
5358  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_136_WIDTH },
5359  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_137_CHECKER_TYPE,
5360  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_137_WIDTH },
5361  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_138_CHECKER_TYPE,
5362  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_138_WIDTH },
5363  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_139_CHECKER_TYPE,
5364  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_139_WIDTH },
5365  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_140_CHECKER_TYPE,
5366  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_140_WIDTH },
5367  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_141_CHECKER_TYPE,
5368  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_141_WIDTH },
5369  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_142_CHECKER_TYPE,
5370  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_142_WIDTH },
5371  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_143_CHECKER_TYPE,
5372  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_143_WIDTH },
5373  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_144_CHECKER_TYPE,
5374  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_144_WIDTH },
5375  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_145_CHECKER_TYPE,
5376  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_145_WIDTH },
5377  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_146_CHECKER_TYPE,
5378  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_146_WIDTH },
5379  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_147_CHECKER_TYPE,
5380  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_147_WIDTH },
5381  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_148_CHECKER_TYPE,
5382  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_148_WIDTH },
5383  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_149_CHECKER_TYPE,
5384  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_149_WIDTH },
5385  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_150_CHECKER_TYPE,
5386  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_150_WIDTH },
5387 };
5388 
5394 static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_groupEntries[SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_MAX_NUM_CHECKERS] =
5395 {
5396  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_0_CHECKER_TYPE,
5397  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_0_WIDTH },
5398  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_1_CHECKER_TYPE,
5399  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_1_WIDTH },
5400  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_2_CHECKER_TYPE,
5401  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_2_WIDTH },
5402  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_3_CHECKER_TYPE,
5403  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_3_WIDTH },
5404  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_4_CHECKER_TYPE,
5405  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_4_WIDTH },
5406  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_5_CHECKER_TYPE,
5407  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_5_WIDTH },
5408  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_6_CHECKER_TYPE,
5409  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_6_WIDTH },
5410  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_7_CHECKER_TYPE,
5411  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_7_WIDTH },
5412  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_8_CHECKER_TYPE,
5413  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_8_WIDTH },
5414  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_9_CHECKER_TYPE,
5415  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_9_WIDTH },
5416  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_10_CHECKER_TYPE,
5417  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_10_WIDTH },
5418  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_11_CHECKER_TYPE,
5419  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_11_WIDTH },
5420  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_12_CHECKER_TYPE,
5421  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_12_WIDTH },
5422  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_13_CHECKER_TYPE,
5423  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_13_WIDTH },
5424  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_14_CHECKER_TYPE,
5425  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_14_WIDTH },
5426  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_15_CHECKER_TYPE,
5427  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_15_WIDTH },
5428  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_16_CHECKER_TYPE,
5429  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_16_WIDTH },
5430  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_17_CHECKER_TYPE,
5431  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_17_WIDTH },
5432  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_18_CHECKER_TYPE,
5433  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_18_WIDTH },
5434  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_19_CHECKER_TYPE,
5435  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_19_WIDTH },
5436  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_20_CHECKER_TYPE,
5437  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_20_WIDTH },
5438  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_21_CHECKER_TYPE,
5439  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_21_WIDTH },
5440  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_22_CHECKER_TYPE,
5441  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_22_WIDTH },
5442  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_23_CHECKER_TYPE,
5443  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_23_WIDTH },
5444  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_24_CHECKER_TYPE,
5445  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_24_WIDTH },
5446  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_25_CHECKER_TYPE,
5447  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_25_WIDTH },
5448  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_26_CHECKER_TYPE,
5449  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_26_WIDTH },
5450  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_27_CHECKER_TYPE,
5451  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_27_WIDTH },
5452  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_28_CHECKER_TYPE,
5453  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_28_WIDTH },
5454  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_29_CHECKER_TYPE,
5455  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_29_WIDTH },
5456  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_30_CHECKER_TYPE,
5457  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_30_WIDTH },
5458  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_31_CHECKER_TYPE,
5459  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_31_WIDTH },
5460  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_32_CHECKER_TYPE,
5461  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_32_WIDTH },
5462  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_33_CHECKER_TYPE,
5463  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_33_WIDTH },
5464  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_34_CHECKER_TYPE,
5465  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_34_WIDTH },
5466  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_35_CHECKER_TYPE,
5467  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_35_WIDTH },
5468  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_36_CHECKER_TYPE,
5469  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_36_WIDTH },
5470  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_37_CHECKER_TYPE,
5471  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_37_WIDTH },
5472  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_38_CHECKER_TYPE,
5473  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_38_WIDTH },
5474  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_39_CHECKER_TYPE,
5475  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_39_WIDTH },
5476  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_40_CHECKER_TYPE,
5477  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_40_WIDTH },
5478  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_41_CHECKER_TYPE,
5479  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_41_WIDTH },
5480  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_42_CHECKER_TYPE,
5481  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_42_WIDTH },
5482  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_43_CHECKER_TYPE,
5483  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_43_WIDTH },
5484  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_44_CHECKER_TYPE,
5485  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_44_WIDTH },
5486  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_45_CHECKER_TYPE,
5487  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_45_WIDTH },
5488  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_46_CHECKER_TYPE,
5489  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_46_WIDTH },
5490  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_47_CHECKER_TYPE,
5491  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_47_WIDTH },
5492  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_48_CHECKER_TYPE,
5493  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_48_WIDTH },
5494  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_49_CHECKER_TYPE,
5495  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_49_WIDTH },
5496  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_50_CHECKER_TYPE,
5497  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_50_WIDTH },
5498  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_51_CHECKER_TYPE,
5499  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_51_WIDTH },
5500  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_52_CHECKER_TYPE,
5501  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_52_WIDTH },
5502  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_53_CHECKER_TYPE,
5503  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_53_WIDTH },
5504  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_54_CHECKER_TYPE,
5505  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_54_WIDTH },
5506  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_55_CHECKER_TYPE,
5507  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_55_WIDTH },
5508  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_56_CHECKER_TYPE,
5509  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_56_WIDTH },
5510  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_57_CHECKER_TYPE,
5511  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_57_WIDTH },
5512  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_58_CHECKER_TYPE,
5513  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_58_WIDTH },
5514  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_59_CHECKER_TYPE,
5515  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_59_WIDTH },
5516  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_60_CHECKER_TYPE,
5517  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_60_WIDTH },
5518  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_61_CHECKER_TYPE,
5519  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_61_WIDTH },
5520  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_62_CHECKER_TYPE,
5521  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_62_WIDTH },
5522  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_63_CHECKER_TYPE,
5523  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_63_WIDTH },
5524  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_64_CHECKER_TYPE,
5525  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_64_WIDTH },
5526  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_65_CHECKER_TYPE,
5527  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_65_WIDTH },
5528  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_66_CHECKER_TYPE,
5529  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_66_WIDTH },
5530  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_67_CHECKER_TYPE,
5531  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_67_WIDTH },
5532  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_68_CHECKER_TYPE,
5533  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_68_WIDTH },
5534  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_69_CHECKER_TYPE,
5535  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_69_WIDTH },
5536  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_70_CHECKER_TYPE,
5537  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_70_WIDTH },
5538  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_71_CHECKER_TYPE,
5539  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_71_WIDTH },
5540  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_72_CHECKER_TYPE,
5541  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_72_WIDTH },
5542  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_73_CHECKER_TYPE,
5543  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_73_WIDTH },
5544  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_74_CHECKER_TYPE,
5545  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_74_WIDTH },
5546  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_75_CHECKER_TYPE,
5547  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_75_WIDTH },
5548  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_76_CHECKER_TYPE,
5549  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_76_WIDTH },
5550  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_77_CHECKER_TYPE,
5551  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_77_WIDTH },
5552  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_78_CHECKER_TYPE,
5553  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_78_WIDTH },
5554  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_79_CHECKER_TYPE,
5555  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_79_WIDTH },
5556  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_80_CHECKER_TYPE,
5557  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_80_WIDTH },
5558  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_81_CHECKER_TYPE,
5559  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_81_WIDTH },
5560  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_82_CHECKER_TYPE,
5561  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_82_WIDTH },
5562  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_83_CHECKER_TYPE,
5563  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_83_WIDTH },
5564  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_84_CHECKER_TYPE,
5565  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_84_WIDTH },
5566  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_85_CHECKER_TYPE,
5567  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_85_WIDTH },
5568  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_86_CHECKER_TYPE,
5569  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_86_WIDTH },
5570  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_87_CHECKER_TYPE,
5571  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_87_WIDTH },
5572  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_88_CHECKER_TYPE,
5573  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_88_WIDTH },
5574  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_89_CHECKER_TYPE,
5575  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_89_WIDTH },
5576  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_90_CHECKER_TYPE,
5577  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_90_WIDTH },
5578  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_91_CHECKER_TYPE,
5579  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_91_WIDTH },
5580  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_92_CHECKER_TYPE,
5581  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_92_WIDTH },
5582  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_93_CHECKER_TYPE,
5583  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_93_WIDTH },
5584  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_94_CHECKER_TYPE,
5585  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_94_WIDTH },
5586  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_95_CHECKER_TYPE,
5587  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_95_WIDTH },
5588  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_96_CHECKER_TYPE,
5589  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_96_WIDTH },
5590  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_97_CHECKER_TYPE,
5591  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_97_WIDTH },
5592  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_98_CHECKER_TYPE,
5593  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_98_WIDTH },
5594  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_99_CHECKER_TYPE,
5595  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_99_WIDTH },
5596  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_100_CHECKER_TYPE,
5597  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_100_WIDTH },
5598  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_101_CHECKER_TYPE,
5599  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_101_WIDTH },
5600  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_102_CHECKER_TYPE,
5601  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_102_WIDTH },
5602  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_103_CHECKER_TYPE,
5603  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_103_WIDTH },
5604  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_104_CHECKER_TYPE,
5605  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_104_WIDTH },
5606  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_105_CHECKER_TYPE,
5607  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_105_WIDTH },
5608  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_106_CHECKER_TYPE,
5609  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_106_WIDTH },
5610  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_107_CHECKER_TYPE,
5611  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_107_WIDTH },
5612  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_108_CHECKER_TYPE,
5613  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_108_WIDTH },
5614  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_109_CHECKER_TYPE,
5615  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_109_WIDTH },
5616  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_110_CHECKER_TYPE,
5617  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_110_WIDTH },
5618  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_111_CHECKER_TYPE,
5619  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_111_WIDTH },
5620  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_112_CHECKER_TYPE,
5621  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_112_WIDTH },
5622  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_113_CHECKER_TYPE,
5623  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_113_WIDTH },
5624  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_114_CHECKER_TYPE,
5625  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_114_WIDTH },
5626  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_115_CHECKER_TYPE,
5627  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_115_WIDTH },
5628  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_116_CHECKER_TYPE,
5629  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_116_WIDTH },
5630  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_117_CHECKER_TYPE,
5631  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_117_WIDTH },
5632  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_118_CHECKER_TYPE,
5633  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_118_WIDTH },
5634  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_119_CHECKER_TYPE,
5635  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_119_WIDTH },
5636  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_120_CHECKER_TYPE,
5637  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_120_WIDTH },
5638  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_121_CHECKER_TYPE,
5639  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_121_WIDTH },
5640  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_122_CHECKER_TYPE,
5641  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_122_WIDTH },
5642  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_123_CHECKER_TYPE,
5643  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_123_WIDTH },
5644  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_124_CHECKER_TYPE,
5645  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_124_WIDTH },
5646  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_125_CHECKER_TYPE,
5647  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_125_WIDTH },
5648  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_126_CHECKER_TYPE,
5649  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_126_WIDTH },
5650  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_127_CHECKER_TYPE,
5651  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_127_WIDTH },
5652  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_128_CHECKER_TYPE,
5653  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_128_WIDTH },
5654  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_129_CHECKER_TYPE,
5655  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_129_WIDTH },
5656  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_130_CHECKER_TYPE,
5657  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_130_WIDTH },
5658  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_131_CHECKER_TYPE,
5659  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_131_WIDTH },
5660  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_132_CHECKER_TYPE,
5661  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_132_WIDTH },
5662  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_133_CHECKER_TYPE,
5663  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_133_WIDTH },
5664  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_134_CHECKER_TYPE,
5665  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_134_WIDTH },
5666  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_135_CHECKER_TYPE,
5667  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_135_WIDTH },
5668  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_136_CHECKER_TYPE,
5669  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_136_WIDTH },
5670  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_137_CHECKER_TYPE,
5671  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_137_WIDTH },
5672  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_138_CHECKER_TYPE,
5673  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_138_WIDTH },
5674  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_139_CHECKER_TYPE,
5675  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_139_WIDTH },
5676  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_140_CHECKER_TYPE,
5677  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_140_WIDTH },
5678  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_141_CHECKER_TYPE,
5679  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_141_WIDTH },
5680  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_142_CHECKER_TYPE,
5681  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_142_WIDTH },
5682  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_143_CHECKER_TYPE,
5683  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_143_WIDTH },
5684  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_144_CHECKER_TYPE,
5685  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_144_WIDTH },
5686  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_145_CHECKER_TYPE,
5687  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_145_WIDTH },
5688  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_146_CHECKER_TYPE,
5689  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_146_WIDTH },
5690  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_147_CHECKER_TYPE,
5691  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_147_WIDTH },
5692  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_148_CHECKER_TYPE,
5693  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_148_WIDTH },
5694  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_149_CHECKER_TYPE,
5695  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_149_WIDTH },
5696  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_150_CHECKER_TYPE,
5697  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_150_WIDTH },
5698  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_151_CHECKER_TYPE,
5699  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_151_WIDTH },
5700  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_152_CHECKER_TYPE,
5701  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_152_WIDTH },
5702  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_153_CHECKER_TYPE,
5703  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_153_WIDTH },
5704  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_154_CHECKER_TYPE,
5705  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_154_WIDTH },
5706  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_155_CHECKER_TYPE,
5707  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_155_WIDTH },
5708  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_156_CHECKER_TYPE,
5709  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_156_WIDTH },
5710  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_157_CHECKER_TYPE,
5711  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_157_WIDTH },
5712  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_158_CHECKER_TYPE,
5713  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_158_WIDTH },
5714  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_159_CHECKER_TYPE,
5715  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_159_WIDTH },
5716  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_160_CHECKER_TYPE,
5717  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_160_WIDTH },
5718  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_161_CHECKER_TYPE,
5719  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_161_WIDTH },
5720  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_162_CHECKER_TYPE,
5721  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_162_WIDTH },
5722  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_163_CHECKER_TYPE,
5723  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_163_WIDTH },
5724  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_164_CHECKER_TYPE,
5725  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_164_WIDTH },
5726  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_165_CHECKER_TYPE,
5727  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_165_WIDTH },
5728  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_166_CHECKER_TYPE,
5729  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_166_WIDTH },
5730  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_167_CHECKER_TYPE,
5731  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_167_WIDTH },
5732  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_168_CHECKER_TYPE,
5733  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_168_WIDTH },
5734  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_169_CHECKER_TYPE,
5735  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_169_WIDTH },
5736  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_170_CHECKER_TYPE,
5737  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_170_WIDTH },
5738  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_171_CHECKER_TYPE,
5739  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_171_WIDTH },
5740  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_172_CHECKER_TYPE,
5741  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_172_WIDTH },
5742  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_173_CHECKER_TYPE,
5743  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_173_WIDTH },
5744  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_174_CHECKER_TYPE,
5745  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_174_WIDTH },
5746  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_175_CHECKER_TYPE,
5747  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_175_WIDTH },
5748  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_176_CHECKER_TYPE,
5749  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_176_WIDTH },
5750  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_177_CHECKER_TYPE,
5751  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_177_WIDTH },
5752  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_178_CHECKER_TYPE,
5753  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_178_WIDTH },
5754  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_179_CHECKER_TYPE,
5755  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_179_WIDTH },
5756  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_180_CHECKER_TYPE,
5757  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_180_WIDTH },
5758  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_181_CHECKER_TYPE,
5759  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_181_WIDTH },
5760  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_182_CHECKER_TYPE,
5761  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_182_WIDTH },
5762  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_183_CHECKER_TYPE,
5763  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_183_WIDTH },
5764  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_184_CHECKER_TYPE,
5765  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_184_WIDTH },
5766  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_185_CHECKER_TYPE,
5767  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_185_WIDTH },
5768  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_186_CHECKER_TYPE,
5769  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_186_WIDTH },
5770  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_187_CHECKER_TYPE,
5771  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_187_WIDTH },
5772  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_188_CHECKER_TYPE,
5773  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_188_WIDTH },
5774  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_189_CHECKER_TYPE,
5775  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_189_WIDTH },
5776  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_190_CHECKER_TYPE,
5777  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_190_WIDTH },
5778  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_191_CHECKER_TYPE,
5779  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_191_WIDTH },
5780  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_192_CHECKER_TYPE,
5781  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_192_WIDTH },
5782  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_193_CHECKER_TYPE,
5783  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_193_WIDTH },
5784  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_194_CHECKER_TYPE,
5785  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_194_WIDTH },
5786  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_195_CHECKER_TYPE,
5787  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_195_WIDTH },
5788  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_196_CHECKER_TYPE,
5789  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_196_WIDTH },
5790  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_197_CHECKER_TYPE,
5791  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_197_WIDTH },
5792  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_198_CHECKER_TYPE,
5793  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_198_WIDTH },
5794  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_199_CHECKER_TYPE,
5795  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_199_WIDTH },
5796  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_200_CHECKER_TYPE,
5797  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_200_WIDTH },
5798  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_201_CHECKER_TYPE,
5799  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_201_WIDTH },
5800  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_202_CHECKER_TYPE,
5801  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_202_WIDTH },
5802  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_203_CHECKER_TYPE,
5803  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_203_WIDTH },
5804  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_204_CHECKER_TYPE,
5805  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_204_WIDTH },
5806  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_205_CHECKER_TYPE,
5807  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_205_WIDTH },
5808  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_206_CHECKER_TYPE,
5809  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_206_WIDTH },
5810  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_207_CHECKER_TYPE,
5811  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_207_WIDTH },
5812  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_208_CHECKER_TYPE,
5813  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_208_WIDTH },
5814  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_209_CHECKER_TYPE,
5815  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_209_WIDTH },
5816  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_210_CHECKER_TYPE,
5817  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_210_WIDTH },
5818  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_211_CHECKER_TYPE,
5819  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_211_WIDTH },
5820  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_212_CHECKER_TYPE,
5821  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_212_WIDTH },
5822  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_213_CHECKER_TYPE,
5823  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_213_WIDTH },
5824  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_214_CHECKER_TYPE,
5825  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_214_WIDTH },
5826  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_215_CHECKER_TYPE,
5827  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_215_WIDTH },
5828  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_216_CHECKER_TYPE,
5829  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_216_WIDTH },
5830  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_217_CHECKER_TYPE,
5831  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_217_WIDTH },
5832  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_218_CHECKER_TYPE,
5833  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_218_WIDTH },
5834  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_219_CHECKER_TYPE,
5835  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_219_WIDTH },
5836  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_220_CHECKER_TYPE,
5837  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_220_WIDTH },
5838  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_221_CHECKER_TYPE,
5839  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_221_WIDTH },
5840  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_222_CHECKER_TYPE,
5841  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_222_WIDTH },
5842  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_223_CHECKER_TYPE,
5843  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_223_WIDTH },
5844  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_224_CHECKER_TYPE,
5845  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_224_WIDTH },
5846  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_225_CHECKER_TYPE,
5847  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_225_WIDTH },
5848  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_226_CHECKER_TYPE,
5849  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_226_WIDTH },
5850  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_227_CHECKER_TYPE,
5851  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_227_WIDTH },
5852  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_228_CHECKER_TYPE,
5853  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_228_WIDTH },
5854  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_229_CHECKER_TYPE,
5855  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_229_WIDTH },
5856  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_230_CHECKER_TYPE,
5857  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_230_WIDTH },
5858  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_231_CHECKER_TYPE,
5859  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_231_WIDTH },
5860  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_232_CHECKER_TYPE,
5861  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_232_WIDTH },
5862  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_233_CHECKER_TYPE,
5863  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_233_WIDTH },
5864  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_234_CHECKER_TYPE,
5865  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_234_WIDTH },
5866  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_235_CHECKER_TYPE,
5867  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_235_WIDTH },
5868  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_236_CHECKER_TYPE,
5869  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_236_WIDTH },
5870  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_237_CHECKER_TYPE,
5871  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_237_WIDTH },
5872  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_238_CHECKER_TYPE,
5873  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_238_WIDTH },
5874  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_239_CHECKER_TYPE,
5875  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_239_WIDTH },
5876  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_240_CHECKER_TYPE,
5877  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_240_WIDTH },
5878  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_241_CHECKER_TYPE,
5879  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_241_WIDTH },
5880  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_242_CHECKER_TYPE,
5881  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_242_WIDTH },
5882  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_243_CHECKER_TYPE,
5883  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_243_WIDTH },
5884  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_244_CHECKER_TYPE,
5885  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_244_WIDTH },
5886  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_245_CHECKER_TYPE,
5887  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_245_WIDTH },
5888  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_246_CHECKER_TYPE,
5889  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_246_WIDTH },
5890  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_247_CHECKER_TYPE,
5891  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_247_WIDTH },
5892  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_248_CHECKER_TYPE,
5893  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_248_WIDTH },
5894  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_249_CHECKER_TYPE,
5895  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_249_WIDTH },
5896  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_250_CHECKER_TYPE,
5897  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_250_WIDTH },
5898  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_251_CHECKER_TYPE,
5899  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_251_WIDTH },
5900  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_252_CHECKER_TYPE,
5901  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_252_WIDTH },
5902  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_253_CHECKER_TYPE,
5903  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_253_WIDTH },
5904  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_254_CHECKER_TYPE,
5905  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_254_WIDTH },
5906  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_255_CHECKER_TYPE,
5907  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_255_WIDTH },
5908 };
5909 
5915 static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_groupEntries[SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_MAX_NUM_CHECKERS] =
5916 {
5917  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_0_CHECKER_TYPE,
5918  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_0_WIDTH },
5919  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_1_CHECKER_TYPE,
5920  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_1_WIDTH },
5921  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_2_CHECKER_TYPE,
5922  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_2_WIDTH },
5923  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_3_CHECKER_TYPE,
5924  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_3_WIDTH },
5925  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_4_CHECKER_TYPE,
5926  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_4_WIDTH },
5927  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_5_CHECKER_TYPE,
5928  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_5_WIDTH },
5929  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_6_CHECKER_TYPE,
5930  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_6_WIDTH },
5931  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_7_CHECKER_TYPE,
5932  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_7_WIDTH },
5933  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_8_CHECKER_TYPE,
5934  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_8_WIDTH },
5935  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_9_CHECKER_TYPE,
5936  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_9_WIDTH },
5937  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_10_CHECKER_TYPE,
5938  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_10_WIDTH },
5939  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_11_CHECKER_TYPE,
5940  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_11_WIDTH },
5941  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_12_CHECKER_TYPE,
5942  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_12_WIDTH },
5943  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_13_CHECKER_TYPE,
5944  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_13_WIDTH },
5945  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_14_CHECKER_TYPE,
5946  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_14_WIDTH },
5947  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_15_CHECKER_TYPE,
5948  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_15_WIDTH },
5949  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_16_CHECKER_TYPE,
5950  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_16_WIDTH },
5951  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_17_CHECKER_TYPE,
5952  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_17_WIDTH },
5953  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_18_CHECKER_TYPE,
5954  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_18_WIDTH },
5955  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_19_CHECKER_TYPE,
5956  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_19_WIDTH },
5957  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_20_CHECKER_TYPE,
5958  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_20_WIDTH },
5959  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_21_CHECKER_TYPE,
5960  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_21_WIDTH },
5961  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_22_CHECKER_TYPE,
5962  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_22_WIDTH },
5963  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_23_CHECKER_TYPE,
5964  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_23_WIDTH },
5965  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_24_CHECKER_TYPE,
5966  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_24_WIDTH },
5967  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_25_CHECKER_TYPE,
5968  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_25_WIDTH },
5969  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_26_CHECKER_TYPE,
5970  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_26_WIDTH },
5971  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_27_CHECKER_TYPE,
5972  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_27_WIDTH },
5973  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_28_CHECKER_TYPE,
5974  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_28_WIDTH },
5975  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_29_CHECKER_TYPE,
5976  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_29_WIDTH },
5977  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_30_CHECKER_TYPE,
5978  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_30_WIDTH },
5979  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_31_CHECKER_TYPE,
5980  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_31_WIDTH },
5981  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_32_CHECKER_TYPE,
5982  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_32_WIDTH },
5983  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_33_CHECKER_TYPE,
5984  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_33_WIDTH },
5985  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_34_CHECKER_TYPE,
5986  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_34_WIDTH },
5987  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_35_CHECKER_TYPE,
5988  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_35_WIDTH },
5989  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_36_CHECKER_TYPE,
5990  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_36_WIDTH },
5991  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_37_CHECKER_TYPE,
5992  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_37_WIDTH },
5993  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_38_CHECKER_TYPE,
5994  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_38_WIDTH },
5995  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_39_CHECKER_TYPE,
5996  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_39_WIDTH },
5997  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_40_CHECKER_TYPE,
5998  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_40_WIDTH },
5999  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_41_CHECKER_TYPE,
6000  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_41_WIDTH },
6001  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_42_CHECKER_TYPE,
6002  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_42_WIDTH },
6003  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_43_CHECKER_TYPE,
6004  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_43_WIDTH },
6005  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_44_CHECKER_TYPE,
6006  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_44_WIDTH },
6007  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_45_CHECKER_TYPE,
6008  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_45_WIDTH },
6009  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_46_CHECKER_TYPE,
6010  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_46_WIDTH },
6011  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_47_CHECKER_TYPE,
6012  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_47_WIDTH },
6013  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_48_CHECKER_TYPE,
6014  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_48_WIDTH },
6015  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_49_CHECKER_TYPE,
6016  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_49_WIDTH },
6017  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_50_CHECKER_TYPE,
6018  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_50_WIDTH },
6019  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_51_CHECKER_TYPE,
6020  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_51_WIDTH },
6021  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_52_CHECKER_TYPE,
6022  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_52_WIDTH },
6023  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_53_CHECKER_TYPE,
6024  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_53_WIDTH },
6025  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_54_CHECKER_TYPE,
6026  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_54_WIDTH },
6027  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_55_CHECKER_TYPE,
6028  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_55_WIDTH },
6029  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_56_CHECKER_TYPE,
6030  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_56_WIDTH },
6031  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_57_CHECKER_TYPE,
6032  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_57_WIDTH },
6033  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_58_CHECKER_TYPE,
6034  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_58_WIDTH },
6035  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_59_CHECKER_TYPE,
6036  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_59_WIDTH },
6037  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_60_CHECKER_TYPE,
6038  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_60_WIDTH },
6039  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_61_CHECKER_TYPE,
6040  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_61_WIDTH },
6041  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_62_CHECKER_TYPE,
6042  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_62_WIDTH },
6043  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_63_CHECKER_TYPE,
6044  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_63_WIDTH },
6045  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_64_CHECKER_TYPE,
6046  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_64_WIDTH },
6047  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_65_CHECKER_TYPE,
6048  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_65_WIDTH },
6049  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_66_CHECKER_TYPE,
6050  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_66_WIDTH },
6051  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_67_CHECKER_TYPE,
6052  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_67_WIDTH },
6053  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_68_CHECKER_TYPE,
6054  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_68_WIDTH },
6055  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_69_CHECKER_TYPE,
6056  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_69_WIDTH },
6057  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_70_CHECKER_TYPE,
6058  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_70_WIDTH },
6059  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_71_CHECKER_TYPE,
6060  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_71_WIDTH },
6061  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_72_CHECKER_TYPE,
6062  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_72_WIDTH },
6063  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_73_CHECKER_TYPE,
6064  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_73_WIDTH },
6065  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_74_CHECKER_TYPE,
6066  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_74_WIDTH },
6067  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_75_CHECKER_TYPE,
6068  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_75_WIDTH },
6069  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_76_CHECKER_TYPE,
6070  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_76_WIDTH },
6071  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_77_CHECKER_TYPE,
6072  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_77_WIDTH },
6073  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_78_CHECKER_TYPE,
6074  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_78_WIDTH },
6075  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_79_CHECKER_TYPE,
6076  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_79_WIDTH },
6077  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_80_CHECKER_TYPE,
6078  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_80_WIDTH },
6079  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_81_CHECKER_TYPE,
6080  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_81_WIDTH },
6081  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_82_CHECKER_TYPE,
6082  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_82_WIDTH },
6083  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_83_CHECKER_TYPE,
6084  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_83_WIDTH },
6085  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_84_CHECKER_TYPE,
6086  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_84_WIDTH },
6087  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_85_CHECKER_TYPE,
6088  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_85_WIDTH },
6089  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_86_CHECKER_TYPE,
6090  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_86_WIDTH },
6091  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_87_CHECKER_TYPE,
6092  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_87_WIDTH },
6093  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_88_CHECKER_TYPE,
6094  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_88_WIDTH },
6095  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_89_CHECKER_TYPE,
6096  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_89_WIDTH },
6097  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_90_CHECKER_TYPE,
6098  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_90_WIDTH },
6099  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_91_CHECKER_TYPE,
6100  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_91_WIDTH },
6101  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_92_CHECKER_TYPE,
6102  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_92_WIDTH },
6103  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_93_CHECKER_TYPE,
6104  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_93_WIDTH },
6105  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_94_CHECKER_TYPE,
6106  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_94_WIDTH },
6107  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_95_CHECKER_TYPE,
6108  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_95_WIDTH },
6109  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_96_CHECKER_TYPE,
6110  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_96_WIDTH },
6111  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_97_CHECKER_TYPE,
6112  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_97_WIDTH },
6113  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_98_CHECKER_TYPE,
6114  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_98_WIDTH },
6115  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_99_CHECKER_TYPE,
6116  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_99_WIDTH },
6117  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_100_CHECKER_TYPE,
6118  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_100_WIDTH },
6119  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_101_CHECKER_TYPE,
6120  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_101_WIDTH },
6121  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_102_CHECKER_TYPE,
6122  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_102_WIDTH },
6123  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_103_CHECKER_TYPE,
6124  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_103_WIDTH },
6125  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_104_CHECKER_TYPE,
6126  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_104_WIDTH },
6127  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_105_CHECKER_TYPE,
6128  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_105_WIDTH },
6129  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_106_CHECKER_TYPE,
6130  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_106_WIDTH },
6131  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_107_CHECKER_TYPE,
6132  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_107_WIDTH },
6133  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_108_CHECKER_TYPE,
6134  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_108_WIDTH },
6135  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_109_CHECKER_TYPE,
6136  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_109_WIDTH },
6137  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_110_CHECKER_TYPE,
6138  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_110_WIDTH },
6139  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_111_CHECKER_TYPE,
6140  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_111_WIDTH },
6141  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_112_CHECKER_TYPE,
6142  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_112_WIDTH },
6143  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_113_CHECKER_TYPE,
6144  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_113_WIDTH },
6145  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_114_CHECKER_TYPE,
6146  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_114_WIDTH },
6147  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_115_CHECKER_TYPE,
6148  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_115_WIDTH },
6149  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_116_CHECKER_TYPE,
6150  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_116_WIDTH },
6151  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_117_CHECKER_TYPE,
6152  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_117_WIDTH },
6153  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_118_CHECKER_TYPE,
6154  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_118_WIDTH },
6155  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_119_CHECKER_TYPE,
6156  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_119_WIDTH },
6157  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_120_CHECKER_TYPE,
6158  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_120_WIDTH },
6159  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_121_CHECKER_TYPE,
6160  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_121_WIDTH },
6161  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_122_CHECKER_TYPE,
6162  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_122_WIDTH },
6163  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_123_CHECKER_TYPE,
6164  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_123_WIDTH },
6165  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_124_CHECKER_TYPE,
6166  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_124_WIDTH },
6167  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_125_CHECKER_TYPE,
6168  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_125_WIDTH },
6169  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_126_CHECKER_TYPE,
6170  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_126_WIDTH },
6171  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_127_CHECKER_TYPE,
6172  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_127_WIDTH },
6173  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_128_CHECKER_TYPE,
6174  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_128_WIDTH },
6175  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_129_CHECKER_TYPE,
6176  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_129_WIDTH },
6177  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_130_CHECKER_TYPE,
6178  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_130_WIDTH },
6179  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_131_CHECKER_TYPE,
6180  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_131_WIDTH },
6181  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_132_CHECKER_TYPE,
6182  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_132_WIDTH },
6183  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_133_CHECKER_TYPE,
6184  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_133_WIDTH },
6185  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_134_CHECKER_TYPE,
6186  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_134_WIDTH },
6187  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_135_CHECKER_TYPE,
6188  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_135_WIDTH },
6189  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_136_CHECKER_TYPE,
6190  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_136_WIDTH },
6191  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_137_CHECKER_TYPE,
6192  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_137_WIDTH },
6193  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_138_CHECKER_TYPE,
6194  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_138_WIDTH },
6195  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_139_CHECKER_TYPE,
6196  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_139_WIDTH },
6197  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_140_CHECKER_TYPE,
6198  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_140_WIDTH },
6199  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_141_CHECKER_TYPE,
6200  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_141_WIDTH },
6201  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_142_CHECKER_TYPE,
6202  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_142_WIDTH },
6203  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_143_CHECKER_TYPE,
6204  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_143_WIDTH },
6205  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_144_CHECKER_TYPE,
6206  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_144_WIDTH },
6207  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_145_CHECKER_TYPE,
6208  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_145_WIDTH },
6209  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_146_CHECKER_TYPE,
6210  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_146_WIDTH },
6211  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_147_CHECKER_TYPE,
6212  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_147_WIDTH },
6213  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_148_CHECKER_TYPE,
6214  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_148_WIDTH },
6215  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_149_CHECKER_TYPE,
6216  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_149_WIDTH },
6217  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_150_CHECKER_TYPE,
6218  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_150_WIDTH },
6219  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_151_CHECKER_TYPE,
6220  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_151_WIDTH },
6221  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_152_CHECKER_TYPE,
6222  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_152_WIDTH },
6223  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_153_CHECKER_TYPE,
6224  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_153_WIDTH },
6225  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_154_CHECKER_TYPE,
6226  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_154_WIDTH },
6227  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_155_CHECKER_TYPE,
6228  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_155_WIDTH },
6229  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_156_CHECKER_TYPE,
6230  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_156_WIDTH },
6231  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_157_CHECKER_TYPE,
6232  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_157_WIDTH },
6233  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_158_CHECKER_TYPE,
6234  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_158_WIDTH },
6235  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_159_CHECKER_TYPE,
6236  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_159_WIDTH },
6237  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_160_CHECKER_TYPE,
6238  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_160_WIDTH },
6239  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_161_CHECKER_TYPE,
6240  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_161_WIDTH },
6241  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_162_CHECKER_TYPE,
6242  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_162_WIDTH },
6243  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_163_CHECKER_TYPE,
6244  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_163_WIDTH },
6245  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_164_CHECKER_TYPE,
6246  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_164_WIDTH },
6247  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_165_CHECKER_TYPE,
6248  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_165_WIDTH },
6249  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_166_CHECKER_TYPE,
6250  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_166_WIDTH },
6251  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_167_CHECKER_TYPE,
6252  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_167_WIDTH },
6253  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_168_CHECKER_TYPE,
6254  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_168_WIDTH },
6255  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_169_CHECKER_TYPE,
6256  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_169_WIDTH },
6257  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_170_CHECKER_TYPE,
6258  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_170_WIDTH },
6259  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_171_CHECKER_TYPE,
6260  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_171_WIDTH },
6261  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_172_CHECKER_TYPE,
6262  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_172_WIDTH },
6263  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_173_CHECKER_TYPE,
6264  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_173_WIDTH },
6265  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_174_CHECKER_TYPE,
6266  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_174_WIDTH },
6267  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_175_CHECKER_TYPE,
6268  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_175_WIDTH },
6269  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_176_CHECKER_TYPE,
6270  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_176_WIDTH },
6271  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_177_CHECKER_TYPE,
6272  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_177_WIDTH },
6273  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_178_CHECKER_TYPE,
6274  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_178_WIDTH },
6275  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_179_CHECKER_TYPE,
6276  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_179_WIDTH },
6277  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_180_CHECKER_TYPE,
6278  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_180_WIDTH },
6279  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_181_CHECKER_TYPE,
6280  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_181_WIDTH },
6281  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_182_CHECKER_TYPE,
6282  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_182_WIDTH },
6283  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_183_CHECKER_TYPE,
6284  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_183_WIDTH },
6285  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_184_CHECKER_TYPE,
6286  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_184_WIDTH },
6287  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_185_CHECKER_TYPE,
6288  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_185_WIDTH },
6289  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_186_CHECKER_TYPE,
6290  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_186_WIDTH },
6291  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_187_CHECKER_TYPE,
6292  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_187_WIDTH },
6293  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_188_CHECKER_TYPE,
6294  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_188_WIDTH },
6295  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_189_CHECKER_TYPE,
6296  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_189_WIDTH },
6297  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_190_CHECKER_TYPE,
6298  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_190_WIDTH },
6299  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_191_CHECKER_TYPE,
6300  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_191_WIDTH },
6301  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_192_CHECKER_TYPE,
6302  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_192_WIDTH },
6303  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_193_CHECKER_TYPE,
6304  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_193_WIDTH },
6305  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_194_CHECKER_TYPE,
6306  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_194_WIDTH },
6307  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_195_CHECKER_TYPE,
6308  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_195_WIDTH },
6309  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_196_CHECKER_TYPE,
6310  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_196_WIDTH },
6311  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_197_CHECKER_TYPE,
6312  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_197_WIDTH },
6313  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_198_CHECKER_TYPE,
6314  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_198_WIDTH },
6315  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_199_CHECKER_TYPE,
6316  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_199_WIDTH },
6317  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_200_CHECKER_TYPE,
6318  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_200_WIDTH },
6319  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_201_CHECKER_TYPE,
6320  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_201_WIDTH },
6321  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_202_CHECKER_TYPE,
6322  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_202_WIDTH },
6323  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_203_CHECKER_TYPE,
6324  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_203_WIDTH },
6325  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_204_CHECKER_TYPE,
6326  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_204_WIDTH },
6327  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_205_CHECKER_TYPE,
6328  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_205_WIDTH },
6329  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_206_CHECKER_TYPE,
6330  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_206_WIDTH },
6331  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_207_CHECKER_TYPE,
6332  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_207_WIDTH },
6333  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_208_CHECKER_TYPE,
6334  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_208_WIDTH },
6335  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_209_CHECKER_TYPE,
6336  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_209_WIDTH },
6337  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_210_CHECKER_TYPE,
6338  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_210_WIDTH },
6339  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_211_CHECKER_TYPE,
6340  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_211_WIDTH },
6341  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_212_CHECKER_TYPE,
6342  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_212_WIDTH },
6343  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_213_CHECKER_TYPE,
6344  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_213_WIDTH },
6345  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_214_CHECKER_TYPE,
6346  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_214_WIDTH },
6347  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_215_CHECKER_TYPE,
6348  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_215_WIDTH },
6349 };
6350 
6356 static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_BRIDGE_DST_BUSECC_groupEntries[SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS] =
6357 {
6358  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_BRIDGE_DST_BUSECC_GROUP_0_CHECKER_TYPE,
6359  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_BRIDGE_DST_BUSECC_GROUP_0_WIDTH },
6360  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_BRIDGE_DST_BUSECC_GROUP_1_CHECKER_TYPE,
6361  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_BRIDGE_DST_BUSECC_GROUP_1_WIDTH },
6362  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_BRIDGE_DST_BUSECC_GROUP_2_CHECKER_TYPE,
6363  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_BRIDGE_DST_BUSECC_GROUP_2_WIDTH },
6364  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_BRIDGE_DST_BUSECC_GROUP_3_CHECKER_TYPE,
6365  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_BRIDGE_DST_BUSECC_GROUP_3_WIDTH },
6366  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_BRIDGE_DST_BUSECC_GROUP_4_CHECKER_TYPE,
6367  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_BRIDGE_DST_BUSECC_GROUP_4_WIDTH },
6368  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_BRIDGE_DST_BUSECC_GROUP_5_CHECKER_TYPE,
6369  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_BRIDGE_DST_BUSECC_GROUP_5_WIDTH },
6370  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_BRIDGE_DST_BUSECC_GROUP_6_CHECKER_TYPE,
6371  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_BRIDGE_DST_BUSECC_GROUP_6_WIDTH },
6372  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_BRIDGE_DST_BUSECC_GROUP_7_CHECKER_TYPE,
6373  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_BRIDGE_DST_BUSECC_GROUP_7_WIDTH },
6374  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_BRIDGE_DST_BUSECC_GROUP_8_CHECKER_TYPE,
6375  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_BRIDGE_DST_BUSECC_GROUP_8_WIDTH },
6376  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_BRIDGE_DST_BUSECC_GROUP_9_CHECKER_TYPE,
6377  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_BRIDGE_DST_BUSECC_GROUP_9_WIDTH },
6378  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_BRIDGE_DST_BUSECC_GROUP_10_CHECKER_TYPE,
6379  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_BRIDGE_DST_BUSECC_GROUP_10_WIDTH },
6380  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_BRIDGE_DST_BUSECC_GROUP_11_CHECKER_TYPE,
6381  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_BRIDGE_DST_BUSECC_GROUP_11_WIDTH },
6382  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_BRIDGE_DST_BUSECC_GROUP_12_CHECKER_TYPE,
6383  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_BRIDGE_DST_BUSECC_GROUP_12_WIDTH },
6384  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_BRIDGE_DST_BUSECC_GROUP_13_CHECKER_TYPE,
6385  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_BRIDGE_DST_BUSECC_GROUP_13_WIDTH },
6386 };
6387 
6393 static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_BRIDGE_SRC_BUSECC_groupEntries[SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS] =
6394 {
6395  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_BRIDGE_SRC_BUSECC_GROUP_0_CHECKER_TYPE,
6396  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_BRIDGE_SRC_BUSECC_GROUP_0_WIDTH },
6397  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_BRIDGE_SRC_BUSECC_GROUP_1_CHECKER_TYPE,
6398  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_BRIDGE_SRC_BUSECC_GROUP_1_WIDTH },
6399  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_BRIDGE_SRC_BUSECC_GROUP_2_CHECKER_TYPE,
6400  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_BRIDGE_SRC_BUSECC_GROUP_2_WIDTH },
6401  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_BRIDGE_SRC_BUSECC_GROUP_3_CHECKER_TYPE,
6402  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_BRIDGE_SRC_BUSECC_GROUP_3_WIDTH },
6403  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_BRIDGE_SRC_BUSECC_GROUP_4_CHECKER_TYPE,
6404  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_BRIDGE_SRC_BUSECC_GROUP_4_WIDTH },
6405  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_BRIDGE_SRC_BUSECC_GROUP_5_CHECKER_TYPE,
6406  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_BRIDGE_SRC_BUSECC_GROUP_5_WIDTH },
6407  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_BRIDGE_SRC_BUSECC_GROUP_6_CHECKER_TYPE,
6408  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_BRIDGE_SRC_BUSECC_GROUP_6_WIDTH },
6409  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_BRIDGE_SRC_BUSECC_GROUP_7_CHECKER_TYPE,
6410  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_BRIDGE_SRC_BUSECC_GROUP_7_WIDTH },
6411  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_BRIDGE_SRC_BUSECC_GROUP_8_CHECKER_TYPE,
6412  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_BRIDGE_SRC_BUSECC_GROUP_8_WIDTH },
6413  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_BRIDGE_SRC_BUSECC_GROUP_9_CHECKER_TYPE,
6414  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_BRIDGE_SRC_BUSECC_GROUP_9_WIDTH },
6415  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_BRIDGE_SRC_BUSECC_GROUP_10_CHECKER_TYPE,
6416  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_BRIDGE_SRC_BUSECC_GROUP_10_WIDTH },
6417  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_BRIDGE_SRC_BUSECC_GROUP_11_CHECKER_TYPE,
6418  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_BRIDGE_SRC_BUSECC_GROUP_11_WIDTH },
6419  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_BRIDGE_SRC_BUSECC_GROUP_12_CHECKER_TYPE,
6420  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_BRIDGE_SRC_BUSECC_GROUP_12_WIDTH },
6421  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_BRIDGE_SRC_BUSECC_GROUP_13_CHECKER_TYPE,
6422  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_BRIDGE_SRC_BUSECC_GROUP_13_WIDTH },
6423  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_BRIDGE_SRC_BUSECC_GROUP_14_CHECKER_TYPE,
6424  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_BRIDGE_SRC_BUSECC_GROUP_14_WIDTH },
6425  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_BRIDGE_SRC_BUSECC_GROUP_15_CHECKER_TYPE,
6426  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_BRIDGE_SRC_BUSECC_GROUP_15_WIDTH },
6427  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_BRIDGE_SRC_BUSECC_GROUP_16_CHECKER_TYPE,
6428  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_BRIDGE_SRC_BUSECC_GROUP_16_WIDTH },
6429 };
6430 
6436 static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_P2M_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_BRIDGE_DST_BUSECC_groupEntries[SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_P2M_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS] =
6437 {
6438  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_P2M_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_BRIDGE_DST_BUSECC_GROUP_0_CHECKER_TYPE,
6439  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_P2M_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_BRIDGE_DST_BUSECC_GROUP_0_WIDTH },
6440  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_P2M_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_BRIDGE_DST_BUSECC_GROUP_1_CHECKER_TYPE,
6441  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_P2M_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_BRIDGE_DST_BUSECC_GROUP_1_WIDTH },
6442  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_P2M_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_BRIDGE_DST_BUSECC_GROUP_2_CHECKER_TYPE,
6443  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_P2M_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_BRIDGE_DST_BUSECC_GROUP_2_WIDTH },
6444  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_P2M_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_BRIDGE_DST_BUSECC_GROUP_3_CHECKER_TYPE,
6445  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_P2M_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_BRIDGE_DST_BUSECC_GROUP_3_WIDTH },
6446  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_P2M_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_BRIDGE_DST_BUSECC_GROUP_4_CHECKER_TYPE,
6447  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_P2M_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_BRIDGE_DST_BUSECC_GROUP_4_WIDTH },
6448  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_P2M_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_BRIDGE_DST_BUSECC_GROUP_5_CHECKER_TYPE,
6449  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_P2M_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_BRIDGE_DST_BUSECC_GROUP_5_WIDTH },
6450  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_P2M_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_BRIDGE_DST_BUSECC_GROUP_6_CHECKER_TYPE,
6451  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_P2M_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_BRIDGE_DST_BUSECC_GROUP_6_WIDTH },
6452  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_P2M_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_BRIDGE_DST_BUSECC_GROUP_7_CHECKER_TYPE,
6453  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_P2M_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_BRIDGE_DST_BUSECC_GROUP_7_WIDTH },
6454  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_P2M_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_BRIDGE_DST_BUSECC_GROUP_8_CHECKER_TYPE,
6455  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_P2M_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_BRIDGE_DST_BUSECC_GROUP_8_WIDTH },
6456  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_P2M_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_BRIDGE_DST_BUSECC_GROUP_9_CHECKER_TYPE,
6457  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_P2M_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_BRIDGE_DST_BUSECC_GROUP_9_WIDTH },
6458  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_P2M_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_BRIDGE_DST_BUSECC_GROUP_10_CHECKER_TYPE,
6459  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_P2M_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_BRIDGE_DST_BUSECC_GROUP_10_WIDTH },
6460 };
6461 
6467 static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_P2M_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_BRIDGE_SRC_BUSECC_groupEntries[SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_P2M_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS] =
6468 {
6469  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_P2M_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_BRIDGE_SRC_BUSECC_GROUP_0_CHECKER_TYPE,
6470  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_P2M_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_BRIDGE_SRC_BUSECC_GROUP_0_WIDTH },
6471  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_P2M_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_BRIDGE_SRC_BUSECC_GROUP_1_CHECKER_TYPE,
6472  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_P2M_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_BRIDGE_SRC_BUSECC_GROUP_1_WIDTH },
6473  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_P2M_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_BRIDGE_SRC_BUSECC_GROUP_2_CHECKER_TYPE,
6474  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_P2M_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_BRIDGE_SRC_BUSECC_GROUP_2_WIDTH },
6475  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_P2M_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_BRIDGE_SRC_BUSECC_GROUP_3_CHECKER_TYPE,
6476  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_P2M_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_BRIDGE_SRC_BUSECC_GROUP_3_WIDTH },
6477  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_P2M_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_BRIDGE_SRC_BUSECC_GROUP_4_CHECKER_TYPE,
6478  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_P2M_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_BRIDGE_SRC_BUSECC_GROUP_4_WIDTH },
6479  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_P2M_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_BRIDGE_SRC_BUSECC_GROUP_5_CHECKER_TYPE,
6480  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_P2M_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_BRIDGE_SRC_BUSECC_GROUP_5_WIDTH },
6481  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_P2M_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_BRIDGE_SRC_BUSECC_GROUP_6_CHECKER_TYPE,
6482  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_P2M_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_BRIDGE_SRC_BUSECC_GROUP_6_WIDTH },
6483  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_P2M_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_BRIDGE_SRC_BUSECC_GROUP_7_CHECKER_TYPE,
6484  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_P2M_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_BRIDGE_SRC_BUSECC_GROUP_7_WIDTH },
6485  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_P2M_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_BRIDGE_SRC_BUSECC_GROUP_8_CHECKER_TYPE,
6486  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_P2M_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_BRIDGE_SRC_BUSECC_GROUP_8_WIDTH },
6487  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_P2M_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_BRIDGE_SRC_BUSECC_GROUP_9_CHECKER_TYPE,
6488  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_P2M_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_BRIDGE_SRC_BUSECC_GROUP_9_WIDTH },
6489  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_P2M_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_BRIDGE_SRC_BUSECC_GROUP_10_CHECKER_TYPE,
6490  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_P2M_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_BRIDGE_SRC_BUSECC_GROUP_10_WIDTH },
6491  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_P2M_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_BRIDGE_SRC_BUSECC_GROUP_11_CHECKER_TYPE,
6492  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_P2M_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_BRIDGE_SRC_BUSECC_GROUP_11_WIDTH },
6493  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_P2M_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_BRIDGE_SRC_BUSECC_GROUP_12_CHECKER_TYPE,
6494  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_P2M_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_BRIDGE_SRC_BUSECC_GROUP_12_WIDTH },
6495  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_P2M_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_BRIDGE_SRC_BUSECC_GROUP_13_CHECKER_TYPE,
6496  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_P2M_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_BRIDGE_SRC_BUSECC_GROUP_13_WIDTH },
6497  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_P2M_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_BRIDGE_SRC_BUSECC_GROUP_14_CHECKER_TYPE,
6498  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_P2M_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_BRIDGE_SRC_BUSECC_GROUP_14_WIDTH },
6499  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_P2M_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_BRIDGE_SRC_BUSECC_GROUP_15_CHECKER_TYPE,
6500  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_P2M_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_BRIDGE_SRC_BUSECC_GROUP_15_WIDTH },
6501  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_P2M_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_BRIDGE_SRC_BUSECC_GROUP_16_CHECKER_TYPE,
6502  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_P2M_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_BRIDGE_SRC_BUSECC_GROUP_16_WIDTH },
6503 };
6504 
6510 static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_P2P_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_BRIDGE_DST_BUSECC_groupEntries[SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_P2P_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS] =
6511 {
6512  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_P2P_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_BRIDGE_DST_BUSECC_GROUP_0_CHECKER_TYPE,
6513  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_P2P_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_BRIDGE_DST_BUSECC_GROUP_0_WIDTH },
6514  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_P2P_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_BRIDGE_DST_BUSECC_GROUP_1_CHECKER_TYPE,
6515  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_P2P_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_BRIDGE_DST_BUSECC_GROUP_1_WIDTH },
6516  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_P2P_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_BRIDGE_DST_BUSECC_GROUP_2_CHECKER_TYPE,
6517  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_P2P_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_BRIDGE_DST_BUSECC_GROUP_2_WIDTH },
6518  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_P2P_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_BRIDGE_DST_BUSECC_GROUP_3_CHECKER_TYPE,
6519  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_P2P_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_BRIDGE_DST_BUSECC_GROUP_3_WIDTH },
6520  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_P2P_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_BRIDGE_DST_BUSECC_GROUP_4_CHECKER_TYPE,
6521  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_P2P_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_BRIDGE_DST_BUSECC_GROUP_4_WIDTH },
6522 };
6523 
6529 static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_P2P_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_BRIDGE_SRC_BUSECC_groupEntries[SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_P2P_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS] =
6530 {
6531  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_P2P_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_BRIDGE_SRC_BUSECC_GROUP_0_CHECKER_TYPE,
6532  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_P2P_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_BRIDGE_SRC_BUSECC_GROUP_0_WIDTH },
6533  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_P2P_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_BRIDGE_SRC_BUSECC_GROUP_1_CHECKER_TYPE,
6534  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_P2P_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_BRIDGE_SRC_BUSECC_GROUP_1_WIDTH },
6535  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_P2P_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_BRIDGE_SRC_BUSECC_GROUP_2_CHECKER_TYPE,
6536  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_P2P_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_BRIDGE_SRC_BUSECC_GROUP_2_WIDTH },
6537  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_P2P_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_BRIDGE_SRC_BUSECC_GROUP_3_CHECKER_TYPE,
6538  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_P2P_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_BRIDGE_SRC_BUSECC_GROUP_3_WIDTH },
6539  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_P2P_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_BRIDGE_SRC_BUSECC_GROUP_4_CHECKER_TYPE,
6540  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_P2P_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_BRIDGE_SRC_BUSECC_GROUP_4_WIDTH },
6541  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_P2P_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_BRIDGE_SRC_BUSECC_GROUP_5_CHECKER_TYPE,
6542  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_P2P_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_BRIDGE_SRC_BUSECC_GROUP_5_WIDTH },
6543  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_P2P_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_BRIDGE_SRC_BUSECC_GROUP_6_CHECKER_TYPE,
6544  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_P2P_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_BRIDGE_SRC_BUSECC_GROUP_6_WIDTH },
6545  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_P2P_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_BRIDGE_SRC_BUSECC_GROUP_7_CHECKER_TYPE,
6546  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_P2P_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_BRIDGE_SRC_BUSECC_GROUP_7_WIDTH },
6547  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_P2P_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_BRIDGE_SRC_BUSECC_GROUP_8_CHECKER_TYPE,
6548  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_P2P_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_BRIDGE_SRC_BUSECC_GROUP_8_WIDTH },
6549  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_P2P_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_BRIDGE_SRC_BUSECC_GROUP_9_CHECKER_TYPE,
6550  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_P2P_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_BRIDGE_SRC_BUSECC_GROUP_9_WIDTH },
6551  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_P2P_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_BRIDGE_SRC_BUSECC_GROUP_10_CHECKER_TYPE,
6552  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_P2P_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_BRIDGE_SRC_BUSECC_GROUP_10_WIDTH },
6553  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_P2P_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_BRIDGE_SRC_BUSECC_GROUP_11_CHECKER_TYPE,
6554  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_P2P_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_BRIDGE_SRC_BUSECC_GROUP_11_WIDTH },
6555  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_P2P_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_BRIDGE_SRC_BUSECC_GROUP_12_CHECKER_TYPE,
6556  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_P2P_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_BRIDGE_SRC_BUSECC_GROUP_12_WIDTH },
6557  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_P2P_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_BRIDGE_SRC_BUSECC_GROUP_13_CHECKER_TYPE,
6558  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_P2P_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_BRIDGE_SRC_BUSECC_GROUP_13_WIDTH },
6559  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_P2P_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_BRIDGE_SRC_BUSECC_GROUP_14_CHECKER_TYPE,
6560  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_P2P_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_BRIDGE_SRC_BUSECC_GROUP_14_WIDTH },
6561  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_P2P_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_BRIDGE_SRC_BUSECC_GROUP_15_CHECKER_TYPE,
6562  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_P2P_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_BRIDGE_SRC_BUSECC_GROUP_15_WIDTH },
6563  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_P2P_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_BRIDGE_SRC_BUSECC_GROUP_16_CHECKER_TYPE,
6564  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_P2P_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_BRIDGE_SRC_BUSECC_GROUP_16_WIDTH },
6565 };
6566 
6572 static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_CBASS_DEFAULT_ERR_AM62A_MCU_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_groupEntries[SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_CBASS_DEFAULT_ERR_AM62A_MCU_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS] =
6573 {
6574  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_CBASS_DEFAULT_ERR_AM62A_MCU_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
6575  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_CBASS_DEFAULT_ERR_AM62A_MCU_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
6576  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_CBASS_DEFAULT_ERR_AM62A_MCU_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
6577  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_CBASS_DEFAULT_ERR_AM62A_MCU_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
6578  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_CBASS_DEFAULT_ERR_AM62A_MCU_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
6579  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_CBASS_DEFAULT_ERR_AM62A_MCU_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
6580  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_CBASS_DEFAULT_ERR_AM62A_MCU_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
6581  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_CBASS_DEFAULT_ERR_AM62A_MCU_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
6582  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_CBASS_DEFAULT_ERR_AM62A_MCU_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
6583  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_CBASS_DEFAULT_ERR_AM62A_MCU_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
6584 };
6585 
6591 static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_CBASS_DEFAULT_MMRS_AM62A_MCU_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_groupEntries[SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_CBASS_DEFAULT_MMRS_AM62A_MCU_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS] =
6592 {
6593  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_CBASS_DEFAULT_MMRS_AM62A_MCU_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
6594  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_CBASS_DEFAULT_MMRS_AM62A_MCU_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
6595  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_CBASS_DEFAULT_MMRS_AM62A_MCU_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
6596  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_CBASS_DEFAULT_MMRS_AM62A_MCU_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
6597  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_CBASS_DEFAULT_MMRS_AM62A_MCU_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
6598  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_CBASS_DEFAULT_MMRS_AM62A_MCU_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
6599  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_CBASS_DEFAULT_MMRS_AM62A_MCU_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
6600  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_CBASS_DEFAULT_MMRS_AM62A_MCU_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
6601  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_CBASS_DEFAULT_MMRS_AM62A_MCU_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
6602  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_CBASS_DEFAULT_MMRS_AM62A_MCU_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
6603  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_CBASS_DEFAULT_MMRS_AM62A_MCU_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_5_CHECKER_TYPE,
6604  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_CBASS_DEFAULT_MMRS_AM62A_MCU_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_5_WIDTH },
6605  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_CBASS_DEFAULT_MMRS_AM62A_MCU_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_6_CHECKER_TYPE,
6606  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_CBASS_DEFAULT_MMRS_AM62A_MCU_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_6_WIDTH },
6607  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_CBASS_DEFAULT_MMRS_AM62A_MCU_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_7_CHECKER_TYPE,
6608  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_CBASS_DEFAULT_MMRS_AM62A_MCU_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_7_WIDTH },
6609 };
6610 
6616 static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_groupEntries[SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS] =
6617 {
6618  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
6619  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
6620  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
6621  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
6622  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
6623  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
6624  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
6625  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
6626  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
6627  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
6628  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_5_CHECKER_TYPE,
6629  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_5_WIDTH },
6630  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_6_CHECKER_TYPE,
6631  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_6_WIDTH },
6632  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_7_CHECKER_TYPE,
6633  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_7_WIDTH },
6634  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_8_CHECKER_TYPE,
6635  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_8_WIDTH },
6636  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_9_CHECKER_TYPE,
6637  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_9_WIDTH },
6638  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_10_CHECKER_TYPE,
6639  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_10_WIDTH },
6640  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_11_CHECKER_TYPE,
6641  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_11_WIDTH },
6642  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_12_CHECKER_TYPE,
6643  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_12_WIDTH },
6644  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_13_CHECKER_TYPE,
6645  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_13_WIDTH },
6646  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_14_CHECKER_TYPE,
6647  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_14_WIDTH },
6648  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_15_CHECKER_TYPE,
6649  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_15_WIDTH },
6650  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_16_CHECKER_TYPE,
6651  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_16_WIDTH },
6652  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_17_CHECKER_TYPE,
6653  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_17_WIDTH },
6654  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_18_CHECKER_TYPE,
6655  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_18_WIDTH },
6656  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_19_CHECKER_TYPE,
6657  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_19_WIDTH },
6658  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_20_CHECKER_TYPE,
6659  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_20_WIDTH },
6660  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_21_CHECKER_TYPE,
6661  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_21_WIDTH },
6662  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_22_CHECKER_TYPE,
6663  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_22_WIDTH },
6664  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_23_CHECKER_TYPE,
6665  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_23_WIDTH },
6666  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_24_CHECKER_TYPE,
6667  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_24_WIDTH },
6668  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_25_CHECKER_TYPE,
6669  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_25_WIDTH },
6670  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_26_CHECKER_TYPE,
6671  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_26_WIDTH },
6672  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_27_CHECKER_TYPE,
6673  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_27_WIDTH },
6674  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_28_CHECKER_TYPE,
6675  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_28_WIDTH },
6676  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_29_CHECKER_TYPE,
6677  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_29_WIDTH },
6678  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_30_CHECKER_TYPE,
6679  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_30_WIDTH },
6680  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_31_CHECKER_TYPE,
6681  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_31_WIDTH },
6682  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_32_CHECKER_TYPE,
6683  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_32_WIDTH },
6684  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_33_CHECKER_TYPE,
6685  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_33_WIDTH },
6686  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_34_CHECKER_TYPE,
6687  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_34_WIDTH },
6688  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_35_CHECKER_TYPE,
6689  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_35_WIDTH },
6690  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_36_CHECKER_TYPE,
6691  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_36_WIDTH },
6692  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_37_CHECKER_TYPE,
6693  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_37_WIDTH },
6694  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_38_CHECKER_TYPE,
6695  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_38_WIDTH },
6696  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_39_CHECKER_TYPE,
6697  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_39_WIDTH },
6698  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_40_CHECKER_TYPE,
6699  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_40_WIDTH },
6700  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_41_CHECKER_TYPE,
6701  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_41_WIDTH },
6702 };
6703 
6709 static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_groupEntries[SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_MAX_NUM_CHECKERS] =
6710 {
6711  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_0_CHECKER_TYPE,
6712  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_0_WIDTH },
6713  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_1_CHECKER_TYPE,
6714  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_1_WIDTH },
6715  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_2_CHECKER_TYPE,
6716  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_2_WIDTH },
6717  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_3_CHECKER_TYPE,
6718  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_3_WIDTH },
6719  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_4_CHECKER_TYPE,
6720  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_4_WIDTH },
6721  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_5_CHECKER_TYPE,
6722  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_5_WIDTH },
6723  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_6_CHECKER_TYPE,
6724  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_6_WIDTH },
6725  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_7_CHECKER_TYPE,
6726  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_7_WIDTH },
6727  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_8_CHECKER_TYPE,
6728  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_8_WIDTH },
6729  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_9_CHECKER_TYPE,
6730  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_9_WIDTH },
6731  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_10_CHECKER_TYPE,
6732  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_10_WIDTH },
6733  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_11_CHECKER_TYPE,
6734  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_11_WIDTH },
6735  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_12_CHECKER_TYPE,
6736  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_12_WIDTH },
6737  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_13_CHECKER_TYPE,
6738  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_13_WIDTH },
6739  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_14_CHECKER_TYPE,
6740  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_14_WIDTH },
6741  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_15_CHECKER_TYPE,
6742  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_15_WIDTH },
6743  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_16_CHECKER_TYPE,
6744  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_16_WIDTH },
6745  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_17_CHECKER_TYPE,
6746  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_17_WIDTH },
6747  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_18_CHECKER_TYPE,
6748  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_18_WIDTH },
6749 };
6750 
6756 static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ERR_SCR_AM62A_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_groupEntries[SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ERR_SCR_AM62A_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS] =
6757 {
6758  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ERR_SCR_AM62A_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
6759  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ERR_SCR_AM62A_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
6760  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ERR_SCR_AM62A_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
6761  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ERR_SCR_AM62A_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
6762  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ERR_SCR_AM62A_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
6763  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ERR_SCR_AM62A_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
6764  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ERR_SCR_AM62A_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
6765  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ERR_SCR_AM62A_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
6766  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ERR_SCR_AM62A_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
6767  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ERR_SCR_AM62A_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
6768  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ERR_SCR_AM62A_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_5_CHECKER_TYPE,
6769  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ERR_SCR_AM62A_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_5_WIDTH },
6770  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ERR_SCR_AM62A_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_6_CHECKER_TYPE,
6771  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ERR_SCR_AM62A_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_6_WIDTH },
6772  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ERR_SCR_AM62A_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_7_CHECKER_TYPE,
6773  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ERR_SCR_AM62A_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_7_WIDTH },
6774  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ERR_SCR_AM62A_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_8_CHECKER_TYPE,
6775  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ERR_SCR_AM62A_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_8_WIDTH },
6776  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ERR_SCR_AM62A_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_9_CHECKER_TYPE,
6777  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ERR_SCR_AM62A_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_9_WIDTH },
6778  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ERR_SCR_AM62A_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_10_CHECKER_TYPE,
6779  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ERR_SCR_AM62A_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_10_WIDTH },
6780  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ERR_SCR_AM62A_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_11_CHECKER_TYPE,
6781  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ERR_SCR_AM62A_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_11_WIDTH },
6782  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ERR_SCR_AM62A_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_12_CHECKER_TYPE,
6783  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ERR_SCR_AM62A_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_12_WIDTH },
6784  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ERR_SCR_AM62A_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_13_CHECKER_TYPE,
6785  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ERR_SCR_AM62A_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_13_WIDTH },
6786  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ERR_SCR_AM62A_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_14_CHECKER_TYPE,
6787  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ERR_SCR_AM62A_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_14_WIDTH },
6788  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ERR_SCR_AM62A_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_15_CHECKER_TYPE,
6789  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ERR_SCR_AM62A_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_15_WIDTH },
6790  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ERR_SCR_AM62A_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_16_CHECKER_TYPE,
6791  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ERR_SCR_AM62A_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_16_WIDTH },
6792  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ERR_SCR_AM62A_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_17_CHECKER_TYPE,
6793  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ERR_SCR_AM62A_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_17_WIDTH },
6794  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ERR_SCR_AM62A_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_18_CHECKER_TYPE,
6795  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ERR_SCR_AM62A_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_18_WIDTH },
6796  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ERR_SCR_AM62A_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_19_CHECKER_TYPE,
6797  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ERR_SCR_AM62A_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_19_WIDTH },
6798  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ERR_SCR_AM62A_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_20_CHECKER_TYPE,
6799  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ERR_SCR_AM62A_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_20_WIDTH },
6800  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ERR_SCR_AM62A_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_21_CHECKER_TYPE,
6801  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ERR_SCR_AM62A_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_21_WIDTH },
6802  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ERR_SCR_AM62A_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_22_CHECKER_TYPE,
6803  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ERR_SCR_AM62A_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_22_WIDTH },
6804  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ERR_SCR_AM62A_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_23_CHECKER_TYPE,
6805  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ERR_SCR_AM62A_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_23_WIDTH },
6806  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ERR_SCR_AM62A_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_24_CHECKER_TYPE,
6807  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ERR_SCR_AM62A_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_24_WIDTH },
6808  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ERR_SCR_AM62A_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_25_CHECKER_TYPE,
6809  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ERR_SCR_AM62A_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_25_WIDTH },
6810  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ERR_SCR_AM62A_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_26_CHECKER_TYPE,
6811  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ERR_SCR_AM62A_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_26_WIDTH },
6812  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ERR_SCR_AM62A_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_27_CHECKER_TYPE,
6813  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ERR_SCR_AM62A_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_27_WIDTH },
6814  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ERR_SCR_AM62A_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_28_CHECKER_TYPE,
6815  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ERR_SCR_AM62A_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_28_WIDTH },
6816  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ERR_SCR_AM62A_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_29_CHECKER_TYPE,
6817  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ERR_SCR_AM62A_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_29_WIDTH },
6818  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ERR_SCR_AM62A_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_30_CHECKER_TYPE,
6819  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ERR_SCR_AM62A_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_30_WIDTH },
6820  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ERR_SCR_AM62A_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_31_CHECKER_TYPE,
6821  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ERR_SCR_AM62A_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_31_WIDTH },
6822  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ERR_SCR_AM62A_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_32_CHECKER_TYPE,
6823  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ERR_SCR_AM62A_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_32_WIDTH },
6824  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ERR_SCR_AM62A_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_33_CHECKER_TYPE,
6825  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ERR_SCR_AM62A_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_33_WIDTH },
6826  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ERR_SCR_AM62A_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_34_CHECKER_TYPE,
6827  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ERR_SCR_AM62A_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_34_WIDTH },
6828  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ERR_SCR_AM62A_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_35_CHECKER_TYPE,
6829  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ERR_SCR_AM62A_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_35_WIDTH },
6830  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ERR_SCR_AM62A_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_36_CHECKER_TYPE,
6831  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ERR_SCR_AM62A_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_36_WIDTH },
6832  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ERR_SCR_AM62A_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_37_CHECKER_TYPE,
6833  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ERR_SCR_AM62A_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_37_WIDTH },
6834  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ERR_SCR_AM62A_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_38_CHECKER_TYPE,
6835  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ERR_SCR_AM62A_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_38_WIDTH },
6836  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ERR_SCR_AM62A_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_39_CHECKER_TYPE,
6837  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ERR_SCR_AM62A_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_39_WIDTH },
6838  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ERR_SCR_AM62A_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_40_CHECKER_TYPE,
6839  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ERR_SCR_AM62A_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_40_WIDTH },
6840  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ERR_SCR_AM62A_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_41_CHECKER_TYPE,
6841  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ERR_SCR_AM62A_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_41_WIDTH },
6842 };
6843 
6849 static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_groupEntries[SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_MAX_NUM_CHECKERS] =
6850 {
6851  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_0_CHECKER_TYPE,
6852  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_0_WIDTH },
6853  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_1_CHECKER_TYPE,
6854  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_1_WIDTH },
6855  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_2_CHECKER_TYPE,
6856  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_2_WIDTH },
6857  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_3_CHECKER_TYPE,
6858  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_3_WIDTH },
6859  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_4_CHECKER_TYPE,
6860  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_4_WIDTH },
6861  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_5_CHECKER_TYPE,
6862  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_5_WIDTH },
6863  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_6_CHECKER_TYPE,
6864  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_6_WIDTH },
6865  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_7_CHECKER_TYPE,
6866  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_7_WIDTH },
6867  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_8_CHECKER_TYPE,
6868  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_8_WIDTH },
6869  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_9_CHECKER_TYPE,
6870  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_9_WIDTH },
6871  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_10_CHECKER_TYPE,
6872  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_10_WIDTH },
6873  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_11_CHECKER_TYPE,
6874  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_11_WIDTH },
6875  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_12_CHECKER_TYPE,
6876  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_12_WIDTH },
6877  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_13_CHECKER_TYPE,
6878  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_13_WIDTH },
6879  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_14_CHECKER_TYPE,
6880  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_14_WIDTH },
6881  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_15_CHECKER_TYPE,
6882  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_15_WIDTH },
6883  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_16_CHECKER_TYPE,
6884  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_16_WIDTH },
6885  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_17_CHECKER_TYPE,
6886  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_17_WIDTH },
6887  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_18_CHECKER_TYPE,
6888  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_18_WIDTH },
6889 };
6890 
6896 static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_DST_BUSECC_groupEntries[SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS] =
6897 {
6898  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_DST_BUSECC_GROUP_0_CHECKER_TYPE,
6899  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_DST_BUSECC_GROUP_0_WIDTH },
6900  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_DST_BUSECC_GROUP_1_CHECKER_TYPE,
6901  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_DST_BUSECC_GROUP_1_WIDTH },
6902  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_DST_BUSECC_GROUP_2_CHECKER_TYPE,
6903  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_DST_BUSECC_GROUP_2_WIDTH },
6904  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_DST_BUSECC_GROUP_3_CHECKER_TYPE,
6905  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_DST_BUSECC_GROUP_3_WIDTH },
6906  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_DST_BUSECC_GROUP_4_CHECKER_TYPE,
6907  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_DST_BUSECC_GROUP_4_WIDTH },
6908  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_DST_BUSECC_GROUP_5_CHECKER_TYPE,
6909  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_DST_BUSECC_GROUP_5_WIDTH },
6910  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_DST_BUSECC_GROUP_6_CHECKER_TYPE,
6911  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_DST_BUSECC_GROUP_6_WIDTH },
6912  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_DST_BUSECC_GROUP_7_CHECKER_TYPE,
6913  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_DST_BUSECC_GROUP_7_WIDTH },
6914  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_DST_BUSECC_GROUP_8_CHECKER_TYPE,
6915  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_DST_BUSECC_GROUP_8_WIDTH },
6916  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_DST_BUSECC_GROUP_9_CHECKER_TYPE,
6917  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_DST_BUSECC_GROUP_9_WIDTH },
6918  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_DST_BUSECC_GROUP_10_CHECKER_TYPE,
6919  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_DST_BUSECC_GROUP_10_WIDTH },
6920  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_DST_BUSECC_GROUP_11_CHECKER_TYPE,
6921  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_DST_BUSECC_GROUP_11_WIDTH },
6922  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_DST_BUSECC_GROUP_12_CHECKER_TYPE,
6923  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_DST_BUSECC_GROUP_12_WIDTH },
6924  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_DST_BUSECC_GROUP_13_CHECKER_TYPE,
6925  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_DST_BUSECC_GROUP_13_WIDTH },
6926 };
6927 
6933 static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_SRC_BUSECC_groupEntries[SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS] =
6934 {
6935  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_SRC_BUSECC_GROUP_0_CHECKER_TYPE,
6936  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_SRC_BUSECC_GROUP_0_WIDTH },
6937  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_SRC_BUSECC_GROUP_1_CHECKER_TYPE,
6938  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_SRC_BUSECC_GROUP_1_WIDTH },
6939  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_SRC_BUSECC_GROUP_2_CHECKER_TYPE,
6940  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_SRC_BUSECC_GROUP_2_WIDTH },
6941  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_SRC_BUSECC_GROUP_3_CHECKER_TYPE,
6942  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_SRC_BUSECC_GROUP_3_WIDTH },
6943  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_SRC_BUSECC_GROUP_4_CHECKER_TYPE,
6944  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_SRC_BUSECC_GROUP_4_WIDTH },
6945  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_SRC_BUSECC_GROUP_5_CHECKER_TYPE,
6946  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_SRC_BUSECC_GROUP_5_WIDTH },
6947  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_SRC_BUSECC_GROUP_6_CHECKER_TYPE,
6948  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_SRC_BUSECC_GROUP_6_WIDTH },
6949  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_SRC_BUSECC_GROUP_7_CHECKER_TYPE,
6950  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_SRC_BUSECC_GROUP_7_WIDTH },
6951  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_SRC_BUSECC_GROUP_8_CHECKER_TYPE,
6952  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_SRC_BUSECC_GROUP_8_WIDTH },
6953  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_SRC_BUSECC_GROUP_9_CHECKER_TYPE,
6954  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_SRC_BUSECC_GROUP_9_WIDTH },
6955  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_SRC_BUSECC_GROUP_10_CHECKER_TYPE,
6956  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_SRC_BUSECC_GROUP_10_WIDTH },
6957  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_SRC_BUSECC_GROUP_11_CHECKER_TYPE,
6958  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_SRC_BUSECC_GROUP_11_WIDTH },
6959  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_SRC_BUSECC_GROUP_12_CHECKER_TYPE,
6960  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_SRC_BUSECC_GROUP_12_WIDTH },
6961  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_SRC_BUSECC_GROUP_13_CHECKER_TYPE,
6962  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_SRC_BUSECC_GROUP_13_WIDTH },
6963  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_SRC_BUSECC_GROUP_14_CHECKER_TYPE,
6964  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_SRC_BUSECC_GROUP_14_WIDTH },
6965  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_SRC_BUSECC_GROUP_15_CHECKER_TYPE,
6966  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_SRC_BUSECC_GROUP_15_WIDTH },
6967  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_SRC_BUSECC_GROUP_16_CHECKER_TYPE,
6968  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_SRC_BUSECC_GROUP_16_WIDTH },
6969 };
6970 
6976 static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_SAM62A_MCU_MCU_ECC_AGGR_EDC_CTRL_groupEntries[SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_SAM62A_MCU_MCU_ECC_AGGR_EDC_CTRL_MAX_NUM_CHECKERS] =
6977 {
6978  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_SAM62A_MCU_MCU_ECC_AGGR_EDC_CTRL_GROUP_0_CHECKER_TYPE,
6979  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_SAM62A_MCU_MCU_ECC_AGGR_EDC_CTRL_GROUP_0_WIDTH },
6980  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_SAM62A_MCU_MCU_ECC_AGGR_EDC_CTRL_GROUP_1_CHECKER_TYPE,
6981  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_SAM62A_MCU_MCU_ECC_AGGR_EDC_CTRL_GROUP_1_WIDTH },
6982  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_SAM62A_MCU_MCU_ECC_AGGR_EDC_CTRL_GROUP_2_CHECKER_TYPE,
6983  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_SAM62A_MCU_MCU_ECC_AGGR_EDC_CTRL_GROUP_2_WIDTH },
6984  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_SAM62A_MCU_MCU_ECC_AGGR_EDC_CTRL_GROUP_3_CHECKER_TYPE,
6985  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_SAM62A_MCU_MCU_ECC_AGGR_EDC_CTRL_GROUP_3_WIDTH },
6986  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_SAM62A_MCU_MCU_ECC_AGGR_EDC_CTRL_GROUP_4_CHECKER_TYPE,
6987  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_SAM62A_MCU_MCU_ECC_AGGR_EDC_CTRL_GROUP_4_WIDTH },
6988  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_SAM62A_MCU_MCU_ECC_AGGR_EDC_CTRL_GROUP_5_CHECKER_TYPE,
6989  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_SAM62A_MCU_MCU_ECC_AGGR_EDC_CTRL_GROUP_5_WIDTH },
6990 };
6991 
6996 static const SDL_MemConfig_t SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_MemEntries[SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_RAM_IDS_TOTAL_ENTRIES] =
6997 {
6998  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_CFG_CONFIG_RAM_ID, 0u,
6999  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_CFG_CONFIG_RAM_SIZE, 14u,
7000  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_CFG_CONFIG_ROW_WIDTH, ((bool)false) },
7001  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_CFG_STATE_RAM_ID, 0u,
7002  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_CFG_STATE_RAM_SIZE, 32u,
7003  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_CFG_STATE_ROW_WIDTH, ((bool)false) },
7004  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_TPCFIFO_F0_RAM_ID, 0u,
7005  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_TPCFIFO_F0_RAM_SIZE, 18u,
7006  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_TPCFIFO_F0_ROW_WIDTH, ((bool)false) },
7007  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_TPCFIFO_F1_RAM_ID, 0u,
7008  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_TPCFIFO_F1_RAM_SIZE, 18u,
7009  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_TPCFIFO_F1_ROW_WIDTH, ((bool)false) },
7010  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_RPCFIFO_F0_RAM_ID, 0u,
7011  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_RPCFIFO_F0_RAM_SIZE, 16u,
7012  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_RPCFIFO_F0_ROW_WIDTH, ((bool)false) },
7013  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_RPCFIFO_F1_RAM_ID, 0u,
7014  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_RPCFIFO_F1_RAM_SIZE, 16u,
7015  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_RPCFIFO_F1_ROW_WIDTH, ((bool)false) },
7016  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_RPCFIFO_WC_RAM_ID, 0u,
7017  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_RPCFIFO_WC_RAM_SIZE, 4u,
7018  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_RPCFIFO_WC_ROW_WIDTH, ((bool)false) },
7019  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_STATS_STST0_RAM_ID, 0u,
7020  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_STATS_STST0_RAM_SIZE, 12u,
7021  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_STATS_STST0_ROW_WIDTH, ((bool)false) },
7022  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_STATS_STSR0_RAM_ID, 0u,
7023  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_STATS_STSR0_RAM_SIZE, 16u,
7024  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_STATS_STSR0_ROW_WIDTH, ((bool)false) },
7025  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_RINGOCC_CNTR_RAM_ID, 0u,
7026  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_RINGOCC_CNTR_RAM_SIZE, 4u,
7027  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_RINGOCC_CNTR_ROW_WIDTH, ((bool)false) },
7028  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_STATREG_SR_SPRAM_8X128_SWW_SR_RAM_ID, 0u,
7029  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_STATREG_SR_SPRAM_8X128_SWW_SR_RAM_SIZE, 16u,
7030  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_STATREG_SR_SPRAM_8X128_SWW_SR_ROW_WIDTH, ((bool)false) },
7031  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_COMMON_IM_TPRAM_158X34_SWW_SR_RAM_ID, 0u,
7032  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_COMMON_IM_TPRAM_158X34_SWW_SR_RAM_SIZE, 5u,
7033  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_COMMON_IM_TPRAM_158X34_SWW_SR_ROW_WIDTH, ((bool)false) },
7034  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_STRAM_RAM_ID, 0u,
7035  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_STRAM_RAM_SIZE, 27u,
7036  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_STRAM_ROW_WIDTH, ((bool)false) },
7037  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_BUF_STRAM_RAM_ID, 0u,
7038  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_BUF_STRAM_RAM_SIZE, 12u,
7039  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_BUF_STRAM_ROW_WIDTH, ((bool)false) },
7040  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_BUF_BUFRAM_RAM_ID, 0u,
7041  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_BUF_BUFRAM_RAM_SIZE, 8u,
7042  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_BUF_BUFRAM_ROW_WIDTH, ((bool)false) },
7043  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_ECC0_RAM_ID, 0u,
7044  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_ECC0_RAM_SIZE, 8u,
7045  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_ECC0_ROW_WIDTH, ((bool)false) },
7046 };
7047 
7053 static const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_ECCAGGR_EDC_CTRL_groupEntries[SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_ECCAGGR_EDC_CTRL_MAX_NUM_CHECKERS] =
7054 {
7055  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_ECCAGGR_EDC_CTRL_GROUP_0_CHECKER_TYPE,
7056  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_ECCAGGR_EDC_CTRL_GROUP_0_WIDTH },
7057  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_ECCAGGR_EDC_CTRL_GROUP_1_CHECKER_TYPE,
7058  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_ECCAGGR_EDC_CTRL_GROUP_1_WIDTH },
7059  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_ECCAGGR_EDC_CTRL_GROUP_2_CHECKER_TYPE,
7060  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_ECCAGGR_EDC_CTRL_GROUP_2_WIDTH },
7061  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_ECCAGGR_EDC_CTRL_GROUP_3_CHECKER_TYPE,
7062  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_ECCAGGR_EDC_CTRL_GROUP_3_WIDTH },
7063  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_ECCAGGR_EDC_CTRL_GROUP_4_CHECKER_TYPE,
7064  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_ECCAGGR_EDC_CTRL_GROUP_4_WIDTH },
7065  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_ECCAGGR_EDC_CTRL_GROUP_5_CHECKER_TYPE,
7066  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_ECCAGGR_EDC_CTRL_GROUP_5_WIDTH },
7067 };
7068 
7074 static const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_groupEntries[SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_MAX_NUM_CHECKERS] =
7075 {
7076  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
7077  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_0_WIDTH },
7078  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
7079  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_1_WIDTH },
7080  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
7081  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_2_WIDTH },
7082  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
7083  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_3_WIDTH },
7084  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
7085  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_4_WIDTH },
7086  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
7087  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_5_WIDTH },
7088  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
7089  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_6_WIDTH },
7090  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
7091  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_7_WIDTH },
7092  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
7093  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_8_WIDTH },
7094  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
7095  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_9_WIDTH },
7096  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
7097  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_10_WIDTH },
7098  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
7099  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_11_WIDTH },
7100  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
7101  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_12_WIDTH },
7102  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
7103  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_13_WIDTH },
7104  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
7105  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_14_WIDTH },
7106  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
7107  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_15_WIDTH },
7108  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
7109  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_16_WIDTH },
7110  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
7111  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_17_WIDTH },
7112  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
7113  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_18_WIDTH },
7114  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
7115  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_19_WIDTH },
7116  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
7117  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_20_WIDTH },
7118  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
7119  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_21_WIDTH },
7120  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
7121  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_22_WIDTH },
7122  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
7123  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_23_WIDTH },
7124  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
7125  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_24_WIDTH },
7126  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
7127  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_25_WIDTH },
7128  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
7129  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_26_WIDTH },
7130  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
7131  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_27_WIDTH },
7132  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
7133  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_28_WIDTH },
7134  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
7135  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_29_WIDTH },
7136  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
7137  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_30_WIDTH },
7138  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
7139  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_31_WIDTH },
7140  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
7141  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_32_WIDTH },
7142  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_33_CHECKER_TYPE,
7143  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_33_WIDTH },
7144  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_34_CHECKER_TYPE,
7145  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_34_WIDTH },
7146  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_35_CHECKER_TYPE,
7147  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_35_WIDTH },
7148  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_36_CHECKER_TYPE,
7149  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_36_WIDTH },
7150  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_37_CHECKER_TYPE,
7151  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_37_WIDTH },
7152  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_38_CHECKER_TYPE,
7153  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_38_WIDTH },
7154  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_39_CHECKER_TYPE,
7155  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_39_WIDTH },
7156  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_40_CHECKER_TYPE,
7157  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_40_WIDTH },
7158  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_41_CHECKER_TYPE,
7159  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_41_WIDTH },
7160  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_42_CHECKER_TYPE,
7161  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_42_WIDTH },
7162  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_43_CHECKER_TYPE,
7163  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_43_WIDTH },
7164  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_44_CHECKER_TYPE,
7165  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_44_WIDTH },
7166  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_45_CHECKER_TYPE,
7167  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_45_WIDTH },
7168  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_46_CHECKER_TYPE,
7169  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_46_WIDTH },
7170  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_47_CHECKER_TYPE,
7171  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_47_WIDTH },
7172  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_48_CHECKER_TYPE,
7173  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_48_WIDTH },
7174  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_49_CHECKER_TYPE,
7175  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_49_WIDTH },
7176  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_50_CHECKER_TYPE,
7177  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_50_WIDTH },
7178  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_51_CHECKER_TYPE,
7179  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_51_WIDTH },
7180  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_52_CHECKER_TYPE,
7181  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_52_WIDTH },
7182  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_53_CHECKER_TYPE,
7183  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_53_WIDTH },
7184  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_54_CHECKER_TYPE,
7185  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_54_WIDTH },
7186  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_55_CHECKER_TYPE,
7187  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_55_WIDTH },
7188  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_56_CHECKER_TYPE,
7189  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_56_WIDTH },
7190  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_57_CHECKER_TYPE,
7191  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_57_WIDTH },
7192  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_58_CHECKER_TYPE,
7193  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_58_WIDTH },
7194  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_59_CHECKER_TYPE,
7195  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_59_WIDTH },
7196  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_60_CHECKER_TYPE,
7197  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_60_WIDTH },
7198  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_61_CHECKER_TYPE,
7199  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_61_WIDTH },
7200  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_62_CHECKER_TYPE,
7201  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_62_WIDTH },
7202  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_63_CHECKER_TYPE,
7203  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_63_WIDTH },
7204  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_64_CHECKER_TYPE,
7205  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_64_WIDTH },
7206  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_65_CHECKER_TYPE,
7207  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_65_WIDTH },
7208  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_66_CHECKER_TYPE,
7209  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_66_WIDTH },
7210  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_67_CHECKER_TYPE,
7211  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_67_WIDTH },
7212  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_68_CHECKER_TYPE,
7213  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_68_WIDTH },
7214  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_69_CHECKER_TYPE,
7215  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_69_WIDTH },
7216  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_70_CHECKER_TYPE,
7217  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_70_WIDTH },
7218  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_71_CHECKER_TYPE,
7219  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_71_WIDTH },
7220 };
7221 
7227 static const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_EDC_CTRL_0_groupEntries[SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_EDC_CTRL_0_MAX_NUM_CHECKERS] =
7228 {
7229  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
7230  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_EDC_CTRL_0_GROUP_0_WIDTH },
7231  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
7232  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_EDC_CTRL_0_GROUP_1_WIDTH },
7233  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
7234  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_EDC_CTRL_0_GROUP_2_WIDTH },
7235  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
7236  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_EDC_CTRL_0_GROUP_3_WIDTH },
7237  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
7238  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_EDC_CTRL_0_GROUP_4_WIDTH },
7239  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
7240  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_EDC_CTRL_0_GROUP_5_WIDTH },
7241  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
7242  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_EDC_CTRL_0_GROUP_6_WIDTH },
7243  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
7244  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_EDC_CTRL_0_GROUP_7_WIDTH },
7245  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
7246  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_EDC_CTRL_0_GROUP_8_WIDTH },
7247  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
7248  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_EDC_CTRL_0_GROUP_9_WIDTH },
7249  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
7250  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_EDC_CTRL_0_GROUP_10_WIDTH },
7251  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
7252  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_EDC_CTRL_0_GROUP_11_WIDTH },
7253  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
7254  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_EDC_CTRL_0_GROUP_12_WIDTH },
7255  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
7256  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_EDC_CTRL_0_GROUP_13_WIDTH },
7257  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
7258  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_EDC_CTRL_0_GROUP_14_WIDTH },
7259  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
7260  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_EDC_CTRL_0_GROUP_15_WIDTH },
7261  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
7262  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_EDC_CTRL_0_GROUP_16_WIDTH },
7263  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
7264  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_EDC_CTRL_0_GROUP_17_WIDTH },
7265 };
7266 
7272 static const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_groupEntries[SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_MAX_NUM_CHECKERS] =
7273 {
7274  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
7275  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_0_WIDTH },
7276  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
7277  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_1_WIDTH },
7278  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
7279  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_2_WIDTH },
7280  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
7281  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_3_WIDTH },
7282  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
7283  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_4_WIDTH },
7284  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
7285  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_5_WIDTH },
7286  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
7287  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_6_WIDTH },
7288  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
7289  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_7_WIDTH },
7290  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
7291  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_8_WIDTH },
7292  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
7293  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_9_WIDTH },
7294  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
7295  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_10_WIDTH },
7296  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
7297  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_11_WIDTH },
7298  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
7299  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_12_WIDTH },
7300  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
7301  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_13_WIDTH },
7302  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
7303  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_14_WIDTH },
7304  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
7305  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_15_WIDTH },
7306  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
7307  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_16_WIDTH },
7308  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
7309  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_17_WIDTH },
7310  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
7311  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_18_WIDTH },
7312  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
7313  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_19_WIDTH },
7314  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
7315  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_20_WIDTH },
7316  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
7317  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_21_WIDTH },
7318  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
7319  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_22_WIDTH },
7320  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
7321  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_23_WIDTH },
7322  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
7323  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_24_WIDTH },
7324  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
7325  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_25_WIDTH },
7326  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
7327  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_26_WIDTH },
7328  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
7329  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_27_WIDTH },
7330  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
7331  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_28_WIDTH },
7332  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
7333  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_29_WIDTH },
7334  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
7335  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_30_WIDTH },
7336  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
7337  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_31_WIDTH },
7338  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
7339  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_32_WIDTH },
7340  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_33_CHECKER_TYPE,
7341  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_33_WIDTH },
7342  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_34_CHECKER_TYPE,
7343  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_34_WIDTH },
7344  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_35_CHECKER_TYPE,
7345  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_35_WIDTH },
7346  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_36_CHECKER_TYPE,
7347  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_36_WIDTH },
7348  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_37_CHECKER_TYPE,
7349  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_37_WIDTH },
7350  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_38_CHECKER_TYPE,
7351  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_38_WIDTH },
7352  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_39_CHECKER_TYPE,
7353  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_39_WIDTH },
7354  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_40_CHECKER_TYPE,
7355  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_40_WIDTH },
7356  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_41_CHECKER_TYPE,
7357  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_41_WIDTH },
7358  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_42_CHECKER_TYPE,
7359  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_42_WIDTH },
7360  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_43_CHECKER_TYPE,
7361  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_43_WIDTH },
7362  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_44_CHECKER_TYPE,
7363  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_44_WIDTH },
7364  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_45_CHECKER_TYPE,
7365  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_45_WIDTH },
7366  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_46_CHECKER_TYPE,
7367  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_46_WIDTH },
7368  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_47_CHECKER_TYPE,
7369  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_47_WIDTH },
7370  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_48_CHECKER_TYPE,
7371  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_48_WIDTH },
7372  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_49_CHECKER_TYPE,
7373  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_49_WIDTH },
7374  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_50_CHECKER_TYPE,
7375  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_50_WIDTH },
7376  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_51_CHECKER_TYPE,
7377  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_51_WIDTH },
7378  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_52_CHECKER_TYPE,
7379  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_52_WIDTH },
7380  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_53_CHECKER_TYPE,
7381  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_53_WIDTH },
7382  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_54_CHECKER_TYPE,
7383  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_54_WIDTH },
7384  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_55_CHECKER_TYPE,
7385  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_55_WIDTH },
7386  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_56_CHECKER_TYPE,
7387  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_56_WIDTH },
7388  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_57_CHECKER_TYPE,
7389  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_57_WIDTH },
7390  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_58_CHECKER_TYPE,
7391  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_58_WIDTH },
7392  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_59_CHECKER_TYPE,
7393  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_59_WIDTH },
7394  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_60_CHECKER_TYPE,
7395  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_60_WIDTH },
7396  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_61_CHECKER_TYPE,
7397  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_61_WIDTH },
7398  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_62_CHECKER_TYPE,
7399  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_62_WIDTH },
7400  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_63_CHECKER_TYPE,
7401  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_63_WIDTH },
7402  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_64_CHECKER_TYPE,
7403  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_64_WIDTH },
7404  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_65_CHECKER_TYPE,
7405  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_65_WIDTH },
7406  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_66_CHECKER_TYPE,
7407  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_66_WIDTH },
7408  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_67_CHECKER_TYPE,
7409  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_67_WIDTH },
7410  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_68_CHECKER_TYPE,
7411  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_68_WIDTH },
7412  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_69_CHECKER_TYPE,
7413  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_69_WIDTH },
7414  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_70_CHECKER_TYPE,
7415  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_70_WIDTH },
7416  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_71_CHECKER_TYPE,
7417  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_71_WIDTH },
7418  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_72_CHECKER_TYPE,
7419  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_72_WIDTH },
7420  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_73_CHECKER_TYPE,
7421  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_73_WIDTH },
7422  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_74_CHECKER_TYPE,
7423  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_74_WIDTH },
7424  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_75_CHECKER_TYPE,
7425  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_75_WIDTH },
7426  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_76_CHECKER_TYPE,
7427  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_76_WIDTH },
7428  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_77_CHECKER_TYPE,
7429  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_77_WIDTH },
7430  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_78_CHECKER_TYPE,
7431  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_78_WIDTH },
7432  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_79_CHECKER_TYPE,
7433  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_79_WIDTH },
7434  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_80_CHECKER_TYPE,
7435  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_80_WIDTH },
7436  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_81_CHECKER_TYPE,
7437  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_81_WIDTH },
7438  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_82_CHECKER_TYPE,
7439  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_82_WIDTH },
7440  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_83_CHECKER_TYPE,
7441  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_83_WIDTH },
7442  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_84_CHECKER_TYPE,
7443  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_84_WIDTH },
7444  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_85_CHECKER_TYPE,
7445  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_85_WIDTH },
7446  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_86_CHECKER_TYPE,
7447  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_86_WIDTH },
7448  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_87_CHECKER_TYPE,
7449  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_87_WIDTH },
7450  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_88_CHECKER_TYPE,
7451  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_88_WIDTH },
7452  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_89_CHECKER_TYPE,
7453  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_89_WIDTH },
7454  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_90_CHECKER_TYPE,
7455  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_90_WIDTH },
7456  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_91_CHECKER_TYPE,
7457  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_91_WIDTH },
7458  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_92_CHECKER_TYPE,
7459  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_92_WIDTH },
7460  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_93_CHECKER_TYPE,
7461  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_93_WIDTH },
7462  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_94_CHECKER_TYPE,
7463  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_94_WIDTH },
7464  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_95_CHECKER_TYPE,
7465  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_95_WIDTH },
7466  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_96_CHECKER_TYPE,
7467  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_96_WIDTH },
7468  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_97_CHECKER_TYPE,
7469  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_97_WIDTH },
7470  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_98_CHECKER_TYPE,
7471  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_98_WIDTH },
7472  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_99_CHECKER_TYPE,
7473  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_99_WIDTH },
7474  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_100_CHECKER_TYPE,
7475  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_100_WIDTH },
7476  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_101_CHECKER_TYPE,
7477  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_101_WIDTH },
7478  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_102_CHECKER_TYPE,
7479  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_102_WIDTH },
7480  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_103_CHECKER_TYPE,
7481  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_103_WIDTH },
7482  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_104_CHECKER_TYPE,
7483  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_104_WIDTH },
7484  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_105_CHECKER_TYPE,
7485  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_105_WIDTH },
7486  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_106_CHECKER_TYPE,
7487  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_106_WIDTH },
7488  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_107_CHECKER_TYPE,
7489  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_107_WIDTH },
7490  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_108_CHECKER_TYPE,
7491  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_108_WIDTH },
7492  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_109_CHECKER_TYPE,
7493  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_109_WIDTH },
7494  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_110_CHECKER_TYPE,
7495  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_110_WIDTH },
7496  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_111_CHECKER_TYPE,
7497  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_111_WIDTH },
7498  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_112_CHECKER_TYPE,
7499  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_112_WIDTH },
7500  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_113_CHECKER_TYPE,
7501  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_113_WIDTH },
7502  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_114_CHECKER_TYPE,
7503  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_114_WIDTH },
7504  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_115_CHECKER_TYPE,
7505  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_115_WIDTH },
7506  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_116_CHECKER_TYPE,
7507  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_116_WIDTH },
7508  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_117_CHECKER_TYPE,
7509  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_117_WIDTH },
7510  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_118_CHECKER_TYPE,
7511  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_118_WIDTH },
7512  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_119_CHECKER_TYPE,
7513  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_119_WIDTH },
7514  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_120_CHECKER_TYPE,
7515  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_120_WIDTH },
7516  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_121_CHECKER_TYPE,
7517  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_121_WIDTH },
7518  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_122_CHECKER_TYPE,
7519  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_122_WIDTH },
7520  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_123_CHECKER_TYPE,
7521  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_123_WIDTH },
7522  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_124_CHECKER_TYPE,
7523  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_124_WIDTH },
7524  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_125_CHECKER_TYPE,
7525  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_125_WIDTH },
7526  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_126_CHECKER_TYPE,
7527  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_126_WIDTH },
7528  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_127_CHECKER_TYPE,
7529  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_127_WIDTH },
7530  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_128_CHECKER_TYPE,
7531  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_128_WIDTH },
7532  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_129_CHECKER_TYPE,
7533  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_129_WIDTH },
7534  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_130_CHECKER_TYPE,
7535  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_130_WIDTH },
7536  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_131_CHECKER_TYPE,
7537  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_131_WIDTH },
7538  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_132_CHECKER_TYPE,
7539  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_132_WIDTH },
7540  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_133_CHECKER_TYPE,
7541  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_133_WIDTH },
7542  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_134_CHECKER_TYPE,
7543  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_134_WIDTH },
7544  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_135_CHECKER_TYPE,
7545  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_135_WIDTH },
7546  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_136_CHECKER_TYPE,
7547  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_136_WIDTH },
7548  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_137_CHECKER_TYPE,
7549  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_137_WIDTH },
7550  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_138_CHECKER_TYPE,
7551  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_138_WIDTH },
7552  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_139_CHECKER_TYPE,
7553  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_139_WIDTH },
7554  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_140_CHECKER_TYPE,
7555  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_140_WIDTH },
7556  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_141_CHECKER_TYPE,
7557  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_141_WIDTH },
7558  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_142_CHECKER_TYPE,
7559  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_142_WIDTH },
7560  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_143_CHECKER_TYPE,
7561  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_143_WIDTH },
7562  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_144_CHECKER_TYPE,
7563  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_144_WIDTH },
7564  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_145_CHECKER_TYPE,
7565  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_145_WIDTH },
7566  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_146_CHECKER_TYPE,
7567  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_146_WIDTH },
7568  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_147_CHECKER_TYPE,
7569  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_147_WIDTH },
7570  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_148_CHECKER_TYPE,
7571  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_148_WIDTH },
7572  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_149_CHECKER_TYPE,
7573  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_149_WIDTH },
7574  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_150_CHECKER_TYPE,
7575  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_150_WIDTH },
7576  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_151_CHECKER_TYPE,
7577  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_151_WIDTH },
7578  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_152_CHECKER_TYPE,
7579  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_152_WIDTH },
7580  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_153_CHECKER_TYPE,
7581  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_153_WIDTH },
7582  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_154_CHECKER_TYPE,
7583  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_154_WIDTH },
7584  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_155_CHECKER_TYPE,
7585  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_155_WIDTH },
7586  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_156_CHECKER_TYPE,
7587  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_156_WIDTH },
7588  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_157_CHECKER_TYPE,
7589  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_157_WIDTH },
7590  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_158_CHECKER_TYPE,
7591  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_158_WIDTH },
7592  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_159_CHECKER_TYPE,
7593  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_159_WIDTH },
7594  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_160_CHECKER_TYPE,
7595  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_160_WIDTH },
7596  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_161_CHECKER_TYPE,
7597  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_161_WIDTH },
7598  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_162_CHECKER_TYPE,
7599  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_162_WIDTH },
7600  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_163_CHECKER_TYPE,
7601  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_163_WIDTH },
7602  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_164_CHECKER_TYPE,
7603  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_164_WIDTH },
7604  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_165_CHECKER_TYPE,
7605  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_165_WIDTH },
7606  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_166_CHECKER_TYPE,
7607  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_166_WIDTH },
7608  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_167_CHECKER_TYPE,
7609  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_167_WIDTH },
7610  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_168_CHECKER_TYPE,
7611  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_168_WIDTH },
7612  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_169_CHECKER_TYPE,
7613  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_169_WIDTH },
7614  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_170_CHECKER_TYPE,
7615  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_170_WIDTH },
7616  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_171_CHECKER_TYPE,
7617  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_171_WIDTH },
7618  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_172_CHECKER_TYPE,
7619  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_172_WIDTH },
7620  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_173_CHECKER_TYPE,
7621  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_173_WIDTH },
7622  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_174_CHECKER_TYPE,
7623  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_174_WIDTH },
7624  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_175_CHECKER_TYPE,
7625  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_175_WIDTH },
7626  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_176_CHECKER_TYPE,
7627  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_176_WIDTH },
7628  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_177_CHECKER_TYPE,
7629  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_177_WIDTH },
7630  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_178_CHECKER_TYPE,
7631  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_178_WIDTH },
7632  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_179_CHECKER_TYPE,
7633  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_179_WIDTH },
7634  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_180_CHECKER_TYPE,
7635  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_180_WIDTH },
7636  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_181_CHECKER_TYPE,
7637  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_181_WIDTH },
7638  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_182_CHECKER_TYPE,
7639  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_182_WIDTH },
7640  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_183_CHECKER_TYPE,
7641  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_183_WIDTH },
7642  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_184_CHECKER_TYPE,
7643  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_184_WIDTH },
7644  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_185_CHECKER_TYPE,
7645  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_185_WIDTH },
7646  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_186_CHECKER_TYPE,
7647  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_186_WIDTH },
7648  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_187_CHECKER_TYPE,
7649  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_187_WIDTH },
7650  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_188_CHECKER_TYPE,
7651  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_188_WIDTH },
7652  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_189_CHECKER_TYPE,
7653  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_189_WIDTH },
7654  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_190_CHECKER_TYPE,
7655  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_190_WIDTH },
7656  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_191_CHECKER_TYPE,
7657  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_191_WIDTH },
7658  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_192_CHECKER_TYPE,
7659  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_192_WIDTH },
7660  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_193_CHECKER_TYPE,
7661  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_193_WIDTH },
7662  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_194_CHECKER_TYPE,
7663  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_194_WIDTH },
7664  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_195_CHECKER_TYPE,
7665  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_195_WIDTH },
7666  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_196_CHECKER_TYPE,
7667  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_196_WIDTH },
7668  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_197_CHECKER_TYPE,
7669  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_197_WIDTH },
7670  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_198_CHECKER_TYPE,
7671  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_198_WIDTH },
7672  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_199_CHECKER_TYPE,
7673  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_199_WIDTH },
7674  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_200_CHECKER_TYPE,
7675  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_200_WIDTH },
7676  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_201_CHECKER_TYPE,
7677  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_201_WIDTH },
7678  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_202_CHECKER_TYPE,
7679  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_202_WIDTH },
7680  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_203_CHECKER_TYPE,
7681  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_203_WIDTH },
7682  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_204_CHECKER_TYPE,
7683  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_204_WIDTH },
7684  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_205_CHECKER_TYPE,
7685  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_205_WIDTH },
7686  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_206_CHECKER_TYPE,
7687  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_206_WIDTH },
7688  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_207_CHECKER_TYPE,
7689  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_207_WIDTH },
7690  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_208_CHECKER_TYPE,
7691  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_208_WIDTH },
7692  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_209_CHECKER_TYPE,
7693  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_209_WIDTH },
7694  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_210_CHECKER_TYPE,
7695  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_210_WIDTH },
7696  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_211_CHECKER_TYPE,
7697  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_211_WIDTH },
7698  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_212_CHECKER_TYPE,
7699  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_212_WIDTH },
7700  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_213_CHECKER_TYPE,
7701  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_213_WIDTH },
7702  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_214_CHECKER_TYPE,
7703  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_214_WIDTH },
7704  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_215_CHECKER_TYPE,
7705  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_215_WIDTH },
7706  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_216_CHECKER_TYPE,
7707  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_216_WIDTH },
7708  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_217_CHECKER_TYPE,
7709  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_217_WIDTH },
7710  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_218_CHECKER_TYPE,
7711  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_218_WIDTH },
7712  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_219_CHECKER_TYPE,
7713  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_219_WIDTH },
7714  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_220_CHECKER_TYPE,
7715  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_220_WIDTH },
7716  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_221_CHECKER_TYPE,
7717  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_221_WIDTH },
7718  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_222_CHECKER_TYPE,
7719  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_222_WIDTH },
7720  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_223_CHECKER_TYPE,
7721  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_223_WIDTH },
7722  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_224_CHECKER_TYPE,
7723  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_224_WIDTH },
7724  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_225_CHECKER_TYPE,
7725  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_225_WIDTH },
7726  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_226_CHECKER_TYPE,
7727  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_226_WIDTH },
7728  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_227_CHECKER_TYPE,
7729  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_227_WIDTH },
7730  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_228_CHECKER_TYPE,
7731  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_228_WIDTH },
7732  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_229_CHECKER_TYPE,
7733  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_229_WIDTH },
7734  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_230_CHECKER_TYPE,
7735  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_230_WIDTH },
7736  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_231_CHECKER_TYPE,
7737  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_231_WIDTH },
7738  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_232_CHECKER_TYPE,
7739  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_232_WIDTH },
7740  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_233_CHECKER_TYPE,
7741  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_233_WIDTH },
7742  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_234_CHECKER_TYPE,
7743  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_234_WIDTH },
7744  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_235_CHECKER_TYPE,
7745  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_235_WIDTH },
7746  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_236_CHECKER_TYPE,
7747  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_236_WIDTH },
7748  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_237_CHECKER_TYPE,
7749  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_237_WIDTH },
7750  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_238_CHECKER_TYPE,
7751  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_238_WIDTH },
7752  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_239_CHECKER_TYPE,
7753  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_239_WIDTH },
7754  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_240_CHECKER_TYPE,
7755  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_240_WIDTH },
7756  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_241_CHECKER_TYPE,
7757  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_241_WIDTH },
7758  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_242_CHECKER_TYPE,
7759  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_242_WIDTH },
7760  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_243_CHECKER_TYPE,
7761  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_243_WIDTH },
7762  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_244_CHECKER_TYPE,
7763  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_244_WIDTH },
7764  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_245_CHECKER_TYPE,
7765  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_245_WIDTH },
7766  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_246_CHECKER_TYPE,
7767  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_246_WIDTH },
7768  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_247_CHECKER_TYPE,
7769  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_247_WIDTH },
7770  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_248_CHECKER_TYPE,
7771  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_248_WIDTH },
7772  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_249_CHECKER_TYPE,
7773  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_249_WIDTH },
7774  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_250_CHECKER_TYPE,
7775  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_250_WIDTH },
7776  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_251_CHECKER_TYPE,
7777  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_251_WIDTH },
7778  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_252_CHECKER_TYPE,
7779  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_252_WIDTH },
7780  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_253_CHECKER_TYPE,
7781  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_253_WIDTH },
7782  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_254_CHECKER_TYPE,
7783  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_254_WIDTH },
7784  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_255_CHECKER_TYPE,
7785  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_255_WIDTH },
7786 };
7787 
7793 static const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_groupEntries[SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_MAX_NUM_CHECKERS] =
7794 {
7795  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_0_CHECKER_TYPE,
7796  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_0_WIDTH },
7797  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_1_CHECKER_TYPE,
7798  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_1_WIDTH },
7799  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_2_CHECKER_TYPE,
7800  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_2_WIDTH },
7801  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_3_CHECKER_TYPE,
7802  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_3_WIDTH },
7803  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_4_CHECKER_TYPE,
7804  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_4_WIDTH },
7805  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_5_CHECKER_TYPE,
7806  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_5_WIDTH },
7807  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_6_CHECKER_TYPE,
7808  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_6_WIDTH },
7809  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_7_CHECKER_TYPE,
7810  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_7_WIDTH },
7811  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_8_CHECKER_TYPE,
7812  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_8_WIDTH },
7813  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_9_CHECKER_TYPE,
7814  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_9_WIDTH },
7815  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_10_CHECKER_TYPE,
7816  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_10_WIDTH },
7817  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_11_CHECKER_TYPE,
7818  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_11_WIDTH },
7819  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_12_CHECKER_TYPE,
7820  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_12_WIDTH },
7821  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_13_CHECKER_TYPE,
7822  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_13_WIDTH },
7823  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_14_CHECKER_TYPE,
7824  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_14_WIDTH },
7825  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_15_CHECKER_TYPE,
7826  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_15_WIDTH },
7827  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_16_CHECKER_TYPE,
7828  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_16_WIDTH },
7829  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_17_CHECKER_TYPE,
7830  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_17_WIDTH },
7831  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_18_CHECKER_TYPE,
7832  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_18_WIDTH },
7833  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_19_CHECKER_TYPE,
7834  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_19_WIDTH },
7835  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_20_CHECKER_TYPE,
7836  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_20_WIDTH },
7837  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_21_CHECKER_TYPE,
7838  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_21_WIDTH },
7839  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_22_CHECKER_TYPE,
7840  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_22_WIDTH },
7841  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_23_CHECKER_TYPE,
7842  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_23_WIDTH },
7843  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_24_CHECKER_TYPE,
7844  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_24_WIDTH },
7845  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_25_CHECKER_TYPE,
7846  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_25_WIDTH },
7847  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_26_CHECKER_TYPE,
7848  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_26_WIDTH },
7849  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_27_CHECKER_TYPE,
7850  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_27_WIDTH },
7851  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_28_CHECKER_TYPE,
7852  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_28_WIDTH },
7853  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_29_CHECKER_TYPE,
7854  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_29_WIDTH },
7855  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_30_CHECKER_TYPE,
7856  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_30_WIDTH },
7857  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_31_CHECKER_TYPE,
7858  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_31_WIDTH },
7859  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_32_CHECKER_TYPE,
7860  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_32_WIDTH },
7861  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_33_CHECKER_TYPE,
7862  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_33_WIDTH },
7863  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_34_CHECKER_TYPE,
7864  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_34_WIDTH },
7865  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_35_CHECKER_TYPE,
7866  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_35_WIDTH },
7867  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_36_CHECKER_TYPE,
7868  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_36_WIDTH },
7869  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_37_CHECKER_TYPE,
7870  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_37_WIDTH },
7871  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_38_CHECKER_TYPE,
7872  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_38_WIDTH },
7873  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_39_CHECKER_TYPE,
7874  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_39_WIDTH },
7875  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_40_CHECKER_TYPE,
7876  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_40_WIDTH },
7877  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_41_CHECKER_TYPE,
7878  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_41_WIDTH },
7879  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_42_CHECKER_TYPE,
7880  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_42_WIDTH },
7881  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_43_CHECKER_TYPE,
7882  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_43_WIDTH },
7883  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_44_CHECKER_TYPE,
7884  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_44_WIDTH },
7885  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_45_CHECKER_TYPE,
7886  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_45_WIDTH },
7887  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_46_CHECKER_TYPE,
7888  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_46_WIDTH },
7889  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_47_CHECKER_TYPE,
7890  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_47_WIDTH },
7891  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_48_CHECKER_TYPE,
7892  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_48_WIDTH },
7893  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_49_CHECKER_TYPE,
7894  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_49_WIDTH },
7895  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_50_CHECKER_TYPE,
7896  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_50_WIDTH },
7897  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_51_CHECKER_TYPE,
7898  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_51_WIDTH },
7899  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_52_CHECKER_TYPE,
7900  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_52_WIDTH },
7901  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_53_CHECKER_TYPE,
7902  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_53_WIDTH },
7903  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_54_CHECKER_TYPE,
7904  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_54_WIDTH },
7905  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_55_CHECKER_TYPE,
7906  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_55_WIDTH },
7907  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_56_CHECKER_TYPE,
7908  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_56_WIDTH },
7909 };
7910 
7916 static const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_groupEntries[SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_MAX_NUM_CHECKERS] =
7917 {
7918  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
7919  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_0_WIDTH },
7920  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
7921  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_1_WIDTH },
7922  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
7923  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_2_WIDTH },
7924  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
7925  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_3_WIDTH },
7926  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
7927  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_4_WIDTH },
7928  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
7929  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_5_WIDTH },
7930  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
7931  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_6_WIDTH },
7932  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
7933  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_7_WIDTH },
7934  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
7935  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_8_WIDTH },
7936  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
7937  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_9_WIDTH },
7938  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
7939  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_10_WIDTH },
7940  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
7941  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_11_WIDTH },
7942  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
7943  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_12_WIDTH },
7944  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
7945  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_13_WIDTH },
7946  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
7947  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_14_WIDTH },
7948  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
7949  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_15_WIDTH },
7950  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
7951  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_16_WIDTH },
7952  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
7953  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_17_WIDTH },
7954  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
7955  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_18_WIDTH },
7956  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
7957  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_19_WIDTH },
7958  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
7959  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_20_WIDTH },
7960  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
7961  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_21_WIDTH },
7962  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
7963  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_22_WIDTH },
7964  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
7965  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_23_WIDTH },
7966  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
7967  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_24_WIDTH },
7968  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
7969  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_25_WIDTH },
7970  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
7971  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_26_WIDTH },
7972  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
7973  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_27_WIDTH },
7974  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
7975  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_28_WIDTH },
7976  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
7977  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_29_WIDTH },
7978  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
7979  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_30_WIDTH },
7980  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
7981  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_31_WIDTH },
7982  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
7983  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_32_WIDTH },
7984  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_33_CHECKER_TYPE,
7985  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_33_WIDTH },
7986  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_34_CHECKER_TYPE,
7987  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_34_WIDTH },
7988  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_35_CHECKER_TYPE,
7989  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_35_WIDTH },
7990  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_36_CHECKER_TYPE,
7991  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_36_WIDTH },
7992  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_37_CHECKER_TYPE,
7993  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_37_WIDTH },
7994  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_38_CHECKER_TYPE,
7995  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_38_WIDTH },
7996  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_39_CHECKER_TYPE,
7997  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_39_WIDTH },
7998  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_40_CHECKER_TYPE,
7999  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_40_WIDTH },
8000  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_41_CHECKER_TYPE,
8001  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_41_WIDTH },
8002  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_42_CHECKER_TYPE,
8003  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_42_WIDTH },
8004  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_43_CHECKER_TYPE,
8005  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_43_WIDTH },
8006  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_44_CHECKER_TYPE,
8007  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_44_WIDTH },
8008  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_45_CHECKER_TYPE,
8009  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_45_WIDTH },
8010  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_46_CHECKER_TYPE,
8011  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_46_WIDTH },
8012  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_47_CHECKER_TYPE,
8013  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_47_WIDTH },
8014  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_48_CHECKER_TYPE,
8015  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_48_WIDTH },
8016  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_49_CHECKER_TYPE,
8017  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_49_WIDTH },
8018  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_50_CHECKER_TYPE,
8019  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_50_WIDTH },
8020  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_51_CHECKER_TYPE,
8021  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_51_WIDTH },
8022  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_52_CHECKER_TYPE,
8023  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_52_WIDTH },
8024  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_53_CHECKER_TYPE,
8025  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_53_WIDTH },
8026  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_54_CHECKER_TYPE,
8027  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_54_WIDTH },
8028  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_55_CHECKER_TYPE,
8029  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_55_WIDTH },
8030  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_56_CHECKER_TYPE,
8031  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_56_WIDTH },
8032  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_57_CHECKER_TYPE,
8033  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_57_WIDTH },
8034  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_58_CHECKER_TYPE,
8035  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_58_WIDTH },
8036  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_59_CHECKER_TYPE,
8037  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_59_WIDTH },
8038  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_60_CHECKER_TYPE,
8039  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_60_WIDTH },
8040  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_61_CHECKER_TYPE,
8041  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_61_WIDTH },
8042  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_62_CHECKER_TYPE,
8043  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_62_WIDTH },
8044  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_63_CHECKER_TYPE,
8045  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_63_WIDTH },
8046  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_64_CHECKER_TYPE,
8047  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_64_WIDTH },
8048  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_65_CHECKER_TYPE,
8049  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_65_WIDTH },
8050  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_66_CHECKER_TYPE,
8051  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_66_WIDTH },
8052 };
8053 
8059 static const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries[SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS] =
8060 {
8061  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
8062  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_0_WIDTH },
8063  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
8064  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_1_WIDTH },
8065  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
8066  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_2_WIDTH },
8067  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
8068  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_3_WIDTH },
8069  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
8070  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_4_WIDTH },
8071  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
8072  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_5_WIDTH },
8073  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
8074  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_6_WIDTH },
8075  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
8076  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_7_WIDTH },
8077  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
8078  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_8_WIDTH },
8079  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
8080  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_9_WIDTH },
8081  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
8082  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_10_WIDTH },
8083  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
8084  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_11_WIDTH },
8085  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
8086  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_12_WIDTH },
8087  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
8088  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_13_WIDTH },
8089  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
8090  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_14_WIDTH },
8091  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
8092  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_15_WIDTH },
8093  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
8094  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_16_WIDTH },
8095  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
8096  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_17_WIDTH },
8097  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
8098  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_18_WIDTH },
8099  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
8100  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_19_WIDTH },
8101  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
8102  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_20_WIDTH },
8103  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
8104  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_21_WIDTH },
8105  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
8106  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_22_WIDTH },
8107  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
8108  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_23_WIDTH },
8109  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
8110  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_24_WIDTH },
8111  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
8112  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_25_WIDTH },
8113  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
8114  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_26_WIDTH },
8115  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
8116  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_27_WIDTH },
8117  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
8118  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_28_WIDTH },
8119  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
8120  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_29_WIDTH },
8121  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
8122  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_30_WIDTH },
8123  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
8124  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_31_WIDTH },
8125  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
8126  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_32_WIDTH },
8127  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_33_CHECKER_TYPE,
8128  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_33_WIDTH },
8129  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_34_CHECKER_TYPE,
8130  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_34_WIDTH },
8131  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_35_CHECKER_TYPE,
8132  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_35_WIDTH },
8133  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_36_CHECKER_TYPE,
8134  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_36_WIDTH },
8135  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_37_CHECKER_TYPE,
8136  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_37_WIDTH },
8137  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_38_CHECKER_TYPE,
8138  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_38_WIDTH },
8139  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_39_CHECKER_TYPE,
8140  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_39_WIDTH },
8141  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_40_CHECKER_TYPE,
8142  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_40_WIDTH },
8143  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_41_CHECKER_TYPE,
8144  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_41_WIDTH },
8145  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_42_CHECKER_TYPE,
8146  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_42_WIDTH },
8147  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_43_CHECKER_TYPE,
8148  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_43_WIDTH },
8149  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_44_CHECKER_TYPE,
8150  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_44_WIDTH },
8151  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_45_CHECKER_TYPE,
8152  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_45_WIDTH },
8153  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_46_CHECKER_TYPE,
8154  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_46_WIDTH },
8155  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_47_CHECKER_TYPE,
8156  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_47_WIDTH },
8157  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_48_CHECKER_TYPE,
8158  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_48_WIDTH },
8159  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_49_CHECKER_TYPE,
8160  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_49_WIDTH },
8161  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_50_CHECKER_TYPE,
8162  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_50_WIDTH },
8163  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_51_CHECKER_TYPE,
8164  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_51_WIDTH },
8165  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_52_CHECKER_TYPE,
8166  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_52_WIDTH },
8167  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_53_CHECKER_TYPE,
8168  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_53_WIDTH },
8169  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_54_CHECKER_TYPE,
8170  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_54_WIDTH },
8171  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_55_CHECKER_TYPE,
8172  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_55_WIDTH },
8173  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_56_CHECKER_TYPE,
8174  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_56_WIDTH },
8175  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_57_CHECKER_TYPE,
8176  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_57_WIDTH },
8177  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_58_CHECKER_TYPE,
8178  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_58_WIDTH },
8179  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_59_CHECKER_TYPE,
8180  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_59_WIDTH },
8181  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_60_CHECKER_TYPE,
8182  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_60_WIDTH },
8183  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_61_CHECKER_TYPE,
8184  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_61_WIDTH },
8185  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_62_CHECKER_TYPE,
8186  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_62_WIDTH },
8187  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_63_CHECKER_TYPE,
8188  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_63_WIDTH },
8189  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_64_CHECKER_TYPE,
8190  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_64_WIDTH },
8191  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_65_CHECKER_TYPE,
8192  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_65_WIDTH },
8193  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_66_CHECKER_TYPE,
8194  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_66_WIDTH },
8195  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_67_CHECKER_TYPE,
8196  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_67_WIDTH },
8197  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_68_CHECKER_TYPE,
8198  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_68_WIDTH },
8199  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_69_CHECKER_TYPE,
8200  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_69_WIDTH },
8201  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_70_CHECKER_TYPE,
8202  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_70_WIDTH },
8203  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_71_CHECKER_TYPE,
8204  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_71_WIDTH },
8205 };
8206 
8212 static const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_groupEntries[SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_MAX_NUM_CHECKERS] =
8213 {
8214  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
8215  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_0_WIDTH },
8216  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
8217  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_1_WIDTH },
8218  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
8219  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_2_WIDTH },
8220  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
8221  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_3_WIDTH },
8222  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
8223  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_4_WIDTH },
8224  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
8225  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_5_WIDTH },
8226  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
8227  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_6_WIDTH },
8228  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
8229  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_7_WIDTH },
8230  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
8231  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_8_WIDTH },
8232  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
8233  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_9_WIDTH },
8234  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
8235  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_10_WIDTH },
8236  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
8237  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_11_WIDTH },
8238  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
8239  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_12_WIDTH },
8240  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
8241  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_13_WIDTH },
8242  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
8243  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_14_WIDTH },
8244  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
8245  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_15_WIDTH },
8246  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
8247  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_16_WIDTH },
8248  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
8249  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_17_WIDTH },
8250  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
8251  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_18_WIDTH },
8252  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
8253  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_19_WIDTH },
8254  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
8255  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_20_WIDTH },
8256  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
8257  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_21_WIDTH },
8258  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
8259  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_22_WIDTH },
8260  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
8261  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_23_WIDTH },
8262  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
8263  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_24_WIDTH },
8264  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
8265  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_25_WIDTH },
8266  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
8267  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_26_WIDTH },
8268  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
8269  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_27_WIDTH },
8270  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
8271  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_28_WIDTH },
8272  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
8273  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_29_WIDTH },
8274  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
8275  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_30_WIDTH },
8276  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
8277  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_31_WIDTH },
8278  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
8279  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_32_WIDTH },
8280  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_33_CHECKER_TYPE,
8281  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_33_WIDTH },
8282  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_34_CHECKER_TYPE,
8283  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_34_WIDTH },
8284  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_35_CHECKER_TYPE,
8285  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_35_WIDTH },
8286  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_36_CHECKER_TYPE,
8287  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_36_WIDTH },
8288  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_37_CHECKER_TYPE,
8289  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_37_WIDTH },
8290  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_38_CHECKER_TYPE,
8291  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_38_WIDTH },
8292  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_39_CHECKER_TYPE,
8293  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_39_WIDTH },
8294  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_40_CHECKER_TYPE,
8295  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_40_WIDTH },
8296  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_41_CHECKER_TYPE,
8297  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_41_WIDTH },
8298  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_42_CHECKER_TYPE,
8299  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_42_WIDTH },
8300  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_43_CHECKER_TYPE,
8301  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_43_WIDTH },
8302  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_44_CHECKER_TYPE,
8303  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_44_WIDTH },
8304  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_45_CHECKER_TYPE,
8305  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_45_WIDTH },
8306  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_46_CHECKER_TYPE,
8307  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_46_WIDTH },
8308  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_47_CHECKER_TYPE,
8309  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_47_WIDTH },
8310  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_48_CHECKER_TYPE,
8311  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_48_WIDTH },
8312  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_49_CHECKER_TYPE,
8313  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_49_WIDTH },
8314  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_50_CHECKER_TYPE,
8315  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_50_WIDTH },
8316  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_51_CHECKER_TYPE,
8317  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_51_WIDTH },
8318  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_52_CHECKER_TYPE,
8319  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_52_WIDTH },
8320  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_53_CHECKER_TYPE,
8321  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_53_WIDTH },
8322  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_54_CHECKER_TYPE,
8323  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_54_WIDTH },
8324  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_55_CHECKER_TYPE,
8325  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_55_WIDTH },
8326  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_56_CHECKER_TYPE,
8327  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_56_WIDTH },
8328  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_57_CHECKER_TYPE,
8329  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_57_WIDTH },
8330  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_58_CHECKER_TYPE,
8331  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_58_WIDTH },
8332  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_59_CHECKER_TYPE,
8333  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_59_WIDTH },
8334  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_60_CHECKER_TYPE,
8335  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_60_WIDTH },
8336  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_61_CHECKER_TYPE,
8337  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_61_WIDTH },
8338  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_62_CHECKER_TYPE,
8339  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_62_WIDTH },
8340  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_63_CHECKER_TYPE,
8341  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_63_WIDTH },
8342  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_64_CHECKER_TYPE,
8343  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_64_WIDTH },
8344  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_65_CHECKER_TYPE,
8345  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_65_WIDTH },
8346  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_66_CHECKER_TYPE,
8347  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_66_WIDTH },
8348  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_67_CHECKER_TYPE,
8349  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_67_WIDTH },
8350  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_68_CHECKER_TYPE,
8351  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_68_WIDTH },
8352  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_69_CHECKER_TYPE,
8353  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_69_WIDTH },
8354  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_70_CHECKER_TYPE,
8355  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_70_WIDTH },
8356  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_71_CHECKER_TYPE,
8357  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_71_WIDTH },
8358  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_72_CHECKER_TYPE,
8359  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_72_WIDTH },
8360  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_73_CHECKER_TYPE,
8361  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_73_WIDTH },
8362  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_74_CHECKER_TYPE,
8363  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_74_WIDTH },
8364  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_75_CHECKER_TYPE,
8365  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_75_WIDTH },
8366  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_76_CHECKER_TYPE,
8367  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_76_WIDTH },
8368  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_77_CHECKER_TYPE,
8369  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_77_WIDTH },
8370  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_78_CHECKER_TYPE,
8371  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_78_WIDTH },
8372  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_79_CHECKER_TYPE,
8373  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_79_WIDTH },
8374  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_80_CHECKER_TYPE,
8375  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_80_WIDTH },
8376  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_81_CHECKER_TYPE,
8377  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_81_WIDTH },
8378  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_82_CHECKER_TYPE,
8379  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_82_WIDTH },
8380  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_83_CHECKER_TYPE,
8381  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_83_WIDTH },
8382  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_84_CHECKER_TYPE,
8383  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_84_WIDTH },
8384  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_85_CHECKER_TYPE,
8385  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_85_WIDTH },
8386  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_86_CHECKER_TYPE,
8387  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_86_WIDTH },
8388  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_87_CHECKER_TYPE,
8389  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_87_WIDTH },
8390  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_88_CHECKER_TYPE,
8391  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_88_WIDTH },
8392  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_89_CHECKER_TYPE,
8393  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_89_WIDTH },
8394  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_90_CHECKER_TYPE,
8395  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_90_WIDTH },
8396  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_91_CHECKER_TYPE,
8397  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_91_WIDTH },
8398  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_92_CHECKER_TYPE,
8399  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_92_WIDTH },
8400  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_93_CHECKER_TYPE,
8401  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_93_WIDTH },
8402  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_94_CHECKER_TYPE,
8403  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_94_WIDTH },
8404  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_95_CHECKER_TYPE,
8405  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_95_WIDTH },
8406  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_96_CHECKER_TYPE,
8407  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_96_WIDTH },
8408  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_97_CHECKER_TYPE,
8409  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_97_WIDTH },
8410  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_98_CHECKER_TYPE,
8411  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_98_WIDTH },
8412  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_99_CHECKER_TYPE,
8413  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_99_WIDTH },
8414  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_100_CHECKER_TYPE,
8415  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_100_WIDTH },
8416  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_101_CHECKER_TYPE,
8417  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_101_WIDTH },
8418  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_102_CHECKER_TYPE,
8419  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_102_WIDTH },
8420  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_103_CHECKER_TYPE,
8421  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_103_WIDTH },
8422  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_104_CHECKER_TYPE,
8423  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_104_WIDTH },
8424  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_105_CHECKER_TYPE,
8425  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_105_WIDTH },
8426  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_106_CHECKER_TYPE,
8427  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_106_WIDTH },
8428  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_107_CHECKER_TYPE,
8429  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_107_WIDTH },
8430  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_108_CHECKER_TYPE,
8431  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_108_WIDTH },
8432  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_109_CHECKER_TYPE,
8433  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_109_WIDTH },
8434  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_110_CHECKER_TYPE,
8435  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_110_WIDTH },
8436  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_111_CHECKER_TYPE,
8437  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_111_WIDTH },
8438  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_112_CHECKER_TYPE,
8439  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_112_WIDTH },
8440  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_113_CHECKER_TYPE,
8441  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_113_WIDTH },
8442  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_114_CHECKER_TYPE,
8443  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_114_WIDTH },
8444  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_115_CHECKER_TYPE,
8445  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_115_WIDTH },
8446  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_116_CHECKER_TYPE,
8447  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_116_WIDTH },
8448  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_117_CHECKER_TYPE,
8449  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_117_WIDTH },
8450  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_118_CHECKER_TYPE,
8451  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_118_WIDTH },
8452  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_119_CHECKER_TYPE,
8453  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_119_WIDTH },
8454  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_120_CHECKER_TYPE,
8455  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_120_WIDTH },
8456  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_121_CHECKER_TYPE,
8457  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_121_WIDTH },
8458  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_122_CHECKER_TYPE,
8459  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_122_WIDTH },
8460  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_123_CHECKER_TYPE,
8461  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_123_WIDTH },
8462  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_124_CHECKER_TYPE,
8463  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_124_WIDTH },
8464  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_125_CHECKER_TYPE,
8465  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_125_WIDTH },
8466  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_126_CHECKER_TYPE,
8467  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_126_WIDTH },
8468  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_127_CHECKER_TYPE,
8469  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_127_WIDTH },
8470  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_128_CHECKER_TYPE,
8471  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_128_WIDTH },
8472  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_129_CHECKER_TYPE,
8473  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_129_WIDTH },
8474  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_130_CHECKER_TYPE,
8475  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_130_WIDTH },
8476  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_131_CHECKER_TYPE,
8477  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_131_WIDTH },
8478 };
8479 
8485 static const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_VD2GCLK_EDC_CTRL_0_groupEntries[SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_VD2GCLK_EDC_CTRL_0_MAX_NUM_CHECKERS] =
8486 {
8487  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
8488  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_0_WIDTH },
8489  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
8490  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_1_WIDTH },
8491  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
8492  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_2_WIDTH },
8493 };
8494 
8500 static const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_groupEntries[SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_MAX_NUM_CHECKERS] =
8501 {
8502  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
8503  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_0_WIDTH },
8504  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
8505  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_1_WIDTH },
8506  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
8507  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_2_WIDTH },
8508  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
8509  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_3_WIDTH },
8510  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
8511  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_4_WIDTH },
8512  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
8513  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_5_WIDTH },
8514  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
8515  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_6_WIDTH },
8516  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
8517  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_7_WIDTH },
8518  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
8519  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_8_WIDTH },
8520  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
8521  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_9_WIDTH },
8522  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
8523  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_10_WIDTH },
8524  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
8525  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_11_WIDTH },
8526  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
8527  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_12_WIDTH },
8528  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
8529  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_13_WIDTH },
8530  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
8531  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_14_WIDTH },
8532  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
8533  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_15_WIDTH },
8534  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
8535  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_16_WIDTH },
8536  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
8537  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_17_WIDTH },
8538  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
8539  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_18_WIDTH },
8540  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
8541  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_19_WIDTH },
8542  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
8543  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_20_WIDTH },
8544  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
8545  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_21_WIDTH },
8546  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
8547  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_22_WIDTH },
8548  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
8549  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_23_WIDTH },
8550  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
8551  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_24_WIDTH },
8552  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
8553  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_25_WIDTH },
8554  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
8555  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_26_WIDTH },
8556  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
8557  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_27_WIDTH },
8558  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
8559  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_28_WIDTH },
8560  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
8561  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_29_WIDTH },
8562  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
8563  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_30_WIDTH },
8564  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
8565  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_31_WIDTH },
8566  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
8567  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_32_WIDTH },
8568  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_33_CHECKER_TYPE,
8569  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_33_WIDTH },
8570  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_34_CHECKER_TYPE,
8571  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_34_WIDTH },
8572  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_35_CHECKER_TYPE,
8573  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_35_WIDTH },
8574  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_36_CHECKER_TYPE,
8575  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_36_WIDTH },
8576  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_37_CHECKER_TYPE,
8577  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_37_WIDTH },
8578  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_38_CHECKER_TYPE,
8579  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_38_WIDTH },
8580  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_39_CHECKER_TYPE,
8581  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_39_WIDTH },
8582  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_40_CHECKER_TYPE,
8583  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_40_WIDTH },
8584  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_41_CHECKER_TYPE,
8585  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_41_WIDTH },
8586  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_42_CHECKER_TYPE,
8587  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_42_WIDTH },
8588  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_43_CHECKER_TYPE,
8589  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_43_WIDTH },
8590  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_44_CHECKER_TYPE,
8591  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_44_WIDTH },
8592  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_45_CHECKER_TYPE,
8593  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_45_WIDTH },
8594  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_46_CHECKER_TYPE,
8595  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_46_WIDTH },
8596  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_47_CHECKER_TYPE,
8597  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_47_WIDTH },
8598  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_48_CHECKER_TYPE,
8599  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_48_WIDTH },
8600  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_49_CHECKER_TYPE,
8601  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_49_WIDTH },
8602  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_50_CHECKER_TYPE,
8603  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_50_WIDTH },
8604  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_51_CHECKER_TYPE,
8605  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_51_WIDTH },
8606  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_52_CHECKER_TYPE,
8607  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_52_WIDTH },
8608  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_53_CHECKER_TYPE,
8609  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_53_WIDTH },
8610  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_54_CHECKER_TYPE,
8611  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_54_WIDTH },
8612  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_55_CHECKER_TYPE,
8613  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_55_WIDTH },
8614  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_56_CHECKER_TYPE,
8615  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_56_WIDTH },
8616  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_57_CHECKER_TYPE,
8617  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_57_WIDTH },
8618  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_58_CHECKER_TYPE,
8619  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_58_WIDTH },
8620  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_59_CHECKER_TYPE,
8621  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_59_WIDTH },
8622  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_60_CHECKER_TYPE,
8623  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_60_WIDTH },
8624  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_61_CHECKER_TYPE,
8625  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_61_WIDTH },
8626  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_62_CHECKER_TYPE,
8627  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_62_WIDTH },
8628 };
8629 
8635 static const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_groupEntries[SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_MAX_NUM_CHECKERS] =
8636 {
8637  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
8638  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_0_WIDTH },
8639  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
8640  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_1_WIDTH },
8641  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
8642  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_2_WIDTH },
8643  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
8644  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_3_WIDTH },
8645  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
8646  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_4_WIDTH },
8647  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
8648  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_5_WIDTH },
8649  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
8650  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_6_WIDTH },
8651  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
8652  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_7_WIDTH },
8653  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
8654  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_8_WIDTH },
8655  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
8656  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_9_WIDTH },
8657  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
8658  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_10_WIDTH },
8659  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
8660  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_11_WIDTH },
8661  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
8662  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_12_WIDTH },
8663  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
8664  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_13_WIDTH },
8665  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
8666  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_14_WIDTH },
8667  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
8668  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_15_WIDTH },
8669  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
8670  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_16_WIDTH },
8671  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
8672  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_17_WIDTH },
8673  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
8674  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_18_WIDTH },
8675  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
8676  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_19_WIDTH },
8677  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
8678  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_20_WIDTH },
8679  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
8680  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_21_WIDTH },
8681  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
8682  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_22_WIDTH },
8683  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
8684  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_23_WIDTH },
8685  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
8686  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_24_WIDTH },
8687  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
8688  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_25_WIDTH },
8689  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
8690  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_26_WIDTH },
8691  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
8692  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_27_WIDTH },
8693  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
8694  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_28_WIDTH },
8695  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
8696  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_29_WIDTH },
8697  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
8698  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_30_WIDTH },
8699  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
8700  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_31_WIDTH },
8701  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
8702  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_32_WIDTH },
8703 };
8704 
8710 static const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_groupEntries[SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_MAX_NUM_CHECKERS] =
8711 {
8712  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
8713  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_0_WIDTH },
8714  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
8715  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_1_WIDTH },
8716  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
8717  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_2_WIDTH },
8718  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
8719  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_3_WIDTH },
8720  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
8721  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_4_WIDTH },
8722  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
8723  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_5_WIDTH },
8724  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
8725  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_6_WIDTH },
8726  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
8727  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_7_WIDTH },
8728  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
8729  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_8_WIDTH },
8730  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
8731  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_9_WIDTH },
8732  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
8733  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_10_WIDTH },
8734  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
8735  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_11_WIDTH },
8736  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
8737  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_12_WIDTH },
8738  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
8739  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_13_WIDTH },
8740  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
8741  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_14_WIDTH },
8742  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
8743  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_15_WIDTH },
8744  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
8745  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_16_WIDTH },
8746  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
8747  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_17_WIDTH },
8748  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
8749  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_18_WIDTH },
8750  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
8751  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_19_WIDTH },
8752  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
8753  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_20_WIDTH },
8754  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
8755  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_21_WIDTH },
8756  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
8757  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_22_WIDTH },
8758  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
8759  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_23_WIDTH },
8760  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
8761  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_24_WIDTH },
8762  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
8763  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_25_WIDTH },
8764  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
8765  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_26_WIDTH },
8766  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
8767  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_27_WIDTH },
8768  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
8769  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_28_WIDTH },
8770  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
8771  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_29_WIDTH },
8772  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
8773  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_30_WIDTH },
8774  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
8775  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_31_WIDTH },
8776  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
8777  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_32_WIDTH },
8778 };
8779 
8785 static const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_groupEntries[SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_MAX_NUM_CHECKERS] =
8786 {
8787  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
8788  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_0_WIDTH },
8789  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
8790  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_1_WIDTH },
8791  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
8792  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_2_WIDTH },
8793  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
8794  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_3_WIDTH },
8795  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
8796  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_4_WIDTH },
8797  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
8798  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_5_WIDTH },
8799  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
8800  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_6_WIDTH },
8801  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
8802  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_7_WIDTH },
8803  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
8804  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_8_WIDTH },
8805  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
8806  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_9_WIDTH },
8807  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
8808  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_10_WIDTH },
8809  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
8810  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_11_WIDTH },
8811  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
8812  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_12_WIDTH },
8813  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
8814  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_13_WIDTH },
8815  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
8816  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_14_WIDTH },
8817  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
8818  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_15_WIDTH },
8819  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
8820  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_16_WIDTH },
8821  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
8822  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_17_WIDTH },
8823  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
8824  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_18_WIDTH },
8825  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
8826  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_19_WIDTH },
8827  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
8828  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_20_WIDTH },
8829  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
8830  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_21_WIDTH },
8831  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
8832  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_22_WIDTH },
8833  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
8834  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_23_WIDTH },
8835  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
8836  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_24_WIDTH },
8837  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
8838  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_25_WIDTH },
8839  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
8840  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_26_WIDTH },
8841  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
8842  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_27_WIDTH },
8843  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
8844  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_28_WIDTH },
8845  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
8846  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_29_WIDTH },
8847 };
8848 
8854 static const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_groupEntries[SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_MAX_NUM_CHECKERS] =
8855 {
8856  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
8857  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_0_WIDTH },
8858  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
8859  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_1_WIDTH },
8860  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
8861  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_2_WIDTH },
8862  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
8863  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_3_WIDTH },
8864  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
8865  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_4_WIDTH },
8866  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
8867  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_5_WIDTH },
8868  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
8869  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_6_WIDTH },
8870  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
8871  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_7_WIDTH },
8872  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
8873  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_8_WIDTH },
8874  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
8875  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_9_WIDTH },
8876  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
8877  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_10_WIDTH },
8878  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
8879  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_11_WIDTH },
8880  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
8881  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_12_WIDTH },
8882  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
8883  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_13_WIDTH },
8884  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
8885  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_14_WIDTH },
8886  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
8887  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_15_WIDTH },
8888  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
8889  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_16_WIDTH },
8890  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
8891  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_17_WIDTH },
8892  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
8893  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_18_WIDTH },
8894  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
8895  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_19_WIDTH },
8896  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
8897  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_20_WIDTH },
8898  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
8899  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_21_WIDTH },
8900  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
8901  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_22_WIDTH },
8902  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
8903  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_23_WIDTH },
8904  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
8905  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_24_WIDTH },
8906  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
8907  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_25_WIDTH },
8908  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
8909  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_26_WIDTH },
8910  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
8911  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_27_WIDTH },
8912  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
8913  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_28_WIDTH },
8914  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
8915  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_29_WIDTH },
8916 };
8917 
8923 static const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_groupEntries[SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_MAX_NUM_CHECKERS] =
8924 {
8925  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
8926  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_0_WIDTH },
8927  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
8928  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_1_WIDTH },
8929  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
8930  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_2_WIDTH },
8931  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
8932  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_3_WIDTH },
8933  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
8934  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_4_WIDTH },
8935  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
8936  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_5_WIDTH },
8937  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
8938  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_6_WIDTH },
8939  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
8940  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_7_WIDTH },
8941  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
8942  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_8_WIDTH },
8943  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
8944  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_9_WIDTH },
8945  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
8946  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_10_WIDTH },
8947  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
8948  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_11_WIDTH },
8949  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
8950  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_12_WIDTH },
8951  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
8952  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_13_WIDTH },
8953  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
8954  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_14_WIDTH },
8955  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
8956  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_15_WIDTH },
8957  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
8958  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_16_WIDTH },
8959  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
8960  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_17_WIDTH },
8961  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
8962  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_18_WIDTH },
8963  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
8964  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_19_WIDTH },
8965  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
8966  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_20_WIDTH },
8967  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
8968  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_21_WIDTH },
8969  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
8970  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_22_WIDTH },
8971  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
8972  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_23_WIDTH },
8973  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
8974  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_24_WIDTH },
8975  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
8976  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_25_WIDTH },
8977  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
8978  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_26_WIDTH },
8979  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
8980  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_27_WIDTH },
8981  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
8982  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_28_WIDTH },
8983  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
8984  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_29_WIDTH },
8985  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
8986  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_30_WIDTH },
8987  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
8988  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_31_WIDTH },
8989  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
8990  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_32_WIDTH },
8991  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_33_CHECKER_TYPE,
8992  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_33_WIDTH },
8993  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_34_CHECKER_TYPE,
8994  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_34_WIDTH },
8995  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_35_CHECKER_TYPE,
8996  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_35_WIDTH },
8997  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_36_CHECKER_TYPE,
8998  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_36_WIDTH },
8999  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_37_CHECKER_TYPE,
9000  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_37_WIDTH },
9001  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_38_CHECKER_TYPE,
9002  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_38_WIDTH },
9003  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_39_CHECKER_TYPE,
9004  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_39_WIDTH },
9005  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_40_CHECKER_TYPE,
9006  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_40_WIDTH },
9007  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_41_CHECKER_TYPE,
9008  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_41_WIDTH },
9009  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_42_CHECKER_TYPE,
9010  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_42_WIDTH },
9011  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_43_CHECKER_TYPE,
9012  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_43_WIDTH },
9013  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_44_CHECKER_TYPE,
9014  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_44_WIDTH },
9015  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_45_CHECKER_TYPE,
9016  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_45_WIDTH },
9017  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_46_CHECKER_TYPE,
9018  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_46_WIDTH },
9019  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_47_CHECKER_TYPE,
9020  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_47_WIDTH },
9021  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_48_CHECKER_TYPE,
9022  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_48_WIDTH },
9023  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_49_CHECKER_TYPE,
9024  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_49_WIDTH },
9025  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_50_CHECKER_TYPE,
9026  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_50_WIDTH },
9027  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_51_CHECKER_TYPE,
9028  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_51_WIDTH },
9029  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_52_CHECKER_TYPE,
9030  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_52_WIDTH },
9031  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_53_CHECKER_TYPE,
9032  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_53_WIDTH },
9033  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_54_CHECKER_TYPE,
9034  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_54_WIDTH },
9035  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_55_CHECKER_TYPE,
9036  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_55_WIDTH },
9037  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_56_CHECKER_TYPE,
9038  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_56_WIDTH },
9039  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_57_CHECKER_TYPE,
9040  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_57_WIDTH },
9041  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_58_CHECKER_TYPE,
9042  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_58_WIDTH },
9043  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_59_CHECKER_TYPE,
9044  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_59_WIDTH },
9045  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_60_CHECKER_TYPE,
9046  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_60_WIDTH },
9047  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_61_CHECKER_TYPE,
9048  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_61_WIDTH },
9049  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_62_CHECKER_TYPE,
9050  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_62_WIDTH },
9051  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_63_CHECKER_TYPE,
9052  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_63_WIDTH },
9053  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_64_CHECKER_TYPE,
9054  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_64_WIDTH },
9055  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_65_CHECKER_TYPE,
9056  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_65_WIDTH },
9057  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_66_CHECKER_TYPE,
9058  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_66_WIDTH },
9059  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_67_CHECKER_TYPE,
9060  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_67_WIDTH },
9061  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_68_CHECKER_TYPE,
9062  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_68_WIDTH },
9063  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_69_CHECKER_TYPE,
9064  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_69_WIDTH },
9065  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_70_CHECKER_TYPE,
9066  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_70_WIDTH },
9067  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_71_CHECKER_TYPE,
9068  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_71_WIDTH },
9069  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_72_CHECKER_TYPE,
9070  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_72_WIDTH },
9071  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_73_CHECKER_TYPE,
9072  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_73_WIDTH },
9073  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_74_CHECKER_TYPE,
9074  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_74_WIDTH },
9075  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_75_CHECKER_TYPE,
9076  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_75_WIDTH },
9077  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_76_CHECKER_TYPE,
9078  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_76_WIDTH },
9079  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_77_CHECKER_TYPE,
9080  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_77_WIDTH },
9081  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_78_CHECKER_TYPE,
9082  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_78_WIDTH },
9083  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_79_CHECKER_TYPE,
9084  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_79_WIDTH },
9085  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_80_CHECKER_TYPE,
9086  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_80_WIDTH },
9087  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_81_CHECKER_TYPE,
9088  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_81_WIDTH },
9089  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_82_CHECKER_TYPE,
9090  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_82_WIDTH },
9091  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_83_CHECKER_TYPE,
9092  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_83_WIDTH },
9093  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_84_CHECKER_TYPE,
9094  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_84_WIDTH },
9095  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_85_CHECKER_TYPE,
9096  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_85_WIDTH },
9097  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_86_CHECKER_TYPE,
9098  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_86_WIDTH },
9099  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_87_CHECKER_TYPE,
9100  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_87_WIDTH },
9101  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_88_CHECKER_TYPE,
9102  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_88_WIDTH },
9103  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_89_CHECKER_TYPE,
9104  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_89_WIDTH },
9105  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_90_CHECKER_TYPE,
9106  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_90_WIDTH },
9107  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_91_CHECKER_TYPE,
9108  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_91_WIDTH },
9109  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_92_CHECKER_TYPE,
9110  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_92_WIDTH },
9111  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_93_CHECKER_TYPE,
9112  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_93_WIDTH },
9113  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_94_CHECKER_TYPE,
9114  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_94_WIDTH },
9115  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_95_CHECKER_TYPE,
9116  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_95_WIDTH },
9117  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_96_CHECKER_TYPE,
9118  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_96_WIDTH },
9119  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_97_CHECKER_TYPE,
9120  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_97_WIDTH },
9121  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_98_CHECKER_TYPE,
9122  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_98_WIDTH },
9123  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_99_CHECKER_TYPE,
9124  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_99_WIDTH },
9125  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_100_CHECKER_TYPE,
9126  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_100_WIDTH },
9127 };
9128 
9134 static const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_groupEntries[SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_MAX_NUM_CHECKERS] =
9135 {
9136  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
9137  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_0_WIDTH },
9138  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
9139  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_1_WIDTH },
9140  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
9141  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_2_WIDTH },
9142  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
9143  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_3_WIDTH },
9144  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
9145  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_4_WIDTH },
9146  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
9147  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_5_WIDTH },
9148  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
9149  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_6_WIDTH },
9150  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
9151  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_7_WIDTH },
9152  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
9153  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_8_WIDTH },
9154  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
9155  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_9_WIDTH },
9156  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
9157  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_10_WIDTH },
9158  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
9159  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_11_WIDTH },
9160  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
9161  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_12_WIDTH },
9162  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
9163  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_13_WIDTH },
9164  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
9165  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_14_WIDTH },
9166  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
9167  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_15_WIDTH },
9168  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
9169  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_16_WIDTH },
9170  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
9171  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_17_WIDTH },
9172  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
9173  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_18_WIDTH },
9174  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
9175  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_19_WIDTH },
9176  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
9177  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_20_WIDTH },
9178  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
9179  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_21_WIDTH },
9180  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
9181  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_22_WIDTH },
9182  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
9183  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_23_WIDTH },
9184  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
9185  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_24_WIDTH },
9186  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
9187  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_25_WIDTH },
9188  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
9189  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_26_WIDTH },
9190  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
9191  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_27_WIDTH },
9192  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
9193  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_28_WIDTH },
9194  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
9195  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_29_WIDTH },
9196  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
9197  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_30_WIDTH },
9198  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
9199  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_31_WIDTH },
9200  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
9201  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_32_WIDTH },
9202  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_33_CHECKER_TYPE,
9203  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_33_WIDTH },
9204  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_34_CHECKER_TYPE,
9205  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_34_WIDTH },
9206  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_35_CHECKER_TYPE,
9207  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_35_WIDTH },
9208  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_36_CHECKER_TYPE,
9209  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_36_WIDTH },
9210  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_37_CHECKER_TYPE,
9211  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_37_WIDTH },
9212  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_38_CHECKER_TYPE,
9213  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_38_WIDTH },
9214  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_39_CHECKER_TYPE,
9215  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_39_WIDTH },
9216  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_40_CHECKER_TYPE,
9217  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_40_WIDTH },
9218  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_41_CHECKER_TYPE,
9219  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_41_WIDTH },
9220  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_42_CHECKER_TYPE,
9221  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_42_WIDTH },
9222  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_43_CHECKER_TYPE,
9223  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_43_WIDTH },
9224  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_44_CHECKER_TYPE,
9225  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_44_WIDTH },
9226  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_45_CHECKER_TYPE,
9227  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_45_WIDTH },
9228  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_46_CHECKER_TYPE,
9229  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_46_WIDTH },
9230  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_47_CHECKER_TYPE,
9231  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_47_WIDTH },
9232  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_48_CHECKER_TYPE,
9233  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_48_WIDTH },
9234  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_49_CHECKER_TYPE,
9235  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_49_WIDTH },
9236  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_50_CHECKER_TYPE,
9237  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_50_WIDTH },
9238  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_51_CHECKER_TYPE,
9239  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_51_WIDTH },
9240  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_52_CHECKER_TYPE,
9241  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_52_WIDTH },
9242  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_53_CHECKER_TYPE,
9243  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_53_WIDTH },
9244  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_54_CHECKER_TYPE,
9245  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_54_WIDTH },
9246  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_55_CHECKER_TYPE,
9247  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_55_WIDTH },
9248  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_56_CHECKER_TYPE,
9249  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_56_WIDTH },
9250  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_57_CHECKER_TYPE,
9251  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_57_WIDTH },
9252  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_58_CHECKER_TYPE,
9253  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_58_WIDTH },
9254  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_59_CHECKER_TYPE,
9255  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_59_WIDTH },
9256  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_60_CHECKER_TYPE,
9257  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_60_WIDTH },
9258  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_61_CHECKER_TYPE,
9259  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_61_WIDTH },
9260  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_62_CHECKER_TYPE,
9261  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_62_WIDTH },
9262  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_63_CHECKER_TYPE,
9263  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_63_WIDTH },
9264  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_64_CHECKER_TYPE,
9265  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_64_WIDTH },
9266  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_65_CHECKER_TYPE,
9267  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_65_WIDTH },
9268  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_66_CHECKER_TYPE,
9269  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_66_WIDTH },
9270  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_67_CHECKER_TYPE,
9271  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_67_WIDTH },
9272  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_68_CHECKER_TYPE,
9273  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_68_WIDTH },
9274  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_69_CHECKER_TYPE,
9275  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_69_WIDTH },
9276  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_70_CHECKER_TYPE,
9277  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_70_WIDTH },
9278  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_71_CHECKER_TYPE,
9279  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_71_WIDTH },
9280  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_72_CHECKER_TYPE,
9281  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_72_WIDTH },
9282  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_73_CHECKER_TYPE,
9283  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_73_WIDTH },
9284  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_74_CHECKER_TYPE,
9285  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_74_WIDTH },
9286  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_75_CHECKER_TYPE,
9287  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_75_WIDTH },
9288  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_76_CHECKER_TYPE,
9289  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_76_WIDTH },
9290  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_77_CHECKER_TYPE,
9291  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_77_WIDTH },
9292  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_78_CHECKER_TYPE,
9293  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_78_WIDTH },
9294  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_79_CHECKER_TYPE,
9295  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_79_WIDTH },
9296  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_80_CHECKER_TYPE,
9297  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_80_WIDTH },
9298  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_81_CHECKER_TYPE,
9299  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_81_WIDTH },
9300  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_82_CHECKER_TYPE,
9301  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_82_WIDTH },
9302  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_83_CHECKER_TYPE,
9303  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_83_WIDTH },
9304  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_84_CHECKER_TYPE,
9305  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_84_WIDTH },
9306  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_85_CHECKER_TYPE,
9307  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_85_WIDTH },
9308  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_86_CHECKER_TYPE,
9309  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_86_WIDTH },
9310  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_87_CHECKER_TYPE,
9311  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_87_WIDTH },
9312  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_88_CHECKER_TYPE,
9313  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_88_WIDTH },
9314  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_89_CHECKER_TYPE,
9315  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_89_WIDTH },
9316  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_90_CHECKER_TYPE,
9317  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_90_WIDTH },
9318  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_91_CHECKER_TYPE,
9319  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_91_WIDTH },
9320  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_92_CHECKER_TYPE,
9321  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_92_WIDTH },
9322  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_93_CHECKER_TYPE,
9323  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_93_WIDTH },
9324  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_94_CHECKER_TYPE,
9325  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_94_WIDTH },
9326  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_95_CHECKER_TYPE,
9327  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_95_WIDTH },
9328  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_96_CHECKER_TYPE,
9329  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_96_WIDTH },
9330  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_97_CHECKER_TYPE,
9331  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_97_WIDTH },
9332  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_98_CHECKER_TYPE,
9333  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_98_WIDTH },
9334  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_99_CHECKER_TYPE,
9335  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_99_WIDTH },
9336  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_100_CHECKER_TYPE,
9337  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_100_WIDTH },
9338 };
9339 
9345 static const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_groupEntries[SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_MAX_NUM_CHECKERS] =
9346 {
9347  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
9348  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_0_WIDTH },
9349  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
9350  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_1_WIDTH },
9351  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
9352  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_2_WIDTH },
9353  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
9354  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_3_WIDTH },
9355  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
9356  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_4_WIDTH },
9357  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
9358  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_5_WIDTH },
9359  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
9360  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_6_WIDTH },
9361  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
9362  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_7_WIDTH },
9363  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
9364  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_8_WIDTH },
9365  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
9366  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_9_WIDTH },
9367  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
9368  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_10_WIDTH },
9369  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
9370  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_11_WIDTH },
9371  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
9372  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_12_WIDTH },
9373  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
9374  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_13_WIDTH },
9375  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
9376  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_14_WIDTH },
9377  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
9378  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_15_WIDTH },
9379  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
9380  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_16_WIDTH },
9381  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
9382  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_17_WIDTH },
9383  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
9384  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_18_WIDTH },
9385  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
9386  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_19_WIDTH },
9387  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
9388  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_20_WIDTH },
9389  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
9390  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_21_WIDTH },
9391  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
9392  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_22_WIDTH },
9393  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
9394  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_23_WIDTH },
9395  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
9396  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_24_WIDTH },
9397  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
9398  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_25_WIDTH },
9399  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
9400  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_26_WIDTH },
9401  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
9402  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_27_WIDTH },
9403  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
9404  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_28_WIDTH },
9405  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
9406  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_29_WIDTH },
9407  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
9408  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_30_WIDTH },
9409  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
9410  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_31_WIDTH },
9411  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
9412  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_32_WIDTH },
9413  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_33_CHECKER_TYPE,
9414  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_33_WIDTH },
9415  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_34_CHECKER_TYPE,
9416  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_34_WIDTH },
9417 };
9418 
9424 static const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_groupEntries[SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_MAX_NUM_CHECKERS] =
9425 {
9426  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
9427  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_0_WIDTH },
9428  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
9429  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_1_WIDTH },
9430  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
9431  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_2_WIDTH },
9432  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
9433  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_3_WIDTH },
9434  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
9435  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_4_WIDTH },
9436  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
9437  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_5_WIDTH },
9438  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
9439  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_6_WIDTH },
9440  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
9441  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_7_WIDTH },
9442  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
9443  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_8_WIDTH },
9444  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
9445  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_9_WIDTH },
9446  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
9447  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_10_WIDTH },
9448  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
9449  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_11_WIDTH },
9450  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
9451  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_12_WIDTH },
9452  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
9453  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_13_WIDTH },
9454  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
9455  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_14_WIDTH },
9456  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
9457  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_15_WIDTH },
9458  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
9459  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_16_WIDTH },
9460  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
9461  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_17_WIDTH },
9462  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
9463  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_18_WIDTH },
9464  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
9465  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_19_WIDTH },
9466  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
9467  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_20_WIDTH },
9468  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
9469  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_21_WIDTH },
9470  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
9471  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_22_WIDTH },
9472  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
9473  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_23_WIDTH },
9474  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
9475  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_24_WIDTH },
9476  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
9477  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_25_WIDTH },
9478  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
9479  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_26_WIDTH },
9480  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
9481  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_27_WIDTH },
9482  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
9483  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_28_WIDTH },
9484  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
9485  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_29_WIDTH },
9486  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
9487  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_30_WIDTH },
9488  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
9489  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_31_WIDTH },
9490  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
9491  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_32_WIDTH },
9492  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_33_CHECKER_TYPE,
9493  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_33_WIDTH },
9494  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_34_CHECKER_TYPE,
9495  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_34_WIDTH },
9496 };
9497 
9503 static const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_groupEntries[SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_MAX_NUM_CHECKERS] =
9504 {
9505  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
9506  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_0_WIDTH },
9507  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
9508  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_1_WIDTH },
9509  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
9510  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_2_WIDTH },
9511  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
9512  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_3_WIDTH },
9513  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
9514  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_4_WIDTH },
9515  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
9516  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_5_WIDTH },
9517  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
9518  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_6_WIDTH },
9519  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
9520  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_7_WIDTH },
9521  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
9522  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_8_WIDTH },
9523  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
9524  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_9_WIDTH },
9525  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
9526  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_10_WIDTH },
9527  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
9528  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_11_WIDTH },
9529  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
9530  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_12_WIDTH },
9531  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
9532  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_13_WIDTH },
9533  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
9534  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_14_WIDTH },
9535  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
9536  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_15_WIDTH },
9537  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
9538  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_16_WIDTH },
9539  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
9540  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_17_WIDTH },
9541  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
9542  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_18_WIDTH },
9543  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
9544  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_19_WIDTH },
9545  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
9546  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_20_WIDTH },
9547  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
9548  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_21_WIDTH },
9549  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
9550  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_22_WIDTH },
9551  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
9552  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_23_WIDTH },
9553  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
9554  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_24_WIDTH },
9555  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
9556  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_25_WIDTH },
9557  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
9558  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_26_WIDTH },
9559  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
9560  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_27_WIDTH },
9561  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
9562  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_28_WIDTH },
9563  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
9564  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_29_WIDTH },
9565  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
9566  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_30_WIDTH },
9567  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
9568  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_31_WIDTH },
9569  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
9570  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_32_WIDTH },
9571  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_33_CHECKER_TYPE,
9572  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_33_WIDTH },
9573  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_34_CHECKER_TYPE,
9574  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_34_WIDTH },
9575 };
9576 
9582 static const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_INTAGGR_EVT_EDC_CTRL_0_groupEntries[SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_INTAGGR_EVT_EDC_CTRL_0_MAX_NUM_CHECKERS] =
9583 {
9584  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_INTAGGR_EVT_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
9585  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_INTAGGR_EVT_EDC_CTRL_0_GROUP_0_WIDTH },
9586  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_INTAGGR_EVT_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
9587  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_INTAGGR_EVT_EDC_CTRL_0_GROUP_1_WIDTH },
9588 };
9589 
9595 static const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_INTAGGR_CEVT_EDC_CTRL_0_groupEntries[SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_INTAGGR_CEVT_EDC_CTRL_0_MAX_NUM_CHECKERS] =
9596 {
9597  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_INTAGGR_CEVT_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
9598  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_INTAGGR_CEVT_EDC_CTRL_0_GROUP_0_WIDTH },
9599  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_INTAGGR_CEVT_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
9600  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_INTAGGR_CEVT_EDC_CTRL_0_GROUP_1_WIDTH },
9601 };
9602 
9608 static const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_INTAGGR_MEVT_IN_EDC_CTRL_0_groupEntries[SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_INTAGGR_MEVT_IN_EDC_CTRL_0_MAX_NUM_CHECKERS] =
9609 {
9610  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_INTAGGR_MEVT_IN_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
9611  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_INTAGGR_MEVT_IN_EDC_CTRL_0_GROUP_0_WIDTH },
9612  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_INTAGGR_MEVT_IN_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
9613  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_INTAGGR_MEVT_IN_EDC_CTRL_0_GROUP_1_WIDTH },
9614 };
9615 
9621 static const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_groupEntries[SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_MAX_NUM_CHECKERS] =
9622 {
9623  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
9624  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_0_WIDTH },
9625  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
9626  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_1_WIDTH },
9627  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
9628  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_2_WIDTH },
9629  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
9630  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_3_WIDTH },
9631  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
9632  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_4_WIDTH },
9633  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
9634  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_5_WIDTH },
9635  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
9636  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_6_WIDTH },
9637  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
9638  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_7_WIDTH },
9639  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
9640  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_8_WIDTH },
9641  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
9642  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_9_WIDTH },
9643  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
9644  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_10_WIDTH },
9645  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
9646  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_11_WIDTH },
9647  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
9648  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_12_WIDTH },
9649  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
9650  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_13_WIDTH },
9651  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
9652  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_14_WIDTH },
9653  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
9654  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_15_WIDTH },
9655  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
9656  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_16_WIDTH },
9657  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
9658  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_17_WIDTH },
9659  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
9660  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_18_WIDTH },
9661  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
9662  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_19_WIDTH },
9663  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
9664  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_20_WIDTH },
9665  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
9666  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_21_WIDTH },
9667  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
9668  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_22_WIDTH },
9669  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
9670  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_23_WIDTH },
9671  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
9672  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_24_WIDTH },
9673  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
9674  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_25_WIDTH },
9675  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
9676  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_26_WIDTH },
9677  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
9678  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_27_WIDTH },
9679  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
9680  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_28_WIDTH },
9681  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
9682  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_29_WIDTH },
9683  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
9684  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_30_WIDTH },
9685  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
9686  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_31_WIDTH },
9687  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
9688  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_32_WIDTH },
9689  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_33_CHECKER_TYPE,
9690  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_33_WIDTH },
9691  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_34_CHECKER_TYPE,
9692  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_34_WIDTH },
9693 };
9694 
9700 static const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CFG_EDC_CTRL_0_groupEntries[SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CFG_EDC_CTRL_0_MAX_NUM_CHECKERS] =
9701 {
9702  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CFG_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
9703  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CFG_EDC_CTRL_0_GROUP_0_WIDTH },
9704  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CFG_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
9705  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CFG_EDC_CTRL_0_GROUP_1_WIDTH },
9706  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CFG_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
9707  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CFG_EDC_CTRL_0_GROUP_2_WIDTH },
9708 };
9709 
9715 static const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_groupEntries[SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_MAX_NUM_CHECKERS] =
9716 {
9717  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
9718  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_0_WIDTH },
9719  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
9720  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_1_WIDTH },
9721  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
9722  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_2_WIDTH },
9723  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
9724  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_3_WIDTH },
9725  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
9726  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_4_WIDTH },
9727  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
9728  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_5_WIDTH },
9729  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
9730  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_6_WIDTH },
9731  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
9732  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_7_WIDTH },
9733  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
9734  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_8_WIDTH },
9735  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
9736  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_9_WIDTH },
9737  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
9738  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_10_WIDTH },
9739  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
9740  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_11_WIDTH },
9741  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
9742  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_12_WIDTH },
9743  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
9744  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_13_WIDTH },
9745  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
9746  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_14_WIDTH },
9747  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
9748  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_15_WIDTH },
9749  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
9750  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_16_WIDTH },
9751  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
9752  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_17_WIDTH },
9753  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
9754  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_18_WIDTH },
9755  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
9756  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_19_WIDTH },
9757  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
9758  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_20_WIDTH },
9759  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
9760  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_21_WIDTH },
9761  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
9762  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_22_WIDTH },
9763  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
9764  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_23_WIDTH },
9765  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
9766  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_24_WIDTH },
9767  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
9768  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_25_WIDTH },
9769  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
9770  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_26_WIDTH },
9771  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
9772  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_27_WIDTH },
9773  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
9774  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_28_WIDTH },
9775  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
9776  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_29_WIDTH },
9777  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
9778  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_30_WIDTH },
9779  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
9780  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_31_WIDTH },
9781  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
9782  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_32_WIDTH },
9783  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_33_CHECKER_TYPE,
9784  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_33_WIDTH },
9785  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_34_CHECKER_TYPE,
9786  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_34_WIDTH },
9787  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_35_CHECKER_TYPE,
9788  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_35_WIDTH },
9789  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_36_CHECKER_TYPE,
9790  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_36_WIDTH },
9791  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_37_CHECKER_TYPE,
9792  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_37_WIDTH },
9793  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_38_CHECKER_TYPE,
9794  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_38_WIDTH },
9795  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_39_CHECKER_TYPE,
9796  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_39_WIDTH },
9797  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_40_CHECKER_TYPE,
9798  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_40_WIDTH },
9799  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_41_CHECKER_TYPE,
9800  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_41_WIDTH },
9801  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_42_CHECKER_TYPE,
9802  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_42_WIDTH },
9803  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_43_CHECKER_TYPE,
9804  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_43_WIDTH },
9805  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_44_CHECKER_TYPE,
9806  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_44_WIDTH },
9807  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_45_CHECKER_TYPE,
9808  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_45_WIDTH },
9809  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_46_CHECKER_TYPE,
9810  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_46_WIDTH },
9811  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_47_CHECKER_TYPE,
9812  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_47_WIDTH },
9813  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_48_CHECKER_TYPE,
9814  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_48_WIDTH },
9815  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_49_CHECKER_TYPE,
9816  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_49_WIDTH },
9817  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_50_CHECKER_TYPE,
9818  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_50_WIDTH },
9819  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_51_CHECKER_TYPE,
9820  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_51_WIDTH },
9821  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_52_CHECKER_TYPE,
9822  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_52_WIDTH },
9823  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_53_CHECKER_TYPE,
9824  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_53_WIDTH },
9825  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_54_CHECKER_TYPE,
9826  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_54_WIDTH },
9827  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_55_CHECKER_TYPE,
9828  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_55_WIDTH },
9829  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_56_CHECKER_TYPE,
9830  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_56_WIDTH },
9831  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_57_CHECKER_TYPE,
9832  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_57_WIDTH },
9833  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_58_CHECKER_TYPE,
9834  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_58_WIDTH },
9835  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_59_CHECKER_TYPE,
9836  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_59_WIDTH },
9837  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_60_CHECKER_TYPE,
9838  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_60_WIDTH },
9839  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_61_CHECKER_TYPE,
9840  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_61_WIDTH },
9841  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_62_CHECKER_TYPE,
9842  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_62_WIDTH },
9843  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_63_CHECKER_TYPE,
9844  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_63_WIDTH },
9845  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_64_CHECKER_TYPE,
9846  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_64_WIDTH },
9847  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_65_CHECKER_TYPE,
9848  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_65_WIDTH },
9849  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_66_CHECKER_TYPE,
9850  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_66_WIDTH },
9851  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_67_CHECKER_TYPE,
9852  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_67_WIDTH },
9853  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_68_CHECKER_TYPE,
9854  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_68_WIDTH },
9855  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_69_CHECKER_TYPE,
9856  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_69_WIDTH },
9857  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_70_CHECKER_TYPE,
9858  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_70_WIDTH },
9859  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_71_CHECKER_TYPE,
9860  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_71_WIDTH },
9861  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_72_CHECKER_TYPE,
9862  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_72_WIDTH },
9863  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_73_CHECKER_TYPE,
9864  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_73_WIDTH },
9865  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_74_CHECKER_TYPE,
9866  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_74_WIDTH },
9867  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_75_CHECKER_TYPE,
9868  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_75_WIDTH },
9869  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_76_CHECKER_TYPE,
9870  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_76_WIDTH },
9871  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_77_CHECKER_TYPE,
9872  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_77_WIDTH },
9873  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_78_CHECKER_TYPE,
9874  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_78_WIDTH },
9875  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_79_CHECKER_TYPE,
9876  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_79_WIDTH },
9877  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_80_CHECKER_TYPE,
9878  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_80_WIDTH },
9879  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_81_CHECKER_TYPE,
9880  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_81_WIDTH },
9881  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_82_CHECKER_TYPE,
9882  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_82_WIDTH },
9883  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_83_CHECKER_TYPE,
9884  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_83_WIDTH },
9885  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_84_CHECKER_TYPE,
9886  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_84_WIDTH },
9887  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_85_CHECKER_TYPE,
9888  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_85_WIDTH },
9889  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_86_CHECKER_TYPE,
9890  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_86_WIDTH },
9891  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_87_CHECKER_TYPE,
9892  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_87_WIDTH },
9893  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_88_CHECKER_TYPE,
9894  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_88_WIDTH },
9895  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_89_CHECKER_TYPE,
9896  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_89_WIDTH },
9897  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_90_CHECKER_TYPE,
9898  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_90_WIDTH },
9899  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_91_CHECKER_TYPE,
9900  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_91_WIDTH },
9901  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_92_CHECKER_TYPE,
9902  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_92_WIDTH },
9903  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_93_CHECKER_TYPE,
9904  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_93_WIDTH },
9905  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_94_CHECKER_TYPE,
9906  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_94_WIDTH },
9907  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_95_CHECKER_TYPE,
9908  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_95_WIDTH },
9909  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_96_CHECKER_TYPE,
9910  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_96_WIDTH },
9911  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_97_CHECKER_TYPE,
9912  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_97_WIDTH },
9913  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_98_CHECKER_TYPE,
9914  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_98_WIDTH },
9915  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_99_CHECKER_TYPE,
9916  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_99_WIDTH },
9917  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_100_CHECKER_TYPE,
9918  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_100_WIDTH },
9919  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_101_CHECKER_TYPE,
9920  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_101_WIDTH },
9921  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_102_CHECKER_TYPE,
9922  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_102_WIDTH },
9923  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_103_CHECKER_TYPE,
9924  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_103_WIDTH },
9925  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_104_CHECKER_TYPE,
9926  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_104_WIDTH },
9927  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_105_CHECKER_TYPE,
9928  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_105_WIDTH },
9929 };
9930 
9936 static const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_groupEntries[SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_MAX_NUM_CHECKERS] =
9937 {
9938  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
9939  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_0_WIDTH },
9940  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
9941  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_1_WIDTH },
9942  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
9943  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_2_WIDTH },
9944  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
9945  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_3_WIDTH },
9946  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
9947  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_4_WIDTH },
9948  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
9949  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_5_WIDTH },
9950  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
9951  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_6_WIDTH },
9952  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
9953  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_7_WIDTH },
9954  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
9955  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_8_WIDTH },
9956  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
9957  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_9_WIDTH },
9958  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
9959  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_10_WIDTH },
9960  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
9961  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_11_WIDTH },
9962  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
9963  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_12_WIDTH },
9964  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
9965  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_13_WIDTH },
9966  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
9967  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_14_WIDTH },
9968  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
9969  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_15_WIDTH },
9970  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
9971  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_16_WIDTH },
9972  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
9973  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_17_WIDTH },
9974  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
9975  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_18_WIDTH },
9976  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
9977  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_19_WIDTH },
9978  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
9979  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_20_WIDTH },
9980  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
9981  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_21_WIDTH },
9982  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
9983  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_22_WIDTH },
9984  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
9985  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_23_WIDTH },
9986  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
9987  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_24_WIDTH },
9988  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
9989  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_25_WIDTH },
9990  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
9991  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_26_WIDTH },
9992  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
9993  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_27_WIDTH },
9994  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
9995  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_28_WIDTH },
9996  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
9997  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_29_WIDTH },
9998  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
9999  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_30_WIDTH },
10000  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
10001  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_31_WIDTH },
10002  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
10003  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_32_WIDTH },
10004  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_33_CHECKER_TYPE,
10005  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_33_WIDTH },
10006  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_34_CHECKER_TYPE,
10007  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_34_WIDTH },
10008  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_35_CHECKER_TYPE,
10009  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_35_WIDTH },
10010  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_36_CHECKER_TYPE,
10011  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_36_WIDTH },
10012  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_37_CHECKER_TYPE,
10013  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_37_WIDTH },
10014  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_38_CHECKER_TYPE,
10015  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_38_WIDTH },
10016  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_39_CHECKER_TYPE,
10017  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_39_WIDTH },
10018  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_40_CHECKER_TYPE,
10019  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_40_WIDTH },
10020  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_41_CHECKER_TYPE,
10021  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_41_WIDTH },
10022  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_42_CHECKER_TYPE,
10023  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_42_WIDTH },
10024  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_43_CHECKER_TYPE,
10025  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_43_WIDTH },
10026  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_44_CHECKER_TYPE,
10027  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_44_WIDTH },
10028  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_45_CHECKER_TYPE,
10029  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_45_WIDTH },
10030  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_46_CHECKER_TYPE,
10031  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_46_WIDTH },
10032  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_47_CHECKER_TYPE,
10033  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_47_WIDTH },
10034  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_48_CHECKER_TYPE,
10035  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_48_WIDTH },
10036  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_49_CHECKER_TYPE,
10037  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_49_WIDTH },
10038  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_50_CHECKER_TYPE,
10039  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_50_WIDTH },
10040  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_51_CHECKER_TYPE,
10041  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_51_WIDTH },
10042  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_52_CHECKER_TYPE,
10043  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_52_WIDTH },
10044  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_53_CHECKER_TYPE,
10045  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_53_WIDTH },
10046  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_54_CHECKER_TYPE,
10047  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_54_WIDTH },
10048  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_55_CHECKER_TYPE,
10049  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_55_WIDTH },
10050  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_56_CHECKER_TYPE,
10051  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_56_WIDTH },
10052  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_57_CHECKER_TYPE,
10053  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_57_WIDTH },
10054  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_58_CHECKER_TYPE,
10055  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_58_WIDTH },
10056  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_59_CHECKER_TYPE,
10057  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_59_WIDTH },
10058  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_60_CHECKER_TYPE,
10059  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_60_WIDTH },
10060  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_61_CHECKER_TYPE,
10061  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_61_WIDTH },
10062  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_62_CHECKER_TYPE,
10063  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_62_WIDTH },
10064  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_63_CHECKER_TYPE,
10065  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_63_WIDTH },
10066  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_64_CHECKER_TYPE,
10067  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_64_WIDTH },
10068  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_65_CHECKER_TYPE,
10069  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_65_WIDTH },
10070  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_66_CHECKER_TYPE,
10071  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_66_WIDTH },
10072  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_67_CHECKER_TYPE,
10073  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_67_WIDTH },
10074  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_68_CHECKER_TYPE,
10075  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_68_WIDTH },
10076  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_69_CHECKER_TYPE,
10077  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_69_WIDTH },
10078  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_70_CHECKER_TYPE,
10079  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_70_WIDTH },
10080  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_71_CHECKER_TYPE,
10081  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_71_WIDTH },
10082  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_72_CHECKER_TYPE,
10083  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_72_WIDTH },
10084  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_73_CHECKER_TYPE,
10085  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_73_WIDTH },
10086  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_74_CHECKER_TYPE,
10087  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_74_WIDTH },
10088  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_75_CHECKER_TYPE,
10089  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_75_WIDTH },
10090  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_76_CHECKER_TYPE,
10091  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_76_WIDTH },
10092  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_77_CHECKER_TYPE,
10093  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_77_WIDTH },
10094  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_78_CHECKER_TYPE,
10095  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_78_WIDTH },
10096  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_79_CHECKER_TYPE,
10097  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_79_WIDTH },
10098  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_80_CHECKER_TYPE,
10099  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_80_WIDTH },
10100  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_81_CHECKER_TYPE,
10101  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_81_WIDTH },
10102  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_82_CHECKER_TYPE,
10103  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_82_WIDTH },
10104  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_83_CHECKER_TYPE,
10105  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_83_WIDTH },
10106  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_84_CHECKER_TYPE,
10107  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_84_WIDTH },
10108  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_85_CHECKER_TYPE,
10109  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_85_WIDTH },
10110  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_86_CHECKER_TYPE,
10111  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_86_WIDTH },
10112  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_87_CHECKER_TYPE,
10113  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_87_WIDTH },
10114  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_88_CHECKER_TYPE,
10115  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_88_WIDTH },
10116  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_89_CHECKER_TYPE,
10117  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_89_WIDTH },
10118  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_90_CHECKER_TYPE,
10119  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_90_WIDTH },
10120  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_91_CHECKER_TYPE,
10121  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_91_WIDTH },
10122  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_92_CHECKER_TYPE,
10123  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_92_WIDTH },
10124  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_93_CHECKER_TYPE,
10125  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_93_WIDTH },
10126  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_94_CHECKER_TYPE,
10127  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_94_WIDTH },
10128  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_95_CHECKER_TYPE,
10129  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_95_WIDTH },
10130  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_96_CHECKER_TYPE,
10131  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_96_WIDTH },
10132  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_97_CHECKER_TYPE,
10133  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_97_WIDTH },
10134  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_98_CHECKER_TYPE,
10135  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_98_WIDTH },
10136  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_99_CHECKER_TYPE,
10137  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_99_WIDTH },
10138  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_100_CHECKER_TYPE,
10139  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_100_WIDTH },
10140  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_101_CHECKER_TYPE,
10141  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_101_WIDTH },
10142  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_102_CHECKER_TYPE,
10143  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_102_WIDTH },
10144 };
10145 
10151 static const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_groupEntries[SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_MAX_NUM_CHECKERS] =
10152 {
10153  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
10154  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_0_WIDTH },
10155  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
10156  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_1_WIDTH },
10157  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
10158  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_2_WIDTH },
10159  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
10160  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_3_WIDTH },
10161  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
10162  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_4_WIDTH },
10163  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
10164  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_5_WIDTH },
10165  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
10166  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_6_WIDTH },
10167  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
10168  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_7_WIDTH },
10169  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
10170  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_8_WIDTH },
10171  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
10172  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_9_WIDTH },
10173  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
10174  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_10_WIDTH },
10175  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
10176  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_11_WIDTH },
10177  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
10178  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_12_WIDTH },
10179  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
10180  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_13_WIDTH },
10181  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
10182  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_14_WIDTH },
10183  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
10184  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_15_WIDTH },
10185  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
10186  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_16_WIDTH },
10187  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
10188  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_17_WIDTH },
10189  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
10190  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_18_WIDTH },
10191  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
10192  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_19_WIDTH },
10193  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
10194  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_20_WIDTH },
10195  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
10196  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_21_WIDTH },
10197  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
10198  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_22_WIDTH },
10199  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
10200  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_23_WIDTH },
10201  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
10202  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_24_WIDTH },
10203  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
10204  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_25_WIDTH },
10205  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
10206  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_26_WIDTH },
10207  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
10208  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_27_WIDTH },
10209  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
10210  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_28_WIDTH },
10211  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
10212  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_29_WIDTH },
10213  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
10214  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_30_WIDTH },
10215  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
10216  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_31_WIDTH },
10217  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
10218  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_32_WIDTH },
10219  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_33_CHECKER_TYPE,
10220  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_33_WIDTH },
10221  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_34_CHECKER_TYPE,
10222  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_34_WIDTH },
10223  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_35_CHECKER_TYPE,
10224  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_35_WIDTH },
10225  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_36_CHECKER_TYPE,
10226  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_36_WIDTH },
10227  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_37_CHECKER_TYPE,
10228  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_37_WIDTH },
10229  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_38_CHECKER_TYPE,
10230  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_38_WIDTH },
10231  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_39_CHECKER_TYPE,
10232  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_39_WIDTH },
10233  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_40_CHECKER_TYPE,
10234  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_40_WIDTH },
10235  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_41_CHECKER_TYPE,
10236  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_41_WIDTH },
10237  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_42_CHECKER_TYPE,
10238  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_42_WIDTH },
10239  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_43_CHECKER_TYPE,
10240  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_43_WIDTH },
10241  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_44_CHECKER_TYPE,
10242  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_44_WIDTH },
10243  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_45_CHECKER_TYPE,
10244  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_45_WIDTH },
10245  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_46_CHECKER_TYPE,
10246  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_46_WIDTH },
10247  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_47_CHECKER_TYPE,
10248  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_47_WIDTH },
10249  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_48_CHECKER_TYPE,
10250  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_48_WIDTH },
10251  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_49_CHECKER_TYPE,
10252  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_49_WIDTH },
10253  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_50_CHECKER_TYPE,
10254  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_50_WIDTH },
10255  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_51_CHECKER_TYPE,
10256  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_51_WIDTH },
10257  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_52_CHECKER_TYPE,
10258  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_52_WIDTH },
10259  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_53_CHECKER_TYPE,
10260  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_53_WIDTH },
10261  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_54_CHECKER_TYPE,
10262  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_54_WIDTH },
10263  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_55_CHECKER_TYPE,
10264  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_55_WIDTH },
10265  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_56_CHECKER_TYPE,
10266  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_56_WIDTH },
10267  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_57_CHECKER_TYPE,
10268  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_57_WIDTH },
10269  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_58_CHECKER_TYPE,
10270  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_58_WIDTH },
10271  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_59_CHECKER_TYPE,
10272  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_59_WIDTH },
10273  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_60_CHECKER_TYPE,
10274  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_60_WIDTH },
10275  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_61_CHECKER_TYPE,
10276  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_61_WIDTH },
10277  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_62_CHECKER_TYPE,
10278  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_62_WIDTH },
10279  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_63_CHECKER_TYPE,
10280  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_63_WIDTH },
10281  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_64_CHECKER_TYPE,
10282  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_64_WIDTH },
10283  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_65_CHECKER_TYPE,
10284  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_65_WIDTH },
10285  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_66_CHECKER_TYPE,
10286  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_66_WIDTH },
10287  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_67_CHECKER_TYPE,
10288  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_67_WIDTH },
10289  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_68_CHECKER_TYPE,
10290  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_68_WIDTH },
10291  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_69_CHECKER_TYPE,
10292  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_69_WIDTH },
10293  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_70_CHECKER_TYPE,
10294  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_70_WIDTH },
10295  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_71_CHECKER_TYPE,
10296  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_71_WIDTH },
10297  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_72_CHECKER_TYPE,
10298  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_72_WIDTH },
10299  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_73_CHECKER_TYPE,
10300  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_73_WIDTH },
10301  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_74_CHECKER_TYPE,
10302  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_74_WIDTH },
10303  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_75_CHECKER_TYPE,
10304  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_75_WIDTH },
10305  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_76_CHECKER_TYPE,
10306  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_76_WIDTH },
10307  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_77_CHECKER_TYPE,
10308  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_77_WIDTH },
10309  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_78_CHECKER_TYPE,
10310  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_78_WIDTH },
10311  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_79_CHECKER_TYPE,
10312  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_79_WIDTH },
10313  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_80_CHECKER_TYPE,
10314  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_80_WIDTH },
10315  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_81_CHECKER_TYPE,
10316  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_81_WIDTH },
10317  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_82_CHECKER_TYPE,
10318  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_82_WIDTH },
10319  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_83_CHECKER_TYPE,
10320  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_83_WIDTH },
10321  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_84_CHECKER_TYPE,
10322  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_84_WIDTH },
10323  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_85_CHECKER_TYPE,
10324  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_85_WIDTH },
10325  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_86_CHECKER_TYPE,
10326  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_86_WIDTH },
10327  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_87_CHECKER_TYPE,
10328  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_87_WIDTH },
10329  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_88_CHECKER_TYPE,
10330  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_88_WIDTH },
10331  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_89_CHECKER_TYPE,
10332  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_89_WIDTH },
10333  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_90_CHECKER_TYPE,
10334  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_90_WIDTH },
10335  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_91_CHECKER_TYPE,
10336  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_91_WIDTH },
10337  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_92_CHECKER_TYPE,
10338  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_92_WIDTH },
10339  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_93_CHECKER_TYPE,
10340  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_93_WIDTH },
10341  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_94_CHECKER_TYPE,
10342  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_94_WIDTH },
10343  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_95_CHECKER_TYPE,
10344  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_95_WIDTH },
10345  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_96_CHECKER_TYPE,
10346  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_96_WIDTH },
10347  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_97_CHECKER_TYPE,
10348  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_97_WIDTH },
10349  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_98_CHECKER_TYPE,
10350  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_98_WIDTH },
10351  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_99_CHECKER_TYPE,
10352  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_99_WIDTH },
10353  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_100_CHECKER_TYPE,
10354  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_100_WIDTH },
10355  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_101_CHECKER_TYPE,
10356  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_101_WIDTH },
10357  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_102_CHECKER_TYPE,
10358  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_102_WIDTH },
10359  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_103_CHECKER_TYPE,
10360  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_103_WIDTH },
10361  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_104_CHECKER_TYPE,
10362  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_104_WIDTH },
10363  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_105_CHECKER_TYPE,
10364  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_105_WIDTH },
10365  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_106_CHECKER_TYPE,
10366  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_106_WIDTH },
10367  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_107_CHECKER_TYPE,
10368  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_107_WIDTH },
10369  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_108_CHECKER_TYPE,
10370  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_108_WIDTH },
10371  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_109_CHECKER_TYPE,
10372  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_109_WIDTH },
10373  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_110_CHECKER_TYPE,
10374  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_110_WIDTH },
10375  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_111_CHECKER_TYPE,
10376  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_111_WIDTH },
10377  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_112_CHECKER_TYPE,
10378  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_112_WIDTH },
10379  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_113_CHECKER_TYPE,
10380  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_113_WIDTH },
10381  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_114_CHECKER_TYPE,
10382  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_114_WIDTH },
10383  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_115_CHECKER_TYPE,
10384  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_115_WIDTH },
10385  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_116_CHECKER_TYPE,
10386  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_116_WIDTH },
10387  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_117_CHECKER_TYPE,
10388  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_117_WIDTH },
10389  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_118_CHECKER_TYPE,
10390  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_118_WIDTH },
10391  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_119_CHECKER_TYPE,
10392  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_119_WIDTH },
10393  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_120_CHECKER_TYPE,
10394  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_120_WIDTH },
10395  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_121_CHECKER_TYPE,
10396  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_121_WIDTH },
10397  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_122_CHECKER_TYPE,
10398  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_122_WIDTH },
10399  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_123_CHECKER_TYPE,
10400  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_123_WIDTH },
10401  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_124_CHECKER_TYPE,
10402  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_124_WIDTH },
10403  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_125_CHECKER_TYPE,
10404  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_125_WIDTH },
10405  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_126_CHECKER_TYPE,
10406  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_126_WIDTH },
10407  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_127_CHECKER_TYPE,
10408  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_127_WIDTH },
10409  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_128_CHECKER_TYPE,
10410  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_128_WIDTH },
10411  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_129_CHECKER_TYPE,
10412  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_129_WIDTH },
10413  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_130_CHECKER_TYPE,
10414  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_130_WIDTH },
10415 };
10416 
10422 static const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_VD2GCLK_EDC_CTRL_0_groupEntries[SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_VD2GCLK_EDC_CTRL_0_MAX_NUM_CHECKERS] =
10423 {
10424  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_VD2GCLK_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
10425  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_VD2GCLK_EDC_CTRL_0_GROUP_0_WIDTH },
10426  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_VD2GCLK_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
10427  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_VD2GCLK_EDC_CTRL_0_GROUP_1_WIDTH },
10428  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_VD2GCLK_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
10429  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_VD2GCLK_EDC_CTRL_0_GROUP_2_WIDTH },
10430  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_VD2GCLK_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
10431  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_VD2GCLK_EDC_CTRL_0_GROUP_3_WIDTH },
10432  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_VD2GCLK_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
10433  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_VD2GCLK_EDC_CTRL_0_GROUP_4_WIDTH },
10434  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_VD2GCLK_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
10435  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_VD2GCLK_EDC_CTRL_0_GROUP_5_WIDTH },
10436  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_VD2GCLK_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
10437  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_VD2GCLK_EDC_CTRL_0_GROUP_6_WIDTH },
10438  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_VD2GCLK_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
10439  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_VD2GCLK_EDC_CTRL_0_GROUP_7_WIDTH },
10440  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_VD2GCLK_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
10441  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_VD2GCLK_EDC_CTRL_0_GROUP_8_WIDTH },
10442  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_VD2GCLK_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
10443  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_VD2GCLK_EDC_CTRL_0_GROUP_9_WIDTH },
10444 };
10445 
10451 static const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_DMSS_CFG_P2P_BRIDGE_EDC_CTRL_0_groupEntries[SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_DMSS_CFG_P2P_BRIDGE_EDC_CTRL_0_MAX_NUM_CHECKERS] =
10452 {
10453  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_DMSS_CFG_P2P_BRIDGE_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
10454  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_DMSS_CFG_P2P_BRIDGE_EDC_CTRL_0_GROUP_0_WIDTH },
10455  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_DMSS_CFG_P2P_BRIDGE_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
10456  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_DMSS_CFG_P2P_BRIDGE_EDC_CTRL_0_GROUP_1_WIDTH },
10457  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_DMSS_CFG_P2P_BRIDGE_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
10458  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_DMSS_CFG_P2P_BRIDGE_EDC_CTRL_0_GROUP_2_WIDTH },
10459  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_DMSS_CFG_P2P_BRIDGE_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
10460  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_DMSS_CFG_P2P_BRIDGE_EDC_CTRL_0_GROUP_3_WIDTH },
10461  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_DMSS_CFG_P2P_BRIDGE_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
10462  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_DMSS_CFG_P2P_BRIDGE_EDC_CTRL_0_GROUP_4_WIDTH },
10463  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_DMSS_CFG_P2P_BRIDGE_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
10464  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_DMSS_CFG_P2P_BRIDGE_EDC_CTRL_0_GROUP_5_WIDTH },
10465  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_DMSS_CFG_P2P_BRIDGE_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
10466  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_DMSS_CFG_P2P_BRIDGE_EDC_CTRL_0_GROUP_6_WIDTH },
10467 };
10468 
10474 static const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_groupEntries[SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_MAX_NUM_CHECKERS] =
10475 {
10476  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
10477  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_0_WIDTH },
10478  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
10479  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_1_WIDTH },
10480  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
10481  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_2_WIDTH },
10482  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
10483  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_3_WIDTH },
10484  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
10485  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_4_WIDTH },
10486  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
10487  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_5_WIDTH },
10488  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
10489  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_6_WIDTH },
10490  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
10491  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_7_WIDTH },
10492  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
10493  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_8_WIDTH },
10494  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
10495  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_9_WIDTH },
10496  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
10497  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_10_WIDTH },
10498  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
10499  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_11_WIDTH },
10500  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
10501  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_12_WIDTH },
10502  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
10503  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_13_WIDTH },
10504  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
10505  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_14_WIDTH },
10506  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
10507  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_15_WIDTH },
10508  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
10509  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_16_WIDTH },
10510  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
10511  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_17_WIDTH },
10512  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
10513  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_18_WIDTH },
10514  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
10515  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_19_WIDTH },
10516  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
10517  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_20_WIDTH },
10518  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
10519  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_21_WIDTH },
10520  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
10521  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_22_WIDTH },
10522  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
10523  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_23_WIDTH },
10524  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
10525  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_24_WIDTH },
10526  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
10527  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_25_WIDTH },
10528  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
10529  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_26_WIDTH },
10530  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
10531  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_27_WIDTH },
10532  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
10533  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_28_WIDTH },
10534  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
10535  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_29_WIDTH },
10536  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
10537  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_30_WIDTH },
10538  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
10539  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_31_WIDTH },
10540  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
10541  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_32_WIDTH },
10542  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_33_CHECKER_TYPE,
10543  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_33_WIDTH },
10544  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_34_CHECKER_TYPE,
10545  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_34_WIDTH },
10546  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_35_CHECKER_TYPE,
10547  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_35_WIDTH },
10548  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_36_CHECKER_TYPE,
10549  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_36_WIDTH },
10550  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_37_CHECKER_TYPE,
10551  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_37_WIDTH },
10552  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_38_CHECKER_TYPE,
10553  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_38_WIDTH },
10554  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_39_CHECKER_TYPE,
10555  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_39_WIDTH },
10556  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_40_CHECKER_TYPE,
10557  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_40_WIDTH },
10558  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_41_CHECKER_TYPE,
10559  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_41_WIDTH },
10560  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_42_CHECKER_TYPE,
10561  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_42_WIDTH },
10562  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_43_CHECKER_TYPE,
10563  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_43_WIDTH },
10564  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_44_CHECKER_TYPE,
10565  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_44_WIDTH },
10566  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_45_CHECKER_TYPE,
10567  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_45_WIDTH },
10568  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_46_CHECKER_TYPE,
10569  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_46_WIDTH },
10570  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_47_CHECKER_TYPE,
10571  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_47_WIDTH },
10572  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_48_CHECKER_TYPE,
10573  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_48_WIDTH },
10574  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_49_CHECKER_TYPE,
10575  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_49_WIDTH },
10576  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_50_CHECKER_TYPE,
10577  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_50_WIDTH },
10578  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_51_CHECKER_TYPE,
10579  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_51_WIDTH },
10580  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_52_CHECKER_TYPE,
10581  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_52_WIDTH },
10582  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_53_CHECKER_TYPE,
10583  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_53_WIDTH },
10584  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_54_CHECKER_TYPE,
10585  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_54_WIDTH },
10586  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_55_CHECKER_TYPE,
10587  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_55_WIDTH },
10588  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_56_CHECKER_TYPE,
10589  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_56_WIDTH },
10590  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_57_CHECKER_TYPE,
10591  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_57_WIDTH },
10592  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_58_CHECKER_TYPE,
10593  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_58_WIDTH },
10594  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_59_CHECKER_TYPE,
10595  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_59_WIDTH },
10596  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_60_CHECKER_TYPE,
10597  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_60_WIDTH },
10598  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_61_CHECKER_TYPE,
10599  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_61_WIDTH },
10600  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_62_CHECKER_TYPE,
10601  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_62_WIDTH },
10602  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_63_CHECKER_TYPE,
10603  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_63_WIDTH },
10604  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_64_CHECKER_TYPE,
10605  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_64_WIDTH },
10606  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_65_CHECKER_TYPE,
10607  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_65_WIDTH },
10608  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_66_CHECKER_TYPE,
10609  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_66_WIDTH },
10610  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_67_CHECKER_TYPE,
10611  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_67_WIDTH },
10612  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_68_CHECKER_TYPE,
10613  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_68_WIDTH },
10614  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_69_CHECKER_TYPE,
10615  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_69_WIDTH },
10616  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_70_CHECKER_TYPE,
10617  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_70_WIDTH },
10618  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_71_CHECKER_TYPE,
10619  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_71_WIDTH },
10620  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_72_CHECKER_TYPE,
10621  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_72_WIDTH },
10622  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_73_CHECKER_TYPE,
10623  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_73_WIDTH },
10624  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_74_CHECKER_TYPE,
10625  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_74_WIDTH },
10626  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_75_CHECKER_TYPE,
10627  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_75_WIDTH },
10628  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_76_CHECKER_TYPE,
10629  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_76_WIDTH },
10630  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_77_CHECKER_TYPE,
10631  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_77_WIDTH },
10632  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_78_CHECKER_TYPE,
10633  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_78_WIDTH },
10634  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_79_CHECKER_TYPE,
10635  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_79_WIDTH },
10636  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_80_CHECKER_TYPE,
10637  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_80_WIDTH },
10638  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_81_CHECKER_TYPE,
10639  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_81_WIDTH },
10640  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_82_CHECKER_TYPE,
10641  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_82_WIDTH },
10642  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_83_CHECKER_TYPE,
10643  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_83_WIDTH },
10644  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_84_CHECKER_TYPE,
10645  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_84_WIDTH },
10646  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_85_CHECKER_TYPE,
10647  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_85_WIDTH },
10648  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_86_CHECKER_TYPE,
10649  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_86_WIDTH },
10650  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_87_CHECKER_TYPE,
10651  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_87_WIDTH },
10652  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_88_CHECKER_TYPE,
10653  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_88_WIDTH },
10654  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_89_CHECKER_TYPE,
10655  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_89_WIDTH },
10656  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_90_CHECKER_TYPE,
10657  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_90_WIDTH },
10658 };
10659 
10665 static const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_groupEntries[SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_MAX_NUM_CHECKERS] =
10666 {
10667  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
10668  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_0_WIDTH },
10669  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
10670  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_1_WIDTH },
10671  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
10672  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_2_WIDTH },
10673  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
10674  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_3_WIDTH },
10675  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
10676  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_4_WIDTH },
10677  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
10678  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_5_WIDTH },
10679  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
10680  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_6_WIDTH },
10681  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
10682  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_7_WIDTH },
10683  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
10684  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_8_WIDTH },
10685  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
10686  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_9_WIDTH },
10687  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
10688  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_10_WIDTH },
10689  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
10690  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_11_WIDTH },
10691  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
10692  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_12_WIDTH },
10693  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
10694  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_13_WIDTH },
10695  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
10696  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_14_WIDTH },
10697  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
10698  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_15_WIDTH },
10699  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
10700  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_16_WIDTH },
10701  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
10702  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_17_WIDTH },
10703  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
10704  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_18_WIDTH },
10705  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
10706  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_19_WIDTH },
10707  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
10708  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_20_WIDTH },
10709  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
10710  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_21_WIDTH },
10711  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
10712  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_22_WIDTH },
10713  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
10714  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_23_WIDTH },
10715  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
10716  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_24_WIDTH },
10717  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
10718  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_25_WIDTH },
10719  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
10720  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_26_WIDTH },
10721  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
10722  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_27_WIDTH },
10723  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
10724  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_28_WIDTH },
10725  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
10726  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_29_WIDTH },
10727  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
10728  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_30_WIDTH },
10729  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
10730  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_31_WIDTH },
10731  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
10732  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_32_WIDTH },
10733  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_33_CHECKER_TYPE,
10734  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_33_WIDTH },
10735  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_34_CHECKER_TYPE,
10736  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_34_WIDTH },
10737  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_35_CHECKER_TYPE,
10738  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_35_WIDTH },
10739  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_36_CHECKER_TYPE,
10740  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_36_WIDTH },
10741  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_37_CHECKER_TYPE,
10742  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_37_WIDTH },
10743  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_38_CHECKER_TYPE,
10744  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_38_WIDTH },
10745  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_39_CHECKER_TYPE,
10746  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_39_WIDTH },
10747  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_40_CHECKER_TYPE,
10748  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_40_WIDTH },
10749  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_41_CHECKER_TYPE,
10750  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_41_WIDTH },
10751  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_42_CHECKER_TYPE,
10752  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_42_WIDTH },
10753  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_43_CHECKER_TYPE,
10754  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_43_WIDTH },
10755  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_44_CHECKER_TYPE,
10756  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_44_WIDTH },
10757  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_45_CHECKER_TYPE,
10758  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_45_WIDTH },
10759  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_46_CHECKER_TYPE,
10760  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_46_WIDTH },
10761  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_47_CHECKER_TYPE,
10762  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_47_WIDTH },
10763  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_48_CHECKER_TYPE,
10764  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_48_WIDTH },
10765  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_49_CHECKER_TYPE,
10766  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_49_WIDTH },
10767  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_50_CHECKER_TYPE,
10768  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_50_WIDTH },
10769  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_51_CHECKER_TYPE,
10770  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_51_WIDTH },
10771  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_52_CHECKER_TYPE,
10772  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_52_WIDTH },
10773  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_53_CHECKER_TYPE,
10774  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_53_WIDTH },
10775  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_54_CHECKER_TYPE,
10776  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_54_WIDTH },
10777  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_55_CHECKER_TYPE,
10778  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_55_WIDTH },
10779  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_56_CHECKER_TYPE,
10780  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_56_WIDTH },
10781  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_57_CHECKER_TYPE,
10782  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_57_WIDTH },
10783  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_58_CHECKER_TYPE,
10784  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_58_WIDTH },
10785  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_59_CHECKER_TYPE,
10786  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_59_WIDTH },
10787  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_60_CHECKER_TYPE,
10788  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_60_WIDTH },
10789  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_61_CHECKER_TYPE,
10790  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_61_WIDTH },
10791 };
10792 
10797 static const SDL_MemConfig_t SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_MemEntries[SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES] =
10798 {
10799  { SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_PKTRAM0_ECC_RAM_ID, 0u,
10800  SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_PKTRAM0_ECC_RAM_SIZE, 8u,
10801  SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_PKTRAM0_ECC_ROW_WIDTH, ((bool)false) },
10802  { SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_PKTRAM1_ECC_RAM_ID, 0u,
10803  SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_PKTRAM1_ECC_RAM_SIZE, 8u,
10804  SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_PKTRAM1_ECC_ROW_WIDTH, ((bool)false) },
10805  { SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_PKA_PROG_RAM_ECC_RAM_ID, 0u,
10806  SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_PKA_PROG_RAM_ECC_RAM_SIZE, 4u,
10807  SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_PKA_PROG_RAM_ECC_ROW_WIDTH, ((bool)false) },
10808  { SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_ENCR_CTXRAM_BANK01_ECC_RAM_ID, 0u,
10809  SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_ENCR_CTXRAM_BANK01_ECC_RAM_SIZE, 32u,
10810  SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_ENCR_CTXRAM_BANK01_ECC_ROW_WIDTH, ((bool)false) },
10811  { SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_ENCR_CTXRAM_BANK23_ECC_RAM_ID, 0u,
10812  SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_ENCR_CTXRAM_BANK23_ECC_RAM_SIZE, 32u,
10813  SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_ENCR_CTXRAM_BANK23_ECC_ROW_WIDTH, ((bool)false) },
10814  { SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_ENCR_CTXRAM_BANK4_ECC_RAM_ID, 0u,
10815  SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_ENCR_CTXRAM_BANK4_ECC_RAM_SIZE, 32u,
10816  SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_ENCR_CTXRAM_BANK4_ECC_ROW_WIDTH, ((bool)false) },
10817  { SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_AUTH_CTXRAM_BANK01_ECC_RAM_ID, 0u,
10818  SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_AUTH_CTXRAM_BANK01_ECC_RAM_SIZE, 32u,
10819  SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_AUTH_CTXRAM_BANK01_ECC_ROW_WIDTH, ((bool)false) },
10820  { SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_AUTH_CTXRAM_BANK23_ECC_RAM_ID, 0u,
10821  SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_AUTH_CTXRAM_BANK23_ECC_RAM_SIZE, 32u,
10822  SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_AUTH_CTXRAM_BANK23_ECC_ROW_WIDTH, ((bool)false) },
10823  { SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_AUTH_CTXRAM_BANK45_ECC_RAM_ID, 0u,
10824  SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_AUTH_CTXRAM_BANK45_ECC_RAM_SIZE, 32u,
10825  SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_AUTH_CTXRAM_BANK45_ECC_ROW_WIDTH, ((bool)false) },
10826  { SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_AUTH_CTXRAM_BANK67_ECC_RAM_ID, 0u,
10827  SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_AUTH_CTXRAM_BANK67_ECC_RAM_SIZE, 32u,
10828  SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_AUTH_CTXRAM_BANK67_ECC_ROW_WIDTH, ((bool)false) },
10829  { SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_AUTH_CTXRAM_BANK89_ECC_RAM_ID, 0u,
10830  SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_AUTH_CTXRAM_BANK89_ECC_RAM_SIZE, 32u,
10831  SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_AUTH_CTXRAM_BANK89_ECC_ROW_WIDTH, ((bool)false) },
10832  { SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_AUTH_CTXRAM_BANK10_ECC_RAM_ID, 0u,
10833  SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_AUTH_CTXRAM_BANK10_ECC_RAM_SIZE, 32u,
10834  SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_AUTH_CTXRAM_BANK10_ECC_ROW_WIDTH, ((bool)false) },
10835 };
10836 
10842 static const SDL_GrpChkConfig_t SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_groupEntries[SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_MAX_NUM_CHECKERS] =
10843 {
10844  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_0_CHECKER_TYPE,
10845  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_0_WIDTH },
10846  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_1_CHECKER_TYPE,
10847  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_1_WIDTH },
10848  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_2_CHECKER_TYPE,
10849  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_2_WIDTH },
10850  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_3_CHECKER_TYPE,
10851  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_3_WIDTH },
10852  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_4_CHECKER_TYPE,
10853  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_4_WIDTH },
10854  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_5_CHECKER_TYPE,
10855  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_5_WIDTH },
10856  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_6_CHECKER_TYPE,
10857  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_6_WIDTH },
10858  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_7_CHECKER_TYPE,
10859  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_7_WIDTH },
10860  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_8_CHECKER_TYPE,
10861  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_8_WIDTH },
10862  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_9_CHECKER_TYPE,
10863  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_9_WIDTH },
10864  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_10_CHECKER_TYPE,
10865  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_10_WIDTH },
10866  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_11_CHECKER_TYPE,
10867  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_11_WIDTH },
10868  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_12_CHECKER_TYPE,
10869  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_12_WIDTH },
10870  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_13_CHECKER_TYPE,
10871  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_13_WIDTH },
10872  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_14_CHECKER_TYPE,
10873  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_14_WIDTH },
10874  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_15_CHECKER_TYPE,
10875  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_15_WIDTH },
10876  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_16_CHECKER_TYPE,
10877  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_16_WIDTH },
10878  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_17_CHECKER_TYPE,
10879  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_17_WIDTH },
10880  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_18_CHECKER_TYPE,
10881  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_18_WIDTH },
10882  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_19_CHECKER_TYPE,
10883  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_19_WIDTH },
10884  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_20_CHECKER_TYPE,
10885  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_20_WIDTH },
10886  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_21_CHECKER_TYPE,
10887  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_21_WIDTH },
10888  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_22_CHECKER_TYPE,
10889  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_22_WIDTH },
10890  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_23_CHECKER_TYPE,
10891  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_23_WIDTH },
10892  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_24_CHECKER_TYPE,
10893  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_24_WIDTH },
10894  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_25_CHECKER_TYPE,
10895  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_25_WIDTH },
10896  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_26_CHECKER_TYPE,
10897  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_26_WIDTH },
10898  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_27_CHECKER_TYPE,
10899  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_27_WIDTH },
10900  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_28_CHECKER_TYPE,
10901  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_28_WIDTH },
10902  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_29_CHECKER_TYPE,
10903  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_29_WIDTH },
10904  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_30_CHECKER_TYPE,
10905  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_30_WIDTH },
10906  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_31_CHECKER_TYPE,
10907  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_31_WIDTH },
10908  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_32_CHECKER_TYPE,
10909  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_32_WIDTH },
10910  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_33_CHECKER_TYPE,
10911  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_33_WIDTH },
10912  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_34_CHECKER_TYPE,
10913  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_34_WIDTH },
10914  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_35_CHECKER_TYPE,
10915  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_35_WIDTH },
10916  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_36_CHECKER_TYPE,
10917  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_36_WIDTH },
10918  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_37_CHECKER_TYPE,
10919  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_37_WIDTH },
10920  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_38_CHECKER_TYPE,
10921  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_38_WIDTH },
10922  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_39_CHECKER_TYPE,
10923  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_39_WIDTH },
10924  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_40_CHECKER_TYPE,
10925  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_40_WIDTH },
10926  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_41_CHECKER_TYPE,
10927  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_41_WIDTH },
10928  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_42_CHECKER_TYPE,
10929  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_42_WIDTH },
10930  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_43_CHECKER_TYPE,
10931  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_43_WIDTH },
10932  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_44_CHECKER_TYPE,
10933  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_44_WIDTH },
10934  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_45_CHECKER_TYPE,
10935  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_45_WIDTH },
10936  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_46_CHECKER_TYPE,
10937  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_46_WIDTH },
10938  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_47_CHECKER_TYPE,
10939  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_47_WIDTH },
10940  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_48_CHECKER_TYPE,
10941  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_48_WIDTH },
10942  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_49_CHECKER_TYPE,
10943  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_49_WIDTH },
10944  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_50_CHECKER_TYPE,
10945  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_50_WIDTH },
10946  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_51_CHECKER_TYPE,
10947  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_51_WIDTH },
10948  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_52_CHECKER_TYPE,
10949  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_52_WIDTH },
10950  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_53_CHECKER_TYPE,
10951  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_53_WIDTH },
10952  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_54_CHECKER_TYPE,
10953  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_54_WIDTH },
10954  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_55_CHECKER_TYPE,
10955  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_55_WIDTH },
10956  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_56_CHECKER_TYPE,
10957  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_56_WIDTH },
10958  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_57_CHECKER_TYPE,
10959  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_57_WIDTH },
10960  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_58_CHECKER_TYPE,
10961  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_58_WIDTH },
10962  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_59_CHECKER_TYPE,
10963  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_59_WIDTH },
10964  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_60_CHECKER_TYPE,
10965  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_60_WIDTH },
10966  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_61_CHECKER_TYPE,
10967  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_61_WIDTH },
10968  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_62_CHECKER_TYPE,
10969  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_62_WIDTH },
10970  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_63_CHECKER_TYPE,
10971  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_63_WIDTH },
10972  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_64_CHECKER_TYPE,
10973  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_64_WIDTH },
10974  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_65_CHECKER_TYPE,
10975  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_65_WIDTH },
10976  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_66_CHECKER_TYPE,
10977  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_66_WIDTH },
10978  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_67_CHECKER_TYPE,
10979  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_67_WIDTH },
10980  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_68_CHECKER_TYPE,
10981  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_68_WIDTH },
10982  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_69_CHECKER_TYPE,
10983  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_69_WIDTH },
10984  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_70_CHECKER_TYPE,
10985  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_70_WIDTH },
10986  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_71_CHECKER_TYPE,
10987  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_71_WIDTH },
10988  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_72_CHECKER_TYPE,
10989  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_72_WIDTH },
10990  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_73_CHECKER_TYPE,
10991  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_73_WIDTH },
10992  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_74_CHECKER_TYPE,
10993  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_74_WIDTH },
10994  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_75_CHECKER_TYPE,
10995  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_75_WIDTH },
10996  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_76_CHECKER_TYPE,
10997  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_76_WIDTH },
10998  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_77_CHECKER_TYPE,
10999  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_77_WIDTH },
11000  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_78_CHECKER_TYPE,
11001  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_78_WIDTH },
11002  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_79_CHECKER_TYPE,
11003  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_79_WIDTH },
11004  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_80_CHECKER_TYPE,
11005  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_80_WIDTH },
11006  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_81_CHECKER_TYPE,
11007  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_81_WIDTH },
11008  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_82_CHECKER_TYPE,
11009  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_82_WIDTH },
11010  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_83_CHECKER_TYPE,
11011  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_83_WIDTH },
11012  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_84_CHECKER_TYPE,
11013  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_84_WIDTH },
11014  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_85_CHECKER_TYPE,
11015  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_85_WIDTH },
11016  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_86_CHECKER_TYPE,
11017  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_86_WIDTH },
11018  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_87_CHECKER_TYPE,
11019  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_87_WIDTH },
11020  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_88_CHECKER_TYPE,
11021  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_88_WIDTH },
11022  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_89_CHECKER_TYPE,
11023  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_89_WIDTH },
11024  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_90_CHECKER_TYPE,
11025  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_90_WIDTH },
11026  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_91_CHECKER_TYPE,
11027  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_91_WIDTH },
11028  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_92_CHECKER_TYPE,
11029  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_92_WIDTH },
11030  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_93_CHECKER_TYPE,
11031  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_93_WIDTH },
11032  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_94_CHECKER_TYPE,
11033  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_94_WIDTH },
11034  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_95_CHECKER_TYPE,
11035  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_95_WIDTH },
11036  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_96_CHECKER_TYPE,
11037  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_96_WIDTH },
11038  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_97_CHECKER_TYPE,
11039  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_97_WIDTH },
11040  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_98_CHECKER_TYPE,
11041  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_98_WIDTH },
11042  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_99_CHECKER_TYPE,
11043  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_99_WIDTH },
11044  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_100_CHECKER_TYPE,
11045  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_100_WIDTH },
11046  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_101_CHECKER_TYPE,
11047  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_101_WIDTH },
11048  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_102_CHECKER_TYPE,
11049  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_102_WIDTH },
11050  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_103_CHECKER_TYPE,
11051  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_103_WIDTH },
11052  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_104_CHECKER_TYPE,
11053  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_104_WIDTH },
11054  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_105_CHECKER_TYPE,
11055  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_105_WIDTH },
11056  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_106_CHECKER_TYPE,
11057  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_106_WIDTH },
11058  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_107_CHECKER_TYPE,
11059  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_107_WIDTH },
11060  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_108_CHECKER_TYPE,
11061  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_108_WIDTH },
11062  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_109_CHECKER_TYPE,
11063  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_109_WIDTH },
11064  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_110_CHECKER_TYPE,
11065  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_110_WIDTH },
11066  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_111_CHECKER_TYPE,
11067  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_111_WIDTH },
11068  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_112_CHECKER_TYPE,
11069  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_112_WIDTH },
11070  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_113_CHECKER_TYPE,
11071  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_113_WIDTH },
11072  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_114_CHECKER_TYPE,
11073  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_114_WIDTH },
11074  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_115_CHECKER_TYPE,
11075  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_115_WIDTH },
11076  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_116_CHECKER_TYPE,
11077  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_116_WIDTH },
11078  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_117_CHECKER_TYPE,
11079  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_117_WIDTH },
11080  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_118_CHECKER_TYPE,
11081  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_118_WIDTH },
11082  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_119_CHECKER_TYPE,
11083  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_119_WIDTH },
11084  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_120_CHECKER_TYPE,
11085  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_120_WIDTH },
11086  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_121_CHECKER_TYPE,
11087  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_121_WIDTH },
11088  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_122_CHECKER_TYPE,
11089  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_122_WIDTH },
11090  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_123_CHECKER_TYPE,
11091  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_123_WIDTH },
11092  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_124_CHECKER_TYPE,
11093  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_124_WIDTH },
11094  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_125_CHECKER_TYPE,
11095  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_125_WIDTH },
11096  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_126_CHECKER_TYPE,
11097  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_126_WIDTH },
11098  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_127_CHECKER_TYPE,
11099  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_127_WIDTH },
11100  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_128_CHECKER_TYPE,
11101  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_128_WIDTH },
11102  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_129_CHECKER_TYPE,
11103  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_129_WIDTH },
11104  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_130_CHECKER_TYPE,
11105  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_130_WIDTH },
11106  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_131_CHECKER_TYPE,
11107  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_131_WIDTH },
11108  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_132_CHECKER_TYPE,
11109  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_132_WIDTH },
11110  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_133_CHECKER_TYPE,
11111  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_133_WIDTH },
11112  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_134_CHECKER_TYPE,
11113  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_134_WIDTH },
11114  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_135_CHECKER_TYPE,
11115  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_135_WIDTH },
11116  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_136_CHECKER_TYPE,
11117  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_136_WIDTH },
11118  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_137_CHECKER_TYPE,
11119  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_137_WIDTH },
11120  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_138_CHECKER_TYPE,
11121  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_138_WIDTH },
11122  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_139_CHECKER_TYPE,
11123  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_139_WIDTH },
11124  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_140_CHECKER_TYPE,
11125  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_140_WIDTH },
11126  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_141_CHECKER_TYPE,
11127  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_141_WIDTH },
11128  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_142_CHECKER_TYPE,
11129  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_142_WIDTH },
11130  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_143_CHECKER_TYPE,
11131  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_143_WIDTH },
11132  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_144_CHECKER_TYPE,
11133  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_144_WIDTH },
11134  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_145_CHECKER_TYPE,
11135  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_145_WIDTH },
11136  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_146_CHECKER_TYPE,
11137  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_146_WIDTH },
11138  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_147_CHECKER_TYPE,
11139  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_147_WIDTH },
11140  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_148_CHECKER_TYPE,
11141  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_148_WIDTH },
11142  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_149_CHECKER_TYPE,
11143  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_149_WIDTH },
11144  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_150_CHECKER_TYPE,
11145  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_150_WIDTH },
11146  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_151_CHECKER_TYPE,
11147  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_151_WIDTH },
11148  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_152_CHECKER_TYPE,
11149  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_152_WIDTH },
11150  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_153_CHECKER_TYPE,
11151  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_153_WIDTH },
11152  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_154_CHECKER_TYPE,
11153  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_154_WIDTH },
11154  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_155_CHECKER_TYPE,
11155  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_155_WIDTH },
11156  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_156_CHECKER_TYPE,
11157  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_156_WIDTH },
11158  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_157_CHECKER_TYPE,
11159  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_157_WIDTH },
11160  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_158_CHECKER_TYPE,
11161  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_158_WIDTH },
11162  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_159_CHECKER_TYPE,
11163  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_159_WIDTH },
11164  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_160_CHECKER_TYPE,
11165  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_160_WIDTH },
11166  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_161_CHECKER_TYPE,
11167  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_161_WIDTH },
11168  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_162_CHECKER_TYPE,
11169  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_162_WIDTH },
11170  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_163_CHECKER_TYPE,
11171  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_163_WIDTH },
11172  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_164_CHECKER_TYPE,
11173  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_164_WIDTH },
11174  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_165_CHECKER_TYPE,
11175  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_165_WIDTH },
11176  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_166_CHECKER_TYPE,
11177  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_166_WIDTH },
11178  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_167_CHECKER_TYPE,
11179  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_167_WIDTH },
11180  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_168_CHECKER_TYPE,
11181  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_168_WIDTH },
11182  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_169_CHECKER_TYPE,
11183  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_169_WIDTH },
11184  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_170_CHECKER_TYPE,
11185  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_170_WIDTH },
11186  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_171_CHECKER_TYPE,
11187  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_171_WIDTH },
11188  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_172_CHECKER_TYPE,
11189  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_172_WIDTH },
11190  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_173_CHECKER_TYPE,
11191  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_173_WIDTH },
11192  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_174_CHECKER_TYPE,
11193  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_174_WIDTH },
11194  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_175_CHECKER_TYPE,
11195  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_175_WIDTH },
11196  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_176_CHECKER_TYPE,
11197  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_176_WIDTH },
11198  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_177_CHECKER_TYPE,
11199  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_177_WIDTH },
11200  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_178_CHECKER_TYPE,
11201  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_178_WIDTH },
11202  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_179_CHECKER_TYPE,
11203  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_179_WIDTH },
11204  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_180_CHECKER_TYPE,
11205  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_180_WIDTH },
11206  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_181_CHECKER_TYPE,
11207  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_181_WIDTH },
11208  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_182_CHECKER_TYPE,
11209  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_182_WIDTH },
11210  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_183_CHECKER_TYPE,
11211  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_183_WIDTH },
11212  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_184_CHECKER_TYPE,
11213  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_184_WIDTH },
11214  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_185_CHECKER_TYPE,
11215  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_185_WIDTH },
11216  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_186_CHECKER_TYPE,
11217  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_186_WIDTH },
11218  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_187_CHECKER_TYPE,
11219  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_187_WIDTH },
11220  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_188_CHECKER_TYPE,
11221  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_188_WIDTH },
11222  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_189_CHECKER_TYPE,
11223  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_189_WIDTH },
11224  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_190_CHECKER_TYPE,
11225  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_190_WIDTH },
11226  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_191_CHECKER_TYPE,
11227  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_191_WIDTH },
11228  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_192_CHECKER_TYPE,
11229  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_192_WIDTH },
11230  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_193_CHECKER_TYPE,
11231  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_193_WIDTH },
11232  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_194_CHECKER_TYPE,
11233  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_194_WIDTH },
11234  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_195_CHECKER_TYPE,
11235  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_195_WIDTH },
11236  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_196_CHECKER_TYPE,
11237  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_196_WIDTH },
11238  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_197_CHECKER_TYPE,
11239  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_197_WIDTH },
11240  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_198_CHECKER_TYPE,
11241  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_198_WIDTH },
11242  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_199_CHECKER_TYPE,
11243  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_199_WIDTH },
11244  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_200_CHECKER_TYPE,
11245  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_200_WIDTH },
11246  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_201_CHECKER_TYPE,
11247  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_201_WIDTH },
11248  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_202_CHECKER_TYPE,
11249  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_202_WIDTH },
11250  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_203_CHECKER_TYPE,
11251  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_203_WIDTH },
11252  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_204_CHECKER_TYPE,
11253  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_204_WIDTH },
11254  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_205_CHECKER_TYPE,
11255  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_205_WIDTH },
11256  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_206_CHECKER_TYPE,
11257  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_206_WIDTH },
11258  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_207_CHECKER_TYPE,
11259  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_207_WIDTH },
11260  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_208_CHECKER_TYPE,
11261  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_208_WIDTH },
11262  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_209_CHECKER_TYPE,
11263  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_209_WIDTH },
11264  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_210_CHECKER_TYPE,
11265  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_210_WIDTH },
11266  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_211_CHECKER_TYPE,
11267  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_211_WIDTH },
11268  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_212_CHECKER_TYPE,
11269  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_212_WIDTH },
11270  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_213_CHECKER_TYPE,
11271  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_213_WIDTH },
11272  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_214_CHECKER_TYPE,
11273  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_214_WIDTH },
11274  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_215_CHECKER_TYPE,
11275  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_215_WIDTH },
11276  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_216_CHECKER_TYPE,
11277  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_216_WIDTH },
11278  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_217_CHECKER_TYPE,
11279  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_217_WIDTH },
11280  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_218_CHECKER_TYPE,
11281  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_218_WIDTH },
11282  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_219_CHECKER_TYPE,
11283  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_219_WIDTH },
11284  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_220_CHECKER_TYPE,
11285  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_220_WIDTH },
11286  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_221_CHECKER_TYPE,
11287  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_221_WIDTH },
11288  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_222_CHECKER_TYPE,
11289  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_222_WIDTH },
11290  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_223_CHECKER_TYPE,
11291  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_223_WIDTH },
11292  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_224_CHECKER_TYPE,
11293  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_224_WIDTH },
11294  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_225_CHECKER_TYPE,
11295  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_225_WIDTH },
11296  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_226_CHECKER_TYPE,
11297  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_226_WIDTH },
11298  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_227_CHECKER_TYPE,
11299  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_227_WIDTH },
11300  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_228_CHECKER_TYPE,
11301  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_228_WIDTH },
11302  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_229_CHECKER_TYPE,
11303  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_229_WIDTH },
11304  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_230_CHECKER_TYPE,
11305  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_230_WIDTH },
11306  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_231_CHECKER_TYPE,
11307  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_231_WIDTH },
11308  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_232_CHECKER_TYPE,
11309  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_232_WIDTH },
11310  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_233_CHECKER_TYPE,
11311  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_233_WIDTH },
11312  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_234_CHECKER_TYPE,
11313  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_234_WIDTH },
11314  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_235_CHECKER_TYPE,
11315  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_235_WIDTH },
11316  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_236_CHECKER_TYPE,
11317  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_236_WIDTH },
11318  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_237_CHECKER_TYPE,
11319  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_237_WIDTH },
11320  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_238_CHECKER_TYPE,
11321  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_238_WIDTH },
11322  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_239_CHECKER_TYPE,
11323  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_239_WIDTH },
11324  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_240_CHECKER_TYPE,
11325  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_240_WIDTH },
11326  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_241_CHECKER_TYPE,
11327  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_241_WIDTH },
11328  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_242_CHECKER_TYPE,
11329  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_242_WIDTH },
11330  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_243_CHECKER_TYPE,
11331  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_243_WIDTH },
11332  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_244_CHECKER_TYPE,
11333  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_244_WIDTH },
11334  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_245_CHECKER_TYPE,
11335  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_245_WIDTH },
11336  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_246_CHECKER_TYPE,
11337  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_246_WIDTH },
11338  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_247_CHECKER_TYPE,
11339  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_247_WIDTH },
11340  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_248_CHECKER_TYPE,
11341  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_248_WIDTH },
11342  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_249_CHECKER_TYPE,
11343  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_249_WIDTH },
11344  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_250_CHECKER_TYPE,
11345  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_250_WIDTH },
11346  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_251_CHECKER_TYPE,
11347  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_251_WIDTH },
11348  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_252_CHECKER_TYPE,
11349  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_252_WIDTH },
11350  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_253_CHECKER_TYPE,
11351  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_253_WIDTH },
11352  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_254_CHECKER_TYPE,
11353  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_254_WIDTH },
11354  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_255_CHECKER_TYPE,
11355  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_255_WIDTH },
11356 };
11357 
11363 static const SDL_GrpChkConfig_t SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_groupEntries[SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_MAX_NUM_CHECKERS] =
11364 {
11365  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_0_CHECKER_TYPE,
11366  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_0_WIDTH },
11367  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_1_CHECKER_TYPE,
11368  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_1_WIDTH },
11369  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_2_CHECKER_TYPE,
11370  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_2_WIDTH },
11371  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_3_CHECKER_TYPE,
11372  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_3_WIDTH },
11373  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_4_CHECKER_TYPE,
11374  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_4_WIDTH },
11375  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_5_CHECKER_TYPE,
11376  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_5_WIDTH },
11377  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_6_CHECKER_TYPE,
11378  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_6_WIDTH },
11379  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_7_CHECKER_TYPE,
11380  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_7_WIDTH },
11381  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_8_CHECKER_TYPE,
11382  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_8_WIDTH },
11383  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_9_CHECKER_TYPE,
11384  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_9_WIDTH },
11385  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_10_CHECKER_TYPE,
11386  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_10_WIDTH },
11387  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_11_CHECKER_TYPE,
11388  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_11_WIDTH },
11389  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_12_CHECKER_TYPE,
11390  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_12_WIDTH },
11391  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_13_CHECKER_TYPE,
11392  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_13_WIDTH },
11393  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_14_CHECKER_TYPE,
11394  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_14_WIDTH },
11395  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_15_CHECKER_TYPE,
11396  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_15_WIDTH },
11397  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_16_CHECKER_TYPE,
11398  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_16_WIDTH },
11399  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_17_CHECKER_TYPE,
11400  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_17_WIDTH },
11401  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_18_CHECKER_TYPE,
11402  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_18_WIDTH },
11403  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_19_CHECKER_TYPE,
11404  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_19_WIDTH },
11405  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_20_CHECKER_TYPE,
11406  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_20_WIDTH },
11407  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_21_CHECKER_TYPE,
11408  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_21_WIDTH },
11409  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_22_CHECKER_TYPE,
11410  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_22_WIDTH },
11411  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_23_CHECKER_TYPE,
11412  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_23_WIDTH },
11413  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_24_CHECKER_TYPE,
11414  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_24_WIDTH },
11415  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_25_CHECKER_TYPE,
11416  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_25_WIDTH },
11417  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_26_CHECKER_TYPE,
11418  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_26_WIDTH },
11419  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_27_CHECKER_TYPE,
11420  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_27_WIDTH },
11421  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_28_CHECKER_TYPE,
11422  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_28_WIDTH },
11423  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_29_CHECKER_TYPE,
11424  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_29_WIDTH },
11425  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_30_CHECKER_TYPE,
11426  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_30_WIDTH },
11427  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_31_CHECKER_TYPE,
11428  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_31_WIDTH },
11429  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_32_CHECKER_TYPE,
11430  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_32_WIDTH },
11431  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_33_CHECKER_TYPE,
11432  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_33_WIDTH },
11433  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_34_CHECKER_TYPE,
11434  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_34_WIDTH },
11435  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_35_CHECKER_TYPE,
11436  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_35_WIDTH },
11437  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_36_CHECKER_TYPE,
11438  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_36_WIDTH },
11439  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_37_CHECKER_TYPE,
11440  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_37_WIDTH },
11441  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_38_CHECKER_TYPE,
11442  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_38_WIDTH },
11443  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_39_CHECKER_TYPE,
11444  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_39_WIDTH },
11445  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_40_CHECKER_TYPE,
11446  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_40_WIDTH },
11447  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_41_CHECKER_TYPE,
11448  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_41_WIDTH },
11449  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_42_CHECKER_TYPE,
11450  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_42_WIDTH },
11451  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_43_CHECKER_TYPE,
11452  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_43_WIDTH },
11453  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_44_CHECKER_TYPE,
11454  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_44_WIDTH },
11455  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_45_CHECKER_TYPE,
11456  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_45_WIDTH },
11457  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_46_CHECKER_TYPE,
11458  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_46_WIDTH },
11459  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_47_CHECKER_TYPE,
11460  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_47_WIDTH },
11461  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_48_CHECKER_TYPE,
11462  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_48_WIDTH },
11463  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_49_CHECKER_TYPE,
11464  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_49_WIDTH },
11465  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_50_CHECKER_TYPE,
11466  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_50_WIDTH },
11467  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_51_CHECKER_TYPE,
11468  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_51_WIDTH },
11469  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_52_CHECKER_TYPE,
11470  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_52_WIDTH },
11471  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_53_CHECKER_TYPE,
11472  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_53_WIDTH },
11473  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_54_CHECKER_TYPE,
11474  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_54_WIDTH },
11475  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_55_CHECKER_TYPE,
11476  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_55_WIDTH },
11477  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_56_CHECKER_TYPE,
11478  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_56_WIDTH },
11479  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_57_CHECKER_TYPE,
11480  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_57_WIDTH },
11481  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_58_CHECKER_TYPE,
11482  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_58_WIDTH },
11483  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_59_CHECKER_TYPE,
11484  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_59_WIDTH },
11485  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_60_CHECKER_TYPE,
11486  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_60_WIDTH },
11487  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_61_CHECKER_TYPE,
11488  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_61_WIDTH },
11489  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_62_CHECKER_TYPE,
11490  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_62_WIDTH },
11491  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_63_CHECKER_TYPE,
11492  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_63_WIDTH },
11493  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_64_CHECKER_TYPE,
11494  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_64_WIDTH },
11495  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_65_CHECKER_TYPE,
11496  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_65_WIDTH },
11497  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_66_CHECKER_TYPE,
11498  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_66_WIDTH },
11499  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_67_CHECKER_TYPE,
11500  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_67_WIDTH },
11501  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_68_CHECKER_TYPE,
11502  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_68_WIDTH },
11503  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_69_CHECKER_TYPE,
11504  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_69_WIDTH },
11505  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_70_CHECKER_TYPE,
11506  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_70_WIDTH },
11507  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_71_CHECKER_TYPE,
11508  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_71_WIDTH },
11509  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_72_CHECKER_TYPE,
11510  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_72_WIDTH },
11511  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_73_CHECKER_TYPE,
11512  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_73_WIDTH },
11513 };
11514 
11520 static const SDL_GrpChkConfig_t SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_PLL_MMR_EDC_CTRL_BUSECC_groupEntries[SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_PLL_MMR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS] =
11521 {
11522  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
11523  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
11524  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
11525  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
11526  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
11527  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
11528  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
11529  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
11530  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
11531  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
11532  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_5_CHECKER_TYPE,
11533  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_5_WIDTH },
11534  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_6_CHECKER_TYPE,
11535  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_6_WIDTH },
11536  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_7_CHECKER_TYPE,
11537  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_7_WIDTH },
11538  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_8_CHECKER_TYPE,
11539  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_8_WIDTH },
11540  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_9_CHECKER_TYPE,
11541  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_9_WIDTH },
11542  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_10_CHECKER_TYPE,
11543  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_10_WIDTH },
11544  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_11_CHECKER_TYPE,
11545  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_11_WIDTH },
11546  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_12_CHECKER_TYPE,
11547  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_12_WIDTH },
11548  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_13_CHECKER_TYPE,
11549  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_13_WIDTH },
11550  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_14_CHECKER_TYPE,
11551  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_14_WIDTH },
11552  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_15_CHECKER_TYPE,
11553  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_15_WIDTH },
11554  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_16_CHECKER_TYPE,
11555  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_16_WIDTH },
11556  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_17_CHECKER_TYPE,
11557  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_17_WIDTH },
11558  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_18_CHECKER_TYPE,
11559  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_18_WIDTH },
11560  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_19_CHECKER_TYPE,
11561  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_19_WIDTH },
11562  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_20_CHECKER_TYPE,
11563  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_20_WIDTH },
11564  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_21_CHECKER_TYPE,
11565  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_21_WIDTH },
11566  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_22_CHECKER_TYPE,
11567  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_22_WIDTH },
11568  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_23_CHECKER_TYPE,
11569  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_23_WIDTH },
11570  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_24_CHECKER_TYPE,
11571  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_24_WIDTH },
11572  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_25_CHECKER_TYPE,
11573  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_25_WIDTH },
11574  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_26_CHECKER_TYPE,
11575  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_26_WIDTH },
11576  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_27_CHECKER_TYPE,
11577  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_27_WIDTH },
11578  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_28_CHECKER_TYPE,
11579  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_28_WIDTH },
11580  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_29_CHECKER_TYPE,
11581  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_29_WIDTH },
11582  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_30_CHECKER_TYPE,
11583  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_30_WIDTH },
11584  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_31_CHECKER_TYPE,
11585  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_31_WIDTH },
11586  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_32_CHECKER_TYPE,
11587  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_32_WIDTH },
11588  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_33_CHECKER_TYPE,
11589  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_33_WIDTH },
11590  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_34_CHECKER_TYPE,
11591  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_34_WIDTH },
11592  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_35_CHECKER_TYPE,
11593  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_35_WIDTH },
11594  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_36_CHECKER_TYPE,
11595  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_36_WIDTH },
11596  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_37_CHECKER_TYPE,
11597  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_37_WIDTH },
11598  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_38_CHECKER_TYPE,
11599  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_38_WIDTH },
11600  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_39_CHECKER_TYPE,
11601  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_39_WIDTH },
11602  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_40_CHECKER_TYPE,
11603  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_40_WIDTH },
11604  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_41_CHECKER_TYPE,
11605  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_41_WIDTH },
11606  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_42_CHECKER_TYPE,
11607  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_42_WIDTH },
11608  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_43_CHECKER_TYPE,
11609  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_43_WIDTH },
11610  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_44_CHECKER_TYPE,
11611  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_44_WIDTH },
11612  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_45_CHECKER_TYPE,
11613  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_45_WIDTH },
11614  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_46_CHECKER_TYPE,
11615  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_46_WIDTH },
11616  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_47_CHECKER_TYPE,
11617  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_47_WIDTH },
11618  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_48_CHECKER_TYPE,
11619  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_48_WIDTH },
11620  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_49_CHECKER_TYPE,
11621  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_49_WIDTH },
11622  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_50_CHECKER_TYPE,
11623  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_50_WIDTH },
11624  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_51_CHECKER_TYPE,
11625  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_51_WIDTH },
11626  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_52_CHECKER_TYPE,
11627  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_52_WIDTH },
11628 };
11629 
11635 static const SDL_GrpChkConfig_t SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_groupEntries[SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_MAX_NUM_CHECKERS] =
11636 {
11637  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_0_CHECKER_TYPE,
11638  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_0_WIDTH },
11639  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_1_CHECKER_TYPE,
11640  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_1_WIDTH },
11641  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_2_CHECKER_TYPE,
11642  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_2_WIDTH },
11643  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_3_CHECKER_TYPE,
11644  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_3_WIDTH },
11645  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_4_CHECKER_TYPE,
11646  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_4_WIDTH },
11647  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_5_CHECKER_TYPE,
11648  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_5_WIDTH },
11649  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_6_CHECKER_TYPE,
11650  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_6_WIDTH },
11651  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_7_CHECKER_TYPE,
11652  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_7_WIDTH },
11653  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_8_CHECKER_TYPE,
11654  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_8_WIDTH },
11655  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_9_CHECKER_TYPE,
11656  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_9_WIDTH },
11657  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_10_CHECKER_TYPE,
11658  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_10_WIDTH },
11659  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_11_CHECKER_TYPE,
11660  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_11_WIDTH },
11661  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_12_CHECKER_TYPE,
11662  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_12_WIDTH },
11663  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_13_CHECKER_TYPE,
11664  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_13_WIDTH },
11665  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_14_CHECKER_TYPE,
11666  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_14_WIDTH },
11667  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_15_CHECKER_TYPE,
11668  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_15_WIDTH },
11669  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_16_CHECKER_TYPE,
11670  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_16_WIDTH },
11671  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_17_CHECKER_TYPE,
11672  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_17_WIDTH },
11673  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_18_CHECKER_TYPE,
11674  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_18_WIDTH },
11675  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_19_CHECKER_TYPE,
11676  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_19_WIDTH },
11677  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_20_CHECKER_TYPE,
11678  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_20_WIDTH },
11679  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_21_CHECKER_TYPE,
11680  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_21_WIDTH },
11681  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_22_CHECKER_TYPE,
11682  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_22_WIDTH },
11683  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_23_CHECKER_TYPE,
11684  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_23_WIDTH },
11685  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_24_CHECKER_TYPE,
11686  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_24_WIDTH },
11687  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_25_CHECKER_TYPE,
11688  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_25_WIDTH },
11689  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_26_CHECKER_TYPE,
11690  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_26_WIDTH },
11691  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_27_CHECKER_TYPE,
11692  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_27_WIDTH },
11693  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_28_CHECKER_TYPE,
11694  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_28_WIDTH },
11695  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_29_CHECKER_TYPE,
11696  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_29_WIDTH },
11697  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_30_CHECKER_TYPE,
11698  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_30_WIDTH },
11699  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_31_CHECKER_TYPE,
11700  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_31_WIDTH },
11701  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_32_CHECKER_TYPE,
11702  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_32_WIDTH },
11703  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_33_CHECKER_TYPE,
11704  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_33_WIDTH },
11705  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_34_CHECKER_TYPE,
11706  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_34_WIDTH },
11707  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_35_CHECKER_TYPE,
11708  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_35_WIDTH },
11709  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_36_CHECKER_TYPE,
11710  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_36_WIDTH },
11711  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_37_CHECKER_TYPE,
11712  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_37_WIDTH },
11713  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_38_CHECKER_TYPE,
11714  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_38_WIDTH },
11715  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_39_CHECKER_TYPE,
11716  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_39_WIDTH },
11717  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_40_CHECKER_TYPE,
11718  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_40_WIDTH },
11719  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_41_CHECKER_TYPE,
11720  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_41_WIDTH },
11721  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_42_CHECKER_TYPE,
11722  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_42_WIDTH },
11723  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_43_CHECKER_TYPE,
11724  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_43_WIDTH },
11725  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_44_CHECKER_TYPE,
11726  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_44_WIDTH },
11727  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_45_CHECKER_TYPE,
11728  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_45_WIDTH },
11729  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_46_CHECKER_TYPE,
11730  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_46_WIDTH },
11731  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_47_CHECKER_TYPE,
11732  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_47_WIDTH },
11733  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_48_CHECKER_TYPE,
11734  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_48_WIDTH },
11735  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_49_CHECKER_TYPE,
11736  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_49_WIDTH },
11737  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_50_CHECKER_TYPE,
11738  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_50_WIDTH },
11739  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_51_CHECKER_TYPE,
11740  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_51_WIDTH },
11741  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_52_CHECKER_TYPE,
11742  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_52_WIDTH },
11743  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_53_CHECKER_TYPE,
11744  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_53_WIDTH },
11745  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_54_CHECKER_TYPE,
11746  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_54_WIDTH },
11747  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_55_CHECKER_TYPE,
11748  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_55_WIDTH },
11749  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_56_CHECKER_TYPE,
11750  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_56_WIDTH },
11751  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_57_CHECKER_TYPE,
11752  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_57_WIDTH },
11753  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_58_CHECKER_TYPE,
11754  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_58_WIDTH },
11755  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_59_CHECKER_TYPE,
11756  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_59_WIDTH },
11757  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_60_CHECKER_TYPE,
11758  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_60_WIDTH },
11759  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_61_CHECKER_TYPE,
11760  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_61_WIDTH },
11761  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_62_CHECKER_TYPE,
11762  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_62_WIDTH },
11763  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_63_CHECKER_TYPE,
11764  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_63_WIDTH },
11765  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_64_CHECKER_TYPE,
11766  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_64_WIDTH },
11767  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_65_CHECKER_TYPE,
11768  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_65_WIDTH },
11769  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_66_CHECKER_TYPE,
11770  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_66_WIDTH },
11771  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_67_CHECKER_TYPE,
11772  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_67_WIDTH },
11773  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_68_CHECKER_TYPE,
11774  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_68_WIDTH },
11775  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_69_CHECKER_TYPE,
11776  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_69_WIDTH },
11777  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_70_CHECKER_TYPE,
11778  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_70_WIDTH },
11779  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_71_CHECKER_TYPE,
11780  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_71_WIDTH },
11781  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_72_CHECKER_TYPE,
11782  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_72_WIDTH },
11783  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_73_CHECKER_TYPE,
11784  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_73_WIDTH },
11785  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_74_CHECKER_TYPE,
11786  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_74_WIDTH },
11787  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_75_CHECKER_TYPE,
11788  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_75_WIDTH },
11789  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_76_CHECKER_TYPE,
11790  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_76_WIDTH },
11791  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_77_CHECKER_TYPE,
11792  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_77_WIDTH },
11793  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_78_CHECKER_TYPE,
11794  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_78_WIDTH },
11795  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_79_CHECKER_TYPE,
11796  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_79_WIDTH },
11797  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_80_CHECKER_TYPE,
11798  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_80_WIDTH },
11799  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_81_CHECKER_TYPE,
11800  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_81_WIDTH },
11801  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_82_CHECKER_TYPE,
11802  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_82_WIDTH },
11803  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_83_CHECKER_TYPE,
11804  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_83_WIDTH },
11805  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_84_CHECKER_TYPE,
11806  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_84_WIDTH },
11807  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_85_CHECKER_TYPE,
11808  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_85_WIDTH },
11809  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_86_CHECKER_TYPE,
11810  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_86_WIDTH },
11811  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_87_CHECKER_TYPE,
11812  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_87_WIDTH },
11813  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_88_CHECKER_TYPE,
11814  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_88_WIDTH },
11815  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_89_CHECKER_TYPE,
11816  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_89_WIDTH },
11817  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_90_CHECKER_TYPE,
11818  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_90_WIDTH },
11819  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_91_CHECKER_TYPE,
11820  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_91_WIDTH },
11821  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_92_CHECKER_TYPE,
11822  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_92_WIDTH },
11823  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_93_CHECKER_TYPE,
11824  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_93_WIDTH },
11825  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_94_CHECKER_TYPE,
11826  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_94_WIDTH },
11827  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_95_CHECKER_TYPE,
11828  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_95_WIDTH },
11829  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_96_CHECKER_TYPE,
11830  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_96_WIDTH },
11831  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_97_CHECKER_TYPE,
11832  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_97_WIDTH },
11833  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_98_CHECKER_TYPE,
11834  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_98_WIDTH },
11835  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_99_CHECKER_TYPE,
11836  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_99_WIDTH },
11837  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_100_CHECKER_TYPE,
11838  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_100_WIDTH },
11839  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_101_CHECKER_TYPE,
11840  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_101_WIDTH },
11841  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_102_CHECKER_TYPE,
11842  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_102_WIDTH },
11843  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_103_CHECKER_TYPE,
11844  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_103_WIDTH },
11845  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_104_CHECKER_TYPE,
11846  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_104_WIDTH },
11847  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_105_CHECKER_TYPE,
11848  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_105_WIDTH },
11849  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_106_CHECKER_TYPE,
11850  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_106_WIDTH },
11851  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_107_CHECKER_TYPE,
11852  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_107_WIDTH },
11853  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_108_CHECKER_TYPE,
11854  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_108_WIDTH },
11855  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_109_CHECKER_TYPE,
11856  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_109_WIDTH },
11857  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_110_CHECKER_TYPE,
11858  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_110_WIDTH },
11859  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_111_CHECKER_TYPE,
11860  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_111_WIDTH },
11861  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_112_CHECKER_TYPE,
11862  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_112_WIDTH },
11863  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_113_CHECKER_TYPE,
11864  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_113_WIDTH },
11865  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_114_CHECKER_TYPE,
11866  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_114_WIDTH },
11867  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_115_CHECKER_TYPE,
11868  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_115_WIDTH },
11869  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_116_CHECKER_TYPE,
11870  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_116_WIDTH },
11871  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_117_CHECKER_TYPE,
11872  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_117_WIDTH },
11873  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_118_CHECKER_TYPE,
11874  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_118_WIDTH },
11875  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_119_CHECKER_TYPE,
11876  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_119_WIDTH },
11877  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_120_CHECKER_TYPE,
11878  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_120_WIDTH },
11879  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_121_CHECKER_TYPE,
11880  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_121_WIDTH },
11881  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_122_CHECKER_TYPE,
11882  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_122_WIDTH },
11883  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_123_CHECKER_TYPE,
11884  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_123_WIDTH },
11885  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_124_CHECKER_TYPE,
11886  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_124_WIDTH },
11887  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_125_CHECKER_TYPE,
11888  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_125_WIDTH },
11889  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_126_CHECKER_TYPE,
11890  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_126_WIDTH },
11891  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_127_CHECKER_TYPE,
11892  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_127_WIDTH },
11893  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_128_CHECKER_TYPE,
11894  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_128_WIDTH },
11895  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_129_CHECKER_TYPE,
11896  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_129_WIDTH },
11897  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_130_CHECKER_TYPE,
11898  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_130_WIDTH },
11899  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_131_CHECKER_TYPE,
11900  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_131_WIDTH },
11901  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_132_CHECKER_TYPE,
11902  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_132_WIDTH },
11903  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_133_CHECKER_TYPE,
11904  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_133_WIDTH },
11905  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_134_CHECKER_TYPE,
11906  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_134_WIDTH },
11907  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_135_CHECKER_TYPE,
11908  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_135_WIDTH },
11909  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_136_CHECKER_TYPE,
11910  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_136_WIDTH },
11911  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_137_CHECKER_TYPE,
11912  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_137_WIDTH },
11913  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_138_CHECKER_TYPE,
11914  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_138_WIDTH },
11915  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_139_CHECKER_TYPE,
11916  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_139_WIDTH },
11917  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_140_CHECKER_TYPE,
11918  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_140_WIDTH },
11919  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_141_CHECKER_TYPE,
11920  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_141_WIDTH },
11921  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_142_CHECKER_TYPE,
11922  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_142_WIDTH },
11923  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_143_CHECKER_TYPE,
11924  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_143_WIDTH },
11925  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_144_CHECKER_TYPE,
11926  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_144_WIDTH },
11927  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_145_CHECKER_TYPE,
11928  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_145_WIDTH },
11929  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_146_CHECKER_TYPE,
11930  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_146_WIDTH },
11931  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_147_CHECKER_TYPE,
11932  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_147_WIDTH },
11933  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_148_CHECKER_TYPE,
11934  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_148_WIDTH },
11935  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_149_CHECKER_TYPE,
11936  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_149_WIDTH },
11937  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_150_CHECKER_TYPE,
11938  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_150_WIDTH },
11939  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_151_CHECKER_TYPE,
11940  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_151_WIDTH },
11941  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_152_CHECKER_TYPE,
11942  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_152_WIDTH },
11943  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_153_CHECKER_TYPE,
11944  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_153_WIDTH },
11945  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_154_CHECKER_TYPE,
11946  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_154_WIDTH },
11947  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_155_CHECKER_TYPE,
11948  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_155_WIDTH },
11949  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_156_CHECKER_TYPE,
11950  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_156_WIDTH },
11951  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_157_CHECKER_TYPE,
11952  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_157_WIDTH },
11953  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_158_CHECKER_TYPE,
11954  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_158_WIDTH },
11955  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_159_CHECKER_TYPE,
11956  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_159_WIDTH },
11957  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_160_CHECKER_TYPE,
11958  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_160_WIDTH },
11959  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_161_CHECKER_TYPE,
11960  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_161_WIDTH },
11961  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_162_CHECKER_TYPE,
11962  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_162_WIDTH },
11963  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_163_CHECKER_TYPE,
11964  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_163_WIDTH },
11965  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_164_CHECKER_TYPE,
11966  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_164_WIDTH },
11967  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_165_CHECKER_TYPE,
11968  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_165_WIDTH },
11969  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_166_CHECKER_TYPE,
11970  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_166_WIDTH },
11971  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_167_CHECKER_TYPE,
11972  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_167_WIDTH },
11973  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_168_CHECKER_TYPE,
11974  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_168_WIDTH },
11975  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_169_CHECKER_TYPE,
11976  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_169_WIDTH },
11977  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_170_CHECKER_TYPE,
11978  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_170_WIDTH },
11979  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_171_CHECKER_TYPE,
11980  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_171_WIDTH },
11981  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_172_CHECKER_TYPE,
11982  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_172_WIDTH },
11983  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_173_CHECKER_TYPE,
11984  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_173_WIDTH },
11985  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_174_CHECKER_TYPE,
11986  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_174_WIDTH },
11987  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_175_CHECKER_TYPE,
11988  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_175_WIDTH },
11989  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_176_CHECKER_TYPE,
11990  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_176_WIDTH },
11991  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_177_CHECKER_TYPE,
11992  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_177_WIDTH },
11993  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_178_CHECKER_TYPE,
11994  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_178_WIDTH },
11995  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_179_CHECKER_TYPE,
11996  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_179_WIDTH },
11997  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_180_CHECKER_TYPE,
11998  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_180_WIDTH },
11999  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_181_CHECKER_TYPE,
12000  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_181_WIDTH },
12001  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_182_CHECKER_TYPE,
12002  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_182_WIDTH },
12003  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_183_CHECKER_TYPE,
12004  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_183_WIDTH },
12005  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_184_CHECKER_TYPE,
12006  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_184_WIDTH },
12007  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_185_CHECKER_TYPE,
12008  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_185_WIDTH },
12009  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_186_CHECKER_TYPE,
12010  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_186_WIDTH },
12011  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_187_CHECKER_TYPE,
12012  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_187_WIDTH },
12013  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_188_CHECKER_TYPE,
12014  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_188_WIDTH },
12015  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_189_CHECKER_TYPE,
12016  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_189_WIDTH },
12017  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_190_CHECKER_TYPE,
12018  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_190_WIDTH },
12019  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_191_CHECKER_TYPE,
12020  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_191_WIDTH },
12021  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_192_CHECKER_TYPE,
12022  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_192_WIDTH },
12023  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_193_CHECKER_TYPE,
12024  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_193_WIDTH },
12025  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_194_CHECKER_TYPE,
12026  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_194_WIDTH },
12027  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_195_CHECKER_TYPE,
12028  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_195_WIDTH },
12029  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_196_CHECKER_TYPE,
12030  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_196_WIDTH },
12031  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_197_CHECKER_TYPE,
12032  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_197_WIDTH },
12033  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_198_CHECKER_TYPE,
12034  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_198_WIDTH },
12035  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_199_CHECKER_TYPE,
12036  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_199_WIDTH },
12037  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_200_CHECKER_TYPE,
12038  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_200_WIDTH },
12039  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_201_CHECKER_TYPE,
12040  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_201_WIDTH },
12041  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_202_CHECKER_TYPE,
12042  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_202_WIDTH },
12043  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_203_CHECKER_TYPE,
12044  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_203_WIDTH },
12045  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_204_CHECKER_TYPE,
12046  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_204_WIDTH },
12047  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_205_CHECKER_TYPE,
12048  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_205_WIDTH },
12049  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_206_CHECKER_TYPE,
12050  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_206_WIDTH },
12051  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_207_CHECKER_TYPE,
12052  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_207_WIDTH },
12053  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_208_CHECKER_TYPE,
12054  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_208_WIDTH },
12055  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_209_CHECKER_TYPE,
12056  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_209_WIDTH },
12057  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_210_CHECKER_TYPE,
12058  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_210_WIDTH },
12059  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_211_CHECKER_TYPE,
12060  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_211_WIDTH },
12061  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_212_CHECKER_TYPE,
12062  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_212_WIDTH },
12063  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_213_CHECKER_TYPE,
12064  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_213_WIDTH },
12065  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_214_CHECKER_TYPE,
12066  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_214_WIDTH },
12067  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_215_CHECKER_TYPE,
12068  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_215_WIDTH },
12069  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_216_CHECKER_TYPE,
12070  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_216_WIDTH },
12071  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_217_CHECKER_TYPE,
12072  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_217_WIDTH },
12073  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_218_CHECKER_TYPE,
12074  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_218_WIDTH },
12075  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_219_CHECKER_TYPE,
12076  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_219_WIDTH },
12077  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_220_CHECKER_TYPE,
12078  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_220_WIDTH },
12079  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_221_CHECKER_TYPE,
12080  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_221_WIDTH },
12081  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_222_CHECKER_TYPE,
12082  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_222_WIDTH },
12083  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_223_CHECKER_TYPE,
12084  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_223_WIDTH },
12085  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_224_CHECKER_TYPE,
12086  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_224_WIDTH },
12087  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_225_CHECKER_TYPE,
12088  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_225_WIDTH },
12089  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_226_CHECKER_TYPE,
12090  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_226_WIDTH },
12091  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_227_CHECKER_TYPE,
12092  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_227_WIDTH },
12093  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_228_CHECKER_TYPE,
12094  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_228_WIDTH },
12095  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_229_CHECKER_TYPE,
12096  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_229_WIDTH },
12097  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_230_CHECKER_TYPE,
12098  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_230_WIDTH },
12099  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_231_CHECKER_TYPE,
12100  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_231_WIDTH },
12101  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_232_CHECKER_TYPE,
12102  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_232_WIDTH },
12103  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_233_CHECKER_TYPE,
12104  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_233_WIDTH },
12105  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_234_CHECKER_TYPE,
12106  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_234_WIDTH },
12107  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_235_CHECKER_TYPE,
12108  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_235_WIDTH },
12109  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_236_CHECKER_TYPE,
12110  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_236_WIDTH },
12111  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_237_CHECKER_TYPE,
12112  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_237_WIDTH },
12113  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_238_CHECKER_TYPE,
12114  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_238_WIDTH },
12115  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_239_CHECKER_TYPE,
12116  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_239_WIDTH },
12117  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_240_CHECKER_TYPE,
12118  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_240_WIDTH },
12119  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_241_CHECKER_TYPE,
12120  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_241_WIDTH },
12121  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_242_CHECKER_TYPE,
12122  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_242_WIDTH },
12123  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_243_CHECKER_TYPE,
12124  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_243_WIDTH },
12125  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_244_CHECKER_TYPE,
12126  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_244_WIDTH },
12127  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_245_CHECKER_TYPE,
12128  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_245_WIDTH },
12129  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_246_CHECKER_TYPE,
12130  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_246_WIDTH },
12131  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_247_CHECKER_TYPE,
12132  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_247_WIDTH },
12133  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_248_CHECKER_TYPE,
12134  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_248_WIDTH },
12135  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_249_CHECKER_TYPE,
12136  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_249_WIDTH },
12137  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_250_CHECKER_TYPE,
12138  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_250_WIDTH },
12139  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_251_CHECKER_TYPE,
12140  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_251_WIDTH },
12141  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_252_CHECKER_TYPE,
12142  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_252_WIDTH },
12143  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_253_CHECKER_TYPE,
12144  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_253_WIDTH },
12145  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_254_CHECKER_TYPE,
12146  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_254_WIDTH },
12147  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_255_CHECKER_TYPE,
12148  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_255_WIDTH },
12149 };
12150 
12156 static const SDL_GrpChkConfig_t SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_groupEntries[SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_MAX_NUM_CHECKERS] =
12157 {
12158  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_0_CHECKER_TYPE,
12159  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_0_WIDTH },
12160  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_1_CHECKER_TYPE,
12161  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_1_WIDTH },
12162  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_2_CHECKER_TYPE,
12163  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_2_WIDTH },
12164  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_3_CHECKER_TYPE,
12165  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_3_WIDTH },
12166  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_4_CHECKER_TYPE,
12167  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_4_WIDTH },
12168  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_5_CHECKER_TYPE,
12169  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_5_WIDTH },
12170  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_6_CHECKER_TYPE,
12171  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_6_WIDTH },
12172  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_7_CHECKER_TYPE,
12173  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_7_WIDTH },
12174  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_8_CHECKER_TYPE,
12175  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_8_WIDTH },
12176  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_9_CHECKER_TYPE,
12177  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_9_WIDTH },
12178  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_10_CHECKER_TYPE,
12179  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_10_WIDTH },
12180  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_11_CHECKER_TYPE,
12181  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_11_WIDTH },
12182  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_12_CHECKER_TYPE,
12183  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_12_WIDTH },
12184  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_13_CHECKER_TYPE,
12185  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_13_WIDTH },
12186  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_14_CHECKER_TYPE,
12187  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_14_WIDTH },
12188  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_15_CHECKER_TYPE,
12189  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_15_WIDTH },
12190  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_16_CHECKER_TYPE,
12191  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_16_WIDTH },
12192  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_17_CHECKER_TYPE,
12193  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_17_WIDTH },
12194  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_18_CHECKER_TYPE,
12195  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_18_WIDTH },
12196  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_19_CHECKER_TYPE,
12197  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_19_WIDTH },
12198  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_20_CHECKER_TYPE,
12199  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_20_WIDTH },
12200  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_21_CHECKER_TYPE,
12201  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_21_WIDTH },
12202  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_22_CHECKER_TYPE,
12203  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_22_WIDTH },
12204  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_23_CHECKER_TYPE,
12205  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_23_WIDTH },
12206  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_24_CHECKER_TYPE,
12207  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_24_WIDTH },
12208  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_25_CHECKER_TYPE,
12209  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_25_WIDTH },
12210  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_26_CHECKER_TYPE,
12211  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_26_WIDTH },
12212  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_27_CHECKER_TYPE,
12213  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_27_WIDTH },
12214  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_28_CHECKER_TYPE,
12215  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_28_WIDTH },
12216  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_29_CHECKER_TYPE,
12217  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_29_WIDTH },
12218  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_30_CHECKER_TYPE,
12219  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_30_WIDTH },
12220  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_31_CHECKER_TYPE,
12221  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_31_WIDTH },
12222  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_32_CHECKER_TYPE,
12223  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_32_WIDTH },
12224  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_33_CHECKER_TYPE,
12225  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_33_WIDTH },
12226  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_34_CHECKER_TYPE,
12227  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_34_WIDTH },
12228  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_35_CHECKER_TYPE,
12229  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_35_WIDTH },
12230  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_36_CHECKER_TYPE,
12231  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_36_WIDTH },
12232  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_37_CHECKER_TYPE,
12233  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_37_WIDTH },
12234  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_38_CHECKER_TYPE,
12235  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_38_WIDTH },
12236  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_39_CHECKER_TYPE,
12237  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_39_WIDTH },
12238  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_40_CHECKER_TYPE,
12239  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_40_WIDTH },
12240  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_41_CHECKER_TYPE,
12241  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_41_WIDTH },
12242  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_42_CHECKER_TYPE,
12243  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_42_WIDTH },
12244  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_43_CHECKER_TYPE,
12245  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_43_WIDTH },
12246  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_44_CHECKER_TYPE,
12247  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_44_WIDTH },
12248  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_45_CHECKER_TYPE,
12249  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_45_WIDTH },
12250  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_46_CHECKER_TYPE,
12251  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_46_WIDTH },
12252  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_47_CHECKER_TYPE,
12253  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_47_WIDTH },
12254  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_48_CHECKER_TYPE,
12255  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_48_WIDTH },
12256  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_49_CHECKER_TYPE,
12257  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_49_WIDTH },
12258  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_50_CHECKER_TYPE,
12259  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_50_WIDTH },
12260  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_51_CHECKER_TYPE,
12261  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_51_WIDTH },
12262  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_52_CHECKER_TYPE,
12263  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_52_WIDTH },
12264  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_53_CHECKER_TYPE,
12265  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_53_WIDTH },
12266  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_54_CHECKER_TYPE,
12267  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_54_WIDTH },
12268  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_55_CHECKER_TYPE,
12269  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_55_WIDTH },
12270  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_56_CHECKER_TYPE,
12271  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_56_WIDTH },
12272  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_57_CHECKER_TYPE,
12273  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_57_WIDTH },
12274  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_58_CHECKER_TYPE,
12275  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_58_WIDTH },
12276  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_59_CHECKER_TYPE,
12277  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_59_WIDTH },
12278  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_60_CHECKER_TYPE,
12279  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_60_WIDTH },
12280  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_61_CHECKER_TYPE,
12281  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_61_WIDTH },
12282  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_62_CHECKER_TYPE,
12283  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_62_WIDTH },
12284  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_63_CHECKER_TYPE,
12285  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_63_WIDTH },
12286  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_64_CHECKER_TYPE,
12287  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_64_WIDTH },
12288  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_65_CHECKER_TYPE,
12289  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_65_WIDTH },
12290  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_66_CHECKER_TYPE,
12291  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_66_WIDTH },
12292  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_67_CHECKER_TYPE,
12293  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_67_WIDTH },
12294  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_68_CHECKER_TYPE,
12295  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_68_WIDTH },
12296  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_69_CHECKER_TYPE,
12297  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_69_WIDTH },
12298  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_70_CHECKER_TYPE,
12299  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_70_WIDTH },
12300  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_71_CHECKER_TYPE,
12301  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_71_WIDTH },
12302  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_72_CHECKER_TYPE,
12303  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_72_WIDTH },
12304  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_73_CHECKER_TYPE,
12305  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_73_WIDTH },
12306  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_74_CHECKER_TYPE,
12307  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_74_WIDTH },
12308  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_75_CHECKER_TYPE,
12309  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_75_WIDTH },
12310  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_76_CHECKER_TYPE,
12311  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_76_WIDTH },
12312  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_77_CHECKER_TYPE,
12313  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_77_WIDTH },
12314  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_78_CHECKER_TYPE,
12315  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_78_WIDTH },
12316  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_79_CHECKER_TYPE,
12317  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_79_WIDTH },
12318  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_80_CHECKER_TYPE,
12319  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_80_WIDTH },
12320  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_81_CHECKER_TYPE,
12321  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_81_WIDTH },
12322  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_82_CHECKER_TYPE,
12323  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_82_WIDTH },
12324  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_83_CHECKER_TYPE,
12325  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_83_WIDTH },
12326  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_84_CHECKER_TYPE,
12327  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_84_WIDTH },
12328  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_85_CHECKER_TYPE,
12329  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_85_WIDTH },
12330  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_86_CHECKER_TYPE,
12331  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_86_WIDTH },
12332  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_87_CHECKER_TYPE,
12333  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_87_WIDTH },
12334  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_88_CHECKER_TYPE,
12335  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_88_WIDTH },
12336  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_89_CHECKER_TYPE,
12337  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_89_WIDTH },
12338  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_90_CHECKER_TYPE,
12339  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_90_WIDTH },
12340  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_91_CHECKER_TYPE,
12341  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_91_WIDTH },
12342  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_92_CHECKER_TYPE,
12343  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_92_WIDTH },
12344  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_93_CHECKER_TYPE,
12345  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_93_WIDTH },
12346  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_94_CHECKER_TYPE,
12347  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_94_WIDTH },
12348  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_95_CHECKER_TYPE,
12349  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_95_WIDTH },
12350  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_96_CHECKER_TYPE,
12351  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_96_WIDTH },
12352  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_97_CHECKER_TYPE,
12353  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_97_WIDTH },
12354  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_98_CHECKER_TYPE,
12355  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_98_WIDTH },
12356  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_99_CHECKER_TYPE,
12357  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_99_WIDTH },
12358  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_100_CHECKER_TYPE,
12359  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_100_WIDTH },
12360  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_101_CHECKER_TYPE,
12361  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_101_WIDTH },
12362  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_102_CHECKER_TYPE,
12363  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_102_WIDTH },
12364  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_103_CHECKER_TYPE,
12365  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_103_WIDTH },
12366  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_104_CHECKER_TYPE,
12367  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_104_WIDTH },
12368  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_105_CHECKER_TYPE,
12369  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_105_WIDTH },
12370  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_106_CHECKER_TYPE,
12371  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_106_WIDTH },
12372  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_107_CHECKER_TYPE,
12373  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_107_WIDTH },
12374  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_108_CHECKER_TYPE,
12375  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_108_WIDTH },
12376  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_109_CHECKER_TYPE,
12377  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_109_WIDTH },
12378  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_110_CHECKER_TYPE,
12379  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_110_WIDTH },
12380  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_111_CHECKER_TYPE,
12381  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_111_WIDTH },
12382  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_112_CHECKER_TYPE,
12383  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_112_WIDTH },
12384  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_113_CHECKER_TYPE,
12385  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_113_WIDTH },
12386  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_114_CHECKER_TYPE,
12387  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_114_WIDTH },
12388  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_115_CHECKER_TYPE,
12389  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_115_WIDTH },
12390  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_116_CHECKER_TYPE,
12391  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_116_WIDTH },
12392  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_117_CHECKER_TYPE,
12393  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_117_WIDTH },
12394  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_118_CHECKER_TYPE,
12395  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_118_WIDTH },
12396  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_119_CHECKER_TYPE,
12397  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_119_WIDTH },
12398  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_120_CHECKER_TYPE,
12399  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_120_WIDTH },
12400  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_121_CHECKER_TYPE,
12401  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_121_WIDTH },
12402  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_122_CHECKER_TYPE,
12403  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_122_WIDTH },
12404  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_123_CHECKER_TYPE,
12405  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_123_WIDTH },
12406  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_124_CHECKER_TYPE,
12407  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_124_WIDTH },
12408  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_125_CHECKER_TYPE,
12409  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_125_WIDTH },
12410  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_126_CHECKER_TYPE,
12411  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_126_WIDTH },
12412  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_127_CHECKER_TYPE,
12413  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_127_WIDTH },
12414  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_128_CHECKER_TYPE,
12415  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_128_WIDTH },
12416  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_129_CHECKER_TYPE,
12417  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_129_WIDTH },
12418  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_130_CHECKER_TYPE,
12419  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_130_WIDTH },
12420  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_131_CHECKER_TYPE,
12421  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_131_WIDTH },
12422  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_132_CHECKER_TYPE,
12423  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_132_WIDTH },
12424  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_133_CHECKER_TYPE,
12425  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_133_WIDTH },
12426  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_134_CHECKER_TYPE,
12427  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_134_WIDTH },
12428  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_135_CHECKER_TYPE,
12429  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_135_WIDTH },
12430  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_136_CHECKER_TYPE,
12431  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_136_WIDTH },
12432  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_137_CHECKER_TYPE,
12433  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_137_WIDTH },
12434  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_138_CHECKER_TYPE,
12435  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_138_WIDTH },
12436  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_139_CHECKER_TYPE,
12437  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_139_WIDTH },
12438  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_140_CHECKER_TYPE,
12439  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_140_WIDTH },
12440  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_141_CHECKER_TYPE,
12441  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_141_WIDTH },
12442  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_142_CHECKER_TYPE,
12443  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_142_WIDTH },
12444  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_143_CHECKER_TYPE,
12445  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_143_WIDTH },
12446  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_144_CHECKER_TYPE,
12447  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_144_WIDTH },
12448  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_145_CHECKER_TYPE,
12449  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_145_WIDTH },
12450  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_146_CHECKER_TYPE,
12451  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_146_WIDTH },
12452  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_147_CHECKER_TYPE,
12453  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_147_WIDTH },
12454  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_148_CHECKER_TYPE,
12455  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_148_WIDTH },
12456  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_149_CHECKER_TYPE,
12457  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_149_WIDTH },
12458  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_150_CHECKER_TYPE,
12459  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_150_WIDTH },
12460  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_151_CHECKER_TYPE,
12461  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_151_WIDTH },
12462  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_152_CHECKER_TYPE,
12463  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_152_WIDTH },
12464  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_153_CHECKER_TYPE,
12465  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_153_WIDTH },
12466  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_154_CHECKER_TYPE,
12467  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_154_WIDTH },
12468  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_155_CHECKER_TYPE,
12469  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_155_WIDTH },
12470  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_156_CHECKER_TYPE,
12471  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_156_WIDTH },
12472  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_157_CHECKER_TYPE,
12473  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_157_WIDTH },
12474  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_158_CHECKER_TYPE,
12475  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_158_WIDTH },
12476  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_159_CHECKER_TYPE,
12477  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_159_WIDTH },
12478  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_160_CHECKER_TYPE,
12479  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_160_WIDTH },
12480  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_161_CHECKER_TYPE,
12481  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_161_WIDTH },
12482  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_162_CHECKER_TYPE,
12483  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_162_WIDTH },
12484  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_163_CHECKER_TYPE,
12485  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_163_WIDTH },
12486  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_164_CHECKER_TYPE,
12487  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_164_WIDTH },
12488  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_165_CHECKER_TYPE,
12489  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_165_WIDTH },
12490  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_166_CHECKER_TYPE,
12491  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_166_WIDTH },
12492  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_167_CHECKER_TYPE,
12493  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_167_WIDTH },
12494  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_168_CHECKER_TYPE,
12495  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_168_WIDTH },
12496  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_169_CHECKER_TYPE,
12497  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_169_WIDTH },
12498  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_170_CHECKER_TYPE,
12499  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_170_WIDTH },
12500  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_171_CHECKER_TYPE,
12501  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_171_WIDTH },
12502  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_172_CHECKER_TYPE,
12503  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_172_WIDTH },
12504  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_173_CHECKER_TYPE,
12505  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_173_WIDTH },
12506  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_174_CHECKER_TYPE,
12507  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_174_WIDTH },
12508  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_175_CHECKER_TYPE,
12509  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_175_WIDTH },
12510  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_176_CHECKER_TYPE,
12511  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_176_WIDTH },
12512  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_177_CHECKER_TYPE,
12513  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_177_WIDTH },
12514  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_178_CHECKER_TYPE,
12515  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_178_WIDTH },
12516  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_179_CHECKER_TYPE,
12517  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_179_WIDTH },
12518  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_180_CHECKER_TYPE,
12519  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_180_WIDTH },
12520  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_181_CHECKER_TYPE,
12521  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_181_WIDTH },
12522  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_182_CHECKER_TYPE,
12523  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_182_WIDTH },
12524  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_183_CHECKER_TYPE,
12525  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_183_WIDTH },
12526  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_184_CHECKER_TYPE,
12527  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_184_WIDTH },
12528  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_185_CHECKER_TYPE,
12529  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_185_WIDTH },
12530  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_186_CHECKER_TYPE,
12531  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_186_WIDTH },
12532  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_187_CHECKER_TYPE,
12533  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_187_WIDTH },
12534  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_188_CHECKER_TYPE,
12535  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_188_WIDTH },
12536  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_189_CHECKER_TYPE,
12537  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_189_WIDTH },
12538  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_190_CHECKER_TYPE,
12539  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_190_WIDTH },
12540  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_191_CHECKER_TYPE,
12541  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_191_WIDTH },
12542  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_192_CHECKER_TYPE,
12543  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_192_WIDTH },
12544  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_193_CHECKER_TYPE,
12545  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_193_WIDTH },
12546  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_194_CHECKER_TYPE,
12547  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_194_WIDTH },
12548  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_195_CHECKER_TYPE,
12549  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_195_WIDTH },
12550  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_196_CHECKER_TYPE,
12551  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_196_WIDTH },
12552  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_197_CHECKER_TYPE,
12553  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_197_WIDTH },
12554  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_198_CHECKER_TYPE,
12555  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_198_WIDTH },
12556  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_199_CHECKER_TYPE,
12557  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_199_WIDTH },
12558  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_200_CHECKER_TYPE,
12559  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_200_WIDTH },
12560  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_201_CHECKER_TYPE,
12561  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_201_WIDTH },
12562  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_202_CHECKER_TYPE,
12563  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_202_WIDTH },
12564  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_203_CHECKER_TYPE,
12565  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_203_WIDTH },
12566  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_204_CHECKER_TYPE,
12567  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_204_WIDTH },
12568  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_205_CHECKER_TYPE,
12569  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_205_WIDTH },
12570  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_206_CHECKER_TYPE,
12571  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_206_WIDTH },
12572  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_207_CHECKER_TYPE,
12573  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_207_WIDTH },
12574  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_208_CHECKER_TYPE,
12575  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_208_WIDTH },
12576  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_209_CHECKER_TYPE,
12577  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_209_WIDTH },
12578  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_210_CHECKER_TYPE,
12579  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_210_WIDTH },
12580  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_211_CHECKER_TYPE,
12581  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_211_WIDTH },
12582  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_212_CHECKER_TYPE,
12583  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_212_WIDTH },
12584  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_213_CHECKER_TYPE,
12585  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_213_WIDTH },
12586  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_214_CHECKER_TYPE,
12587  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_214_WIDTH },
12588  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_215_CHECKER_TYPE,
12589  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_215_WIDTH },
12590  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_216_CHECKER_TYPE,
12591  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_216_WIDTH },
12592  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_217_CHECKER_TYPE,
12593  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_217_WIDTH },
12594  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_218_CHECKER_TYPE,
12595  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_218_WIDTH },
12596  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_219_CHECKER_TYPE,
12597  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_219_WIDTH },
12598  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_220_CHECKER_TYPE,
12599  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_220_WIDTH },
12600  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_221_CHECKER_TYPE,
12601  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_221_WIDTH },
12602  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_222_CHECKER_TYPE,
12603  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_222_WIDTH },
12604  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_223_CHECKER_TYPE,
12605  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_223_WIDTH },
12606  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_224_CHECKER_TYPE,
12607  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_224_WIDTH },
12608  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_225_CHECKER_TYPE,
12609  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_225_WIDTH },
12610  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_226_CHECKER_TYPE,
12611  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_226_WIDTH },
12612  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_227_CHECKER_TYPE,
12613  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_227_WIDTH },
12614  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_228_CHECKER_TYPE,
12615  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_228_WIDTH },
12616  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_229_CHECKER_TYPE,
12617  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_229_WIDTH },
12618  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_230_CHECKER_TYPE,
12619  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_230_WIDTH },
12620  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_231_CHECKER_TYPE,
12621  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_231_WIDTH },
12622  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_232_CHECKER_TYPE,
12623  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_232_WIDTH },
12624  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_233_CHECKER_TYPE,
12625  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_233_WIDTH },
12626  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_234_CHECKER_TYPE,
12627  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_234_WIDTH },
12628  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_235_CHECKER_TYPE,
12629  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_235_WIDTH },
12630  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_236_CHECKER_TYPE,
12631  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_236_WIDTH },
12632  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_237_CHECKER_TYPE,
12633  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_237_WIDTH },
12634  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_238_CHECKER_TYPE,
12635  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_238_WIDTH },
12636  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_239_CHECKER_TYPE,
12637  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_239_WIDTH },
12638  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_240_CHECKER_TYPE,
12639  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_240_WIDTH },
12640  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_241_CHECKER_TYPE,
12641  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_241_WIDTH },
12642  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_242_CHECKER_TYPE,
12643  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_242_WIDTH },
12644  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_243_CHECKER_TYPE,
12645  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_243_WIDTH },
12646  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_244_CHECKER_TYPE,
12647  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_244_WIDTH },
12648  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_245_CHECKER_TYPE,
12649  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_245_WIDTH },
12650  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_246_CHECKER_TYPE,
12651  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_246_WIDTH },
12652  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_247_CHECKER_TYPE,
12653  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_247_WIDTH },
12654  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_248_CHECKER_TYPE,
12655  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_248_WIDTH },
12656  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_249_CHECKER_TYPE,
12657  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_249_WIDTH },
12658  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_250_CHECKER_TYPE,
12659  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_250_WIDTH },
12660  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_251_CHECKER_TYPE,
12661  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_251_WIDTH },
12662  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_252_CHECKER_TYPE,
12663  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_252_WIDTH },
12664  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_253_CHECKER_TYPE,
12665  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_253_WIDTH },
12666  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_254_CHECKER_TYPE,
12667  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_254_WIDTH },
12668  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_255_CHECKER_TYPE,
12669  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_255_WIDTH },
12670 };
12671 
12677 static const SDL_GrpChkConfig_t SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_groupEntries[SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_MAX_NUM_CHECKERS] =
12678 {
12679  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_0_CHECKER_TYPE,
12680  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_0_WIDTH },
12681  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_1_CHECKER_TYPE,
12682  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_1_WIDTH },
12683  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_2_CHECKER_TYPE,
12684  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_2_WIDTH },
12685  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_3_CHECKER_TYPE,
12686  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_3_WIDTH },
12687  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_4_CHECKER_TYPE,
12688  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_4_WIDTH },
12689  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_5_CHECKER_TYPE,
12690  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_5_WIDTH },
12691  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_6_CHECKER_TYPE,
12692  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_6_WIDTH },
12693  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_7_CHECKER_TYPE,
12694  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_7_WIDTH },
12695  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_8_CHECKER_TYPE,
12696  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_8_WIDTH },
12697  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_9_CHECKER_TYPE,
12698  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_9_WIDTH },
12699  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_10_CHECKER_TYPE,
12700  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_10_WIDTH },
12701  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_11_CHECKER_TYPE,
12702  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_11_WIDTH },
12703  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_12_CHECKER_TYPE,
12704  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_12_WIDTH },
12705  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_13_CHECKER_TYPE,
12706  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_13_WIDTH },
12707  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_14_CHECKER_TYPE,
12708  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_14_WIDTH },
12709  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_15_CHECKER_TYPE,
12710  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_15_WIDTH },
12711  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_16_CHECKER_TYPE,
12712  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_16_WIDTH },
12713  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_17_CHECKER_TYPE,
12714  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_17_WIDTH },
12715  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_18_CHECKER_TYPE,
12716  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_18_WIDTH },
12717  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_19_CHECKER_TYPE,
12718  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_19_WIDTH },
12719  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_20_CHECKER_TYPE,
12720  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_20_WIDTH },
12721  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_21_CHECKER_TYPE,
12722  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_21_WIDTH },
12723  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_22_CHECKER_TYPE,
12724  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_22_WIDTH },
12725  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_23_CHECKER_TYPE,
12726  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_23_WIDTH },
12727  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_24_CHECKER_TYPE,
12728  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_24_WIDTH },
12729  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_25_CHECKER_TYPE,
12730  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_25_WIDTH },
12731  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_26_CHECKER_TYPE,
12732  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_26_WIDTH },
12733  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_27_CHECKER_TYPE,
12734  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_27_WIDTH },
12735  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_28_CHECKER_TYPE,
12736  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_28_WIDTH },
12737  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_29_CHECKER_TYPE,
12738  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_29_WIDTH },
12739  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_30_CHECKER_TYPE,
12740  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_30_WIDTH },
12741  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_31_CHECKER_TYPE,
12742  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_31_WIDTH },
12743  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_32_CHECKER_TYPE,
12744  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_32_WIDTH },
12745  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_33_CHECKER_TYPE,
12746  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_33_WIDTH },
12747  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_34_CHECKER_TYPE,
12748  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_34_WIDTH },
12749  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_35_CHECKER_TYPE,
12750  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_35_WIDTH },
12751  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_36_CHECKER_TYPE,
12752  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_36_WIDTH },
12753  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_37_CHECKER_TYPE,
12754  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_37_WIDTH },
12755  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_38_CHECKER_TYPE,
12756  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_38_WIDTH },
12757  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_39_CHECKER_TYPE,
12758  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_39_WIDTH },
12759  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_40_CHECKER_TYPE,
12760  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_40_WIDTH },
12761  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_41_CHECKER_TYPE,
12762  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_41_WIDTH },
12763  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_42_CHECKER_TYPE,
12764  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_42_WIDTH },
12765  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_43_CHECKER_TYPE,
12766  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_43_WIDTH },
12767  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_44_CHECKER_TYPE,
12768  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_44_WIDTH },
12769  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_45_CHECKER_TYPE,
12770  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_45_WIDTH },
12771  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_46_CHECKER_TYPE,
12772  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_46_WIDTH },
12773  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_47_CHECKER_TYPE,
12774  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_47_WIDTH },
12775  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_48_CHECKER_TYPE,
12776  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_48_WIDTH },
12777  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_49_CHECKER_TYPE,
12778  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_49_WIDTH },
12779  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_50_CHECKER_TYPE,
12780  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_50_WIDTH },
12781  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_51_CHECKER_TYPE,
12782  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_51_WIDTH },
12783  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_52_CHECKER_TYPE,
12784  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_52_WIDTH },
12785  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_53_CHECKER_TYPE,
12786  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_53_WIDTH },
12787  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_54_CHECKER_TYPE,
12788  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_54_WIDTH },
12789  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_55_CHECKER_TYPE,
12790  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_55_WIDTH },
12791  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_56_CHECKER_TYPE,
12792  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_56_WIDTH },
12793  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_57_CHECKER_TYPE,
12794  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_57_WIDTH },
12795  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_58_CHECKER_TYPE,
12796  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_58_WIDTH },
12797  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_59_CHECKER_TYPE,
12798  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_59_WIDTH },
12799  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_60_CHECKER_TYPE,
12800  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_60_WIDTH },
12801  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_61_CHECKER_TYPE,
12802  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_61_WIDTH },
12803  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_62_CHECKER_TYPE,
12804  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_62_WIDTH },
12805  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_63_CHECKER_TYPE,
12806  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_63_WIDTH },
12807  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_64_CHECKER_TYPE,
12808  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_64_WIDTH },
12809  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_65_CHECKER_TYPE,
12810  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_65_WIDTH },
12811  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_66_CHECKER_TYPE,
12812  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_66_WIDTH },
12813  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_67_CHECKER_TYPE,
12814  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_67_WIDTH },
12815  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_68_CHECKER_TYPE,
12816  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_68_WIDTH },
12817  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_69_CHECKER_TYPE,
12818  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_69_WIDTH },
12819  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_70_CHECKER_TYPE,
12820  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_70_WIDTH },
12821  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_71_CHECKER_TYPE,
12822  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_71_WIDTH },
12823  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_72_CHECKER_TYPE,
12824  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_72_WIDTH },
12825  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_73_CHECKER_TYPE,
12826  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_73_WIDTH },
12827  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_74_CHECKER_TYPE,
12828  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_74_WIDTH },
12829  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_75_CHECKER_TYPE,
12830  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_75_WIDTH },
12831  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_76_CHECKER_TYPE,
12832  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_76_WIDTH },
12833  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_77_CHECKER_TYPE,
12834  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_77_WIDTH },
12835  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_78_CHECKER_TYPE,
12836  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_78_WIDTH },
12837  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_79_CHECKER_TYPE,
12838  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_79_WIDTH },
12839  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_80_CHECKER_TYPE,
12840  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_80_WIDTH },
12841  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_81_CHECKER_TYPE,
12842  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_81_WIDTH },
12843  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_82_CHECKER_TYPE,
12844  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_82_WIDTH },
12845  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_83_CHECKER_TYPE,
12846  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_83_WIDTH },
12847  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_84_CHECKER_TYPE,
12848  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_84_WIDTH },
12849  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_85_CHECKER_TYPE,
12850  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_85_WIDTH },
12851  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_86_CHECKER_TYPE,
12852  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_86_WIDTH },
12853  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_87_CHECKER_TYPE,
12854  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_87_WIDTH },
12855  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_88_CHECKER_TYPE,
12856  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_88_WIDTH },
12857  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_89_CHECKER_TYPE,
12858  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_89_WIDTH },
12859  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_90_CHECKER_TYPE,
12860  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_90_WIDTH },
12861  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_91_CHECKER_TYPE,
12862  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_91_WIDTH },
12863  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_92_CHECKER_TYPE,
12864  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_92_WIDTH },
12865  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_93_CHECKER_TYPE,
12866  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_93_WIDTH },
12867  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_94_CHECKER_TYPE,
12868  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_94_WIDTH },
12869  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_95_CHECKER_TYPE,
12870  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_95_WIDTH },
12871  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_96_CHECKER_TYPE,
12872  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_96_WIDTH },
12873  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_97_CHECKER_TYPE,
12874  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_97_WIDTH },
12875  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_98_CHECKER_TYPE,
12876  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_98_WIDTH },
12877  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_99_CHECKER_TYPE,
12878  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_99_WIDTH },
12879  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_100_CHECKER_TYPE,
12880  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_100_WIDTH },
12881  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_101_CHECKER_TYPE,
12882  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_101_WIDTH },
12883  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_102_CHECKER_TYPE,
12884  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_102_WIDTH },
12885  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_103_CHECKER_TYPE,
12886  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_103_WIDTH },
12887  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_104_CHECKER_TYPE,
12888  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_104_WIDTH },
12889  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_105_CHECKER_TYPE,
12890  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_105_WIDTH },
12891  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_106_CHECKER_TYPE,
12892  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_106_WIDTH },
12893  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_107_CHECKER_TYPE,
12894  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_107_WIDTH },
12895  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_108_CHECKER_TYPE,
12896  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_108_WIDTH },
12897  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_109_CHECKER_TYPE,
12898  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_109_WIDTH },
12899  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_110_CHECKER_TYPE,
12900  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_110_WIDTH },
12901  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_111_CHECKER_TYPE,
12902  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_111_WIDTH },
12903  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_112_CHECKER_TYPE,
12904  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_112_WIDTH },
12905  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_113_CHECKER_TYPE,
12906  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_113_WIDTH },
12907  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_114_CHECKER_TYPE,
12908  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_114_WIDTH },
12909  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_115_CHECKER_TYPE,
12910  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_115_WIDTH },
12911  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_116_CHECKER_TYPE,
12912  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_116_WIDTH },
12913  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_117_CHECKER_TYPE,
12914  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_117_WIDTH },
12915  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_118_CHECKER_TYPE,
12916  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_118_WIDTH },
12917  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_119_CHECKER_TYPE,
12918  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_119_WIDTH },
12919  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_120_CHECKER_TYPE,
12920  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_120_WIDTH },
12921  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_121_CHECKER_TYPE,
12922  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_121_WIDTH },
12923  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_122_CHECKER_TYPE,
12924  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_122_WIDTH },
12925  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_123_CHECKER_TYPE,
12926  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_123_WIDTH },
12927  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_124_CHECKER_TYPE,
12928  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_124_WIDTH },
12929  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_125_CHECKER_TYPE,
12930  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_125_WIDTH },
12931  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_126_CHECKER_TYPE,
12932  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_126_WIDTH },
12933  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_127_CHECKER_TYPE,
12934  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_127_WIDTH },
12935  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_128_CHECKER_TYPE,
12936  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_128_WIDTH },
12937  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_129_CHECKER_TYPE,
12938  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_129_WIDTH },
12939  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_130_CHECKER_TYPE,
12940  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_130_WIDTH },
12941  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_131_CHECKER_TYPE,
12942  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_131_WIDTH },
12943  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_132_CHECKER_TYPE,
12944  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_132_WIDTH },
12945  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_133_CHECKER_TYPE,
12946  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_133_WIDTH },
12947  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_134_CHECKER_TYPE,
12948  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_134_WIDTH },
12949  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_135_CHECKER_TYPE,
12950  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_135_WIDTH },
12951  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_136_CHECKER_TYPE,
12952  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_136_WIDTH },
12953  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_137_CHECKER_TYPE,
12954  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_137_WIDTH },
12955  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_138_CHECKER_TYPE,
12956  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_138_WIDTH },
12957  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_139_CHECKER_TYPE,
12958  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_139_WIDTH },
12959  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_140_CHECKER_TYPE,
12960  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_140_WIDTH },
12961  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_141_CHECKER_TYPE,
12962  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_141_WIDTH },
12963  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_142_CHECKER_TYPE,
12964  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_142_WIDTH },
12965  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_143_CHECKER_TYPE,
12966  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_143_WIDTH },
12967  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_144_CHECKER_TYPE,
12968  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_144_WIDTH },
12969  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_145_CHECKER_TYPE,
12970  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_145_WIDTH },
12971  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_146_CHECKER_TYPE,
12972  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_146_WIDTH },
12973  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_147_CHECKER_TYPE,
12974  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_147_WIDTH },
12975  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_148_CHECKER_TYPE,
12976  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_148_WIDTH },
12977  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_149_CHECKER_TYPE,
12978  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_149_WIDTH },
12979  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_150_CHECKER_TYPE,
12980  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_150_WIDTH },
12981  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_151_CHECKER_TYPE,
12982  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_151_WIDTH },
12983  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_152_CHECKER_TYPE,
12984  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_152_WIDTH },
12985  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_153_CHECKER_TYPE,
12986  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_153_WIDTH },
12987  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_154_CHECKER_TYPE,
12988  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_154_WIDTH },
12989  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_155_CHECKER_TYPE,
12990  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_155_WIDTH },
12991  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_156_CHECKER_TYPE,
12992  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_156_WIDTH },
12993  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_157_CHECKER_TYPE,
12994  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_157_WIDTH },
12995  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_158_CHECKER_TYPE,
12996  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_158_WIDTH },
12997  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_159_CHECKER_TYPE,
12998  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_159_WIDTH },
12999  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_160_CHECKER_TYPE,
13000  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_160_WIDTH },
13001  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_161_CHECKER_TYPE,
13002  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_161_WIDTH },
13003  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_162_CHECKER_TYPE,
13004  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_162_WIDTH },
13005  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_163_CHECKER_TYPE,
13006  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_163_WIDTH },
13007  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_164_CHECKER_TYPE,
13008  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_164_WIDTH },
13009  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_165_CHECKER_TYPE,
13010  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_165_WIDTH },
13011  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_166_CHECKER_TYPE,
13012  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_166_WIDTH },
13013  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_167_CHECKER_TYPE,
13014  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_167_WIDTH },
13015  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_168_CHECKER_TYPE,
13016  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_168_WIDTH },
13017  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_169_CHECKER_TYPE,
13018  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_169_WIDTH },
13019  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_170_CHECKER_TYPE,
13020  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_170_WIDTH },
13021  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_171_CHECKER_TYPE,
13022  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_171_WIDTH },
13023 };
13024 
13030 static const SDL_GrpChkConfig_t SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_ISAM62A_DM2WS_VBUSM_GASKET_MCU_0_EDC_CTRL_groupEntries[SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_ISAM62A_DM2WS_VBUSM_GASKET_MCU_0_EDC_CTRL_MAX_NUM_CHECKERS] =
13031 {
13032  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_ISAM62A_DM2WS_VBUSM_GASKET_MCU_0_EDC_CTRL_GROUP_0_CHECKER_TYPE,
13033  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_ISAM62A_DM2WS_VBUSM_GASKET_MCU_0_EDC_CTRL_GROUP_0_WIDTH },
13034 };
13035 
13041 static const SDL_GrpChkConfig_t SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_IAM62A_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM62A_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_BRIDGE_BUSECC_groupEntries[SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_IAM62A_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM62A_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_BRIDGE_BUSECC_MAX_NUM_CHECKERS] =
13042 {
13043  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_IAM62A_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM62A_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_BRIDGE_BUSECC_GROUP_0_CHECKER_TYPE,
13044  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_IAM62A_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM62A_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_BRIDGE_BUSECC_GROUP_0_WIDTH },
13045  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_IAM62A_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM62A_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_BRIDGE_BUSECC_GROUP_1_CHECKER_TYPE,
13046  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_IAM62A_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM62A_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_BRIDGE_BUSECC_GROUP_1_WIDTH },
13047  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_IAM62A_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM62A_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_BRIDGE_BUSECC_GROUP_2_CHECKER_TYPE,
13048  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_IAM62A_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM62A_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_BRIDGE_BUSECC_GROUP_2_WIDTH },
13049  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_IAM62A_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM62A_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_BRIDGE_BUSECC_GROUP_3_CHECKER_TYPE,
13050  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_IAM62A_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM62A_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_BRIDGE_BUSECC_GROUP_3_WIDTH },
13051  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_IAM62A_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM62A_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_BRIDGE_BUSECC_GROUP_4_CHECKER_TYPE,
13052  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_IAM62A_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM62A_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_BRIDGE_BUSECC_GROUP_4_WIDTH },
13053  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_IAM62A_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM62A_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_BRIDGE_BUSECC_GROUP_5_CHECKER_TYPE,
13054  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_IAM62A_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM62A_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_BRIDGE_BUSECC_GROUP_5_WIDTH },
13055  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_IAM62A_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM62A_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_BRIDGE_BUSECC_GROUP_6_CHECKER_TYPE,
13056  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_IAM62A_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM62A_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_BRIDGE_BUSECC_GROUP_6_WIDTH },
13057  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_IAM62A_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM62A_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_BRIDGE_BUSECC_GROUP_7_CHECKER_TYPE,
13058  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_IAM62A_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM62A_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_BRIDGE_BUSECC_GROUP_7_WIDTH },
13059  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_IAM62A_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM62A_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_BRIDGE_BUSECC_GROUP_8_CHECKER_TYPE,
13060  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_IAM62A_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM62A_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_BRIDGE_BUSECC_GROUP_8_WIDTH },
13061  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_IAM62A_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM62A_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_BRIDGE_BUSECC_GROUP_9_CHECKER_TYPE,
13062  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_IAM62A_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM62A_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_BRIDGE_BUSECC_GROUP_9_WIDTH },
13063  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_IAM62A_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM62A_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_BRIDGE_BUSECC_GROUP_10_CHECKER_TYPE,
13064  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_IAM62A_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM62A_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_BRIDGE_BUSECC_GROUP_10_WIDTH },
13065  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_IAM62A_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM62A_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_BRIDGE_BUSECC_GROUP_11_CHECKER_TYPE,
13066  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_IAM62A_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM62A_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_BRIDGE_BUSECC_GROUP_11_WIDTH },
13067  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_IAM62A_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM62A_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_BRIDGE_BUSECC_GROUP_12_CHECKER_TYPE,
13068  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_IAM62A_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM62A_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_BRIDGE_BUSECC_GROUP_12_WIDTH },
13069 };
13070 
13076 static const SDL_GrpChkConfig_t SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ISAM62A_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM62A_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_BRIDGE_BUSECC_groupEntries[SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ISAM62A_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM62A_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_BRIDGE_BUSECC_MAX_NUM_CHECKERS] =
13077 {
13078  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ISAM62A_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM62A_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_BRIDGE_BUSECC_GROUP_0_CHECKER_TYPE,
13079  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ISAM62A_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM62A_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_BRIDGE_BUSECC_GROUP_0_WIDTH },
13080  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ISAM62A_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM62A_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_BRIDGE_BUSECC_GROUP_1_CHECKER_TYPE,
13081  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ISAM62A_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM62A_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_BRIDGE_BUSECC_GROUP_1_WIDTH },
13082  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ISAM62A_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM62A_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_BRIDGE_BUSECC_GROUP_2_CHECKER_TYPE,
13083  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ISAM62A_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM62A_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_BRIDGE_BUSECC_GROUP_2_WIDTH },
13084  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ISAM62A_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM62A_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_BRIDGE_BUSECC_GROUP_3_CHECKER_TYPE,
13085  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ISAM62A_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM62A_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_BRIDGE_BUSECC_GROUP_3_WIDTH },
13086  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ISAM62A_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM62A_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_BRIDGE_BUSECC_GROUP_4_CHECKER_TYPE,
13087  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ISAM62A_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM62A_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_BRIDGE_BUSECC_GROUP_4_WIDTH },
13088  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ISAM62A_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM62A_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_BRIDGE_BUSECC_GROUP_5_CHECKER_TYPE,
13089  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ISAM62A_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM62A_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_BRIDGE_BUSECC_GROUP_5_WIDTH },
13090  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ISAM62A_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM62A_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_BRIDGE_BUSECC_GROUP_6_CHECKER_TYPE,
13091  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ISAM62A_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM62A_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_BRIDGE_BUSECC_GROUP_6_WIDTH },
13092  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ISAM62A_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM62A_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_BRIDGE_BUSECC_GROUP_7_CHECKER_TYPE,
13093  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ISAM62A_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM62A_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_BRIDGE_BUSECC_GROUP_7_WIDTH },
13094  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ISAM62A_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM62A_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_BRIDGE_BUSECC_GROUP_8_CHECKER_TYPE,
13095  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ISAM62A_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM62A_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_BRIDGE_BUSECC_GROUP_8_WIDTH },
13096  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ISAM62A_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM62A_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_BRIDGE_BUSECC_GROUP_9_CHECKER_TYPE,
13097  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ISAM62A_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM62A_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_BRIDGE_BUSECC_GROUP_9_WIDTH },
13098  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ISAM62A_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM62A_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_BRIDGE_BUSECC_GROUP_10_CHECKER_TYPE,
13099  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ISAM62A_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM62A_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_BRIDGE_BUSECC_GROUP_10_WIDTH },
13100  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ISAM62A_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM62A_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_BRIDGE_BUSECC_GROUP_11_CHECKER_TYPE,
13101  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ISAM62A_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM62A_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_BRIDGE_BUSECC_GROUP_11_WIDTH },
13102  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ISAM62A_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM62A_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_BRIDGE_BUSECC_GROUP_12_CHECKER_TYPE,
13103  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ISAM62A_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM62A_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_BRIDGE_BUSECC_GROUP_12_WIDTH },
13104 };
13105 
13111 static const SDL_GrpChkConfig_t SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_groupEntries[SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_MAX_NUM_CHECKERS] =
13112 {
13113  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_0_CHECKER_TYPE,
13114  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_0_WIDTH },
13115  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_1_CHECKER_TYPE,
13116  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_1_WIDTH },
13117  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_2_CHECKER_TYPE,
13118  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_2_WIDTH },
13119  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_3_CHECKER_TYPE,
13120  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_3_WIDTH },
13121  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_4_CHECKER_TYPE,
13122  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_4_WIDTH },
13123  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_5_CHECKER_TYPE,
13124  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_5_WIDTH },
13125  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_6_CHECKER_TYPE,
13126  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_6_WIDTH },
13127  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_7_CHECKER_TYPE,
13128  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_7_WIDTH },
13129  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_8_CHECKER_TYPE,
13130  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_8_WIDTH },
13131  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_9_CHECKER_TYPE,
13132  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_9_WIDTH },
13133  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_10_CHECKER_TYPE,
13134  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_10_WIDTH },
13135  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_11_CHECKER_TYPE,
13136  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_11_WIDTH },
13137  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_12_CHECKER_TYPE,
13138  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_12_WIDTH },
13139  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_13_CHECKER_TYPE,
13140  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_13_WIDTH },
13141  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_14_CHECKER_TYPE,
13142  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_14_WIDTH },
13143  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_15_CHECKER_TYPE,
13144  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_15_WIDTH },
13145  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_16_CHECKER_TYPE,
13146  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_16_WIDTH },
13147  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_17_CHECKER_TYPE,
13148  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_17_WIDTH },
13149  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_18_CHECKER_TYPE,
13150  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_18_WIDTH },
13151  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_19_CHECKER_TYPE,
13152  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_19_WIDTH },
13153  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_20_CHECKER_TYPE,
13154  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_20_WIDTH },
13155  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_21_CHECKER_TYPE,
13156  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_21_WIDTH },
13157  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_22_CHECKER_TYPE,
13158  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_22_WIDTH },
13159  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_23_CHECKER_TYPE,
13160  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_23_WIDTH },
13161  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_24_CHECKER_TYPE,
13162  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_24_WIDTH },
13163  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_25_CHECKER_TYPE,
13164  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_25_WIDTH },
13165  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_26_CHECKER_TYPE,
13166  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_26_WIDTH },
13167  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_27_CHECKER_TYPE,
13168  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_27_WIDTH },
13169  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_28_CHECKER_TYPE,
13170  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_28_WIDTH },
13171  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_29_CHECKER_TYPE,
13172  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_29_WIDTH },
13173  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_30_CHECKER_TYPE,
13174  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_30_WIDTH },
13175  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_31_CHECKER_TYPE,
13176  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_31_WIDTH },
13177  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_32_CHECKER_TYPE,
13178  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_32_WIDTH },
13179  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_33_CHECKER_TYPE,
13180  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_33_WIDTH },
13181  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_34_CHECKER_TYPE,
13182  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_34_WIDTH },
13183  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_35_CHECKER_TYPE,
13184  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_35_WIDTH },
13185  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_36_CHECKER_TYPE,
13186  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_36_WIDTH },
13187  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_37_CHECKER_TYPE,
13188  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_37_WIDTH },
13189  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_38_CHECKER_TYPE,
13190  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_38_WIDTH },
13191  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_39_CHECKER_TYPE,
13192  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_39_WIDTH },
13193  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_40_CHECKER_TYPE,
13194  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_40_WIDTH },
13195  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_41_CHECKER_TYPE,
13196  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_41_WIDTH },
13197  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_42_CHECKER_TYPE,
13198  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_42_WIDTH },
13199  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_43_CHECKER_TYPE,
13200  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_43_WIDTH },
13201  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_44_CHECKER_TYPE,
13202  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_44_WIDTH },
13203  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_45_CHECKER_TYPE,
13204  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_45_WIDTH },
13205  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_46_CHECKER_TYPE,
13206  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_46_WIDTH },
13207  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_47_CHECKER_TYPE,
13208  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_47_WIDTH },
13209  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_48_CHECKER_TYPE,
13210  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_48_WIDTH },
13211  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_49_CHECKER_TYPE,
13212  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_49_WIDTH },
13213  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_50_CHECKER_TYPE,
13214  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_50_WIDTH },
13215  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_51_CHECKER_TYPE,
13216  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_51_WIDTH },
13217  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_52_CHECKER_TYPE,
13218  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_52_WIDTH },
13219  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_53_CHECKER_TYPE,
13220  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_53_WIDTH },
13221  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_54_CHECKER_TYPE,
13222  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_54_WIDTH },
13223  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_55_CHECKER_TYPE,
13224  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_55_WIDTH },
13225  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_56_CHECKER_TYPE,
13226  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_56_WIDTH },
13227  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_57_CHECKER_TYPE,
13228  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_57_WIDTH },
13229  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_58_CHECKER_TYPE,
13230  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_58_WIDTH },
13231  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_59_CHECKER_TYPE,
13232  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_59_WIDTH },
13233  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_60_CHECKER_TYPE,
13234  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_60_WIDTH },
13235  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_61_CHECKER_TYPE,
13236  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_61_WIDTH },
13237  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_62_CHECKER_TYPE,
13238  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_62_WIDTH },
13239  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_63_CHECKER_TYPE,
13240  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_63_WIDTH },
13241  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_64_CHECKER_TYPE,
13242  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_64_WIDTH },
13243  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_65_CHECKER_TYPE,
13244  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_65_WIDTH },
13245  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_66_CHECKER_TYPE,
13246  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_66_WIDTH },
13247  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_67_CHECKER_TYPE,
13248  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_67_WIDTH },
13249  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_68_CHECKER_TYPE,
13250  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_68_WIDTH },
13251  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_69_CHECKER_TYPE,
13252  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_69_WIDTH },
13253  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_70_CHECKER_TYPE,
13254  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_70_WIDTH },
13255  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_71_CHECKER_TYPE,
13256  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_71_WIDTH },
13257  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_72_CHECKER_TYPE,
13258  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_72_WIDTH },
13259  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_73_CHECKER_TYPE,
13260  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_73_WIDTH },
13261  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_74_CHECKER_TYPE,
13262  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_74_WIDTH },
13263  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_75_CHECKER_TYPE,
13264  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_75_WIDTH },
13265  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_76_CHECKER_TYPE,
13266  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_76_WIDTH },
13267  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_77_CHECKER_TYPE,
13268  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_77_WIDTH },
13269  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_78_CHECKER_TYPE,
13270  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_78_WIDTH },
13271  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_79_CHECKER_TYPE,
13272  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_79_WIDTH },
13273  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_80_CHECKER_TYPE,
13274  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_80_WIDTH },
13275  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_81_CHECKER_TYPE,
13276  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_81_WIDTH },
13277  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_82_CHECKER_TYPE,
13278  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_82_WIDTH },
13279  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_83_CHECKER_TYPE,
13280  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_83_WIDTH },
13281  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_84_CHECKER_TYPE,
13282  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_84_WIDTH },
13283  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_85_CHECKER_TYPE,
13284  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_85_WIDTH },
13285  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_86_CHECKER_TYPE,
13286  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_86_WIDTH },
13287  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_87_CHECKER_TYPE,
13288  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_87_WIDTH },
13289  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_88_CHECKER_TYPE,
13290  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_88_WIDTH },
13291  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_89_CHECKER_TYPE,
13292  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_89_WIDTH },
13293  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_90_CHECKER_TYPE,
13294  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_90_WIDTH },
13295  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_91_CHECKER_TYPE,
13296  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_91_WIDTH },
13297  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_92_CHECKER_TYPE,
13298  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_92_WIDTH },
13299  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_93_CHECKER_TYPE,
13300  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_93_WIDTH },
13301  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_94_CHECKER_TYPE,
13302  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_94_WIDTH },
13303  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_95_CHECKER_TYPE,
13304  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_95_WIDTH },
13305  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_96_CHECKER_TYPE,
13306  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_96_WIDTH },
13307  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_97_CHECKER_TYPE,
13308  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_97_WIDTH },
13309  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_98_CHECKER_TYPE,
13310  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_98_WIDTH },
13311  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_99_CHECKER_TYPE,
13312  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_99_WIDTH },
13313  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_100_CHECKER_TYPE,
13314  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_100_WIDTH },
13315  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_101_CHECKER_TYPE,
13316  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_101_WIDTH },
13317  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_102_CHECKER_TYPE,
13318  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_102_WIDTH },
13319  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_103_CHECKER_TYPE,
13320  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_103_WIDTH },
13321  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_104_CHECKER_TYPE,
13322  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_104_WIDTH },
13323  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_105_CHECKER_TYPE,
13324  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_105_WIDTH },
13325  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_106_CHECKER_TYPE,
13326  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_106_WIDTH },
13327  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_107_CHECKER_TYPE,
13328  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_107_WIDTH },
13329  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_108_CHECKER_TYPE,
13330  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_108_WIDTH },
13331  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_109_CHECKER_TYPE,
13332  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_109_WIDTH },
13333  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_110_CHECKER_TYPE,
13334  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_110_WIDTH },
13335  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_111_CHECKER_TYPE,
13336  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_111_WIDTH },
13337  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_112_CHECKER_TYPE,
13338  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_112_WIDTH },
13339  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_113_CHECKER_TYPE,
13340  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_113_WIDTH },
13341  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_114_CHECKER_TYPE,
13342  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_114_WIDTH },
13343  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_115_CHECKER_TYPE,
13344  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_115_WIDTH },
13345  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_116_CHECKER_TYPE,
13346  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_116_WIDTH },
13347  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_117_CHECKER_TYPE,
13348  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_117_WIDTH },
13349  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_118_CHECKER_TYPE,
13350  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_118_WIDTH },
13351  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_119_CHECKER_TYPE,
13352  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_119_WIDTH },
13353  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_120_CHECKER_TYPE,
13354  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_120_WIDTH },
13355 };
13356 
13362 static const SDL_GrpChkConfig_t SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_groupEntries[SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_MAX_NUM_CHECKERS] =
13363 {
13364  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_0_CHECKER_TYPE,
13365  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_0_WIDTH },
13366  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_1_CHECKER_TYPE,
13367  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_1_WIDTH },
13368  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_2_CHECKER_TYPE,
13369  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_2_WIDTH },
13370  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_3_CHECKER_TYPE,
13371  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_3_WIDTH },
13372  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_4_CHECKER_TYPE,
13373  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_4_WIDTH },
13374  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_5_CHECKER_TYPE,
13375  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_5_WIDTH },
13376  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_6_CHECKER_TYPE,
13377  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_6_WIDTH },
13378  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_7_CHECKER_TYPE,
13379  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_7_WIDTH },
13380  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_8_CHECKER_TYPE,
13381  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_8_WIDTH },
13382  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_9_CHECKER_TYPE,
13383  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_9_WIDTH },
13384  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_10_CHECKER_TYPE,
13385  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_10_WIDTH },
13386  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_11_CHECKER_TYPE,
13387  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_11_WIDTH },
13388  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_12_CHECKER_TYPE,
13389  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_12_WIDTH },
13390  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_13_CHECKER_TYPE,
13391  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_13_WIDTH },
13392  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_14_CHECKER_TYPE,
13393  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_14_WIDTH },
13394  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_15_CHECKER_TYPE,
13395  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_15_WIDTH },
13396  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_16_CHECKER_TYPE,
13397  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_16_WIDTH },
13398  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_17_CHECKER_TYPE,
13399  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_17_WIDTH },
13400  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_18_CHECKER_TYPE,
13401  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_18_WIDTH },
13402  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_19_CHECKER_TYPE,
13403  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_19_WIDTH },
13404  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_20_CHECKER_TYPE,
13405  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_20_WIDTH },
13406  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_21_CHECKER_TYPE,
13407  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_21_WIDTH },
13408  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_22_CHECKER_TYPE,
13409  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_22_WIDTH },
13410  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_23_CHECKER_TYPE,
13411  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_23_WIDTH },
13412  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_24_CHECKER_TYPE,
13413  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_24_WIDTH },
13414  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_25_CHECKER_TYPE,
13415  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_25_WIDTH },
13416  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_26_CHECKER_TYPE,
13417  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_26_WIDTH },
13418  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_27_CHECKER_TYPE,
13419  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_27_WIDTH },
13420  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_28_CHECKER_TYPE,
13421  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_28_WIDTH },
13422  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_29_CHECKER_TYPE,
13423  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_29_WIDTH },
13424  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_30_CHECKER_TYPE,
13425  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_30_WIDTH },
13426  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_31_CHECKER_TYPE,
13427  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_31_WIDTH },
13428  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_32_CHECKER_TYPE,
13429  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_32_WIDTH },
13430  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_33_CHECKER_TYPE,
13431  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_33_WIDTH },
13432  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_34_CHECKER_TYPE,
13433  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_34_WIDTH },
13434  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_35_CHECKER_TYPE,
13435  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_35_WIDTH },
13436  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_36_CHECKER_TYPE,
13437  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_36_WIDTH },
13438  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_37_CHECKER_TYPE,
13439  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_37_WIDTH },
13440  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_38_CHECKER_TYPE,
13441  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_38_WIDTH },
13442  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_39_CHECKER_TYPE,
13443  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_39_WIDTH },
13444  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_40_CHECKER_TYPE,
13445  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_40_WIDTH },
13446  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_41_CHECKER_TYPE,
13447  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_41_WIDTH },
13448  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_42_CHECKER_TYPE,
13449  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_42_WIDTH },
13450  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_43_CHECKER_TYPE,
13451  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_43_WIDTH },
13452  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_44_CHECKER_TYPE,
13453  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_44_WIDTH },
13454  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_45_CHECKER_TYPE,
13455  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_45_WIDTH },
13456  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_46_CHECKER_TYPE,
13457  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_46_WIDTH },
13458  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_47_CHECKER_TYPE,
13459  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_47_WIDTH },
13460  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_48_CHECKER_TYPE,
13461  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_48_WIDTH },
13462  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_49_CHECKER_TYPE,
13463  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_49_WIDTH },
13464  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_50_CHECKER_TYPE,
13465  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_50_WIDTH },
13466  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_51_CHECKER_TYPE,
13467  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_51_WIDTH },
13468  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_52_CHECKER_TYPE,
13469  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_52_WIDTH },
13470  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_53_CHECKER_TYPE,
13471  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_53_WIDTH },
13472  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_54_CHECKER_TYPE,
13473  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_54_WIDTH },
13474  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_55_CHECKER_TYPE,
13475  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_55_WIDTH },
13476  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_56_CHECKER_TYPE,
13477  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_56_WIDTH },
13478  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_57_CHECKER_TYPE,
13479  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_57_WIDTH },
13480  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_58_CHECKER_TYPE,
13481  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_58_WIDTH },
13482  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_59_CHECKER_TYPE,
13483  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_59_WIDTH },
13484  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_60_CHECKER_TYPE,
13485  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_60_WIDTH },
13486  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_61_CHECKER_TYPE,
13487  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_61_WIDTH },
13488  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_62_CHECKER_TYPE,
13489  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_62_WIDTH },
13490  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_63_CHECKER_TYPE,
13491  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_63_WIDTH },
13492  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_64_CHECKER_TYPE,
13493  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_64_WIDTH },
13494  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_65_CHECKER_TYPE,
13495  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_65_WIDTH },
13496  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_66_CHECKER_TYPE,
13497  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_66_WIDTH },
13498  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_67_CHECKER_TYPE,
13499  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_67_WIDTH },
13500  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_68_CHECKER_TYPE,
13501  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_68_WIDTH },
13502  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_69_CHECKER_TYPE,
13503  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_69_WIDTH },
13504  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_70_CHECKER_TYPE,
13505  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_70_WIDTH },
13506  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_71_CHECKER_TYPE,
13507  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_71_WIDTH },
13508  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_72_CHECKER_TYPE,
13509  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_72_WIDTH },
13510  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_73_CHECKER_TYPE,
13511  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_73_WIDTH },
13512  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_74_CHECKER_TYPE,
13513  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_74_WIDTH },
13514  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_75_CHECKER_TYPE,
13515  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_75_WIDTH },
13516  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_76_CHECKER_TYPE,
13517  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_76_WIDTH },
13518  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_77_CHECKER_TYPE,
13519  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_77_WIDTH },
13520  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_78_CHECKER_TYPE,
13521  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_78_WIDTH },
13522  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_79_CHECKER_TYPE,
13523  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_79_WIDTH },
13524  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_80_CHECKER_TYPE,
13525  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_80_WIDTH },
13526  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_81_CHECKER_TYPE,
13527  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_81_WIDTH },
13528  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_82_CHECKER_TYPE,
13529  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_82_WIDTH },
13530  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_83_CHECKER_TYPE,
13531  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_83_WIDTH },
13532  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_84_CHECKER_TYPE,
13533  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_84_WIDTH },
13534  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_85_CHECKER_TYPE,
13535  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_85_WIDTH },
13536  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_86_CHECKER_TYPE,
13537  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_86_WIDTH },
13538  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_87_CHECKER_TYPE,
13539  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_87_WIDTH },
13540  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_88_CHECKER_TYPE,
13541  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_88_WIDTH },
13542  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_89_CHECKER_TYPE,
13543  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_89_WIDTH },
13544  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_90_CHECKER_TYPE,
13545  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_90_WIDTH },
13546  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_91_CHECKER_TYPE,
13547  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_91_WIDTH },
13548  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_92_CHECKER_TYPE,
13549  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_92_WIDTH },
13550  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_93_CHECKER_TYPE,
13551  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_93_WIDTH },
13552  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_94_CHECKER_TYPE,
13553  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_94_WIDTH },
13554  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_95_CHECKER_TYPE,
13555  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_95_WIDTH },
13556  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_96_CHECKER_TYPE,
13557  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_96_WIDTH },
13558  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_97_CHECKER_TYPE,
13559  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_97_WIDTH },
13560  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_98_CHECKER_TYPE,
13561  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_98_WIDTH },
13562  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_99_CHECKER_TYPE,
13563  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_99_WIDTH },
13564  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_100_CHECKER_TYPE,
13565  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_100_WIDTH },
13566  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_101_CHECKER_TYPE,
13567  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_101_WIDTH },
13568  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_102_CHECKER_TYPE,
13569  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_102_WIDTH },
13570  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_103_CHECKER_TYPE,
13571  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_103_WIDTH },
13572  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_104_CHECKER_TYPE,
13573  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_104_WIDTH },
13574  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_105_CHECKER_TYPE,
13575  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_105_WIDTH },
13576  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_106_CHECKER_TYPE,
13577  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_106_WIDTH },
13578  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_107_CHECKER_TYPE,
13579  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_107_WIDTH },
13580  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_108_CHECKER_TYPE,
13581  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_108_WIDTH },
13582  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_109_CHECKER_TYPE,
13583  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_109_WIDTH },
13584  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_110_CHECKER_TYPE,
13585  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_110_WIDTH },
13586  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_111_CHECKER_TYPE,
13587  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_111_WIDTH },
13588  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_112_CHECKER_TYPE,
13589  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_112_WIDTH },
13590  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_113_CHECKER_TYPE,
13591  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_113_WIDTH },
13592  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_114_CHECKER_TYPE,
13593  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_114_WIDTH },
13594  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_115_CHECKER_TYPE,
13595  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_115_WIDTH },
13596  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_116_CHECKER_TYPE,
13597  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_116_WIDTH },
13598  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_117_CHECKER_TYPE,
13599  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_117_WIDTH },
13600  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_118_CHECKER_TYPE,
13601  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_118_WIDTH },
13602  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_119_CHECKER_TYPE,
13603  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_119_WIDTH },
13604  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_120_CHECKER_TYPE,
13605  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_120_WIDTH },
13606  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_121_CHECKER_TYPE,
13607  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_121_WIDTH },
13608  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_122_CHECKER_TYPE,
13609  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_122_WIDTH },
13610  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_123_CHECKER_TYPE,
13611  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_123_WIDTH },
13612  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_124_CHECKER_TYPE,
13613  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_124_WIDTH },
13614  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_125_CHECKER_TYPE,
13615  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_125_WIDTH },
13616  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_126_CHECKER_TYPE,
13617  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_126_WIDTH },
13618  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_127_CHECKER_TYPE,
13619  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_127_WIDTH },
13620  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_128_CHECKER_TYPE,
13621  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_128_WIDTH },
13622  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_129_CHECKER_TYPE,
13623  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_129_WIDTH },
13624  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_130_CHECKER_TYPE,
13625  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_130_WIDTH },
13626  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_131_CHECKER_TYPE,
13627  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_131_WIDTH },
13628  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_132_CHECKER_TYPE,
13629  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_132_WIDTH },
13630  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_133_CHECKER_TYPE,
13631  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_133_WIDTH },
13632  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_134_CHECKER_TYPE,
13633  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_134_WIDTH },
13634  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_135_CHECKER_TYPE,
13635  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_135_WIDTH },
13636  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_136_CHECKER_TYPE,
13637  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_136_WIDTH },
13638  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_137_CHECKER_TYPE,
13639  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_137_WIDTH },
13640  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_138_CHECKER_TYPE,
13641  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_138_WIDTH },
13642  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_139_CHECKER_TYPE,
13643  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_139_WIDTH },
13644  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_140_CHECKER_TYPE,
13645  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_140_WIDTH },
13646  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_141_CHECKER_TYPE,
13647  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_141_WIDTH },
13648  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_142_CHECKER_TYPE,
13649  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_142_WIDTH },
13650  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_143_CHECKER_TYPE,
13651  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_143_WIDTH },
13652  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_144_CHECKER_TYPE,
13653  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_144_WIDTH },
13654  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_145_CHECKER_TYPE,
13655  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_145_WIDTH },
13656  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_146_CHECKER_TYPE,
13657  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_146_WIDTH },
13658  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_147_CHECKER_TYPE,
13659  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_147_WIDTH },
13660  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_148_CHECKER_TYPE,
13661  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_148_WIDTH },
13662  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_149_CHECKER_TYPE,
13663  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_149_WIDTH },
13664  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_150_CHECKER_TYPE,
13665  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_150_WIDTH },
13666  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_151_CHECKER_TYPE,
13667  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_151_WIDTH },
13668  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_152_CHECKER_TYPE,
13669  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_152_WIDTH },
13670  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_153_CHECKER_TYPE,
13671  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_153_WIDTH },
13672  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_154_CHECKER_TYPE,
13673  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_154_WIDTH },
13674  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_155_CHECKER_TYPE,
13675  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_155_WIDTH },
13676  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_156_CHECKER_TYPE,
13677  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_156_WIDTH },
13678  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_157_CHECKER_TYPE,
13679  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_157_WIDTH },
13680  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_158_CHECKER_TYPE,
13681  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_158_WIDTH },
13682  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_159_CHECKER_TYPE,
13683  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_159_WIDTH },
13684  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_160_CHECKER_TYPE,
13685  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_160_WIDTH },
13686  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_161_CHECKER_TYPE,
13687  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_161_WIDTH },
13688  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_162_CHECKER_TYPE,
13689  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_162_WIDTH },
13690  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_163_CHECKER_TYPE,
13691  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_163_WIDTH },
13692  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_164_CHECKER_TYPE,
13693  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_164_WIDTH },
13694  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_165_CHECKER_TYPE,
13695  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_165_WIDTH },
13696  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_166_CHECKER_TYPE,
13697  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_166_WIDTH },
13698  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_167_CHECKER_TYPE,
13699  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_167_WIDTH },
13700  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_168_CHECKER_TYPE,
13701  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_168_WIDTH },
13702  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_169_CHECKER_TYPE,
13703  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_169_WIDTH },
13704  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_170_CHECKER_TYPE,
13705  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_170_WIDTH },
13706  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_171_CHECKER_TYPE,
13707  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_171_WIDTH },
13708  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_172_CHECKER_TYPE,
13709  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_172_WIDTH },
13710  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_173_CHECKER_TYPE,
13711  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_173_WIDTH },
13712  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_174_CHECKER_TYPE,
13713  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_174_WIDTH },
13714  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_175_CHECKER_TYPE,
13715  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_175_WIDTH },
13716  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_176_CHECKER_TYPE,
13717  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_176_WIDTH },
13718  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_177_CHECKER_TYPE,
13719  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_177_WIDTH },
13720  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_178_CHECKER_TYPE,
13721  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_178_WIDTH },
13722  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_179_CHECKER_TYPE,
13723  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_179_WIDTH },
13724  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_180_CHECKER_TYPE,
13725  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_180_WIDTH },
13726  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_181_CHECKER_TYPE,
13727  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_181_WIDTH },
13728  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_182_CHECKER_TYPE,
13729  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_182_WIDTH },
13730  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_183_CHECKER_TYPE,
13731  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_183_WIDTH },
13732  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_184_CHECKER_TYPE,
13733  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_184_WIDTH },
13734  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_185_CHECKER_TYPE,
13735  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_185_WIDTH },
13736  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_186_CHECKER_TYPE,
13737  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_186_WIDTH },
13738  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_187_CHECKER_TYPE,
13739  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_187_WIDTH },
13740  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_188_CHECKER_TYPE,
13741  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_188_WIDTH },
13742  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_189_CHECKER_TYPE,
13743  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_189_WIDTH },
13744  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_190_CHECKER_TYPE,
13745  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_190_WIDTH },
13746  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_191_CHECKER_TYPE,
13747  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_191_WIDTH },
13748  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_192_CHECKER_TYPE,
13749  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_192_WIDTH },
13750  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_193_CHECKER_TYPE,
13751  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_193_WIDTH },
13752  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_194_CHECKER_TYPE,
13753  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_194_WIDTH },
13754  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_195_CHECKER_TYPE,
13755  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_195_WIDTH },
13756  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_196_CHECKER_TYPE,
13757  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_196_WIDTH },
13758  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_197_CHECKER_TYPE,
13759  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_197_WIDTH },
13760  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_198_CHECKER_TYPE,
13761  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_198_WIDTH },
13762  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_199_CHECKER_TYPE,
13763  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_199_WIDTH },
13764  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_200_CHECKER_TYPE,
13765  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_200_WIDTH },
13766  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_201_CHECKER_TYPE,
13767  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_201_WIDTH },
13768  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_202_CHECKER_TYPE,
13769  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_202_WIDTH },
13770  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_203_CHECKER_TYPE,
13771  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_203_WIDTH },
13772  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_204_CHECKER_TYPE,
13773  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_204_WIDTH },
13774  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_205_CHECKER_TYPE,
13775  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_205_WIDTH },
13776  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_206_CHECKER_TYPE,
13777  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_206_WIDTH },
13778  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_207_CHECKER_TYPE,
13779  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_207_WIDTH },
13780  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_208_CHECKER_TYPE,
13781  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_208_WIDTH },
13782  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_209_CHECKER_TYPE,
13783  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_209_WIDTH },
13784  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_210_CHECKER_TYPE,
13785  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_210_WIDTH },
13786  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_211_CHECKER_TYPE,
13787  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_211_WIDTH },
13788  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_212_CHECKER_TYPE,
13789  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_212_WIDTH },
13790  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_213_CHECKER_TYPE,
13791  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_213_WIDTH },
13792  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_214_CHECKER_TYPE,
13793  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_214_WIDTH },
13794  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_215_CHECKER_TYPE,
13795  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_215_WIDTH },
13796  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_216_CHECKER_TYPE,
13797  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_216_WIDTH },
13798  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_217_CHECKER_TYPE,
13799  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_217_WIDTH },
13800  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_218_CHECKER_TYPE,
13801  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_218_WIDTH },
13802  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_219_CHECKER_TYPE,
13803  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_219_WIDTH },
13804  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_220_CHECKER_TYPE,
13805  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_220_WIDTH },
13806  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_221_CHECKER_TYPE,
13807  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_221_WIDTH },
13808  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_222_CHECKER_TYPE,
13809  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_222_WIDTH },
13810  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_223_CHECKER_TYPE,
13811  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_223_WIDTH },
13812  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_224_CHECKER_TYPE,
13813  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_224_WIDTH },
13814  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_225_CHECKER_TYPE,
13815  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_225_WIDTH },
13816  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_226_CHECKER_TYPE,
13817  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_226_WIDTH },
13818  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_227_CHECKER_TYPE,
13819  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_227_WIDTH },
13820  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_228_CHECKER_TYPE,
13821  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_228_WIDTH },
13822  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_229_CHECKER_TYPE,
13823  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_229_WIDTH },
13824  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_230_CHECKER_TYPE,
13825  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_230_WIDTH },
13826  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_231_CHECKER_TYPE,
13827  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_231_WIDTH },
13828  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_232_CHECKER_TYPE,
13829  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_232_WIDTH },
13830  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_233_CHECKER_TYPE,
13831  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_233_WIDTH },
13832  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_234_CHECKER_TYPE,
13833  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_234_WIDTH },
13834  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_235_CHECKER_TYPE,
13835  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_235_WIDTH },
13836  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_236_CHECKER_TYPE,
13837  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_236_WIDTH },
13838  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_237_CHECKER_TYPE,
13839  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_237_WIDTH },
13840  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_238_CHECKER_TYPE,
13841  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_238_WIDTH },
13842  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_239_CHECKER_TYPE,
13843  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_239_WIDTH },
13844  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_240_CHECKER_TYPE,
13845  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_240_WIDTH },
13846  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_241_CHECKER_TYPE,
13847  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_241_WIDTH },
13848  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_242_CHECKER_TYPE,
13849  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_242_WIDTH },
13850  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_243_CHECKER_TYPE,
13851  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_243_WIDTH },
13852  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_244_CHECKER_TYPE,
13853  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_244_WIDTH },
13854  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_245_CHECKER_TYPE,
13855  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_245_WIDTH },
13856  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_246_CHECKER_TYPE,
13857  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_246_WIDTH },
13858  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_247_CHECKER_TYPE,
13859  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_247_WIDTH },
13860  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_248_CHECKER_TYPE,
13861  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_248_WIDTH },
13862  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_249_CHECKER_TYPE,
13863  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_249_WIDTH },
13864  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_250_CHECKER_TYPE,
13865  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_250_WIDTH },
13866  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_251_CHECKER_TYPE,
13867  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_251_WIDTH },
13868  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_252_CHECKER_TYPE,
13869  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_252_WIDTH },
13870  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_253_CHECKER_TYPE,
13871  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_253_WIDTH },
13872  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_254_CHECKER_TYPE,
13873  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_254_WIDTH },
13874  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_255_CHECKER_TYPE,
13875  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_255_WIDTH },
13876 };
13877 
13883 static const SDL_GrpChkConfig_t SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_groupEntries[SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_MAX_NUM_CHECKERS] =
13884 {
13885  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_0_CHECKER_TYPE,
13886  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_0_WIDTH },
13887  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_1_CHECKER_TYPE,
13888  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_1_WIDTH },
13889  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_2_CHECKER_TYPE,
13890  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_2_WIDTH },
13891  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_3_CHECKER_TYPE,
13892  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_3_WIDTH },
13893  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_4_CHECKER_TYPE,
13894  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_4_WIDTH },
13895  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_5_CHECKER_TYPE,
13896  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_5_WIDTH },
13897  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_6_CHECKER_TYPE,
13898  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_6_WIDTH },
13899  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_7_CHECKER_TYPE,
13900  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_7_WIDTH },
13901  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_8_CHECKER_TYPE,
13902  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_8_WIDTH },
13903  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_9_CHECKER_TYPE,
13904  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_9_WIDTH },
13905  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_10_CHECKER_TYPE,
13906  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_10_WIDTH },
13907  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_11_CHECKER_TYPE,
13908  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_11_WIDTH },
13909  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_12_CHECKER_TYPE,
13910  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_12_WIDTH },
13911  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_13_CHECKER_TYPE,
13912  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_13_WIDTH },
13913  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_14_CHECKER_TYPE,
13914  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_14_WIDTH },
13915  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_15_CHECKER_TYPE,
13916  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_15_WIDTH },
13917  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_16_CHECKER_TYPE,
13918  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_16_WIDTH },
13919  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_17_CHECKER_TYPE,
13920  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_17_WIDTH },
13921  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_18_CHECKER_TYPE,
13922  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_18_WIDTH },
13923  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_19_CHECKER_TYPE,
13924  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_19_WIDTH },
13925  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_20_CHECKER_TYPE,
13926  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_20_WIDTH },
13927  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_21_CHECKER_TYPE,
13928  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_21_WIDTH },
13929  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_22_CHECKER_TYPE,
13930  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_22_WIDTH },
13931  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_23_CHECKER_TYPE,
13932  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_23_WIDTH },
13933  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_24_CHECKER_TYPE,
13934  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_24_WIDTH },
13935  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_25_CHECKER_TYPE,
13936  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_25_WIDTH },
13937  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_26_CHECKER_TYPE,
13938  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_26_WIDTH },
13939  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_27_CHECKER_TYPE,
13940  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_27_WIDTH },
13941  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_28_CHECKER_TYPE,
13942  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_28_WIDTH },
13943  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_29_CHECKER_TYPE,
13944  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_29_WIDTH },
13945  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_30_CHECKER_TYPE,
13946  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_30_WIDTH },
13947  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_31_CHECKER_TYPE,
13948  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_31_WIDTH },
13949  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_32_CHECKER_TYPE,
13950  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_32_WIDTH },
13951  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_33_CHECKER_TYPE,
13952  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_33_WIDTH },
13953  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_34_CHECKER_TYPE,
13954  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_34_WIDTH },
13955  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_35_CHECKER_TYPE,
13956  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_35_WIDTH },
13957  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_36_CHECKER_TYPE,
13958  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_36_WIDTH },
13959  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_37_CHECKER_TYPE,
13960  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_37_WIDTH },
13961  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_38_CHECKER_TYPE,
13962  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_38_WIDTH },
13963  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_39_CHECKER_TYPE,
13964  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_39_WIDTH },
13965  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_40_CHECKER_TYPE,
13966  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_40_WIDTH },
13967  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_41_CHECKER_TYPE,
13968  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_41_WIDTH },
13969  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_42_CHECKER_TYPE,
13970  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_42_WIDTH },
13971  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_43_CHECKER_TYPE,
13972  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_43_WIDTH },
13973  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_44_CHECKER_TYPE,
13974  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_44_WIDTH },
13975  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_45_CHECKER_TYPE,
13976  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_45_WIDTH },
13977  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_46_CHECKER_TYPE,
13978  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_46_WIDTH },
13979  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_47_CHECKER_TYPE,
13980  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_47_WIDTH },
13981  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_48_CHECKER_TYPE,
13982  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_48_WIDTH },
13983  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_49_CHECKER_TYPE,
13984  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_49_WIDTH },
13985  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_50_CHECKER_TYPE,
13986  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_50_WIDTH },
13987  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_51_CHECKER_TYPE,
13988  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_51_WIDTH },
13989  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_52_CHECKER_TYPE,
13990  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_52_WIDTH },
13991  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_53_CHECKER_TYPE,
13992  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_53_WIDTH },
13993  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_54_CHECKER_TYPE,
13994  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_54_WIDTH },
13995  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_55_CHECKER_TYPE,
13996  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_55_WIDTH },
13997  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_56_CHECKER_TYPE,
13998  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_56_WIDTH },
13999  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_57_CHECKER_TYPE,
14000  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_57_WIDTH },
14001  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_58_CHECKER_TYPE,
14002  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_58_WIDTH },
14003  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_59_CHECKER_TYPE,
14004  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_59_WIDTH },
14005  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_60_CHECKER_TYPE,
14006  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_60_WIDTH },
14007  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_61_CHECKER_TYPE,
14008  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_61_WIDTH },
14009  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_62_CHECKER_TYPE,
14010  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_62_WIDTH },
14011  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_63_CHECKER_TYPE,
14012  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_63_WIDTH },
14013  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_64_CHECKER_TYPE,
14014  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_64_WIDTH },
14015  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_65_CHECKER_TYPE,
14016  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_65_WIDTH },
14017  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_66_CHECKER_TYPE,
14018  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_66_WIDTH },
14019  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_67_CHECKER_TYPE,
14020  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_67_WIDTH },
14021  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_68_CHECKER_TYPE,
14022  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_68_WIDTH },
14023  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_69_CHECKER_TYPE,
14024  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_69_WIDTH },
14025  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_70_CHECKER_TYPE,
14026  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_70_WIDTH },
14027  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_71_CHECKER_TYPE,
14028  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_71_WIDTH },
14029  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_72_CHECKER_TYPE,
14030  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_72_WIDTH },
14031  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_73_CHECKER_TYPE,
14032  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_73_WIDTH },
14033  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_74_CHECKER_TYPE,
14034  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_74_WIDTH },
14035  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_75_CHECKER_TYPE,
14036  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_75_WIDTH },
14037  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_76_CHECKER_TYPE,
14038  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_76_WIDTH },
14039  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_77_CHECKER_TYPE,
14040  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_77_WIDTH },
14041  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_78_CHECKER_TYPE,
14042  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_78_WIDTH },
14043  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_79_CHECKER_TYPE,
14044  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_79_WIDTH },
14045  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_80_CHECKER_TYPE,
14046  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_80_WIDTH },
14047  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_81_CHECKER_TYPE,
14048  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_81_WIDTH },
14049  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_82_CHECKER_TYPE,
14050  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_82_WIDTH },
14051  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_83_CHECKER_TYPE,
14052  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_83_WIDTH },
14053  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_84_CHECKER_TYPE,
14054  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_84_WIDTH },
14055  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_85_CHECKER_TYPE,
14056  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_85_WIDTH },
14057  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_86_CHECKER_TYPE,
14058  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_86_WIDTH },
14059  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_87_CHECKER_TYPE,
14060  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_87_WIDTH },
14061  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_88_CHECKER_TYPE,
14062  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_88_WIDTH },
14063  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_89_CHECKER_TYPE,
14064  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_89_WIDTH },
14065  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_90_CHECKER_TYPE,
14066  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_90_WIDTH },
14067  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_91_CHECKER_TYPE,
14068  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_91_WIDTH },
14069  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_92_CHECKER_TYPE,
14070  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_92_WIDTH },
14071  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_93_CHECKER_TYPE,
14072  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_93_WIDTH },
14073  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_94_CHECKER_TYPE,
14074  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_94_WIDTH },
14075  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_95_CHECKER_TYPE,
14076  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_95_WIDTH },
14077  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_96_CHECKER_TYPE,
14078  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_96_WIDTH },
14079  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_97_CHECKER_TYPE,
14080  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_97_WIDTH },
14081  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_98_CHECKER_TYPE,
14082  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_98_WIDTH },
14083  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_99_CHECKER_TYPE,
14084  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_99_WIDTH },
14085  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_100_CHECKER_TYPE,
14086  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_100_WIDTH },
14087  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_101_CHECKER_TYPE,
14088  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_101_WIDTH },
14089  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_102_CHECKER_TYPE,
14090  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_102_WIDTH },
14091  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_103_CHECKER_TYPE,
14092  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_103_WIDTH },
14093  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_104_CHECKER_TYPE,
14094  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_104_WIDTH },
14095  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_105_CHECKER_TYPE,
14096  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_105_WIDTH },
14097  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_106_CHECKER_TYPE,
14098  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_106_WIDTH },
14099  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_107_CHECKER_TYPE,
14100  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_107_WIDTH },
14101  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_108_CHECKER_TYPE,
14102  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_108_WIDTH },
14103  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_109_CHECKER_TYPE,
14104  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_109_WIDTH },
14105  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_110_CHECKER_TYPE,
14106  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_110_WIDTH },
14107  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_111_CHECKER_TYPE,
14108  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_111_WIDTH },
14109  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_112_CHECKER_TYPE,
14110  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_112_WIDTH },
14111  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_113_CHECKER_TYPE,
14112  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_113_WIDTH },
14113  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_114_CHECKER_TYPE,
14114  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_114_WIDTH },
14115  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_115_CHECKER_TYPE,
14116  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_115_WIDTH },
14117  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_116_CHECKER_TYPE,
14118  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_116_WIDTH },
14119  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_117_CHECKER_TYPE,
14120  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_117_WIDTH },
14121  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_118_CHECKER_TYPE,
14122  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_118_WIDTH },
14123  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_119_CHECKER_TYPE,
14124  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_119_WIDTH },
14125  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_120_CHECKER_TYPE,
14126  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_120_WIDTH },
14127  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_121_CHECKER_TYPE,
14128  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_121_WIDTH },
14129  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_122_CHECKER_TYPE,
14130  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_122_WIDTH },
14131  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_123_CHECKER_TYPE,
14132  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_123_WIDTH },
14133  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_124_CHECKER_TYPE,
14134  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_124_WIDTH },
14135  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_125_CHECKER_TYPE,
14136  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_125_WIDTH },
14137  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_126_CHECKER_TYPE,
14138  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_126_WIDTH },
14139  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_127_CHECKER_TYPE,
14140  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_127_WIDTH },
14141  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_128_CHECKER_TYPE,
14142  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_128_WIDTH },
14143  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_129_CHECKER_TYPE,
14144  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_129_WIDTH },
14145  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_130_CHECKER_TYPE,
14146  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_130_WIDTH },
14147  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_131_CHECKER_TYPE,
14148  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_131_WIDTH },
14149  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_132_CHECKER_TYPE,
14150  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_132_WIDTH },
14151  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_133_CHECKER_TYPE,
14152  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_133_WIDTH },
14153  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_134_CHECKER_TYPE,
14154  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_134_WIDTH },
14155  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_135_CHECKER_TYPE,
14156  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_135_WIDTH },
14157  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_136_CHECKER_TYPE,
14158  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_136_WIDTH },
14159  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_137_CHECKER_TYPE,
14160  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_137_WIDTH },
14161  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_138_CHECKER_TYPE,
14162  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_138_WIDTH },
14163  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_139_CHECKER_TYPE,
14164  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_139_WIDTH },
14165  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_140_CHECKER_TYPE,
14166  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_140_WIDTH },
14167  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_141_CHECKER_TYPE,
14168  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_141_WIDTH },
14169  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_142_CHECKER_TYPE,
14170  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_142_WIDTH },
14171  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_143_CHECKER_TYPE,
14172  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_143_WIDTH },
14173  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_144_CHECKER_TYPE,
14174  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_144_WIDTH },
14175  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_145_CHECKER_TYPE,
14176  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_145_WIDTH },
14177  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_146_CHECKER_TYPE,
14178  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_146_WIDTH },
14179  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_147_CHECKER_TYPE,
14180  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_147_WIDTH },
14181  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_148_CHECKER_TYPE,
14182  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_148_WIDTH },
14183  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_149_CHECKER_TYPE,
14184  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_149_WIDTH },
14185  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_150_CHECKER_TYPE,
14186  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_150_WIDTH },
14187  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_151_CHECKER_TYPE,
14188  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_151_WIDTH },
14189  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_152_CHECKER_TYPE,
14190  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_152_WIDTH },
14191  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_153_CHECKER_TYPE,
14192  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_153_WIDTH },
14193 };
14194 
14200 static const SDL_GrpChkConfig_t SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_CBASS_DEFAULT_ERR_AM62A_WKUP_SAFE_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_groupEntries[SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_CBASS_DEFAULT_ERR_AM62A_WKUP_SAFE_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS] =
14201 {
14202  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_CBASS_DEFAULT_ERR_AM62A_WKUP_SAFE_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
14203  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_CBASS_DEFAULT_ERR_AM62A_WKUP_SAFE_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
14204  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_CBASS_DEFAULT_ERR_AM62A_WKUP_SAFE_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
14205  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_CBASS_DEFAULT_ERR_AM62A_WKUP_SAFE_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
14206  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_CBASS_DEFAULT_ERR_AM62A_WKUP_SAFE_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
14207  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_CBASS_DEFAULT_ERR_AM62A_WKUP_SAFE_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
14208  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_CBASS_DEFAULT_ERR_AM62A_WKUP_SAFE_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
14209  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_CBASS_DEFAULT_ERR_AM62A_WKUP_SAFE_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
14210  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_CBASS_DEFAULT_ERR_AM62A_WKUP_SAFE_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
14211  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_CBASS_DEFAULT_ERR_AM62A_WKUP_SAFE_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
14212 };
14213 
14219 static const SDL_GrpChkConfig_t SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_groupEntries[SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS] =
14220 {
14221  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
14222  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
14223  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
14224  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
14225  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
14226  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
14227  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
14228  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
14229  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
14230  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
14231  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_5_CHECKER_TYPE,
14232  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_5_WIDTH },
14233  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_6_CHECKER_TYPE,
14234  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_6_WIDTH },
14235  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_7_CHECKER_TYPE,
14236  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_7_WIDTH },
14237  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_8_CHECKER_TYPE,
14238  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_8_WIDTH },
14239  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_9_CHECKER_TYPE,
14240  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_9_WIDTH },
14241  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_10_CHECKER_TYPE,
14242  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_10_WIDTH },
14243  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_11_CHECKER_TYPE,
14244  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_11_WIDTH },
14245  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_12_CHECKER_TYPE,
14246  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_12_WIDTH },
14247  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_13_CHECKER_TYPE,
14248  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_13_WIDTH },
14249  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_14_CHECKER_TYPE,
14250  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_14_WIDTH },
14251  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_15_CHECKER_TYPE,
14252  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_15_WIDTH },
14253  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_16_CHECKER_TYPE,
14254  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_16_WIDTH },
14255  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_17_CHECKER_TYPE,
14256  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_17_WIDTH },
14257  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_18_CHECKER_TYPE,
14258  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_18_WIDTH },
14259  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_19_CHECKER_TYPE,
14260  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_19_WIDTH },
14261  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_20_CHECKER_TYPE,
14262  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_20_WIDTH },
14263  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_21_CHECKER_TYPE,
14264  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_21_WIDTH },
14265  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_22_CHECKER_TYPE,
14266  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_22_WIDTH },
14267  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_23_CHECKER_TYPE,
14268  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_23_WIDTH },
14269  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_24_CHECKER_TYPE,
14270  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_24_WIDTH },
14271  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_25_CHECKER_TYPE,
14272  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_25_WIDTH },
14273  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_26_CHECKER_TYPE,
14274  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_26_WIDTH },
14275  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_27_CHECKER_TYPE,
14276  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_27_WIDTH },
14277  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_28_CHECKER_TYPE,
14278  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_28_WIDTH },
14279  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_29_CHECKER_TYPE,
14280  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_29_WIDTH },
14281  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_30_CHECKER_TYPE,
14282  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_30_WIDTH },
14283  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_31_CHECKER_TYPE,
14284  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_31_WIDTH },
14285  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_32_CHECKER_TYPE,
14286  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_32_WIDTH },
14287  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_33_CHECKER_TYPE,
14288  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_33_WIDTH },
14289  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_34_CHECKER_TYPE,
14290  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_34_WIDTH },
14291  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_35_CHECKER_TYPE,
14292  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_35_WIDTH },
14293  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_36_CHECKER_TYPE,
14294  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_36_WIDTH },
14295  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_37_CHECKER_TYPE,
14296  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_37_WIDTH },
14297  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_38_CHECKER_TYPE,
14298  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_38_WIDTH },
14299  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_39_CHECKER_TYPE,
14300  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_39_WIDTH },
14301  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_40_CHECKER_TYPE,
14302  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_40_WIDTH },
14303  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_41_CHECKER_TYPE,
14304  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_41_WIDTH },
14305 };
14306 
14312 static const SDL_GrpChkConfig_t SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_groupEntries[SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_MAX_NUM_CHECKERS] =
14313 {
14314  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_0_CHECKER_TYPE,
14315  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_0_WIDTH },
14316  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_1_CHECKER_TYPE,
14317  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_1_WIDTH },
14318  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_2_CHECKER_TYPE,
14319  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_2_WIDTH },
14320  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_3_CHECKER_TYPE,
14321  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_3_WIDTH },
14322  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_4_CHECKER_TYPE,
14323  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_4_WIDTH },
14324  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_5_CHECKER_TYPE,
14325  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_5_WIDTH },
14326  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_6_CHECKER_TYPE,
14327  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_6_WIDTH },
14328  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_7_CHECKER_TYPE,
14329  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_7_WIDTH },
14330  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_8_CHECKER_TYPE,
14331  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_8_WIDTH },
14332  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_9_CHECKER_TYPE,
14333  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_9_WIDTH },
14334  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_10_CHECKER_TYPE,
14335  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_10_WIDTH },
14336  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_11_CHECKER_TYPE,
14337  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_11_WIDTH },
14338  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_12_CHECKER_TYPE,
14339  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_12_WIDTH },
14340  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_13_CHECKER_TYPE,
14341  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_13_WIDTH },
14342  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_14_CHECKER_TYPE,
14343  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_14_WIDTH },
14344  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_15_CHECKER_TYPE,
14345  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_15_WIDTH },
14346  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_16_CHECKER_TYPE,
14347  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_16_WIDTH },
14348  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_17_CHECKER_TYPE,
14349  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_17_WIDTH },
14350  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_18_CHECKER_TYPE,
14351  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_18_WIDTH },
14352 };
14353 
14359 static const SDL_GrpChkConfig_t SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_groupEntries[SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_MAX_NUM_CHECKERS] =
14360 {
14361  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_0_CHECKER_TYPE,
14362  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_0_WIDTH },
14363  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_1_CHECKER_TYPE,
14364  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_1_WIDTH },
14365  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_2_CHECKER_TYPE,
14366  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_2_WIDTH },
14367  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_3_CHECKER_TYPE,
14368  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_3_WIDTH },
14369  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_4_CHECKER_TYPE,
14370  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_4_WIDTH },
14371  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_5_CHECKER_TYPE,
14372  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_5_WIDTH },
14373  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_6_CHECKER_TYPE,
14374  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_6_WIDTH },
14375  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_7_CHECKER_TYPE,
14376  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_7_WIDTH },
14377  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_8_CHECKER_TYPE,
14378  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_8_WIDTH },
14379  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_9_CHECKER_TYPE,
14380  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_9_WIDTH },
14381  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_10_CHECKER_TYPE,
14382  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_10_WIDTH },
14383  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_11_CHECKER_TYPE,
14384  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_11_WIDTH },
14385  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_12_CHECKER_TYPE,
14386  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_12_WIDTH },
14387  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_13_CHECKER_TYPE,
14388  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_13_WIDTH },
14389  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_14_CHECKER_TYPE,
14390  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_14_WIDTH },
14391  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_15_CHECKER_TYPE,
14392  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_15_WIDTH },
14393  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_16_CHECKER_TYPE,
14394  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_16_WIDTH },
14395  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_17_CHECKER_TYPE,
14396  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_17_WIDTH },
14397  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_18_CHECKER_TYPE,
14398  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_18_WIDTH },
14399  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_19_CHECKER_TYPE,
14400  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_19_WIDTH },
14401  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_20_CHECKER_TYPE,
14402  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_20_WIDTH },
14403  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_21_CHECKER_TYPE,
14404  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_21_WIDTH },
14405  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_22_CHECKER_TYPE,
14406  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_22_WIDTH },
14407  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_23_CHECKER_TYPE,
14408  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_23_WIDTH },
14409  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_24_CHECKER_TYPE,
14410  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_24_WIDTH },
14411  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_25_CHECKER_TYPE,
14412  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_25_WIDTH },
14413  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_26_CHECKER_TYPE,
14414  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_26_WIDTH },
14415  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_27_CHECKER_TYPE,
14416  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_27_WIDTH },
14417  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_28_CHECKER_TYPE,
14418  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_28_WIDTH },
14419  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_29_CHECKER_TYPE,
14420  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_29_WIDTH },
14421  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_30_CHECKER_TYPE,
14422  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_30_WIDTH },
14423 };
14424 
14430 static const SDL_GrpChkConfig_t SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_SAM62A_WKUP_SAFE_ECC_AGGR_EDC_CTRL_groupEntries[SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_SAM62A_WKUP_SAFE_ECC_AGGR_EDC_CTRL_MAX_NUM_CHECKERS] =
14431 {
14432  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_SAM62A_WKUP_SAFE_ECC_AGGR_EDC_CTRL_GROUP_0_CHECKER_TYPE,
14433  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_SAM62A_WKUP_SAFE_ECC_AGGR_EDC_CTRL_GROUP_0_WIDTH },
14434  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_SAM62A_WKUP_SAFE_ECC_AGGR_EDC_CTRL_GROUP_1_CHECKER_TYPE,
14435  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_SAM62A_WKUP_SAFE_ECC_AGGR_EDC_CTRL_GROUP_1_WIDTH },
14436  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_SAM62A_WKUP_SAFE_ECC_AGGR_EDC_CTRL_GROUP_2_CHECKER_TYPE,
14437  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_SAM62A_WKUP_SAFE_ECC_AGGR_EDC_CTRL_GROUP_2_WIDTH },
14438  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_SAM62A_WKUP_SAFE_ECC_AGGR_EDC_CTRL_GROUP_3_CHECKER_TYPE,
14439  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_SAM62A_WKUP_SAFE_ECC_AGGR_EDC_CTRL_GROUP_3_WIDTH },
14440  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_SAM62A_WKUP_SAFE_ECC_AGGR_EDC_CTRL_GROUP_4_CHECKER_TYPE,
14441  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_SAM62A_WKUP_SAFE_ECC_AGGR_EDC_CTRL_GROUP_4_WIDTH },
14442  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_SAM62A_WKUP_SAFE_ECC_AGGR_EDC_CTRL_GROUP_5_CHECKER_TYPE,
14443  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_SAM62A_WKUP_SAFE_ECC_AGGR_EDC_CTRL_GROUP_5_WIDTH },
14444 };
14445 
14450 static const SDL_MemConfig_t SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_MemEntries[SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES] =
14451 {
14452  { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_ITAG_RAM0_RAM_ID, 0u,
14453  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_ITAG_RAM0_RAM_SIZE, 4u,
14454  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_ITAG_RAM0_ROW_WIDTH, ((bool)false) },
14455  { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_ITAG_RAM1_RAM_ID, 0u,
14456  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_ITAG_RAM1_RAM_SIZE, 4u,
14457  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_ITAG_RAM1_ROW_WIDTH, ((bool)false) },
14458  { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_ITAG_RAM2_RAM_ID, 0u,
14459  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_ITAG_RAM2_RAM_SIZE, 4u,
14460  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_ITAG_RAM2_ROW_WIDTH, ((bool)false) },
14461  { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_ITAG_RAM3_RAM_ID, 0u,
14462  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_ITAG_RAM3_RAM_SIZE, 4u,
14463  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_ITAG_RAM3_ROW_WIDTH, ((bool)false) },
14464  { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_IDATA_BANK0_RAM_ID, 0u,
14465  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_IDATA_BANK0_RAM_SIZE, 8u,
14466  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_IDATA_BANK0_ROW_WIDTH, ((bool)true) },
14467  { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_IDATA_BANK1_RAM_ID, 0u,
14468  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_IDATA_BANK1_RAM_SIZE, 8u,
14469  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_IDATA_BANK1_ROW_WIDTH, ((bool)true) },
14470  { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_IDATA_BANK2_RAM_ID, 0u,
14471  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_IDATA_BANK2_RAM_SIZE, 8u,
14472  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_IDATA_BANK2_ROW_WIDTH, ((bool)true) },
14473  { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_IDATA_BANK3_RAM_ID, 0u,
14474  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_IDATA_BANK3_RAM_SIZE, 8u,
14475  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_IDATA_BANK3_ROW_WIDTH, ((bool)true) },
14476  { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DTAG_RAM0_RAM_ID, 0u,
14477  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DTAG_RAM0_RAM_SIZE, 4u,
14478  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DTAG_RAM0_ROW_WIDTH, ((bool)false) },
14479  { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DTAG_RAM1_RAM_ID, 0u,
14480  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DTAG_RAM1_RAM_SIZE, 4u,
14481  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DTAG_RAM1_ROW_WIDTH, ((bool)false) },
14482  { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DTAG_RAM2_RAM_ID, 0u,
14483  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DTAG_RAM2_RAM_SIZE, 4u,
14484  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DTAG_RAM2_ROW_WIDTH, ((bool)false) },
14485  { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DTAG_RAM3_RAM_ID, 0u,
14486  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DTAG_RAM3_RAM_SIZE, 4u,
14487  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DTAG_RAM3_ROW_WIDTH, ((bool)false) },
14488  { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDIRTY_RAM_RAM_ID, 0u,
14489  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDIRTY_RAM_RAM_SIZE, 4u,
14490  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDIRTY_RAM_ROW_WIDTH, ((bool)false) },
14491  { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM0_RAM_ID, 0u,
14492  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM0_RAM_SIZE, 4u,
14493  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM0_ROW_WIDTH, ((bool)true) },
14494  { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM1_RAM_ID, 0u,
14495  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM1_RAM_SIZE, 4u,
14496  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM1_ROW_WIDTH, ((bool)true) },
14497  { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM2_RAM_ID, 0u,
14498  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM2_RAM_SIZE, 4u,
14499  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM2_ROW_WIDTH, ((bool)true) },
14500  { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM3_RAM_ID, 0u,
14501  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM3_RAM_SIZE, 4u,
14502  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM3_ROW_WIDTH, ((bool)true) },
14503  { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM4_RAM_ID, 0u,
14504  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM4_RAM_SIZE, 4u,
14505  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM4_ROW_WIDTH, ((bool)true) },
14506  { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM5_RAM_ID, 0u,
14507  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM5_RAM_SIZE, 4u,
14508  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM5_ROW_WIDTH, ((bool)true) },
14509  { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM6_RAM_ID, 0u,
14510  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM6_RAM_SIZE, 4u,
14511  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM6_ROW_WIDTH, ((bool)true) },
14512  { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM7_RAM_ID, 0u,
14513  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM7_RAM_SIZE, 4u,
14514  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM7_ROW_WIDTH, ((bool)true) },
14515  { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_ATCM0_BANK0_RAM_ID, 0x0078000000u,
14516  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_ATCM0_BANK0_RAM_SIZE, 4u,
14517  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_ATCM0_BANK0_ROW_WIDTH, ((bool)true) },
14518  { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_ATCM0_BANK1_RAM_ID, 0x0078000000u,
14519  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_ATCM0_BANK1_RAM_SIZE, 4u,
14520  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_ATCM0_BANK1_ROW_WIDTH, ((bool)true) },
14521  { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_B0TCM0_BANK0_RAM_ID, 0x0078100000u,
14522  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_B0TCM0_BANK0_RAM_SIZE, 4u,
14523  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_B0TCM0_BANK0_ROW_WIDTH, ((bool)true) },
14524  { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_B0TCM0_BANK1_RAM_ID, 0x0078100000u,
14525  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_B0TCM0_BANK1_RAM_SIZE, 4u,
14526  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_B0TCM0_BANK1_ROW_WIDTH, ((bool)true) },
14527  { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_B1TCM0_BANK0_RAM_ID, 0x0078100000u,
14528  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_B1TCM0_BANK0_RAM_SIZE, 4u,
14529  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_B1TCM0_BANK0_ROW_WIDTH, ((bool)true) },
14530  { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_B1TCM0_BANK1_RAM_ID, 0x0078100000u,
14531  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_B1TCM0_BANK1_RAM_SIZE, 4u,
14532  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_B1TCM0_BANK1_ROW_WIDTH, ((bool)true) },
14533  { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_PULSAR_KS_VIM_COMMON_CORE0_RAM_RAM_ID, 0u,
14534  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_PULSAR_KS_VIM_COMMON_CORE0_RAM_RAM_SIZE, 4u,
14535  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_PULSAR_KS_VIM_COMMON_CORE0_RAM_ROW_WIDTH, ((bool)false) },
14536  { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_MEM_MST0_KSBUS_AXI2VBUSM_R_RDATA_BUFFER_RAM_ID, 0u,
14537  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_MEM_MST0_KSBUS_AXI2VBUSM_R_RDATA_BUFFER_RAM_SIZE, 8u,
14538  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_MEM_MST0_KSBUS_AXI2VBUSM_R_RDATA_BUFFER_ROW_WIDTH, ((bool)false) },
14539 };
14540 
14545 static const SDL_MemConfig_t SDL_SMS0_SMS_HSM_ECC_MemEntries[SDL_SMS0_SMS_HSM_ECC_RAM_IDS_TOTAL_ENTRIES] =
14546 {
14547  { SDL_SMS0_SMS_HSM_ECC_ISRAM0_RAMECC_RAM_ID, 0u,
14548  SDL_SMS0_SMS_HSM_ECC_ISRAM0_RAMECC_RAM_SIZE, 4u,
14549  SDL_SMS0_SMS_HSM_ECC_ISRAM0_RAMECC_ROW_WIDTH, ((bool)false) },
14550  { SDL_SMS0_SMS_HSM_ECC_ISRAM1_RAMECC_RAM_ID, 0u,
14551  SDL_SMS0_SMS_HSM_ECC_ISRAM1_RAMECC_RAM_SIZE, 4u,
14552  SDL_SMS0_SMS_HSM_ECC_ISRAM1_RAMECC_ROW_WIDTH, ((bool)false) },
14553 };
14554 
14560 static const SDL_GrpChkConfig_t SDL_SMS0_SMS_HSM_ECC_ISRAM0_BUSECC_groupEntries[SDL_SMS0_SMS_HSM_ECC_ISRAM0_BUSECC_MAX_NUM_CHECKERS] =
14561 {
14562  { SDL_SMS0_SMS_HSM_ECC_ISRAM0_BUSECC_GROUP_0_CHECKER_TYPE,
14563  SDL_SMS0_SMS_HSM_ECC_ISRAM0_BUSECC_GROUP_0_WIDTH },
14564  { SDL_SMS0_SMS_HSM_ECC_ISRAM0_BUSECC_GROUP_1_CHECKER_TYPE,
14565  SDL_SMS0_SMS_HSM_ECC_ISRAM0_BUSECC_GROUP_1_WIDTH },
14566  { SDL_SMS0_SMS_HSM_ECC_ISRAM0_BUSECC_GROUP_2_CHECKER_TYPE,
14567  SDL_SMS0_SMS_HSM_ECC_ISRAM0_BUSECC_GROUP_2_WIDTH },
14568  { SDL_SMS0_SMS_HSM_ECC_ISRAM0_BUSECC_GROUP_3_CHECKER_TYPE,
14569  SDL_SMS0_SMS_HSM_ECC_ISRAM0_BUSECC_GROUP_3_WIDTH },
14570  { SDL_SMS0_SMS_HSM_ECC_ISRAM0_BUSECC_GROUP_4_CHECKER_TYPE,
14571  SDL_SMS0_SMS_HSM_ECC_ISRAM0_BUSECC_GROUP_4_WIDTH },
14572  { SDL_SMS0_SMS_HSM_ECC_ISRAM0_BUSECC_GROUP_5_CHECKER_TYPE,
14573  SDL_SMS0_SMS_HSM_ECC_ISRAM0_BUSECC_GROUP_5_WIDTH },
14574  { SDL_SMS0_SMS_HSM_ECC_ISRAM0_BUSECC_GROUP_6_CHECKER_TYPE,
14575  SDL_SMS0_SMS_HSM_ECC_ISRAM0_BUSECC_GROUP_6_WIDTH },
14576  { SDL_SMS0_SMS_HSM_ECC_ISRAM0_BUSECC_GROUP_7_CHECKER_TYPE,
14577  SDL_SMS0_SMS_HSM_ECC_ISRAM0_BUSECC_GROUP_7_WIDTH },
14578  { SDL_SMS0_SMS_HSM_ECC_ISRAM0_BUSECC_GROUP_8_CHECKER_TYPE,
14579  SDL_SMS0_SMS_HSM_ECC_ISRAM0_BUSECC_GROUP_8_WIDTH },
14580  { SDL_SMS0_SMS_HSM_ECC_ISRAM0_BUSECC_GROUP_9_CHECKER_TYPE,
14581  SDL_SMS0_SMS_HSM_ECC_ISRAM0_BUSECC_GROUP_9_WIDTH },
14582  { SDL_SMS0_SMS_HSM_ECC_ISRAM0_BUSECC_GROUP_10_CHECKER_TYPE,
14583  SDL_SMS0_SMS_HSM_ECC_ISRAM0_BUSECC_GROUP_10_WIDTH },
14584  { SDL_SMS0_SMS_HSM_ECC_ISRAM0_BUSECC_GROUP_11_CHECKER_TYPE,
14585  SDL_SMS0_SMS_HSM_ECC_ISRAM0_BUSECC_GROUP_11_WIDTH },
14586  { SDL_SMS0_SMS_HSM_ECC_ISRAM0_BUSECC_GROUP_12_CHECKER_TYPE,
14587  SDL_SMS0_SMS_HSM_ECC_ISRAM0_BUSECC_GROUP_12_WIDTH },
14588  { SDL_SMS0_SMS_HSM_ECC_ISRAM0_BUSECC_GROUP_13_CHECKER_TYPE,
14589  SDL_SMS0_SMS_HSM_ECC_ISRAM0_BUSECC_GROUP_13_WIDTH },
14590  { SDL_SMS0_SMS_HSM_ECC_ISRAM0_BUSECC_GROUP_14_CHECKER_TYPE,
14591  SDL_SMS0_SMS_HSM_ECC_ISRAM0_BUSECC_GROUP_14_WIDTH },
14592  { SDL_SMS0_SMS_HSM_ECC_ISRAM0_BUSECC_GROUP_15_CHECKER_TYPE,
14593  SDL_SMS0_SMS_HSM_ECC_ISRAM0_BUSECC_GROUP_15_WIDTH },
14594  { SDL_SMS0_SMS_HSM_ECC_ISRAM0_BUSECC_GROUP_16_CHECKER_TYPE,
14595  SDL_SMS0_SMS_HSM_ECC_ISRAM0_BUSECC_GROUP_16_WIDTH },
14596  { SDL_SMS0_SMS_HSM_ECC_ISRAM0_BUSECC_GROUP_17_CHECKER_TYPE,
14597  SDL_SMS0_SMS_HSM_ECC_ISRAM0_BUSECC_GROUP_17_WIDTH },
14598  { SDL_SMS0_SMS_HSM_ECC_ISRAM0_BUSECC_GROUP_18_CHECKER_TYPE,
14599  SDL_SMS0_SMS_HSM_ECC_ISRAM0_BUSECC_GROUP_18_WIDTH },
14600  { SDL_SMS0_SMS_HSM_ECC_ISRAM0_BUSECC_GROUP_19_CHECKER_TYPE,
14601  SDL_SMS0_SMS_HSM_ECC_ISRAM0_BUSECC_GROUP_19_WIDTH },
14602 };
14603 
14609 static const SDL_GrpChkConfig_t SDL_SMS0_SMS_HSM_ECC_ISRAM1_BUSECC_groupEntries[SDL_SMS0_SMS_HSM_ECC_ISRAM1_BUSECC_MAX_NUM_CHECKERS] =
14610 {
14611  { SDL_SMS0_SMS_HSM_ECC_ISRAM1_BUSECC_GROUP_0_CHECKER_TYPE,
14612  SDL_SMS0_SMS_HSM_ECC_ISRAM1_BUSECC_GROUP_0_WIDTH },
14613  { SDL_SMS0_SMS_HSM_ECC_ISRAM1_BUSECC_GROUP_1_CHECKER_TYPE,
14614  SDL_SMS0_SMS_HSM_ECC_ISRAM1_BUSECC_GROUP_1_WIDTH },
14615  { SDL_SMS0_SMS_HSM_ECC_ISRAM1_BUSECC_GROUP_2_CHECKER_TYPE,
14616  SDL_SMS0_SMS_HSM_ECC_ISRAM1_BUSECC_GROUP_2_WIDTH },
14617  { SDL_SMS0_SMS_HSM_ECC_ISRAM1_BUSECC_GROUP_3_CHECKER_TYPE,
14618  SDL_SMS0_SMS_HSM_ECC_ISRAM1_BUSECC_GROUP_3_WIDTH },
14619  { SDL_SMS0_SMS_HSM_ECC_ISRAM1_BUSECC_GROUP_4_CHECKER_TYPE,
14620  SDL_SMS0_SMS_HSM_ECC_ISRAM1_BUSECC_GROUP_4_WIDTH },
14621  { SDL_SMS0_SMS_HSM_ECC_ISRAM1_BUSECC_GROUP_5_CHECKER_TYPE,
14622  SDL_SMS0_SMS_HSM_ECC_ISRAM1_BUSECC_GROUP_5_WIDTH },
14623  { SDL_SMS0_SMS_HSM_ECC_ISRAM1_BUSECC_GROUP_6_CHECKER_TYPE,
14624  SDL_SMS0_SMS_HSM_ECC_ISRAM1_BUSECC_GROUP_6_WIDTH },
14625  { SDL_SMS0_SMS_HSM_ECC_ISRAM1_BUSECC_GROUP_7_CHECKER_TYPE,
14626  SDL_SMS0_SMS_HSM_ECC_ISRAM1_BUSECC_GROUP_7_WIDTH },
14627  { SDL_SMS0_SMS_HSM_ECC_ISRAM1_BUSECC_GROUP_8_CHECKER_TYPE,
14628  SDL_SMS0_SMS_HSM_ECC_ISRAM1_BUSECC_GROUP_8_WIDTH },
14629  { SDL_SMS0_SMS_HSM_ECC_ISRAM1_BUSECC_GROUP_9_CHECKER_TYPE,
14630  SDL_SMS0_SMS_HSM_ECC_ISRAM1_BUSECC_GROUP_9_WIDTH },
14631  { SDL_SMS0_SMS_HSM_ECC_ISRAM1_BUSECC_GROUP_10_CHECKER_TYPE,
14632  SDL_SMS0_SMS_HSM_ECC_ISRAM1_BUSECC_GROUP_10_WIDTH },
14633  { SDL_SMS0_SMS_HSM_ECC_ISRAM1_BUSECC_GROUP_11_CHECKER_TYPE,
14634  SDL_SMS0_SMS_HSM_ECC_ISRAM1_BUSECC_GROUP_11_WIDTH },
14635  { SDL_SMS0_SMS_HSM_ECC_ISRAM1_BUSECC_GROUP_12_CHECKER_TYPE,
14636  SDL_SMS0_SMS_HSM_ECC_ISRAM1_BUSECC_GROUP_12_WIDTH },
14637  { SDL_SMS0_SMS_HSM_ECC_ISRAM1_BUSECC_GROUP_13_CHECKER_TYPE,
14638  SDL_SMS0_SMS_HSM_ECC_ISRAM1_BUSECC_GROUP_13_WIDTH },
14639  { SDL_SMS0_SMS_HSM_ECC_ISRAM1_BUSECC_GROUP_14_CHECKER_TYPE,
14640  SDL_SMS0_SMS_HSM_ECC_ISRAM1_BUSECC_GROUP_14_WIDTH },
14641  { SDL_SMS0_SMS_HSM_ECC_ISRAM1_BUSECC_GROUP_15_CHECKER_TYPE,
14642  SDL_SMS0_SMS_HSM_ECC_ISRAM1_BUSECC_GROUP_15_WIDTH },
14643  { SDL_SMS0_SMS_HSM_ECC_ISRAM1_BUSECC_GROUP_16_CHECKER_TYPE,
14644  SDL_SMS0_SMS_HSM_ECC_ISRAM1_BUSECC_GROUP_16_WIDTH },
14645  { SDL_SMS0_SMS_HSM_ECC_ISRAM1_BUSECC_GROUP_17_CHECKER_TYPE,
14646  SDL_SMS0_SMS_HSM_ECC_ISRAM1_BUSECC_GROUP_17_WIDTH },
14647  { SDL_SMS0_SMS_HSM_ECC_ISRAM1_BUSECC_GROUP_18_CHECKER_TYPE,
14648  SDL_SMS0_SMS_HSM_ECC_ISRAM1_BUSECC_GROUP_18_WIDTH },
14649  { SDL_SMS0_SMS_HSM_ECC_ISRAM1_BUSECC_GROUP_19_CHECKER_TYPE,
14650  SDL_SMS0_SMS_HSM_ECC_ISRAM1_BUSECC_GROUP_19_WIDTH },
14651 };
14652 
14658 static const SDL_GrpChkConfig_t SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_groupEntries[SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_MAX_NUM_CHECKERS] =
14659 {
14660  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_0_CHECKER_TYPE,
14661  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_0_WIDTH },
14662  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_1_CHECKER_TYPE,
14663  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_1_WIDTH },
14664  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_2_CHECKER_TYPE,
14665  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_2_WIDTH },
14666  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_3_CHECKER_TYPE,
14667  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_3_WIDTH },
14668  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_4_CHECKER_TYPE,
14669  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_4_WIDTH },
14670  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_5_CHECKER_TYPE,
14671  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_5_WIDTH },
14672  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_6_CHECKER_TYPE,
14673  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_6_WIDTH },
14674  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_7_CHECKER_TYPE,
14675  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_7_WIDTH },
14676  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_8_CHECKER_TYPE,
14677  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_8_WIDTH },
14678  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_9_CHECKER_TYPE,
14679  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_9_WIDTH },
14680  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_10_CHECKER_TYPE,
14681  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_10_WIDTH },
14682  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_11_CHECKER_TYPE,
14683  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_11_WIDTH },
14684  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_12_CHECKER_TYPE,
14685  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_12_WIDTH },
14686  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_13_CHECKER_TYPE,
14687  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_13_WIDTH },
14688  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_14_CHECKER_TYPE,
14689  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_14_WIDTH },
14690  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_15_CHECKER_TYPE,
14691  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_15_WIDTH },
14692  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_16_CHECKER_TYPE,
14693  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_16_WIDTH },
14694  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_17_CHECKER_TYPE,
14695  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_17_WIDTH },
14696  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_18_CHECKER_TYPE,
14697  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_18_WIDTH },
14698  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_19_CHECKER_TYPE,
14699  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_19_WIDTH },
14700  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_20_CHECKER_TYPE,
14701  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_20_WIDTH },
14702  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_21_CHECKER_TYPE,
14703  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_21_WIDTH },
14704  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_22_CHECKER_TYPE,
14705  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_22_WIDTH },
14706  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_23_CHECKER_TYPE,
14707  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_23_WIDTH },
14708  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_24_CHECKER_TYPE,
14709  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_24_WIDTH },
14710  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_25_CHECKER_TYPE,
14711  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_25_WIDTH },
14712  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_26_CHECKER_TYPE,
14713  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_26_WIDTH },
14714  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_27_CHECKER_TYPE,
14715  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_27_WIDTH },
14716  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_28_CHECKER_TYPE,
14717  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_28_WIDTH },
14718  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_29_CHECKER_TYPE,
14719  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_29_WIDTH },
14720  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_30_CHECKER_TYPE,
14721  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_30_WIDTH },
14722  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_31_CHECKER_TYPE,
14723  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_31_WIDTH },
14724  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_32_CHECKER_TYPE,
14725  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_32_WIDTH },
14726  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_33_CHECKER_TYPE,
14727  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_33_WIDTH },
14728  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_34_CHECKER_TYPE,
14729  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_34_WIDTH },
14730  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_35_CHECKER_TYPE,
14731  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_35_WIDTH },
14732  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_36_CHECKER_TYPE,
14733  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_36_WIDTH },
14734  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_37_CHECKER_TYPE,
14735  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_37_WIDTH },
14736  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_38_CHECKER_TYPE,
14737  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_38_WIDTH },
14738  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_39_CHECKER_TYPE,
14739  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_39_WIDTH },
14740  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_40_CHECKER_TYPE,
14741  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_40_WIDTH },
14742  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_41_CHECKER_TYPE,
14743  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_41_WIDTH },
14744  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_42_CHECKER_TYPE,
14745  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_42_WIDTH },
14746  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_43_CHECKER_TYPE,
14747  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_43_WIDTH },
14748  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_44_CHECKER_TYPE,
14749  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_44_WIDTH },
14750  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_45_CHECKER_TYPE,
14751  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_45_WIDTH },
14752  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_46_CHECKER_TYPE,
14753  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_46_WIDTH },
14754  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_47_CHECKER_TYPE,
14755  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_47_WIDTH },
14756  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_48_CHECKER_TYPE,
14757  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_48_WIDTH },
14758  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_49_CHECKER_TYPE,
14759  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_49_WIDTH },
14760  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_50_CHECKER_TYPE,
14761  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_50_WIDTH },
14762  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_51_CHECKER_TYPE,
14763  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_51_WIDTH },
14764  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_52_CHECKER_TYPE,
14765  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_52_WIDTH },
14766  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_53_CHECKER_TYPE,
14767  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_53_WIDTH },
14768  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_54_CHECKER_TYPE,
14769  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_54_WIDTH },
14770  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_55_CHECKER_TYPE,
14771  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_55_WIDTH },
14772  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_56_CHECKER_TYPE,
14773  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_56_WIDTH },
14774  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_57_CHECKER_TYPE,
14775  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_57_WIDTH },
14776  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_58_CHECKER_TYPE,
14777  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_58_WIDTH },
14778  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_59_CHECKER_TYPE,
14779  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_59_WIDTH },
14780  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_60_CHECKER_TYPE,
14781  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_60_WIDTH },
14782  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_61_CHECKER_TYPE,
14783  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_61_WIDTH },
14784  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_62_CHECKER_TYPE,
14785  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_62_WIDTH },
14786  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_63_CHECKER_TYPE,
14787  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_63_WIDTH },
14788  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_64_CHECKER_TYPE,
14789  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_64_WIDTH },
14790  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_65_CHECKER_TYPE,
14791  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_65_WIDTH },
14792  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_66_CHECKER_TYPE,
14793  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_66_WIDTH },
14794  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_67_CHECKER_TYPE,
14795  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_67_WIDTH },
14796  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_68_CHECKER_TYPE,
14797  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_68_WIDTH },
14798  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_69_CHECKER_TYPE,
14799  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_69_WIDTH },
14800  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_70_CHECKER_TYPE,
14801  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_70_WIDTH },
14802  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_71_CHECKER_TYPE,
14803  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_71_WIDTH },
14804  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_72_CHECKER_TYPE,
14805  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_72_WIDTH },
14806  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_73_CHECKER_TYPE,
14807  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_73_WIDTH },
14808  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_74_CHECKER_TYPE,
14809  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_74_WIDTH },
14810  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_75_CHECKER_TYPE,
14811  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_75_WIDTH },
14812  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_76_CHECKER_TYPE,
14813  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_76_WIDTH },
14814  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_77_CHECKER_TYPE,
14815  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_77_WIDTH },
14816  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_78_CHECKER_TYPE,
14817  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_78_WIDTH },
14818  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_79_CHECKER_TYPE,
14819  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_79_WIDTH },
14820  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_80_CHECKER_TYPE,
14821  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_80_WIDTH },
14822  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_81_CHECKER_TYPE,
14823  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_81_WIDTH },
14824  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_82_CHECKER_TYPE,
14825  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_82_WIDTH },
14826  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_83_CHECKER_TYPE,
14827  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_83_WIDTH },
14828  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_84_CHECKER_TYPE,
14829  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_84_WIDTH },
14830  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_85_CHECKER_TYPE,
14831  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_85_WIDTH },
14832  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_86_CHECKER_TYPE,
14833  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_86_WIDTH },
14834  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_87_CHECKER_TYPE,
14835  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_87_WIDTH },
14836  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_88_CHECKER_TYPE,
14837  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_88_WIDTH },
14838  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_89_CHECKER_TYPE,
14839  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_89_WIDTH },
14840  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_90_CHECKER_TYPE,
14841  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_90_WIDTH },
14842  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_91_CHECKER_TYPE,
14843  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_91_WIDTH },
14844  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_92_CHECKER_TYPE,
14845  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_92_WIDTH },
14846  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_93_CHECKER_TYPE,
14847  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_93_WIDTH },
14848  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_94_CHECKER_TYPE,
14849  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_94_WIDTH },
14850  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_95_CHECKER_TYPE,
14851  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_95_WIDTH },
14852  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_96_CHECKER_TYPE,
14853  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_96_WIDTH },
14854  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_97_CHECKER_TYPE,
14855  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_97_WIDTH },
14856  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_98_CHECKER_TYPE,
14857  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_98_WIDTH },
14858  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_99_CHECKER_TYPE,
14859  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_99_WIDTH },
14860  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_100_CHECKER_TYPE,
14861  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_100_WIDTH },
14862  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_101_CHECKER_TYPE,
14863  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_101_WIDTH },
14864  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_102_CHECKER_TYPE,
14865  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_102_WIDTH },
14866  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_103_CHECKER_TYPE,
14867  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_103_WIDTH },
14868  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_104_CHECKER_TYPE,
14869  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_104_WIDTH },
14870  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_105_CHECKER_TYPE,
14871  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_105_WIDTH },
14872  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_106_CHECKER_TYPE,
14873  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_106_WIDTH },
14874  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_107_CHECKER_TYPE,
14875  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_107_WIDTH },
14876  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_108_CHECKER_TYPE,
14877  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_108_WIDTH },
14878  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_109_CHECKER_TYPE,
14879  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_109_WIDTH },
14880  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_110_CHECKER_TYPE,
14881  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_110_WIDTH },
14882  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_111_CHECKER_TYPE,
14883  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_111_WIDTH },
14884  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_112_CHECKER_TYPE,
14885  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_112_WIDTH },
14886  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_113_CHECKER_TYPE,
14887  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_113_WIDTH },
14888  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_114_CHECKER_TYPE,
14889  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_114_WIDTH },
14890  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_115_CHECKER_TYPE,
14891  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_115_WIDTH },
14892  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_116_CHECKER_TYPE,
14893  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_116_WIDTH },
14894  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_117_CHECKER_TYPE,
14895  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_117_WIDTH },
14896  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_118_CHECKER_TYPE,
14897  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_118_WIDTH },
14898  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_119_CHECKER_TYPE,
14899  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_119_WIDTH },
14900  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_120_CHECKER_TYPE,
14901  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_120_WIDTH },
14902  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_121_CHECKER_TYPE,
14903  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_121_WIDTH },
14904  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_122_CHECKER_TYPE,
14905  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_122_WIDTH },
14906  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_123_CHECKER_TYPE,
14907  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_123_WIDTH },
14908  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_124_CHECKER_TYPE,
14909  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_124_WIDTH },
14910  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_125_CHECKER_TYPE,
14911  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_125_WIDTH },
14912  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_126_CHECKER_TYPE,
14913  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_126_WIDTH },
14914  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_127_CHECKER_TYPE,
14915  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_127_WIDTH },
14916  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_128_CHECKER_TYPE,
14917  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_128_WIDTH },
14918  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_129_CHECKER_TYPE,
14919  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_129_WIDTH },
14920  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_130_CHECKER_TYPE,
14921  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_130_WIDTH },
14922  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_131_CHECKER_TYPE,
14923  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_131_WIDTH },
14924  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_132_CHECKER_TYPE,
14925  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_132_WIDTH },
14926  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_133_CHECKER_TYPE,
14927  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_133_WIDTH },
14928  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_134_CHECKER_TYPE,
14929  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_134_WIDTH },
14930  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_135_CHECKER_TYPE,
14931  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_135_WIDTH },
14932  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_136_CHECKER_TYPE,
14933  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_136_WIDTH },
14934  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_137_CHECKER_TYPE,
14935  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_137_WIDTH },
14936  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_138_CHECKER_TYPE,
14937  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_138_WIDTH },
14938  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_139_CHECKER_TYPE,
14939  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_139_WIDTH },
14940  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_140_CHECKER_TYPE,
14941  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_140_WIDTH },
14942  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_141_CHECKER_TYPE,
14943  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_141_WIDTH },
14944  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_142_CHECKER_TYPE,
14945  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_142_WIDTH },
14946  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_143_CHECKER_TYPE,
14947  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_143_WIDTH },
14948  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_144_CHECKER_TYPE,
14949  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_144_WIDTH },
14950  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_145_CHECKER_TYPE,
14951  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_145_WIDTH },
14952  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_146_CHECKER_TYPE,
14953  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_146_WIDTH },
14954  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_147_CHECKER_TYPE,
14955  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_147_WIDTH },
14956  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_148_CHECKER_TYPE,
14957  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_148_WIDTH },
14958  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_149_CHECKER_TYPE,
14959  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_149_WIDTH },
14960  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_150_CHECKER_TYPE,
14961  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_150_WIDTH },
14962  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_151_CHECKER_TYPE,
14963  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_151_WIDTH },
14964  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_152_CHECKER_TYPE,
14965  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_152_WIDTH },
14966  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_153_CHECKER_TYPE,
14967  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_153_WIDTH },
14968  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_154_CHECKER_TYPE,
14969  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_154_WIDTH },
14970  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_155_CHECKER_TYPE,
14971  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_155_WIDTH },
14972  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_156_CHECKER_TYPE,
14973  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_156_WIDTH },
14974  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_157_CHECKER_TYPE,
14975  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_157_WIDTH },
14976  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_158_CHECKER_TYPE,
14977  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_158_WIDTH },
14978  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_159_CHECKER_TYPE,
14979  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_159_WIDTH },
14980  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_160_CHECKER_TYPE,
14981  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_160_WIDTH },
14982  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_161_CHECKER_TYPE,
14983  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_161_WIDTH },
14984  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_162_CHECKER_TYPE,
14985  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_162_WIDTH },
14986  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_163_CHECKER_TYPE,
14987  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_163_WIDTH },
14988  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_164_CHECKER_TYPE,
14989  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_164_WIDTH },
14990  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_165_CHECKER_TYPE,
14991  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_165_WIDTH },
14992  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_166_CHECKER_TYPE,
14993  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_166_WIDTH },
14994  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_167_CHECKER_TYPE,
14995  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_167_WIDTH },
14996  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_168_CHECKER_TYPE,
14997  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_168_WIDTH },
14998  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_169_CHECKER_TYPE,
14999  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_169_WIDTH },
15000  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_170_CHECKER_TYPE,
15001  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_170_WIDTH },
15002  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_171_CHECKER_TYPE,
15003  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_171_WIDTH },
15004  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_172_CHECKER_TYPE,
15005  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_172_WIDTH },
15006  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_173_CHECKER_TYPE,
15007  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_173_WIDTH },
15008  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_174_CHECKER_TYPE,
15009  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_174_WIDTH },
15010  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_175_CHECKER_TYPE,
15011  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_175_WIDTH },
15012  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_176_CHECKER_TYPE,
15013  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_176_WIDTH },
15014  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_177_CHECKER_TYPE,
15015  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_177_WIDTH },
15016  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_178_CHECKER_TYPE,
15017  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_178_WIDTH },
15018  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_179_CHECKER_TYPE,
15019  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_179_WIDTH },
15020  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_180_CHECKER_TYPE,
15021  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_180_WIDTH },
15022  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_181_CHECKER_TYPE,
15023  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_181_WIDTH },
15024  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_182_CHECKER_TYPE,
15025  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_182_WIDTH },
15026  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_183_CHECKER_TYPE,
15027  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_183_WIDTH },
15028  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_184_CHECKER_TYPE,
15029  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_184_WIDTH },
15030  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_185_CHECKER_TYPE,
15031  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_185_WIDTH },
15032 };
15033 
15039 static const SDL_GrpChkConfig_t SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_groupEntries[SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_MAX_NUM_CHECKERS] =
15040 {
15041  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_GROUP_0_CHECKER_TYPE,
15042  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_GROUP_0_WIDTH },
15043  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_GROUP_1_CHECKER_TYPE,
15044  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_GROUP_1_WIDTH },
15045  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_GROUP_2_CHECKER_TYPE,
15046  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_GROUP_2_WIDTH },
15047  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_GROUP_3_CHECKER_TYPE,
15048  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_GROUP_3_WIDTH },
15049  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_GROUP_4_CHECKER_TYPE,
15050  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_GROUP_4_WIDTH },
15051  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_GROUP_5_CHECKER_TYPE,
15052  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_GROUP_5_WIDTH },
15053  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_GROUP_6_CHECKER_TYPE,
15054  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_GROUP_6_WIDTH },
15055  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_GROUP_7_CHECKER_TYPE,
15056  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_GROUP_7_WIDTH },
15057  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_GROUP_8_CHECKER_TYPE,
15058  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_GROUP_8_WIDTH },
15059  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_GROUP_9_CHECKER_TYPE,
15060  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_GROUP_9_WIDTH },
15061  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_GROUP_10_CHECKER_TYPE,
15062  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_GROUP_10_WIDTH },
15063  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_GROUP_11_CHECKER_TYPE,
15064  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_GROUP_11_WIDTH },
15065  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_GROUP_12_CHECKER_TYPE,
15066  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_GROUP_12_WIDTH },
15067 };
15068 
15074 static const SDL_GrpChkConfig_t SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_groupEntries[SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS] =
15075 {
15076  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
15077  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
15078  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
15079  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
15080  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
15081  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
15082  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
15083  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
15084  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
15085  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
15086  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_5_CHECKER_TYPE,
15087  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_5_WIDTH },
15088  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_6_CHECKER_TYPE,
15089  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_6_WIDTH },
15090  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_7_CHECKER_TYPE,
15091  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_7_WIDTH },
15092  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_8_CHECKER_TYPE,
15093  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_8_WIDTH },
15094  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_9_CHECKER_TYPE,
15095  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_9_WIDTH },
15096  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_10_CHECKER_TYPE,
15097  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_10_WIDTH },
15098  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_11_CHECKER_TYPE,
15099  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_11_WIDTH },
15100  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_12_CHECKER_TYPE,
15101  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_12_WIDTH },
15102  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_13_CHECKER_TYPE,
15103  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_13_WIDTH },
15104  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_14_CHECKER_TYPE,
15105  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_14_WIDTH },
15106  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_15_CHECKER_TYPE,
15107  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_15_WIDTH },
15108  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_16_CHECKER_TYPE,
15109  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_16_WIDTH },
15110  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_17_CHECKER_TYPE,
15111  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_17_WIDTH },
15112  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_18_CHECKER_TYPE,
15113  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_18_WIDTH },
15114  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_19_CHECKER_TYPE,
15115  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_19_WIDTH },
15116  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_20_CHECKER_TYPE,
15117  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_20_WIDTH },
15118  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_21_CHECKER_TYPE,
15119  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_21_WIDTH },
15120  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_22_CHECKER_TYPE,
15121  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_22_WIDTH },
15122  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_23_CHECKER_TYPE,
15123  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_23_WIDTH },
15124  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_24_CHECKER_TYPE,
15125  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_24_WIDTH },
15126  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_25_CHECKER_TYPE,
15127  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_25_WIDTH },
15128  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_26_CHECKER_TYPE,
15129  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_26_WIDTH },
15130  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_27_CHECKER_TYPE,
15131  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_27_WIDTH },
15132  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_28_CHECKER_TYPE,
15133  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_28_WIDTH },
15134  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_29_CHECKER_TYPE,
15135  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_29_WIDTH },
15136  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_30_CHECKER_TYPE,
15137  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_30_WIDTH },
15138  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_31_CHECKER_TYPE,
15139  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_31_WIDTH },
15140  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_32_CHECKER_TYPE,
15141  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_32_WIDTH },
15142  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_33_CHECKER_TYPE,
15143  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_33_WIDTH },
15144  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_34_CHECKER_TYPE,
15145  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_34_WIDTH },
15146  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_35_CHECKER_TYPE,
15147  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_35_WIDTH },
15148  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_36_CHECKER_TYPE,
15149  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_36_WIDTH },
15150  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_37_CHECKER_TYPE,
15151  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_37_WIDTH },
15152  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_38_CHECKER_TYPE,
15153  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_38_WIDTH },
15154  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_39_CHECKER_TYPE,
15155  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_39_WIDTH },
15156  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_40_CHECKER_TYPE,
15157  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_40_WIDTH },
15158  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_41_CHECKER_TYPE,
15159  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_41_WIDTH },
15160  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_42_CHECKER_TYPE,
15161  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_42_WIDTH },
15162  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_43_CHECKER_TYPE,
15163  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_43_WIDTH },
15164  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_44_CHECKER_TYPE,
15165  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_44_WIDTH },
15166  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_45_CHECKER_TYPE,
15167  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_45_WIDTH },
15168  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_46_CHECKER_TYPE,
15169  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_46_WIDTH },
15170  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_47_CHECKER_TYPE,
15171  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_47_WIDTH },
15172  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_48_CHECKER_TYPE,
15173  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_48_WIDTH },
15174  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_49_CHECKER_TYPE,
15175  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_49_WIDTH },
15176  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_50_CHECKER_TYPE,
15177  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_50_WIDTH },
15178  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_51_CHECKER_TYPE,
15179  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_51_WIDTH },
15180  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_52_CHECKER_TYPE,
15181  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_52_WIDTH },
15182  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_53_CHECKER_TYPE,
15183  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_53_WIDTH },
15184  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_54_CHECKER_TYPE,
15185  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_54_WIDTH },
15186  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_55_CHECKER_TYPE,
15187  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_55_WIDTH },
15188  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_56_CHECKER_TYPE,
15189  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_56_WIDTH },
15190  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_57_CHECKER_TYPE,
15191  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_57_WIDTH },
15192  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_58_CHECKER_TYPE,
15193  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_58_WIDTH },
15194  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_59_CHECKER_TYPE,
15195  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_59_WIDTH },
15196  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_60_CHECKER_TYPE,
15197  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_60_WIDTH },
15198  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_61_CHECKER_TYPE,
15199  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_61_WIDTH },
15200  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_62_CHECKER_TYPE,
15201  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_62_WIDTH },
15202  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_63_CHECKER_TYPE,
15203  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_63_WIDTH },
15204  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_64_CHECKER_TYPE,
15205  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_64_WIDTH },
15206  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_65_CHECKER_TYPE,
15207  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_65_WIDTH },
15208  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_66_CHECKER_TYPE,
15209  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_66_WIDTH },
15210  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_67_CHECKER_TYPE,
15211  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_67_WIDTH },
15212  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_68_CHECKER_TYPE,
15213  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_68_WIDTH },
15214  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_69_CHECKER_TYPE,
15215  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_69_WIDTH },
15216  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_70_CHECKER_TYPE,
15217  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_70_WIDTH },
15218  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_71_CHECKER_TYPE,
15219  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_71_WIDTH },
15220  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_72_CHECKER_TYPE,
15221  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_72_WIDTH },
15222  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_73_CHECKER_TYPE,
15223  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_73_WIDTH },
15224  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_74_CHECKER_TYPE,
15225  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_74_WIDTH },
15226  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_75_CHECKER_TYPE,
15227  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_75_WIDTH },
15228  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_76_CHECKER_TYPE,
15229  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_76_WIDTH },
15230  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_77_CHECKER_TYPE,
15231  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_77_WIDTH },
15232  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_78_CHECKER_TYPE,
15233  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_78_WIDTH },
15234  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_79_CHECKER_TYPE,
15235  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_79_WIDTH },
15236  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_80_CHECKER_TYPE,
15237  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_80_WIDTH },
15238  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_81_CHECKER_TYPE,
15239  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_81_WIDTH },
15240  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_82_CHECKER_TYPE,
15241  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_82_WIDTH },
15242  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_83_CHECKER_TYPE,
15243  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_83_WIDTH },
15244  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_84_CHECKER_TYPE,
15245  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_84_WIDTH },
15246  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_85_CHECKER_TYPE,
15247  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_85_WIDTH },
15248  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_86_CHECKER_TYPE,
15249  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_86_WIDTH },
15250  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_87_CHECKER_TYPE,
15251  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_87_WIDTH },
15252  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_88_CHECKER_TYPE,
15253  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_88_WIDTH },
15254  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_89_CHECKER_TYPE,
15255  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_89_WIDTH },
15256  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_90_CHECKER_TYPE,
15257  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_90_WIDTH },
15258  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_91_CHECKER_TYPE,
15259  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_91_WIDTH },
15260  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_92_CHECKER_TYPE,
15261  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_92_WIDTH },
15262  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_93_CHECKER_TYPE,
15263  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_93_WIDTH },
15264  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_94_CHECKER_TYPE,
15265  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_94_WIDTH },
15266  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_95_CHECKER_TYPE,
15267  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_95_WIDTH },
15268  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_96_CHECKER_TYPE,
15269  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_96_WIDTH },
15270  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_97_CHECKER_TYPE,
15271  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_97_WIDTH },
15272  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_98_CHECKER_TYPE,
15273  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_98_WIDTH },
15274  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_99_CHECKER_TYPE,
15275  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_99_WIDTH },
15276  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_100_CHECKER_TYPE,
15277  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_100_WIDTH },
15278  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_101_CHECKER_TYPE,
15279  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_101_WIDTH },
15280  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_102_CHECKER_TYPE,
15281  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_102_WIDTH },
15282  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_103_CHECKER_TYPE,
15283  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_103_WIDTH },
15284  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_104_CHECKER_TYPE,
15285  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_104_WIDTH },
15286  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_105_CHECKER_TYPE,
15287  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_105_WIDTH },
15288  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_106_CHECKER_TYPE,
15289  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_106_WIDTH },
15290  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_107_CHECKER_TYPE,
15291  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_107_WIDTH },
15292  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_108_CHECKER_TYPE,
15293  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_108_WIDTH },
15294  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_109_CHECKER_TYPE,
15295  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_109_WIDTH },
15296  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_110_CHECKER_TYPE,
15297  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_110_WIDTH },
15298  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_111_CHECKER_TYPE,
15299  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_111_WIDTH },
15300  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_112_CHECKER_TYPE,
15301  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_112_WIDTH },
15302  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_113_CHECKER_TYPE,
15303  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_113_WIDTH },
15304  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_114_CHECKER_TYPE,
15305  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_114_WIDTH },
15306  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_115_CHECKER_TYPE,
15307  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_115_WIDTH },
15308  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_116_CHECKER_TYPE,
15309  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_116_WIDTH },
15310  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_117_CHECKER_TYPE,
15311  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_117_WIDTH },
15312  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_118_CHECKER_TYPE,
15313  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_118_WIDTH },
15314  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_119_CHECKER_TYPE,
15315  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_119_WIDTH },
15316  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_120_CHECKER_TYPE,
15317  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_120_WIDTH },
15318  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_121_CHECKER_TYPE,
15319  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_121_WIDTH },
15320  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_122_CHECKER_TYPE,
15321  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_122_WIDTH },
15322  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_123_CHECKER_TYPE,
15323  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_123_WIDTH },
15324  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_124_CHECKER_TYPE,
15325  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_124_WIDTH },
15326  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_125_CHECKER_TYPE,
15327  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_125_WIDTH },
15328  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_126_CHECKER_TYPE,
15329  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_126_WIDTH },
15330  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_127_CHECKER_TYPE,
15331  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_127_WIDTH },
15332  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_128_CHECKER_TYPE,
15333  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_128_WIDTH },
15334  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_129_CHECKER_TYPE,
15335  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_129_WIDTH },
15336  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_130_CHECKER_TYPE,
15337  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_130_WIDTH },
15338  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_131_CHECKER_TYPE,
15339  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_131_WIDTH },
15340  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_132_CHECKER_TYPE,
15341  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_132_WIDTH },
15342  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_133_CHECKER_TYPE,
15343  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_133_WIDTH },
15344  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_134_CHECKER_TYPE,
15345  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_134_WIDTH },
15346  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_135_CHECKER_TYPE,
15347  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_135_WIDTH },
15348  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_136_CHECKER_TYPE,
15349  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_136_WIDTH },
15350  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_137_CHECKER_TYPE,
15351  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_137_WIDTH },
15352  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_138_CHECKER_TYPE,
15353  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_138_WIDTH },
15354  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_139_CHECKER_TYPE,
15355  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_139_WIDTH },
15356  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_140_CHECKER_TYPE,
15357  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_140_WIDTH },
15358  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_141_CHECKER_TYPE,
15359  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_141_WIDTH },
15360  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_142_CHECKER_TYPE,
15361  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_142_WIDTH },
15362  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_143_CHECKER_TYPE,
15363  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_143_WIDTH },
15364  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_144_CHECKER_TYPE,
15365  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_144_WIDTH },
15366  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_145_CHECKER_TYPE,
15367  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_145_WIDTH },
15368  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_146_CHECKER_TYPE,
15369  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_146_WIDTH },
15370  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_147_CHECKER_TYPE,
15371  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_147_WIDTH },
15372  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_148_CHECKER_TYPE,
15373  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_148_WIDTH },
15374  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_149_CHECKER_TYPE,
15375  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_149_WIDTH },
15376  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_150_CHECKER_TYPE,
15377  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_150_WIDTH },
15378  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_151_CHECKER_TYPE,
15379  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_151_WIDTH },
15380  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_152_CHECKER_TYPE,
15381  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_152_WIDTH },
15382  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_153_CHECKER_TYPE,
15383  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_153_WIDTH },
15384  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_154_CHECKER_TYPE,
15385  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_154_WIDTH },
15386  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_155_CHECKER_TYPE,
15387  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_155_WIDTH },
15388  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_156_CHECKER_TYPE,
15389  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_156_WIDTH },
15390  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_157_CHECKER_TYPE,
15391  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_157_WIDTH },
15392  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_158_CHECKER_TYPE,
15393  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_158_WIDTH },
15394  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_159_CHECKER_TYPE,
15395  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_159_WIDTH },
15396  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_160_CHECKER_TYPE,
15397  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_160_WIDTH },
15398  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_161_CHECKER_TYPE,
15399  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_161_WIDTH },
15400  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_162_CHECKER_TYPE,
15401  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_162_WIDTH },
15402  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_163_CHECKER_TYPE,
15403  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_163_WIDTH },
15404  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_164_CHECKER_TYPE,
15405  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_164_WIDTH },
15406  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_165_CHECKER_TYPE,
15407  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_165_WIDTH },
15408 };
15409 
15415 static const SDL_GrpChkConfig_t SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_groupEntries[SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS] =
15416 {
15417  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
15418  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
15419  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
15420  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
15421  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
15422  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
15423  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
15424  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
15425  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
15426  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
15427  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_5_CHECKER_TYPE,
15428  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_5_WIDTH },
15429  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_6_CHECKER_TYPE,
15430  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_6_WIDTH },
15431  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_7_CHECKER_TYPE,
15432  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_7_WIDTH },
15433  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_8_CHECKER_TYPE,
15434  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_8_WIDTH },
15435  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_9_CHECKER_TYPE,
15436  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_9_WIDTH },
15437  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_10_CHECKER_TYPE,
15438  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_10_WIDTH },
15439  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_11_CHECKER_TYPE,
15440  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_11_WIDTH },
15441  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_12_CHECKER_TYPE,
15442  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_12_WIDTH },
15443  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_13_CHECKER_TYPE,
15444  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_13_WIDTH },
15445  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_14_CHECKER_TYPE,
15446  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_14_WIDTH },
15447  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_15_CHECKER_TYPE,
15448  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_15_WIDTH },
15449  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_16_CHECKER_TYPE,
15450  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_16_WIDTH },
15451  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_17_CHECKER_TYPE,
15452  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_17_WIDTH },
15453  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_18_CHECKER_TYPE,
15454  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_18_WIDTH },
15455  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_19_CHECKER_TYPE,
15456  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_19_WIDTH },
15457  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_20_CHECKER_TYPE,
15458  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_20_WIDTH },
15459  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_21_CHECKER_TYPE,
15460  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_21_WIDTH },
15461  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_22_CHECKER_TYPE,
15462  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_22_WIDTH },
15463  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_23_CHECKER_TYPE,
15464  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_23_WIDTH },
15465  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_24_CHECKER_TYPE,
15466  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_24_WIDTH },
15467  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_25_CHECKER_TYPE,
15468  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_25_WIDTH },
15469  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_26_CHECKER_TYPE,
15470  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_26_WIDTH },
15471  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_27_CHECKER_TYPE,
15472  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_27_WIDTH },
15473  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_28_CHECKER_TYPE,
15474  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_28_WIDTH },
15475  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_29_CHECKER_TYPE,
15476  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_29_WIDTH },
15477  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_30_CHECKER_TYPE,
15478  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_30_WIDTH },
15479  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_31_CHECKER_TYPE,
15480  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_31_WIDTH },
15481  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_32_CHECKER_TYPE,
15482  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_32_WIDTH },
15483  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_33_CHECKER_TYPE,
15484  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_33_WIDTH },
15485  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_34_CHECKER_TYPE,
15486  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_34_WIDTH },
15487  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_35_CHECKER_TYPE,
15488  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_35_WIDTH },
15489  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_36_CHECKER_TYPE,
15490  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_36_WIDTH },
15491  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_37_CHECKER_TYPE,
15492  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_37_WIDTH },
15493  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_38_CHECKER_TYPE,
15494  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_38_WIDTH },
15495  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_39_CHECKER_TYPE,
15496  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_39_WIDTH },
15497  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_40_CHECKER_TYPE,
15498  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_40_WIDTH },
15499  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_41_CHECKER_TYPE,
15500  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_41_WIDTH },
15501  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_42_CHECKER_TYPE,
15502  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_42_WIDTH },
15503  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_43_CHECKER_TYPE,
15504  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_43_WIDTH },
15505  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_44_CHECKER_TYPE,
15506  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_44_WIDTH },
15507  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_45_CHECKER_TYPE,
15508  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_45_WIDTH },
15509  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_46_CHECKER_TYPE,
15510  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_46_WIDTH },
15511  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_47_CHECKER_TYPE,
15512  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_47_WIDTH },
15513  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_48_CHECKER_TYPE,
15514  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_48_WIDTH },
15515  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_49_CHECKER_TYPE,
15516  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_49_WIDTH },
15517  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_50_CHECKER_TYPE,
15518  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_50_WIDTH },
15519  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_51_CHECKER_TYPE,
15520  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_51_WIDTH },
15521  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_52_CHECKER_TYPE,
15522  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_52_WIDTH },
15523  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_53_CHECKER_TYPE,
15524  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_53_WIDTH },
15525  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_54_CHECKER_TYPE,
15526  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_54_WIDTH },
15527  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_55_CHECKER_TYPE,
15528  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_55_WIDTH },
15529  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_56_CHECKER_TYPE,
15530  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_56_WIDTH },
15531  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_57_CHECKER_TYPE,
15532  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_57_WIDTH },
15533  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_58_CHECKER_TYPE,
15534  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_58_WIDTH },
15535  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_59_CHECKER_TYPE,
15536  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_59_WIDTH },
15537  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_60_CHECKER_TYPE,
15538  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_60_WIDTH },
15539  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_61_CHECKER_TYPE,
15540  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_61_WIDTH },
15541  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_62_CHECKER_TYPE,
15542  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_62_WIDTH },
15543 };
15544 
15550 static const SDL_GrpChkConfig_t SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_DEFAULT_MMRS_SMS_HSM_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_groupEntries[SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_DEFAULT_MMRS_SMS_HSM_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS] =
15551 {
15552  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_DEFAULT_MMRS_SMS_HSM_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
15553  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_DEFAULT_MMRS_SMS_HSM_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
15554  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_DEFAULT_MMRS_SMS_HSM_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
15555  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_DEFAULT_MMRS_SMS_HSM_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
15556  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_DEFAULT_MMRS_SMS_HSM_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
15557  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_DEFAULT_MMRS_SMS_HSM_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
15558  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_DEFAULT_MMRS_SMS_HSM_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
15559  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_DEFAULT_MMRS_SMS_HSM_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
15560  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_DEFAULT_MMRS_SMS_HSM_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
15561  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_DEFAULT_MMRS_SMS_HSM_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
15562  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_DEFAULT_MMRS_SMS_HSM_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_5_CHECKER_TYPE,
15563  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_DEFAULT_MMRS_SMS_HSM_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_5_WIDTH },
15564  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_DEFAULT_MMRS_SMS_HSM_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_6_CHECKER_TYPE,
15565  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_DEFAULT_MMRS_SMS_HSM_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_6_WIDTH },
15566  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_DEFAULT_MMRS_SMS_HSM_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_7_CHECKER_TYPE,
15567  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_DEFAULT_MMRS_SMS_HSM_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_7_WIDTH },
15568 };
15569 
15575 static const SDL_GrpChkConfig_t SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_groupEntries[SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS] =
15576 {
15577  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
15578  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
15579  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
15580  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
15581  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
15582  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
15583  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
15584  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
15585  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
15586  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
15587  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_5_CHECKER_TYPE,
15588  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_5_WIDTH },
15589  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_6_CHECKER_TYPE,
15590  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_6_WIDTH },
15591  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_7_CHECKER_TYPE,
15592  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_7_WIDTH },
15593  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_8_CHECKER_TYPE,
15594  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_8_WIDTH },
15595  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_9_CHECKER_TYPE,
15596  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_9_WIDTH },
15597  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_10_CHECKER_TYPE,
15598  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_10_WIDTH },
15599  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_11_CHECKER_TYPE,
15600  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_11_WIDTH },
15601  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_12_CHECKER_TYPE,
15602  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_12_WIDTH },
15603  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_13_CHECKER_TYPE,
15604  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_13_WIDTH },
15605  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_14_CHECKER_TYPE,
15606  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_14_WIDTH },
15607  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_15_CHECKER_TYPE,
15608  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_15_WIDTH },
15609  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_16_CHECKER_TYPE,
15610  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_16_WIDTH },
15611  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_17_CHECKER_TYPE,
15612  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_17_WIDTH },
15613  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_18_CHECKER_TYPE,
15614  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_18_WIDTH },
15615  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_19_CHECKER_TYPE,
15616  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_19_WIDTH },
15617  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_20_CHECKER_TYPE,
15618  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_20_WIDTH },
15619  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_21_CHECKER_TYPE,
15620  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_21_WIDTH },
15621  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_22_CHECKER_TYPE,
15622  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_22_WIDTH },
15623  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_23_CHECKER_TYPE,
15624  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_23_WIDTH },
15625  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_24_CHECKER_TYPE,
15626  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_24_WIDTH },
15627  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_25_CHECKER_TYPE,
15628  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_25_WIDTH },
15629  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_26_CHECKER_TYPE,
15630  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_26_WIDTH },
15631  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_27_CHECKER_TYPE,
15632  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_27_WIDTH },
15633  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_28_CHECKER_TYPE,
15634  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_28_WIDTH },
15635  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_29_CHECKER_TYPE,
15636  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_29_WIDTH },
15637  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_30_CHECKER_TYPE,
15638  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_30_WIDTH },
15639  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_31_CHECKER_TYPE,
15640  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_31_WIDTH },
15641  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_32_CHECKER_TYPE,
15642  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_32_WIDTH },
15643  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_33_CHECKER_TYPE,
15644  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_33_WIDTH },
15645  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_34_CHECKER_TYPE,
15646  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_34_WIDTH },
15647  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_35_CHECKER_TYPE,
15648  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_35_WIDTH },
15649  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_36_CHECKER_TYPE,
15650  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_36_WIDTH },
15651  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_37_CHECKER_TYPE,
15652  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_37_WIDTH },
15653  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_38_CHECKER_TYPE,
15654  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_38_WIDTH },
15655  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_39_CHECKER_TYPE,
15656  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_39_WIDTH },
15657  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_40_CHECKER_TYPE,
15658  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_40_WIDTH },
15659  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_41_CHECKER_TYPE,
15660  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_41_WIDTH },
15661 };
15662 
15668 static const SDL_GrpChkConfig_t SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_groupEntries[SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_MAX_NUM_CHECKERS] =
15669 {
15670  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_0_CHECKER_TYPE,
15671  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_0_WIDTH },
15672  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_1_CHECKER_TYPE,
15673  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_1_WIDTH },
15674  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_2_CHECKER_TYPE,
15675  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_2_WIDTH },
15676  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_3_CHECKER_TYPE,
15677  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_3_WIDTH },
15678  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_4_CHECKER_TYPE,
15679  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_4_WIDTH },
15680  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_5_CHECKER_TYPE,
15681  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_5_WIDTH },
15682  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_6_CHECKER_TYPE,
15683  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_6_WIDTH },
15684  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_7_CHECKER_TYPE,
15685  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_7_WIDTH },
15686  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_8_CHECKER_TYPE,
15687  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_8_WIDTH },
15688  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_9_CHECKER_TYPE,
15689  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_9_WIDTH },
15690  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_10_CHECKER_TYPE,
15691  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_10_WIDTH },
15692  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_11_CHECKER_TYPE,
15693  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_11_WIDTH },
15694  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_12_CHECKER_TYPE,
15695  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_12_WIDTH },
15696  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_13_CHECKER_TYPE,
15697  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_13_WIDTH },
15698  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_14_CHECKER_TYPE,
15699  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_14_WIDTH },
15700  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_15_CHECKER_TYPE,
15701  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_15_WIDTH },
15702  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_16_CHECKER_TYPE,
15703  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_16_WIDTH },
15704  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_17_CHECKER_TYPE,
15705  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_17_WIDTH },
15706  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_18_CHECKER_TYPE,
15707  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_18_WIDTH },
15708 };
15709 
15715 static const SDL_GrpChkConfig_t SDL_SMS0_SMS_HSM_ECC_SMS_HSM_WWRTI_CM_EDC_CTRL_BUSECC_groupEntries[SDL_SMS0_SMS_HSM_ECC_SMS_HSM_WWRTI_CM_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS] =
15716 {
15717  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_WWRTI_CM_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
15718  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_WWRTI_CM_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
15719  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_WWRTI_CM_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
15720  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_WWRTI_CM_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
15721  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_WWRTI_CM_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
15722  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_WWRTI_CM_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
15723  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_WWRTI_CM_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
15724  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_WWRTI_CM_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
15725  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_WWRTI_CM_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
15726  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_WWRTI_CM_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
15727  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_WWRTI_CM_EDC_CTRL_BUSECC_GROUP_5_CHECKER_TYPE,
15728  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_WWRTI_CM_EDC_CTRL_BUSECC_GROUP_5_WIDTH },
15729  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_WWRTI_CM_EDC_CTRL_BUSECC_GROUP_6_CHECKER_TYPE,
15730  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_WWRTI_CM_EDC_CTRL_BUSECC_GROUP_6_WIDTH },
15731  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_WWRTI_CM_EDC_CTRL_BUSECC_GROUP_7_CHECKER_TYPE,
15732  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_WWRTI_CM_EDC_CTRL_BUSECC_GROUP_7_WIDTH },
15733  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_WWRTI_CM_EDC_CTRL_BUSECC_GROUP_8_CHECKER_TYPE,
15734  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_WWRTI_CM_EDC_CTRL_BUSECC_GROUP_8_WIDTH },
15735  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_WWRTI_CM_EDC_CTRL_BUSECC_GROUP_9_CHECKER_TYPE,
15736  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_WWRTI_CM_EDC_CTRL_BUSECC_GROUP_9_WIDTH },
15737  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_WWRTI_CM_EDC_CTRL_BUSECC_GROUP_10_CHECKER_TYPE,
15738  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_WWRTI_CM_EDC_CTRL_BUSECC_GROUP_10_WIDTH },
15739  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_WWRTI_CM_EDC_CTRL_BUSECC_GROUP_11_CHECKER_TYPE,
15740  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_WWRTI_CM_EDC_CTRL_BUSECC_GROUP_11_WIDTH },
15741  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_WWRTI_CM_EDC_CTRL_BUSECC_GROUP_12_CHECKER_TYPE,
15742  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_WWRTI_CM_EDC_CTRL_BUSECC_GROUP_12_WIDTH },
15743  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_WWRTI_CM_EDC_CTRL_BUSECC_GROUP_13_CHECKER_TYPE,
15744  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_WWRTI_CM_EDC_CTRL_BUSECC_GROUP_13_WIDTH },
15745  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_WWRTI_CM_EDC_CTRL_BUSECC_GROUP_14_CHECKER_TYPE,
15746  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_WWRTI_CM_EDC_CTRL_BUSECC_GROUP_14_WIDTH },
15747  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_WWRTI_CM_EDC_CTRL_BUSECC_GROUP_15_CHECKER_TYPE,
15748  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_WWRTI_CM_EDC_CTRL_BUSECC_GROUP_15_WIDTH },
15749 };
15750 
15756 static const SDL_GrpChkConfig_t SDL_SMS0_SMS_HSM_ECC_SMS_HSM_ECC_EDC_CTRL_groupEntries[SDL_SMS0_SMS_HSM_ECC_SMS_HSM_ECC_EDC_CTRL_MAX_NUM_CHECKERS] =
15757 {
15758  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_ECC_EDC_CTRL_GROUP_0_CHECKER_TYPE,
15759  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_ECC_EDC_CTRL_GROUP_0_WIDTH },
15760  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_ECC_EDC_CTRL_GROUP_1_CHECKER_TYPE,
15761  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_ECC_EDC_CTRL_GROUP_1_WIDTH },
15762  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_ECC_EDC_CTRL_GROUP_2_CHECKER_TYPE,
15763  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_ECC_EDC_CTRL_GROUP_2_WIDTH },
15764  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_ECC_EDC_CTRL_GROUP_3_CHECKER_TYPE,
15765  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_ECC_EDC_CTRL_GROUP_3_WIDTH },
15766  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_ECC_EDC_CTRL_GROUP_4_CHECKER_TYPE,
15767  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_ECC_EDC_CTRL_GROUP_4_WIDTH },
15768  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_ECC_EDC_CTRL_GROUP_5_CHECKER_TYPE,
15769  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_ECC_EDC_CTRL_GROUP_5_WIDTH },
15770 };
15771 
15776 static const SDL_MemConfig_t SDL_SMS0_SMS_TIFS_ECC_MemEntries[SDL_SMS0_SMS_TIFS_ECC_RAM_IDS_TOTAL_ENTRIES] =
15777 {
15778  { SDL_SMS0_SMS_TIFS_ECC_ISRAM0_RAMECC_RAM_ID, 0u,
15779  SDL_SMS0_SMS_TIFS_ECC_ISRAM0_RAMECC_RAM_SIZE, 4u,
15780  SDL_SMS0_SMS_TIFS_ECC_ISRAM0_RAMECC_ROW_WIDTH, ((bool)false) },
15781  { SDL_SMS0_SMS_TIFS_ECC_ISRAM1_RAMECC_RAM_ID, 0u,
15782  SDL_SMS0_SMS_TIFS_ECC_ISRAM1_RAMECC_RAM_SIZE, 4u,
15783  SDL_SMS0_SMS_TIFS_ECC_ISRAM1_RAMECC_ROW_WIDTH, ((bool)false) },
15784 };
15785 
15791 static const SDL_GrpChkConfig_t SDL_SMS0_SMS_TIFS_ECC_ISRAM0_BUSECC_groupEntries[SDL_SMS0_SMS_TIFS_ECC_ISRAM0_BUSECC_MAX_NUM_CHECKERS] =
15792 {
15793  { SDL_SMS0_SMS_TIFS_ECC_ISRAM0_BUSECC_GROUP_0_CHECKER_TYPE,
15794  SDL_SMS0_SMS_TIFS_ECC_ISRAM0_BUSECC_GROUP_0_WIDTH },
15795  { SDL_SMS0_SMS_TIFS_ECC_ISRAM0_BUSECC_GROUP_1_CHECKER_TYPE,
15796  SDL_SMS0_SMS_TIFS_ECC_ISRAM0_BUSECC_GROUP_1_WIDTH },
15797  { SDL_SMS0_SMS_TIFS_ECC_ISRAM0_BUSECC_GROUP_2_CHECKER_TYPE,
15798  SDL_SMS0_SMS_TIFS_ECC_ISRAM0_BUSECC_GROUP_2_WIDTH },
15799  { SDL_SMS0_SMS_TIFS_ECC_ISRAM0_BUSECC_GROUP_3_CHECKER_TYPE,
15800  SDL_SMS0_SMS_TIFS_ECC_ISRAM0_BUSECC_GROUP_3_WIDTH },
15801  { SDL_SMS0_SMS_TIFS_ECC_ISRAM0_BUSECC_GROUP_4_CHECKER_TYPE,
15802  SDL_SMS0_SMS_TIFS_ECC_ISRAM0_BUSECC_GROUP_4_WIDTH },
15803  { SDL_SMS0_SMS_TIFS_ECC_ISRAM0_BUSECC_GROUP_5_CHECKER_TYPE,
15804  SDL_SMS0_SMS_TIFS_ECC_ISRAM0_BUSECC_GROUP_5_WIDTH },
15805  { SDL_SMS0_SMS_TIFS_ECC_ISRAM0_BUSECC_GROUP_6_CHECKER_TYPE,
15806  SDL_SMS0_SMS_TIFS_ECC_ISRAM0_BUSECC_GROUP_6_WIDTH },
15807  { SDL_SMS0_SMS_TIFS_ECC_ISRAM0_BUSECC_GROUP_7_CHECKER_TYPE,
15808  SDL_SMS0_SMS_TIFS_ECC_ISRAM0_BUSECC_GROUP_7_WIDTH },
15809  { SDL_SMS0_SMS_TIFS_ECC_ISRAM0_BUSECC_GROUP_8_CHECKER_TYPE,
15810  SDL_SMS0_SMS_TIFS_ECC_ISRAM0_BUSECC_GROUP_8_WIDTH },
15811  { SDL_SMS0_SMS_TIFS_ECC_ISRAM0_BUSECC_GROUP_9_CHECKER_TYPE,
15812  SDL_SMS0_SMS_TIFS_ECC_ISRAM0_BUSECC_GROUP_9_WIDTH },
15813  { SDL_SMS0_SMS_TIFS_ECC_ISRAM0_BUSECC_GROUP_10_CHECKER_TYPE,
15814  SDL_SMS0_SMS_TIFS_ECC_ISRAM0_BUSECC_GROUP_10_WIDTH },
15815  { SDL_SMS0_SMS_TIFS_ECC_ISRAM0_BUSECC_GROUP_11_CHECKER_TYPE,
15816  SDL_SMS0_SMS_TIFS_ECC_ISRAM0_BUSECC_GROUP_11_WIDTH },
15817  { SDL_SMS0_SMS_TIFS_ECC_ISRAM0_BUSECC_GROUP_12_CHECKER_TYPE,
15818  SDL_SMS0_SMS_TIFS_ECC_ISRAM0_BUSECC_GROUP_12_WIDTH },
15819  { SDL_SMS0_SMS_TIFS_ECC_ISRAM0_BUSECC_GROUP_13_CHECKER_TYPE,
15820  SDL_SMS0_SMS_TIFS_ECC_ISRAM0_BUSECC_GROUP_13_WIDTH },
15821  { SDL_SMS0_SMS_TIFS_ECC_ISRAM0_BUSECC_GROUP_14_CHECKER_TYPE,
15822  SDL_SMS0_SMS_TIFS_ECC_ISRAM0_BUSECC_GROUP_14_WIDTH },
15823  { SDL_SMS0_SMS_TIFS_ECC_ISRAM0_BUSECC_GROUP_15_CHECKER_TYPE,
15824  SDL_SMS0_SMS_TIFS_ECC_ISRAM0_BUSECC_GROUP_15_WIDTH },
15825  { SDL_SMS0_SMS_TIFS_ECC_ISRAM0_BUSECC_GROUP_16_CHECKER_TYPE,
15826  SDL_SMS0_SMS_TIFS_ECC_ISRAM0_BUSECC_GROUP_16_WIDTH },
15827  { SDL_SMS0_SMS_TIFS_ECC_ISRAM0_BUSECC_GROUP_17_CHECKER_TYPE,
15828  SDL_SMS0_SMS_TIFS_ECC_ISRAM0_BUSECC_GROUP_17_WIDTH },
15829  { SDL_SMS0_SMS_TIFS_ECC_ISRAM0_BUSECC_GROUP_18_CHECKER_TYPE,
15830  SDL_SMS0_SMS_TIFS_ECC_ISRAM0_BUSECC_GROUP_18_WIDTH },
15831  { SDL_SMS0_SMS_TIFS_ECC_ISRAM0_BUSECC_GROUP_19_CHECKER_TYPE,
15832  SDL_SMS0_SMS_TIFS_ECC_ISRAM0_BUSECC_GROUP_19_WIDTH },
15833 };
15834 
15840 static const SDL_GrpChkConfig_t SDL_SMS0_SMS_TIFS_ECC_ISRAM1_BUSECC_groupEntries[SDL_SMS0_SMS_TIFS_ECC_ISRAM1_BUSECC_MAX_NUM_CHECKERS] =
15841 {
15842  { SDL_SMS0_SMS_TIFS_ECC_ISRAM1_BUSECC_GROUP_0_CHECKER_TYPE,
15843  SDL_SMS0_SMS_TIFS_ECC_ISRAM1_BUSECC_GROUP_0_WIDTH },
15844  { SDL_SMS0_SMS_TIFS_ECC_ISRAM1_BUSECC_GROUP_1_CHECKER_TYPE,
15845  SDL_SMS0_SMS_TIFS_ECC_ISRAM1_BUSECC_GROUP_1_WIDTH },
15846  { SDL_SMS0_SMS_TIFS_ECC_ISRAM1_BUSECC_GROUP_2_CHECKER_TYPE,
15847  SDL_SMS0_SMS_TIFS_ECC_ISRAM1_BUSECC_GROUP_2_WIDTH },
15848  { SDL_SMS0_SMS_TIFS_ECC_ISRAM1_BUSECC_GROUP_3_CHECKER_TYPE,
15849  SDL_SMS0_SMS_TIFS_ECC_ISRAM1_BUSECC_GROUP_3_WIDTH },
15850  { SDL_SMS0_SMS_TIFS_ECC_ISRAM1_BUSECC_GROUP_4_CHECKER_TYPE,
15851  SDL_SMS0_SMS_TIFS_ECC_ISRAM1_BUSECC_GROUP_4_WIDTH },
15852  { SDL_SMS0_SMS_TIFS_ECC_ISRAM1_BUSECC_GROUP_5_CHECKER_TYPE,
15853  SDL_SMS0_SMS_TIFS_ECC_ISRAM1_BUSECC_GROUP_5_WIDTH },
15854  { SDL_SMS0_SMS_TIFS_ECC_ISRAM1_BUSECC_GROUP_6_CHECKER_TYPE,
15855  SDL_SMS0_SMS_TIFS_ECC_ISRAM1_BUSECC_GROUP_6_WIDTH },
15856  { SDL_SMS0_SMS_TIFS_ECC_ISRAM1_BUSECC_GROUP_7_CHECKER_TYPE,
15857  SDL_SMS0_SMS_TIFS_ECC_ISRAM1_BUSECC_GROUP_7_WIDTH },
15858  { SDL_SMS0_SMS_TIFS_ECC_ISRAM1_BUSECC_GROUP_8_CHECKER_TYPE,
15859  SDL_SMS0_SMS_TIFS_ECC_ISRAM1_BUSECC_GROUP_8_WIDTH },
15860  { SDL_SMS0_SMS_TIFS_ECC_ISRAM1_BUSECC_GROUP_9_CHECKER_TYPE,
15861  SDL_SMS0_SMS_TIFS_ECC_ISRAM1_BUSECC_GROUP_9_WIDTH },
15862  { SDL_SMS0_SMS_TIFS_ECC_ISRAM1_BUSECC_GROUP_10_CHECKER_TYPE,
15863  SDL_SMS0_SMS_TIFS_ECC_ISRAM1_BUSECC_GROUP_10_WIDTH },
15864  { SDL_SMS0_SMS_TIFS_ECC_ISRAM1_BUSECC_GROUP_11_CHECKER_TYPE,
15865  SDL_SMS0_SMS_TIFS_ECC_ISRAM1_BUSECC_GROUP_11_WIDTH },
15866  { SDL_SMS0_SMS_TIFS_ECC_ISRAM1_BUSECC_GROUP_12_CHECKER_TYPE,
15867  SDL_SMS0_SMS_TIFS_ECC_ISRAM1_BUSECC_GROUP_12_WIDTH },
15868  { SDL_SMS0_SMS_TIFS_ECC_ISRAM1_BUSECC_GROUP_13_CHECKER_TYPE,
15869  SDL_SMS0_SMS_TIFS_ECC_ISRAM1_BUSECC_GROUP_13_WIDTH },
15870  { SDL_SMS0_SMS_TIFS_ECC_ISRAM1_BUSECC_GROUP_14_CHECKER_TYPE,
15871  SDL_SMS0_SMS_TIFS_ECC_ISRAM1_BUSECC_GROUP_14_WIDTH },
15872  { SDL_SMS0_SMS_TIFS_ECC_ISRAM1_BUSECC_GROUP_15_CHECKER_TYPE,
15873  SDL_SMS0_SMS_TIFS_ECC_ISRAM1_BUSECC_GROUP_15_WIDTH },
15874  { SDL_SMS0_SMS_TIFS_ECC_ISRAM1_BUSECC_GROUP_16_CHECKER_TYPE,
15875  SDL_SMS0_SMS_TIFS_ECC_ISRAM1_BUSECC_GROUP_16_WIDTH },
15876  { SDL_SMS0_SMS_TIFS_ECC_ISRAM1_BUSECC_GROUP_17_CHECKER_TYPE,
15877  SDL_SMS0_SMS_TIFS_ECC_ISRAM1_BUSECC_GROUP_17_WIDTH },
15878  { SDL_SMS0_SMS_TIFS_ECC_ISRAM1_BUSECC_GROUP_18_CHECKER_TYPE,
15879  SDL_SMS0_SMS_TIFS_ECC_ISRAM1_BUSECC_GROUP_18_WIDTH },
15880  { SDL_SMS0_SMS_TIFS_ECC_ISRAM1_BUSECC_GROUP_19_CHECKER_TYPE,
15881  SDL_SMS0_SMS_TIFS_ECC_ISRAM1_BUSECC_GROUP_19_WIDTH },
15882 };
15883 
15889 static const SDL_GrpChkConfig_t SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_groupEntries[SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_MAX_NUM_CHECKERS] =
15890 {
15891  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_0_CHECKER_TYPE,
15892  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_0_WIDTH },
15893  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_1_CHECKER_TYPE,
15894  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_1_WIDTH },
15895  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_2_CHECKER_TYPE,
15896  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_2_WIDTH },
15897  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_3_CHECKER_TYPE,
15898  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_3_WIDTH },
15899  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_4_CHECKER_TYPE,
15900  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_4_WIDTH },
15901  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_5_CHECKER_TYPE,
15902  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_5_WIDTH },
15903  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_6_CHECKER_TYPE,
15904  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_6_WIDTH },
15905  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_7_CHECKER_TYPE,
15906  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_7_WIDTH },
15907  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_8_CHECKER_TYPE,
15908  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_8_WIDTH },
15909  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_9_CHECKER_TYPE,
15910  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_9_WIDTH },
15911  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_10_CHECKER_TYPE,
15912  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_10_WIDTH },
15913  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_11_CHECKER_TYPE,
15914  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_11_WIDTH },
15915  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_12_CHECKER_TYPE,
15916  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_12_WIDTH },
15917  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_13_CHECKER_TYPE,
15918  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_13_WIDTH },
15919  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_14_CHECKER_TYPE,
15920  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_14_WIDTH },
15921  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_15_CHECKER_TYPE,
15922  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_15_WIDTH },
15923  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_16_CHECKER_TYPE,
15924  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_16_WIDTH },
15925  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_17_CHECKER_TYPE,
15926  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_17_WIDTH },
15927  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_18_CHECKER_TYPE,
15928  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_18_WIDTH },
15929  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_19_CHECKER_TYPE,
15930  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_19_WIDTH },
15931  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_20_CHECKER_TYPE,
15932  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_20_WIDTH },
15933  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_21_CHECKER_TYPE,
15934  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_21_WIDTH },
15935  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_22_CHECKER_TYPE,
15936  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_22_WIDTH },
15937  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_23_CHECKER_TYPE,
15938  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_23_WIDTH },
15939  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_24_CHECKER_TYPE,
15940  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_24_WIDTH },
15941  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_25_CHECKER_TYPE,
15942  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_25_WIDTH },
15943  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_26_CHECKER_TYPE,
15944  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_26_WIDTH },
15945  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_27_CHECKER_TYPE,
15946  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_27_WIDTH },
15947  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_28_CHECKER_TYPE,
15948  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_28_WIDTH },
15949  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_29_CHECKER_TYPE,
15950  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_29_WIDTH },
15951  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_30_CHECKER_TYPE,
15952  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_30_WIDTH },
15953  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_31_CHECKER_TYPE,
15954  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_31_WIDTH },
15955  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_32_CHECKER_TYPE,
15956  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_32_WIDTH },
15957  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_33_CHECKER_TYPE,
15958  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_33_WIDTH },
15959  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_34_CHECKER_TYPE,
15960  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_34_WIDTH },
15961  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_35_CHECKER_TYPE,
15962  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_35_WIDTH },
15963  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_36_CHECKER_TYPE,
15964  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_36_WIDTH },
15965  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_37_CHECKER_TYPE,
15966  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_37_WIDTH },
15967  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_38_CHECKER_TYPE,
15968  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_38_WIDTH },
15969  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_39_CHECKER_TYPE,
15970  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_39_WIDTH },
15971  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_40_CHECKER_TYPE,
15972  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_40_WIDTH },
15973  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_41_CHECKER_TYPE,
15974  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_41_WIDTH },
15975  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_42_CHECKER_TYPE,
15976  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_42_WIDTH },
15977  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_43_CHECKER_TYPE,
15978  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_43_WIDTH },
15979  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_44_CHECKER_TYPE,
15980  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_44_WIDTH },
15981  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_45_CHECKER_TYPE,
15982  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_45_WIDTH },
15983  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_46_CHECKER_TYPE,
15984  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_46_WIDTH },
15985  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_47_CHECKER_TYPE,
15986  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_47_WIDTH },
15987  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_48_CHECKER_TYPE,
15988  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_48_WIDTH },
15989  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_49_CHECKER_TYPE,
15990  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_49_WIDTH },
15991  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_50_CHECKER_TYPE,
15992  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_50_WIDTH },
15993  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_51_CHECKER_TYPE,
15994  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_51_WIDTH },
15995  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_52_CHECKER_TYPE,
15996  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_52_WIDTH },
15997  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_53_CHECKER_TYPE,
15998  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_53_WIDTH },
15999  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_54_CHECKER_TYPE,
16000  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_54_WIDTH },
16001  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_55_CHECKER_TYPE,
16002  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_55_WIDTH },
16003  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_56_CHECKER_TYPE,
16004  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_56_WIDTH },
16005  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_57_CHECKER_TYPE,
16006  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_57_WIDTH },
16007  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_58_CHECKER_TYPE,
16008  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_58_WIDTH },
16009  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_59_CHECKER_TYPE,
16010  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_59_WIDTH },
16011  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_60_CHECKER_TYPE,
16012  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_60_WIDTH },
16013  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_61_CHECKER_TYPE,
16014  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_61_WIDTH },
16015  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_62_CHECKER_TYPE,
16016  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_62_WIDTH },
16017  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_63_CHECKER_TYPE,
16018  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_63_WIDTH },
16019  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_64_CHECKER_TYPE,
16020  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_64_WIDTH },
16021  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_65_CHECKER_TYPE,
16022  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_65_WIDTH },
16023  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_66_CHECKER_TYPE,
16024  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_66_WIDTH },
16025  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_67_CHECKER_TYPE,
16026  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_67_WIDTH },
16027  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_68_CHECKER_TYPE,
16028  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_68_WIDTH },
16029  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_69_CHECKER_TYPE,
16030  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_69_WIDTH },
16031  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_70_CHECKER_TYPE,
16032  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_70_WIDTH },
16033  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_71_CHECKER_TYPE,
16034  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_71_WIDTH },
16035  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_72_CHECKER_TYPE,
16036  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_72_WIDTH },
16037  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_73_CHECKER_TYPE,
16038  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_73_WIDTH },
16039  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_74_CHECKER_TYPE,
16040  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_74_WIDTH },
16041  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_75_CHECKER_TYPE,
16042  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_75_WIDTH },
16043  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_76_CHECKER_TYPE,
16044  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_76_WIDTH },
16045  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_77_CHECKER_TYPE,
16046  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_77_WIDTH },
16047  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_78_CHECKER_TYPE,
16048  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_78_WIDTH },
16049  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_79_CHECKER_TYPE,
16050  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_79_WIDTH },
16051  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_80_CHECKER_TYPE,
16052  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_80_WIDTH },
16053  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_81_CHECKER_TYPE,
16054  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_81_WIDTH },
16055  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_82_CHECKER_TYPE,
16056  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_82_WIDTH },
16057  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_83_CHECKER_TYPE,
16058  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_83_WIDTH },
16059  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_84_CHECKER_TYPE,
16060  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_84_WIDTH },
16061  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_85_CHECKER_TYPE,
16062  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_85_WIDTH },
16063  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_86_CHECKER_TYPE,
16064  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_86_WIDTH },
16065  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_87_CHECKER_TYPE,
16066  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_87_WIDTH },
16067  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_88_CHECKER_TYPE,
16068  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_88_WIDTH },
16069  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_89_CHECKER_TYPE,
16070  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_89_WIDTH },
16071  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_90_CHECKER_TYPE,
16072  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_90_WIDTH },
16073  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_91_CHECKER_TYPE,
16074  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_91_WIDTH },
16075  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_92_CHECKER_TYPE,
16076  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_92_WIDTH },
16077  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_93_CHECKER_TYPE,
16078  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_93_WIDTH },
16079  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_94_CHECKER_TYPE,
16080  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_94_WIDTH },
16081  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_95_CHECKER_TYPE,
16082  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_95_WIDTH },
16083  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_96_CHECKER_TYPE,
16084  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_96_WIDTH },
16085  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_97_CHECKER_TYPE,
16086  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_97_WIDTH },
16087  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_98_CHECKER_TYPE,
16088  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_98_WIDTH },
16089  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_99_CHECKER_TYPE,
16090  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_99_WIDTH },
16091  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_100_CHECKER_TYPE,
16092  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_100_WIDTH },
16093  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_101_CHECKER_TYPE,
16094  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_101_WIDTH },
16095  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_102_CHECKER_TYPE,
16096  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_102_WIDTH },
16097  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_103_CHECKER_TYPE,
16098  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_103_WIDTH },
16099  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_104_CHECKER_TYPE,
16100  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_104_WIDTH },
16101  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_105_CHECKER_TYPE,
16102  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_105_WIDTH },
16103  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_106_CHECKER_TYPE,
16104  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_106_WIDTH },
16105  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_107_CHECKER_TYPE,
16106  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_107_WIDTH },
16107  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_108_CHECKER_TYPE,
16108  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_108_WIDTH },
16109  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_109_CHECKER_TYPE,
16110  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_109_WIDTH },
16111  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_110_CHECKER_TYPE,
16112  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_110_WIDTH },
16113  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_111_CHECKER_TYPE,
16114  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_111_WIDTH },
16115  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_112_CHECKER_TYPE,
16116  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_112_WIDTH },
16117  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_113_CHECKER_TYPE,
16118  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_113_WIDTH },
16119  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_114_CHECKER_TYPE,
16120  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_114_WIDTH },
16121  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_115_CHECKER_TYPE,
16122  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_115_WIDTH },
16123  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_116_CHECKER_TYPE,
16124  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_116_WIDTH },
16125  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_117_CHECKER_TYPE,
16126  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_117_WIDTH },
16127  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_118_CHECKER_TYPE,
16128  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_118_WIDTH },
16129  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_119_CHECKER_TYPE,
16130  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_119_WIDTH },
16131  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_120_CHECKER_TYPE,
16132  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_120_WIDTH },
16133  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_121_CHECKER_TYPE,
16134  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_121_WIDTH },
16135  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_122_CHECKER_TYPE,
16136  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_122_WIDTH },
16137  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_123_CHECKER_TYPE,
16138  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_123_WIDTH },
16139  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_124_CHECKER_TYPE,
16140  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_124_WIDTH },
16141  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_125_CHECKER_TYPE,
16142  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_125_WIDTH },
16143  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_126_CHECKER_TYPE,
16144  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_126_WIDTH },
16145  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_127_CHECKER_TYPE,
16146  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_127_WIDTH },
16147  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_128_CHECKER_TYPE,
16148  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_128_WIDTH },
16149  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_129_CHECKER_TYPE,
16150  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_129_WIDTH },
16151  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_130_CHECKER_TYPE,
16152  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_130_WIDTH },
16153  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_131_CHECKER_TYPE,
16154  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_131_WIDTH },
16155  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_132_CHECKER_TYPE,
16156  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_132_WIDTH },
16157  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_133_CHECKER_TYPE,
16158  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_133_WIDTH },
16159  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_134_CHECKER_TYPE,
16160  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_134_WIDTH },
16161  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_135_CHECKER_TYPE,
16162  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_135_WIDTH },
16163  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_136_CHECKER_TYPE,
16164  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_136_WIDTH },
16165  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_137_CHECKER_TYPE,
16166  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_137_WIDTH },
16167  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_138_CHECKER_TYPE,
16168  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_138_WIDTH },
16169  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_139_CHECKER_TYPE,
16170  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_139_WIDTH },
16171  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_140_CHECKER_TYPE,
16172  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_140_WIDTH },
16173  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_141_CHECKER_TYPE,
16174  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_141_WIDTH },
16175  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_142_CHECKER_TYPE,
16176  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_142_WIDTH },
16177  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_143_CHECKER_TYPE,
16178  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_143_WIDTH },
16179  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_144_CHECKER_TYPE,
16180  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_144_WIDTH },
16181  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_145_CHECKER_TYPE,
16182  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_145_WIDTH },
16183  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_146_CHECKER_TYPE,
16184  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_146_WIDTH },
16185  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_147_CHECKER_TYPE,
16186  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_147_WIDTH },
16187  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_148_CHECKER_TYPE,
16188  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_148_WIDTH },
16189  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_149_CHECKER_TYPE,
16190  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_149_WIDTH },
16191  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_150_CHECKER_TYPE,
16192  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_150_WIDTH },
16193  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_151_CHECKER_TYPE,
16194  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_151_WIDTH },
16195  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_152_CHECKER_TYPE,
16196  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_152_WIDTH },
16197  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_153_CHECKER_TYPE,
16198  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_153_WIDTH },
16199  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_154_CHECKER_TYPE,
16200  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_154_WIDTH },
16201  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_155_CHECKER_TYPE,
16202  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_155_WIDTH },
16203  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_156_CHECKER_TYPE,
16204  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_156_WIDTH },
16205  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_157_CHECKER_TYPE,
16206  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_157_WIDTH },
16207  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_158_CHECKER_TYPE,
16208  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_158_WIDTH },
16209  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_159_CHECKER_TYPE,
16210  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_159_WIDTH },
16211  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_160_CHECKER_TYPE,
16212  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_160_WIDTH },
16213  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_161_CHECKER_TYPE,
16214  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_161_WIDTH },
16215  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_162_CHECKER_TYPE,
16216  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_162_WIDTH },
16217  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_163_CHECKER_TYPE,
16218  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_163_WIDTH },
16219  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_164_CHECKER_TYPE,
16220  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_164_WIDTH },
16221  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_165_CHECKER_TYPE,
16222  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_165_WIDTH },
16223  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_166_CHECKER_TYPE,
16224  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_166_WIDTH },
16225  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_167_CHECKER_TYPE,
16226  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_167_WIDTH },
16227  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_168_CHECKER_TYPE,
16228  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_168_WIDTH },
16229  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_169_CHECKER_TYPE,
16230  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_169_WIDTH },
16231  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_170_CHECKER_TYPE,
16232  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_170_WIDTH },
16233  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_171_CHECKER_TYPE,
16234  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_171_WIDTH },
16235  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_172_CHECKER_TYPE,
16236  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_172_WIDTH },
16237  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_173_CHECKER_TYPE,
16238  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_173_WIDTH },
16239  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_174_CHECKER_TYPE,
16240  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_174_WIDTH },
16241  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_175_CHECKER_TYPE,
16242  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_175_WIDTH },
16243  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_176_CHECKER_TYPE,
16244  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_176_WIDTH },
16245  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_177_CHECKER_TYPE,
16246  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_177_WIDTH },
16247  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_178_CHECKER_TYPE,
16248  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_178_WIDTH },
16249  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_179_CHECKER_TYPE,
16250  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_179_WIDTH },
16251  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_180_CHECKER_TYPE,
16252  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_180_WIDTH },
16253  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_181_CHECKER_TYPE,
16254  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_181_WIDTH },
16255  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_182_CHECKER_TYPE,
16256  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_182_WIDTH },
16257  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_183_CHECKER_TYPE,
16258  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_183_WIDTH },
16259  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_184_CHECKER_TYPE,
16260  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_184_WIDTH },
16261  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_185_CHECKER_TYPE,
16262  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_185_WIDTH },
16263  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_186_CHECKER_TYPE,
16264  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_186_WIDTH },
16265  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_187_CHECKER_TYPE,
16266  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_187_WIDTH },
16267  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_188_CHECKER_TYPE,
16268  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_188_WIDTH },
16269  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_189_CHECKER_TYPE,
16270  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_189_WIDTH },
16271  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_190_CHECKER_TYPE,
16272  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_190_WIDTH },
16273  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_191_CHECKER_TYPE,
16274  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_191_WIDTH },
16275  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_192_CHECKER_TYPE,
16276  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_192_WIDTH },
16277  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_193_CHECKER_TYPE,
16278  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_193_WIDTH },
16279  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_194_CHECKER_TYPE,
16280  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_194_WIDTH },
16281  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_195_CHECKER_TYPE,
16282  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_195_WIDTH },
16283  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_196_CHECKER_TYPE,
16284  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_196_WIDTH },
16285  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_197_CHECKER_TYPE,
16286  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_197_WIDTH },
16287  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_198_CHECKER_TYPE,
16288  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_198_WIDTH },
16289  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_199_CHECKER_TYPE,
16290  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_199_WIDTH },
16291  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_200_CHECKER_TYPE,
16292  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_200_WIDTH },
16293  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_201_CHECKER_TYPE,
16294  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_201_WIDTH },
16295  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_202_CHECKER_TYPE,
16296  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_202_WIDTH },
16297  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_203_CHECKER_TYPE,
16298  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_203_WIDTH },
16299  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_204_CHECKER_TYPE,
16300  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_204_WIDTH },
16301  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_205_CHECKER_TYPE,
16302  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_205_WIDTH },
16303  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_206_CHECKER_TYPE,
16304  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_206_WIDTH },
16305  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_207_CHECKER_TYPE,
16306  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_207_WIDTH },
16307  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_208_CHECKER_TYPE,
16308  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_208_WIDTH },
16309  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_209_CHECKER_TYPE,
16310  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_209_WIDTH },
16311  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_210_CHECKER_TYPE,
16312  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_210_WIDTH },
16313  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_211_CHECKER_TYPE,
16314  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_211_WIDTH },
16315  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_212_CHECKER_TYPE,
16316  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_212_WIDTH },
16317  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_213_CHECKER_TYPE,
16318  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_213_WIDTH },
16319  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_214_CHECKER_TYPE,
16320  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_214_WIDTH },
16321  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_215_CHECKER_TYPE,
16322  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_215_WIDTH },
16323  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_216_CHECKER_TYPE,
16324  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_216_WIDTH },
16325  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_217_CHECKER_TYPE,
16326  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_217_WIDTH },
16327  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_218_CHECKER_TYPE,
16328  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_218_WIDTH },
16329  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_219_CHECKER_TYPE,
16330  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_219_WIDTH },
16331  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_220_CHECKER_TYPE,
16332  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_220_WIDTH },
16333  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_221_CHECKER_TYPE,
16334  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_221_WIDTH },
16335  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_222_CHECKER_TYPE,
16336  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_222_WIDTH },
16337  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_223_CHECKER_TYPE,
16338  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_223_WIDTH },
16339  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_224_CHECKER_TYPE,
16340  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_224_WIDTH },
16341  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_225_CHECKER_TYPE,
16342  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_225_WIDTH },
16343  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_226_CHECKER_TYPE,
16344  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_226_WIDTH },
16345  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_227_CHECKER_TYPE,
16346  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_227_WIDTH },
16347  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_228_CHECKER_TYPE,
16348  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_228_WIDTH },
16349  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_229_CHECKER_TYPE,
16350  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_229_WIDTH },
16351  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_230_CHECKER_TYPE,
16352  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_230_WIDTH },
16353  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_231_CHECKER_TYPE,
16354  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_231_WIDTH },
16355  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_232_CHECKER_TYPE,
16356  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_232_WIDTH },
16357  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_233_CHECKER_TYPE,
16358  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_233_WIDTH },
16359  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_234_CHECKER_TYPE,
16360  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_234_WIDTH },
16361  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_235_CHECKER_TYPE,
16362  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_235_WIDTH },
16363  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_236_CHECKER_TYPE,
16364  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_236_WIDTH },
16365  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_237_CHECKER_TYPE,
16366  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_237_WIDTH },
16367  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_238_CHECKER_TYPE,
16368  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_238_WIDTH },
16369  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_239_CHECKER_TYPE,
16370  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_239_WIDTH },
16371  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_240_CHECKER_TYPE,
16372  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_240_WIDTH },
16373  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_241_CHECKER_TYPE,
16374  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_241_WIDTH },
16375  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_242_CHECKER_TYPE,
16376  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_242_WIDTH },
16377  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_243_CHECKER_TYPE,
16378  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_243_WIDTH },
16379  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_244_CHECKER_TYPE,
16380  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_244_WIDTH },
16381  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_245_CHECKER_TYPE,
16382  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_245_WIDTH },
16383  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_246_CHECKER_TYPE,
16384  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_246_WIDTH },
16385  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_247_CHECKER_TYPE,
16386  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_247_WIDTH },
16387  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_248_CHECKER_TYPE,
16388  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_248_WIDTH },
16389  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_249_CHECKER_TYPE,
16390  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_249_WIDTH },
16391  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_250_CHECKER_TYPE,
16392  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_250_WIDTH },
16393  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_251_CHECKER_TYPE,
16394  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_251_WIDTH },
16395  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_252_CHECKER_TYPE,
16396  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_252_WIDTH },
16397  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_253_CHECKER_TYPE,
16398  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_253_WIDTH },
16399  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_254_CHECKER_TYPE,
16400  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_254_WIDTH },
16401  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_255_CHECKER_TYPE,
16402  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_255_WIDTH },
16403 };
16404 
16410 static const SDL_GrpChkConfig_t SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_groupEntries[SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_MAX_NUM_CHECKERS] =
16411 {
16412  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_0_CHECKER_TYPE,
16413  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_0_WIDTH },
16414  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_1_CHECKER_TYPE,
16415  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_1_WIDTH },
16416  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_2_CHECKER_TYPE,
16417  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_2_WIDTH },
16418  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_3_CHECKER_TYPE,
16419  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_3_WIDTH },
16420  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_4_CHECKER_TYPE,
16421  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_4_WIDTH },
16422  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_5_CHECKER_TYPE,
16423  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_5_WIDTH },
16424  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_6_CHECKER_TYPE,
16425  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_6_WIDTH },
16426  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_7_CHECKER_TYPE,
16427  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_7_WIDTH },
16428  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_8_CHECKER_TYPE,
16429  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_8_WIDTH },
16430  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_9_CHECKER_TYPE,
16431  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_9_WIDTH },
16432  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_10_CHECKER_TYPE,
16433  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_10_WIDTH },
16434  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_11_CHECKER_TYPE,
16435  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_11_WIDTH },
16436  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_12_CHECKER_TYPE,
16437  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_12_WIDTH },
16438  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_13_CHECKER_TYPE,
16439  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_13_WIDTH },
16440  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_14_CHECKER_TYPE,
16441  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_14_WIDTH },
16442  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_15_CHECKER_TYPE,
16443  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_15_WIDTH },
16444  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_16_CHECKER_TYPE,
16445  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_16_WIDTH },
16446  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_17_CHECKER_TYPE,
16447  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_17_WIDTH },
16448  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_18_CHECKER_TYPE,
16449  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_18_WIDTH },
16450  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_19_CHECKER_TYPE,
16451  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_19_WIDTH },
16452  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_20_CHECKER_TYPE,
16453  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_20_WIDTH },
16454  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_21_CHECKER_TYPE,
16455  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_21_WIDTH },
16456  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_22_CHECKER_TYPE,
16457  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_22_WIDTH },
16458  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_23_CHECKER_TYPE,
16459  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_23_WIDTH },
16460  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_24_CHECKER_TYPE,
16461  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_24_WIDTH },
16462  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_25_CHECKER_TYPE,
16463  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_25_WIDTH },
16464  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_26_CHECKER_TYPE,
16465  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_26_WIDTH },
16466  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_27_CHECKER_TYPE,
16467  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_27_WIDTH },
16468  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_28_CHECKER_TYPE,
16469  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_28_WIDTH },
16470  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_29_CHECKER_TYPE,
16471  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_29_WIDTH },
16472  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_30_CHECKER_TYPE,
16473  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_30_WIDTH },
16474  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_31_CHECKER_TYPE,
16475  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_31_WIDTH },
16476  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_32_CHECKER_TYPE,
16477  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_32_WIDTH },
16478  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_33_CHECKER_TYPE,
16479  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_33_WIDTH },
16480  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_34_CHECKER_TYPE,
16481  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_34_WIDTH },
16482  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_35_CHECKER_TYPE,
16483  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_35_WIDTH },
16484  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_36_CHECKER_TYPE,
16485  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_36_WIDTH },
16486  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_37_CHECKER_TYPE,
16487  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_37_WIDTH },
16488  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_38_CHECKER_TYPE,
16489  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_38_WIDTH },
16490  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_39_CHECKER_TYPE,
16491  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_39_WIDTH },
16492  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_40_CHECKER_TYPE,
16493  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_40_WIDTH },
16494  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_41_CHECKER_TYPE,
16495  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_41_WIDTH },
16496  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_42_CHECKER_TYPE,
16497  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_42_WIDTH },
16498  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_43_CHECKER_TYPE,
16499  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_43_WIDTH },
16500  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_44_CHECKER_TYPE,
16501  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_44_WIDTH },
16502  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_45_CHECKER_TYPE,
16503  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_45_WIDTH },
16504  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_46_CHECKER_TYPE,
16505  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_46_WIDTH },
16506  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_47_CHECKER_TYPE,
16507  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_47_WIDTH },
16508  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_48_CHECKER_TYPE,
16509  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_48_WIDTH },
16510  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_49_CHECKER_TYPE,
16511  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_49_WIDTH },
16512  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_50_CHECKER_TYPE,
16513  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_50_WIDTH },
16514  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_51_CHECKER_TYPE,
16515  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_51_WIDTH },
16516  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_52_CHECKER_TYPE,
16517  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_52_WIDTH },
16518  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_53_CHECKER_TYPE,
16519  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_53_WIDTH },
16520  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_54_CHECKER_TYPE,
16521  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_54_WIDTH },
16522  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_55_CHECKER_TYPE,
16523  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_55_WIDTH },
16524  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_56_CHECKER_TYPE,
16525  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_56_WIDTH },
16526  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_57_CHECKER_TYPE,
16527  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_57_WIDTH },
16528  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_58_CHECKER_TYPE,
16529  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_58_WIDTH },
16530  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_59_CHECKER_TYPE,
16531  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_59_WIDTH },
16532  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_60_CHECKER_TYPE,
16533  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_60_WIDTH },
16534  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_61_CHECKER_TYPE,
16535  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_61_WIDTH },
16536  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_62_CHECKER_TYPE,
16537  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_62_WIDTH },
16538  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_63_CHECKER_TYPE,
16539  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_63_WIDTH },
16540  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_64_CHECKER_TYPE,
16541  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_64_WIDTH },
16542  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_65_CHECKER_TYPE,
16543  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_65_WIDTH },
16544  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_66_CHECKER_TYPE,
16545  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_66_WIDTH },
16546  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_67_CHECKER_TYPE,
16547  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_67_WIDTH },
16548  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_68_CHECKER_TYPE,
16549  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_68_WIDTH },
16550  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_69_CHECKER_TYPE,
16551  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_69_WIDTH },
16552  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_70_CHECKER_TYPE,
16553  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_70_WIDTH },
16554  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_71_CHECKER_TYPE,
16555  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_71_WIDTH },
16556  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_72_CHECKER_TYPE,
16557  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_72_WIDTH },
16558  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_73_CHECKER_TYPE,
16559  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_73_WIDTH },
16560  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_74_CHECKER_TYPE,
16561  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_74_WIDTH },
16562  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_75_CHECKER_TYPE,
16563  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_75_WIDTH },
16564  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_76_CHECKER_TYPE,
16565  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_76_WIDTH },
16566  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_77_CHECKER_TYPE,
16567  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_77_WIDTH },
16568  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_78_CHECKER_TYPE,
16569  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_78_WIDTH },
16570  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_79_CHECKER_TYPE,
16571  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_79_WIDTH },
16572  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_80_CHECKER_TYPE,
16573  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_80_WIDTH },
16574  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_81_CHECKER_TYPE,
16575  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_81_WIDTH },
16576  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_82_CHECKER_TYPE,
16577  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_82_WIDTH },
16578  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_83_CHECKER_TYPE,
16579  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_83_WIDTH },
16580  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_84_CHECKER_TYPE,
16581  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_84_WIDTH },
16582  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_85_CHECKER_TYPE,
16583  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_85_WIDTH },
16584  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_86_CHECKER_TYPE,
16585  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_86_WIDTH },
16586  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_87_CHECKER_TYPE,
16587  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_87_WIDTH },
16588  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_88_CHECKER_TYPE,
16589  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_88_WIDTH },
16590  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_89_CHECKER_TYPE,
16591  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_89_WIDTH },
16592  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_90_CHECKER_TYPE,
16593  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_90_WIDTH },
16594  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_91_CHECKER_TYPE,
16595  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_91_WIDTH },
16596  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_92_CHECKER_TYPE,
16597  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_92_WIDTH },
16598  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_93_CHECKER_TYPE,
16599  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_93_WIDTH },
16600  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_94_CHECKER_TYPE,
16601  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_94_WIDTH },
16602  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_95_CHECKER_TYPE,
16603  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_95_WIDTH },
16604  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_96_CHECKER_TYPE,
16605  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_96_WIDTH },
16606  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_97_CHECKER_TYPE,
16607  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_97_WIDTH },
16608  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_98_CHECKER_TYPE,
16609  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_98_WIDTH },
16610  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_99_CHECKER_TYPE,
16611  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_99_WIDTH },
16612  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_100_CHECKER_TYPE,
16613  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_100_WIDTH },
16614  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_101_CHECKER_TYPE,
16615  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_101_WIDTH },
16616  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_102_CHECKER_TYPE,
16617  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_102_WIDTH },
16618  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_103_CHECKER_TYPE,
16619  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_103_WIDTH },
16620  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_104_CHECKER_TYPE,
16621  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_104_WIDTH },
16622  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_105_CHECKER_TYPE,
16623  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_105_WIDTH },
16624  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_106_CHECKER_TYPE,
16625  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_106_WIDTH },
16626  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_107_CHECKER_TYPE,
16627  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_107_WIDTH },
16628  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_108_CHECKER_TYPE,
16629  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_108_WIDTH },
16630  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_109_CHECKER_TYPE,
16631  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_109_WIDTH },
16632  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_110_CHECKER_TYPE,
16633  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_110_WIDTH },
16634  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_111_CHECKER_TYPE,
16635  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_111_WIDTH },
16636  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_112_CHECKER_TYPE,
16637  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_112_WIDTH },
16638  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_113_CHECKER_TYPE,
16639  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_113_WIDTH },
16640  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_114_CHECKER_TYPE,
16641  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_114_WIDTH },
16642  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_115_CHECKER_TYPE,
16643  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_115_WIDTH },
16644  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_116_CHECKER_TYPE,
16645  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_116_WIDTH },
16646  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_117_CHECKER_TYPE,
16647  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_117_WIDTH },
16648  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_118_CHECKER_TYPE,
16649  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_118_WIDTH },
16650  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_119_CHECKER_TYPE,
16651  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_119_WIDTH },
16652  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_120_CHECKER_TYPE,
16653  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_120_WIDTH },
16654  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_121_CHECKER_TYPE,
16655  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_121_WIDTH },
16656  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_122_CHECKER_TYPE,
16657  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_122_WIDTH },
16658  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_123_CHECKER_TYPE,
16659  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_123_WIDTH },
16660  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_124_CHECKER_TYPE,
16661  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_124_WIDTH },
16662  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_125_CHECKER_TYPE,
16663  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_125_WIDTH },
16664  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_126_CHECKER_TYPE,
16665  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_126_WIDTH },
16666  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_127_CHECKER_TYPE,
16667  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_127_WIDTH },
16668  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_128_CHECKER_TYPE,
16669  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_128_WIDTH },
16670  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_129_CHECKER_TYPE,
16671  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_129_WIDTH },
16672  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_130_CHECKER_TYPE,
16673  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_130_WIDTH },
16674  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_131_CHECKER_TYPE,
16675  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_131_WIDTH },
16676  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_132_CHECKER_TYPE,
16677  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_132_WIDTH },
16678  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_133_CHECKER_TYPE,
16679  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_133_WIDTH },
16680  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_134_CHECKER_TYPE,
16681  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_134_WIDTH },
16682  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_135_CHECKER_TYPE,
16683  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_135_WIDTH },
16684  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_136_CHECKER_TYPE,
16685  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_136_WIDTH },
16686  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_137_CHECKER_TYPE,
16687  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_137_WIDTH },
16688  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_138_CHECKER_TYPE,
16689  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_138_WIDTH },
16690  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_139_CHECKER_TYPE,
16691  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_139_WIDTH },
16692  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_140_CHECKER_TYPE,
16693  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_140_WIDTH },
16694  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_141_CHECKER_TYPE,
16695  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_141_WIDTH },
16696  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_142_CHECKER_TYPE,
16697  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_142_WIDTH },
16698  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_143_CHECKER_TYPE,
16699  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_143_WIDTH },
16700  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_144_CHECKER_TYPE,
16701  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_144_WIDTH },
16702  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_145_CHECKER_TYPE,
16703  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_145_WIDTH },
16704  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_146_CHECKER_TYPE,
16705  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_146_WIDTH },
16706  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_147_CHECKER_TYPE,
16707  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_147_WIDTH },
16708  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_148_CHECKER_TYPE,
16709  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_148_WIDTH },
16710  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_149_CHECKER_TYPE,
16711  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_149_WIDTH },
16712  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_150_CHECKER_TYPE,
16713  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_150_WIDTH },
16714  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_151_CHECKER_TYPE,
16715  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_151_WIDTH },
16716  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_152_CHECKER_TYPE,
16717  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_152_WIDTH },
16718  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_153_CHECKER_TYPE,
16719  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_153_WIDTH },
16720  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_154_CHECKER_TYPE,
16721  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_154_WIDTH },
16722  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_155_CHECKER_TYPE,
16723  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_155_WIDTH },
16724  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_156_CHECKER_TYPE,
16725  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_156_WIDTH },
16726  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_157_CHECKER_TYPE,
16727  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_157_WIDTH },
16728  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_158_CHECKER_TYPE,
16729  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_158_WIDTH },
16730  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_159_CHECKER_TYPE,
16731  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_159_WIDTH },
16732  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_160_CHECKER_TYPE,
16733  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_160_WIDTH },
16734  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_161_CHECKER_TYPE,
16735  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_161_WIDTH },
16736  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_162_CHECKER_TYPE,
16737  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_162_WIDTH },
16738  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_163_CHECKER_TYPE,
16739  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_163_WIDTH },
16740  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_164_CHECKER_TYPE,
16741  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_164_WIDTH },
16742  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_165_CHECKER_TYPE,
16743  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_165_WIDTH },
16744  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_166_CHECKER_TYPE,
16745  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_166_WIDTH },
16746  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_167_CHECKER_TYPE,
16747  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_167_WIDTH },
16748  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_168_CHECKER_TYPE,
16749  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_168_WIDTH },
16750  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_169_CHECKER_TYPE,
16751  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_169_WIDTH },
16752  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_170_CHECKER_TYPE,
16753  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_170_WIDTH },
16754  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_171_CHECKER_TYPE,
16755  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_171_WIDTH },
16756  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_172_CHECKER_TYPE,
16757  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_172_WIDTH },
16758  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_173_CHECKER_TYPE,
16759  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_173_WIDTH },
16760  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_174_CHECKER_TYPE,
16761  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_174_WIDTH },
16762  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_175_CHECKER_TYPE,
16763  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_175_WIDTH },
16764  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_176_CHECKER_TYPE,
16765  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_176_WIDTH },
16766  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_177_CHECKER_TYPE,
16767  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_177_WIDTH },
16768  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_178_CHECKER_TYPE,
16769  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_178_WIDTH },
16770  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_179_CHECKER_TYPE,
16771  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_179_WIDTH },
16772  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_180_CHECKER_TYPE,
16773  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_180_WIDTH },
16774  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_181_CHECKER_TYPE,
16775  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_181_WIDTH },
16776  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_182_CHECKER_TYPE,
16777  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_182_WIDTH },
16778  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_183_CHECKER_TYPE,
16779  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_183_WIDTH },
16780  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_184_CHECKER_TYPE,
16781  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_184_WIDTH },
16782  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_185_CHECKER_TYPE,
16783  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_185_WIDTH },
16784  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_186_CHECKER_TYPE,
16785  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_186_WIDTH },
16786  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_187_CHECKER_TYPE,
16787  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_187_WIDTH },
16788  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_188_CHECKER_TYPE,
16789  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_188_WIDTH },
16790  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_189_CHECKER_TYPE,
16791  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_189_WIDTH },
16792  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_190_CHECKER_TYPE,
16793  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_190_WIDTH },
16794  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_191_CHECKER_TYPE,
16795  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_191_WIDTH },
16796  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_192_CHECKER_TYPE,
16797  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_192_WIDTH },
16798  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_193_CHECKER_TYPE,
16799  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_193_WIDTH },
16800  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_194_CHECKER_TYPE,
16801  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_194_WIDTH },
16802  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_195_CHECKER_TYPE,
16803  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_195_WIDTH },
16804  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_196_CHECKER_TYPE,
16805  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_196_WIDTH },
16806  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_197_CHECKER_TYPE,
16807  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_197_WIDTH },
16808  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_198_CHECKER_TYPE,
16809  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_198_WIDTH },
16810  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_199_CHECKER_TYPE,
16811  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_199_WIDTH },
16812  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_200_CHECKER_TYPE,
16813  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_200_WIDTH },
16814  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_201_CHECKER_TYPE,
16815  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_201_WIDTH },
16816  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_202_CHECKER_TYPE,
16817  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_202_WIDTH },
16818  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_203_CHECKER_TYPE,
16819  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_203_WIDTH },
16820  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_204_CHECKER_TYPE,
16821  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_204_WIDTH },
16822  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_205_CHECKER_TYPE,
16823  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_205_WIDTH },
16824  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_206_CHECKER_TYPE,
16825  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_206_WIDTH },
16826  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_207_CHECKER_TYPE,
16827  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_207_WIDTH },
16828  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_208_CHECKER_TYPE,
16829  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_208_WIDTH },
16830  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_209_CHECKER_TYPE,
16831  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_209_WIDTH },
16832  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_210_CHECKER_TYPE,
16833  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_210_WIDTH },
16834  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_211_CHECKER_TYPE,
16835  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_211_WIDTH },
16836  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_212_CHECKER_TYPE,
16837  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_212_WIDTH },
16838  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_213_CHECKER_TYPE,
16839  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_213_WIDTH },
16840  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_214_CHECKER_TYPE,
16841  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_214_WIDTH },
16842  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_215_CHECKER_TYPE,
16843  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_215_WIDTH },
16844  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_216_CHECKER_TYPE,
16845  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_216_WIDTH },
16846  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_217_CHECKER_TYPE,
16847  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_217_WIDTH },
16848  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_218_CHECKER_TYPE,
16849  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_218_WIDTH },
16850  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_219_CHECKER_TYPE,
16851  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_219_WIDTH },
16852  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_220_CHECKER_TYPE,
16853  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_220_WIDTH },
16854  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_221_CHECKER_TYPE,
16855  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_221_WIDTH },
16856  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_222_CHECKER_TYPE,
16857  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_222_WIDTH },
16858  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_223_CHECKER_TYPE,
16859  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_223_WIDTH },
16860  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_224_CHECKER_TYPE,
16861  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_224_WIDTH },
16862  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_225_CHECKER_TYPE,
16863  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_225_WIDTH },
16864  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_226_CHECKER_TYPE,
16865  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_226_WIDTH },
16866  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_227_CHECKER_TYPE,
16867  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_227_WIDTH },
16868  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_228_CHECKER_TYPE,
16869  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_228_WIDTH },
16870  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_229_CHECKER_TYPE,
16871  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_229_WIDTH },
16872  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_230_CHECKER_TYPE,
16873  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_230_WIDTH },
16874  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_231_CHECKER_TYPE,
16875  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_231_WIDTH },
16876  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_232_CHECKER_TYPE,
16877  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_232_WIDTH },
16878  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_233_CHECKER_TYPE,
16879  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_233_WIDTH },
16880  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_234_CHECKER_TYPE,
16881  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_234_WIDTH },
16882  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_235_CHECKER_TYPE,
16883  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_235_WIDTH },
16884  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_236_CHECKER_TYPE,
16885  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_236_WIDTH },
16886  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_237_CHECKER_TYPE,
16887  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_237_WIDTH },
16888  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_238_CHECKER_TYPE,
16889  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_238_WIDTH },
16890  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_239_CHECKER_TYPE,
16891  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_239_WIDTH },
16892  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_240_CHECKER_TYPE,
16893  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_240_WIDTH },
16894  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_241_CHECKER_TYPE,
16895  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_241_WIDTH },
16896  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_242_CHECKER_TYPE,
16897  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_242_WIDTH },
16898  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_243_CHECKER_TYPE,
16899  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_243_WIDTH },
16900  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_244_CHECKER_TYPE,
16901  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_244_WIDTH },
16902  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_245_CHECKER_TYPE,
16903  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_245_WIDTH },
16904  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_246_CHECKER_TYPE,
16905  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_246_WIDTH },
16906  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_247_CHECKER_TYPE,
16907  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_247_WIDTH },
16908  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_248_CHECKER_TYPE,
16909  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_248_WIDTH },
16910  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_249_CHECKER_TYPE,
16911  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_249_WIDTH },
16912  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_250_CHECKER_TYPE,
16913  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_250_WIDTH },
16914  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_251_CHECKER_TYPE,
16915  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_251_WIDTH },
16916  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_252_CHECKER_TYPE,
16917  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_252_WIDTH },
16918  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_253_CHECKER_TYPE,
16919  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_253_WIDTH },
16920  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_254_CHECKER_TYPE,
16921  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_254_WIDTH },
16922  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_255_CHECKER_TYPE,
16923  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_255_WIDTH },
16924 };
16925 
16931 static const SDL_GrpChkConfig_t SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_2_groupEntries[SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_2_MAX_NUM_CHECKERS] =
16932 {
16933  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_2_GROUP_0_CHECKER_TYPE,
16934  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_2_GROUP_0_WIDTH },
16935  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_2_GROUP_1_CHECKER_TYPE,
16936  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_2_GROUP_1_WIDTH },
16937  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_2_GROUP_2_CHECKER_TYPE,
16938  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_2_GROUP_2_WIDTH },
16939  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_2_GROUP_3_CHECKER_TYPE,
16940  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_2_GROUP_3_WIDTH },
16941  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_2_GROUP_4_CHECKER_TYPE,
16942  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_2_GROUP_4_WIDTH },
16943  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_2_GROUP_5_CHECKER_TYPE,
16944  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_2_GROUP_5_WIDTH },
16945  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_2_GROUP_6_CHECKER_TYPE,
16946  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_2_GROUP_6_WIDTH },
16947  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_2_GROUP_7_CHECKER_TYPE,
16948  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_2_GROUP_7_WIDTH },
16949  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_2_GROUP_8_CHECKER_TYPE,
16950  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_2_GROUP_8_WIDTH },
16951  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_2_GROUP_9_CHECKER_TYPE,
16952  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_2_GROUP_9_WIDTH },
16953  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_2_GROUP_10_CHECKER_TYPE,
16954  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_2_GROUP_10_WIDTH },
16955  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_2_GROUP_11_CHECKER_TYPE,
16956  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_2_GROUP_11_WIDTH },
16957  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_2_GROUP_12_CHECKER_TYPE,
16958  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_2_GROUP_12_WIDTH },
16959  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_2_GROUP_13_CHECKER_TYPE,
16960  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_2_GROUP_13_WIDTH },
16961  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_2_GROUP_14_CHECKER_TYPE,
16962  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_2_GROUP_14_WIDTH },
16963  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_2_GROUP_15_CHECKER_TYPE,
16964  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_2_GROUP_15_WIDTH },
16965  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_2_GROUP_16_CHECKER_TYPE,
16966  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_2_GROUP_16_WIDTH },
16967  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_2_GROUP_17_CHECKER_TYPE,
16968  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_2_GROUP_17_WIDTH },
16969  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_2_GROUP_18_CHECKER_TYPE,
16970  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_2_GROUP_18_WIDTH },
16971  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_2_GROUP_19_CHECKER_TYPE,
16972  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_2_GROUP_19_WIDTH },
16973  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_2_GROUP_20_CHECKER_TYPE,
16974  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_2_GROUP_20_WIDTH },
16975  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_2_GROUP_21_CHECKER_TYPE,
16976  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_2_GROUP_21_WIDTH },
16977  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_2_GROUP_22_CHECKER_TYPE,
16978  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_2_GROUP_22_WIDTH },
16979  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_2_GROUP_23_CHECKER_TYPE,
16980  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_2_GROUP_23_WIDTH },
16981  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_2_GROUP_24_CHECKER_TYPE,
16982  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_2_GROUP_24_WIDTH },
16983  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_2_GROUP_25_CHECKER_TYPE,
16984  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_2_GROUP_25_WIDTH },
16985 };
16986 
16992 static const SDL_GrpChkConfig_t SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_groupEntries[SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_MAX_NUM_CHECKERS] =
16993 {
16994  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_GROUP_0_CHECKER_TYPE,
16995  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_GROUP_0_WIDTH },
16996  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_GROUP_1_CHECKER_TYPE,
16997  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_GROUP_1_WIDTH },
16998  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_GROUP_2_CHECKER_TYPE,
16999  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_GROUP_2_WIDTH },
17000  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_GROUP_3_CHECKER_TYPE,
17001  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_GROUP_3_WIDTH },
17002  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_GROUP_4_CHECKER_TYPE,
17003  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_GROUP_4_WIDTH },
17004  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_GROUP_5_CHECKER_TYPE,
17005  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_GROUP_5_WIDTH },
17006  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_GROUP_6_CHECKER_TYPE,
17007  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_GROUP_6_WIDTH },
17008  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_GROUP_7_CHECKER_TYPE,
17009  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_GROUP_7_WIDTH },
17010  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_GROUP_8_CHECKER_TYPE,
17011  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_GROUP_8_WIDTH },
17012  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_GROUP_9_CHECKER_TYPE,
17013  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_GROUP_9_WIDTH },
17014  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_GROUP_10_CHECKER_TYPE,
17015  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_GROUP_10_WIDTH },
17016  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_GROUP_11_CHECKER_TYPE,
17017  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_GROUP_11_WIDTH },
17018  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_GROUP_12_CHECKER_TYPE,
17019  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_GROUP_12_WIDTH },
17020 };
17021 
17027 static const SDL_GrpChkConfig_t SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IFWMGR_M_P2P_BRIDGE_IFWMGR_M_BRIDGE_BUSECC_groupEntries[SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IFWMGR_M_P2P_BRIDGE_IFWMGR_M_BRIDGE_BUSECC_MAX_NUM_CHECKERS] =
17028 {
17029  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IFWMGR_M_P2P_BRIDGE_IFWMGR_M_BRIDGE_BUSECC_GROUP_0_CHECKER_TYPE,
17030  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IFWMGR_M_P2P_BRIDGE_IFWMGR_M_BRIDGE_BUSECC_GROUP_0_WIDTH },
17031  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IFWMGR_M_P2P_BRIDGE_IFWMGR_M_BRIDGE_BUSECC_GROUP_1_CHECKER_TYPE,
17032  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IFWMGR_M_P2P_BRIDGE_IFWMGR_M_BRIDGE_BUSECC_GROUP_1_WIDTH },
17033  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IFWMGR_M_P2P_BRIDGE_IFWMGR_M_BRIDGE_BUSECC_GROUP_2_CHECKER_TYPE,
17034  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IFWMGR_M_P2P_BRIDGE_IFWMGR_M_BRIDGE_BUSECC_GROUP_2_WIDTH },
17035  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IFWMGR_M_P2P_BRIDGE_IFWMGR_M_BRIDGE_BUSECC_GROUP_3_CHECKER_TYPE,
17036  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IFWMGR_M_P2P_BRIDGE_IFWMGR_M_BRIDGE_BUSECC_GROUP_3_WIDTH },
17037  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IFWMGR_M_P2P_BRIDGE_IFWMGR_M_BRIDGE_BUSECC_GROUP_4_CHECKER_TYPE,
17038  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IFWMGR_M_P2P_BRIDGE_IFWMGR_M_BRIDGE_BUSECC_GROUP_4_WIDTH },
17039  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IFWMGR_M_P2P_BRIDGE_IFWMGR_M_BRIDGE_BUSECC_GROUP_5_CHECKER_TYPE,
17040  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IFWMGR_M_P2P_BRIDGE_IFWMGR_M_BRIDGE_BUSECC_GROUP_5_WIDTH },
17041  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IFWMGR_M_P2P_BRIDGE_IFWMGR_M_BRIDGE_BUSECC_GROUP_6_CHECKER_TYPE,
17042  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IFWMGR_M_P2P_BRIDGE_IFWMGR_M_BRIDGE_BUSECC_GROUP_6_WIDTH },
17043  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IFWMGR_M_P2P_BRIDGE_IFWMGR_M_BRIDGE_BUSECC_GROUP_7_CHECKER_TYPE,
17044  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IFWMGR_M_P2P_BRIDGE_IFWMGR_M_BRIDGE_BUSECC_GROUP_7_WIDTH },
17045  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IFWMGR_M_P2P_BRIDGE_IFWMGR_M_BRIDGE_BUSECC_GROUP_8_CHECKER_TYPE,
17046  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IFWMGR_M_P2P_BRIDGE_IFWMGR_M_BRIDGE_BUSECC_GROUP_8_WIDTH },
17047  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IFWMGR_M_P2P_BRIDGE_IFWMGR_M_BRIDGE_BUSECC_GROUP_9_CHECKER_TYPE,
17048  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IFWMGR_M_P2P_BRIDGE_IFWMGR_M_BRIDGE_BUSECC_GROUP_9_WIDTH },
17049  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IFWMGR_M_P2P_BRIDGE_IFWMGR_M_BRIDGE_BUSECC_GROUP_10_CHECKER_TYPE,
17050  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IFWMGR_M_P2P_BRIDGE_IFWMGR_M_BRIDGE_BUSECC_GROUP_10_WIDTH },
17051  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IFWMGR_M_P2P_BRIDGE_IFWMGR_M_BRIDGE_BUSECC_GROUP_11_CHECKER_TYPE,
17052  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IFWMGR_M_P2P_BRIDGE_IFWMGR_M_BRIDGE_BUSECC_GROUP_11_WIDTH },
17053  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IFWMGR_M_P2P_BRIDGE_IFWMGR_M_BRIDGE_BUSECC_GROUP_12_CHECKER_TYPE,
17054  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IFWMGR_M_P2P_BRIDGE_IFWMGR_M_BRIDGE_BUSECC_GROUP_12_WIDTH },
17055 };
17056 
17062 static const SDL_GrpChkConfig_t SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_groupEntries[SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_MAX_NUM_CHECKERS] =
17063 {
17064  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_0_CHECKER_TYPE,
17065  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_0_WIDTH },
17066  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_1_CHECKER_TYPE,
17067  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_1_WIDTH },
17068  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_2_CHECKER_TYPE,
17069  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_2_WIDTH },
17070  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_3_CHECKER_TYPE,
17071  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_3_WIDTH },
17072  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_4_CHECKER_TYPE,
17073  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_4_WIDTH },
17074  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_5_CHECKER_TYPE,
17075  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_5_WIDTH },
17076  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_6_CHECKER_TYPE,
17077  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_6_WIDTH },
17078  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_7_CHECKER_TYPE,
17079  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_7_WIDTH },
17080  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_8_CHECKER_TYPE,
17081  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_8_WIDTH },
17082  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_9_CHECKER_TYPE,
17083  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_9_WIDTH },
17084  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_10_CHECKER_TYPE,
17085  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_10_WIDTH },
17086  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_11_CHECKER_TYPE,
17087  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_11_WIDTH },
17088  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_12_CHECKER_TYPE,
17089  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_12_WIDTH },
17090  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_13_CHECKER_TYPE,
17091  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_13_WIDTH },
17092  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_14_CHECKER_TYPE,
17093  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_14_WIDTH },
17094  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_15_CHECKER_TYPE,
17095  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_15_WIDTH },
17096  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_16_CHECKER_TYPE,
17097  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_16_WIDTH },
17098  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_17_CHECKER_TYPE,
17099  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_17_WIDTH },
17100  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_18_CHECKER_TYPE,
17101  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_18_WIDTH },
17102  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_19_CHECKER_TYPE,
17103  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_19_WIDTH },
17104  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_20_CHECKER_TYPE,
17105  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_20_WIDTH },
17106  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_21_CHECKER_TYPE,
17107  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_21_WIDTH },
17108  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_22_CHECKER_TYPE,
17109  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_22_WIDTH },
17110  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_23_CHECKER_TYPE,
17111  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_23_WIDTH },
17112  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_24_CHECKER_TYPE,
17113  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_24_WIDTH },
17114  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_25_CHECKER_TYPE,
17115  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_25_WIDTH },
17116  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_26_CHECKER_TYPE,
17117  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_26_WIDTH },
17118  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_27_CHECKER_TYPE,
17119  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_27_WIDTH },
17120  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_28_CHECKER_TYPE,
17121  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_28_WIDTH },
17122  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_29_CHECKER_TYPE,
17123  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_29_WIDTH },
17124  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_30_CHECKER_TYPE,
17125  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_30_WIDTH },
17126  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_31_CHECKER_TYPE,
17127  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_31_WIDTH },
17128  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_32_CHECKER_TYPE,
17129  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_32_WIDTH },
17130  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_33_CHECKER_TYPE,
17131  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_33_WIDTH },
17132  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_34_CHECKER_TYPE,
17133  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_34_WIDTH },
17134  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_35_CHECKER_TYPE,
17135  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_35_WIDTH },
17136  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_36_CHECKER_TYPE,
17137  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_36_WIDTH },
17138  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_37_CHECKER_TYPE,
17139  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_37_WIDTH },
17140  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_38_CHECKER_TYPE,
17141  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_38_WIDTH },
17142  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_39_CHECKER_TYPE,
17143  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_39_WIDTH },
17144  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_40_CHECKER_TYPE,
17145  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_40_WIDTH },
17146  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_41_CHECKER_TYPE,
17147  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_41_WIDTH },
17148  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_42_CHECKER_TYPE,
17149  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_42_WIDTH },
17150  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_43_CHECKER_TYPE,
17151  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_43_WIDTH },
17152  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_44_CHECKER_TYPE,
17153  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_44_WIDTH },
17154  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_45_CHECKER_TYPE,
17155  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_45_WIDTH },
17156  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_46_CHECKER_TYPE,
17157  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_46_WIDTH },
17158  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_47_CHECKER_TYPE,
17159  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_47_WIDTH },
17160  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_48_CHECKER_TYPE,
17161  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_48_WIDTH },
17162  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_49_CHECKER_TYPE,
17163  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_49_WIDTH },
17164  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_50_CHECKER_TYPE,
17165  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_50_WIDTH },
17166  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_51_CHECKER_TYPE,
17167  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_51_WIDTH },
17168  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_52_CHECKER_TYPE,
17169  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_52_WIDTH },
17170  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_53_CHECKER_TYPE,
17171  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_53_WIDTH },
17172  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_54_CHECKER_TYPE,
17173  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_54_WIDTH },
17174  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_55_CHECKER_TYPE,
17175  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_55_WIDTH },
17176  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_56_CHECKER_TYPE,
17177  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_56_WIDTH },
17178  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_57_CHECKER_TYPE,
17179  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_57_WIDTH },
17180  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_58_CHECKER_TYPE,
17181  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_58_WIDTH },
17182  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_59_CHECKER_TYPE,
17183  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_59_WIDTH },
17184  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_60_CHECKER_TYPE,
17185  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_60_WIDTH },
17186  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_61_CHECKER_TYPE,
17187  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_61_WIDTH },
17188  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_62_CHECKER_TYPE,
17189  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_62_WIDTH },
17190  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_63_CHECKER_TYPE,
17191  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_63_WIDTH },
17192  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_64_CHECKER_TYPE,
17193  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_64_WIDTH },
17194  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_65_CHECKER_TYPE,
17195  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_65_WIDTH },
17196  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_66_CHECKER_TYPE,
17197  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_66_WIDTH },
17198  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_67_CHECKER_TYPE,
17199  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_67_WIDTH },
17200  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_68_CHECKER_TYPE,
17201  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_68_WIDTH },
17202  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_69_CHECKER_TYPE,
17203  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_69_WIDTH },
17204  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_70_CHECKER_TYPE,
17205  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_70_WIDTH },
17206  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_71_CHECKER_TYPE,
17207  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_71_WIDTH },
17208  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_72_CHECKER_TYPE,
17209  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_72_WIDTH },
17210  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_73_CHECKER_TYPE,
17211  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_73_WIDTH },
17212  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_74_CHECKER_TYPE,
17213  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_74_WIDTH },
17214  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_75_CHECKER_TYPE,
17215  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_75_WIDTH },
17216  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_76_CHECKER_TYPE,
17217  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_76_WIDTH },
17218  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_77_CHECKER_TYPE,
17219  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_77_WIDTH },
17220  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_78_CHECKER_TYPE,
17221  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_78_WIDTH },
17222  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_79_CHECKER_TYPE,
17223  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_79_WIDTH },
17224  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_80_CHECKER_TYPE,
17225  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_80_WIDTH },
17226  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_81_CHECKER_TYPE,
17227  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_81_WIDTH },
17228  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_82_CHECKER_TYPE,
17229  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_82_WIDTH },
17230  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_83_CHECKER_TYPE,
17231  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_83_WIDTH },
17232  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_84_CHECKER_TYPE,
17233  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_84_WIDTH },
17234  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_85_CHECKER_TYPE,
17235  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_85_WIDTH },
17236  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_86_CHECKER_TYPE,
17237  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_86_WIDTH },
17238  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_87_CHECKER_TYPE,
17239  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_87_WIDTH },
17240  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_88_CHECKER_TYPE,
17241  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_88_WIDTH },
17242  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_89_CHECKER_TYPE,
17243  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_89_WIDTH },
17244  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_90_CHECKER_TYPE,
17245  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_90_WIDTH },
17246  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_91_CHECKER_TYPE,
17247  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_91_WIDTH },
17248  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_92_CHECKER_TYPE,
17249  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_92_WIDTH },
17250  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_93_CHECKER_TYPE,
17251  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_93_WIDTH },
17252  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_94_CHECKER_TYPE,
17253  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_94_WIDTH },
17254  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_95_CHECKER_TYPE,
17255  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_95_WIDTH },
17256  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_96_CHECKER_TYPE,
17257  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_96_WIDTH },
17258  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_97_CHECKER_TYPE,
17259  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_97_WIDTH },
17260  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_98_CHECKER_TYPE,
17261  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_98_WIDTH },
17262  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_99_CHECKER_TYPE,
17263  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_99_WIDTH },
17264  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_100_CHECKER_TYPE,
17265  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_100_WIDTH },
17266  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_101_CHECKER_TYPE,
17267  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_101_WIDTH },
17268  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_102_CHECKER_TYPE,
17269  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_102_WIDTH },
17270  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_103_CHECKER_TYPE,
17271  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_103_WIDTH },
17272  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_104_CHECKER_TYPE,
17273  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_104_WIDTH },
17274  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_105_CHECKER_TYPE,
17275  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_105_WIDTH },
17276  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_106_CHECKER_TYPE,
17277  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_106_WIDTH },
17278  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_107_CHECKER_TYPE,
17279  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_107_WIDTH },
17280  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_108_CHECKER_TYPE,
17281  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_108_WIDTH },
17282  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_109_CHECKER_TYPE,
17283  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_109_WIDTH },
17284  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_110_CHECKER_TYPE,
17285  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_110_WIDTH },
17286  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_111_CHECKER_TYPE,
17287  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_111_WIDTH },
17288  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_112_CHECKER_TYPE,
17289  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_112_WIDTH },
17290  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_113_CHECKER_TYPE,
17291  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_113_WIDTH },
17292  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_114_CHECKER_TYPE,
17293  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_114_WIDTH },
17294  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_115_CHECKER_TYPE,
17295  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_115_WIDTH },
17296  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_116_CHECKER_TYPE,
17297  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_116_WIDTH },
17298  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_117_CHECKER_TYPE,
17299  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_117_WIDTH },
17300  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_118_CHECKER_TYPE,
17301  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_118_WIDTH },
17302  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_119_CHECKER_TYPE,
17303  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_119_WIDTH },
17304  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_120_CHECKER_TYPE,
17305  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_120_WIDTH },
17306  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_121_CHECKER_TYPE,
17307  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_121_WIDTH },
17308  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_122_CHECKER_TYPE,
17309  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_122_WIDTH },
17310  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_123_CHECKER_TYPE,
17311  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_123_WIDTH },
17312  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_124_CHECKER_TYPE,
17313  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_124_WIDTH },
17314  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_125_CHECKER_TYPE,
17315  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_125_WIDTH },
17316  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_126_CHECKER_TYPE,
17317  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_126_WIDTH },
17318  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_127_CHECKER_TYPE,
17319  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_127_WIDTH },
17320  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_128_CHECKER_TYPE,
17321  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_128_WIDTH },
17322  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_129_CHECKER_TYPE,
17323  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_129_WIDTH },
17324  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_130_CHECKER_TYPE,
17325  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_130_WIDTH },
17326  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_131_CHECKER_TYPE,
17327  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_131_WIDTH },
17328  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_132_CHECKER_TYPE,
17329  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_132_WIDTH },
17330  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_133_CHECKER_TYPE,
17331  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_133_WIDTH },
17332  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_134_CHECKER_TYPE,
17333  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_134_WIDTH },
17334  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_135_CHECKER_TYPE,
17335  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_135_WIDTH },
17336  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_136_CHECKER_TYPE,
17337  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_136_WIDTH },
17338  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_137_CHECKER_TYPE,
17339  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_137_WIDTH },
17340  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_138_CHECKER_TYPE,
17341  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_138_WIDTH },
17342  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_139_CHECKER_TYPE,
17343  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_139_WIDTH },
17344  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_140_CHECKER_TYPE,
17345  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_140_WIDTH },
17346  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_141_CHECKER_TYPE,
17347  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_141_WIDTH },
17348  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_142_CHECKER_TYPE,
17349  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_142_WIDTH },
17350  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_143_CHECKER_TYPE,
17351  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_143_WIDTH },
17352  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_144_CHECKER_TYPE,
17353  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_144_WIDTH },
17354  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_145_CHECKER_TYPE,
17355  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_145_WIDTH },
17356  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_146_CHECKER_TYPE,
17357  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_146_WIDTH },
17358  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_147_CHECKER_TYPE,
17359  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_147_WIDTH },
17360  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_148_CHECKER_TYPE,
17361  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_148_WIDTH },
17362  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_149_CHECKER_TYPE,
17363  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_149_WIDTH },
17364  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_150_CHECKER_TYPE,
17365  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_150_WIDTH },
17366  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_151_CHECKER_TYPE,
17367  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_151_WIDTH },
17368  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_152_CHECKER_TYPE,
17369  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_152_WIDTH },
17370  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_153_CHECKER_TYPE,
17371  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_153_WIDTH },
17372  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_154_CHECKER_TYPE,
17373  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_154_WIDTH },
17374  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_155_CHECKER_TYPE,
17375  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_155_WIDTH },
17376  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_156_CHECKER_TYPE,
17377  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_156_WIDTH },
17378  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_157_CHECKER_TYPE,
17379  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_157_WIDTH },
17380  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_158_CHECKER_TYPE,
17381  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_158_WIDTH },
17382  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_159_CHECKER_TYPE,
17383  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_159_WIDTH },
17384  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_160_CHECKER_TYPE,
17385  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_160_WIDTH },
17386  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_161_CHECKER_TYPE,
17387  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_161_WIDTH },
17388  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_162_CHECKER_TYPE,
17389  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_162_WIDTH },
17390  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_163_CHECKER_TYPE,
17391  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_163_WIDTH },
17392  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_164_CHECKER_TYPE,
17393  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_164_WIDTH },
17394  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_165_CHECKER_TYPE,
17395  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_165_WIDTH },
17396  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_166_CHECKER_TYPE,
17397  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_166_WIDTH },
17398  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_167_CHECKER_TYPE,
17399  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_167_WIDTH },
17400  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_168_CHECKER_TYPE,
17401  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_168_WIDTH },
17402  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_169_CHECKER_TYPE,
17403  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_169_WIDTH },
17404  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_170_CHECKER_TYPE,
17405  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_170_WIDTH },
17406  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_171_CHECKER_TYPE,
17407  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_171_WIDTH },
17408  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_172_CHECKER_TYPE,
17409  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_172_WIDTH },
17410  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_173_CHECKER_TYPE,
17411  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_173_WIDTH },
17412  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_174_CHECKER_TYPE,
17413  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_174_WIDTH },
17414  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_175_CHECKER_TYPE,
17415  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_175_WIDTH },
17416  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_176_CHECKER_TYPE,
17417  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_176_WIDTH },
17418  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_177_CHECKER_TYPE,
17419  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_177_WIDTH },
17420  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_178_CHECKER_TYPE,
17421  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_178_WIDTH },
17422  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_179_CHECKER_TYPE,
17423  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_179_WIDTH },
17424  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_180_CHECKER_TYPE,
17425  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_180_WIDTH },
17426  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_181_CHECKER_TYPE,
17427  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_181_WIDTH },
17428  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_182_CHECKER_TYPE,
17429  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_182_WIDTH },
17430  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_183_CHECKER_TYPE,
17431  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_183_WIDTH },
17432  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_184_CHECKER_TYPE,
17433  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_184_WIDTH },
17434  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_185_CHECKER_TYPE,
17435  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_185_WIDTH },
17436  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_186_CHECKER_TYPE,
17437  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_186_WIDTH },
17438  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_187_CHECKER_TYPE,
17439  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_187_WIDTH },
17440  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_188_CHECKER_TYPE,
17441  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_188_WIDTH },
17442  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_189_CHECKER_TYPE,
17443  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_189_WIDTH },
17444  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_190_CHECKER_TYPE,
17445  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_190_WIDTH },
17446  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_191_CHECKER_TYPE,
17447  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_191_WIDTH },
17448  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_192_CHECKER_TYPE,
17449  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_192_WIDTH },
17450  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_193_CHECKER_TYPE,
17451  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_193_WIDTH },
17452  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_194_CHECKER_TYPE,
17453  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_194_WIDTH },
17454  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_195_CHECKER_TYPE,
17455  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_195_WIDTH },
17456  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_196_CHECKER_TYPE,
17457  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_196_WIDTH },
17458  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_197_CHECKER_TYPE,
17459  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_197_WIDTH },
17460  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_198_CHECKER_TYPE,
17461  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_198_WIDTH },
17462  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_199_CHECKER_TYPE,
17463  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_199_WIDTH },
17464  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_200_CHECKER_TYPE,
17465  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_200_WIDTH },
17466  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_201_CHECKER_TYPE,
17467  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_201_WIDTH },
17468  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_202_CHECKER_TYPE,
17469  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_202_WIDTH },
17470  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_203_CHECKER_TYPE,
17471  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_203_WIDTH },
17472  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_204_CHECKER_TYPE,
17473  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_204_WIDTH },
17474  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_205_CHECKER_TYPE,
17475  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_205_WIDTH },
17476  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_206_CHECKER_TYPE,
17477  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_206_WIDTH },
17478  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_207_CHECKER_TYPE,
17479  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_207_WIDTH },
17480  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_208_CHECKER_TYPE,
17481  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_208_WIDTH },
17482  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_209_CHECKER_TYPE,
17483  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_209_WIDTH },
17484  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_210_CHECKER_TYPE,
17485  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_210_WIDTH },
17486  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_211_CHECKER_TYPE,
17487  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_211_WIDTH },
17488  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_212_CHECKER_TYPE,
17489  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_212_WIDTH },
17490  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_213_CHECKER_TYPE,
17491  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_213_WIDTH },
17492  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_214_CHECKER_TYPE,
17493  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_214_WIDTH },
17494  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_215_CHECKER_TYPE,
17495  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_215_WIDTH },
17496  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_216_CHECKER_TYPE,
17497  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_216_WIDTH },
17498  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_217_CHECKER_TYPE,
17499  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_217_WIDTH },
17500  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_218_CHECKER_TYPE,
17501  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_218_WIDTH },
17502  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_219_CHECKER_TYPE,
17503  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_219_WIDTH },
17504  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_220_CHECKER_TYPE,
17505  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_220_WIDTH },
17506  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_221_CHECKER_TYPE,
17507  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_221_WIDTH },
17508  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_222_CHECKER_TYPE,
17509  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_222_WIDTH },
17510  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_223_CHECKER_TYPE,
17511  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_223_WIDTH },
17512  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_224_CHECKER_TYPE,
17513  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_224_WIDTH },
17514  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_225_CHECKER_TYPE,
17515  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_225_WIDTH },
17516  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_226_CHECKER_TYPE,
17517  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_226_WIDTH },
17518  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_227_CHECKER_TYPE,
17519  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_227_WIDTH },
17520  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_228_CHECKER_TYPE,
17521  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_228_WIDTH },
17522  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_229_CHECKER_TYPE,
17523  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_229_WIDTH },
17524  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_230_CHECKER_TYPE,
17525  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_230_WIDTH },
17526  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_231_CHECKER_TYPE,
17527  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_231_WIDTH },
17528  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_232_CHECKER_TYPE,
17529  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_232_WIDTH },
17530  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_233_CHECKER_TYPE,
17531  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_233_WIDTH },
17532  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_234_CHECKER_TYPE,
17533  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_234_WIDTH },
17534  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_235_CHECKER_TYPE,
17535  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_235_WIDTH },
17536  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_236_CHECKER_TYPE,
17537  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_236_WIDTH },
17538  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_237_CHECKER_TYPE,
17539  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_237_WIDTH },
17540  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_238_CHECKER_TYPE,
17541  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_238_WIDTH },
17542  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_239_CHECKER_TYPE,
17543  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_239_WIDTH },
17544  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_240_CHECKER_TYPE,
17545  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_240_WIDTH },
17546  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_241_CHECKER_TYPE,
17547  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_241_WIDTH },
17548  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_242_CHECKER_TYPE,
17549  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_242_WIDTH },
17550  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_243_CHECKER_TYPE,
17551  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_243_WIDTH },
17552  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_244_CHECKER_TYPE,
17553  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_244_WIDTH },
17554  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_245_CHECKER_TYPE,
17555  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_245_WIDTH },
17556  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_246_CHECKER_TYPE,
17557  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_246_WIDTH },
17558  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_247_CHECKER_TYPE,
17559  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_247_WIDTH },
17560  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_248_CHECKER_TYPE,
17561  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_248_WIDTH },
17562  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_249_CHECKER_TYPE,
17563  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_249_WIDTH },
17564  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_250_CHECKER_TYPE,
17565  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_250_WIDTH },
17566  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_251_CHECKER_TYPE,
17567  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_251_WIDTH },
17568  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_252_CHECKER_TYPE,
17569  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_252_WIDTH },
17570  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_253_CHECKER_TYPE,
17571  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_253_WIDTH },
17572  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_254_CHECKER_TYPE,
17573  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_254_WIDTH },
17574  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_255_CHECKER_TYPE,
17575  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_255_WIDTH },
17576 };
17577 
17583 static const SDL_GrpChkConfig_t SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_groupEntries[SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_MAX_NUM_CHECKERS] =
17584 {
17585  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_0_CHECKER_TYPE,
17586  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_0_WIDTH },
17587  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_1_CHECKER_TYPE,
17588  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_1_WIDTH },
17589  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_2_CHECKER_TYPE,
17590  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_2_WIDTH },
17591  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_3_CHECKER_TYPE,
17592  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_3_WIDTH },
17593  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_4_CHECKER_TYPE,
17594  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_4_WIDTH },
17595  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_5_CHECKER_TYPE,
17596  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_5_WIDTH },
17597  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_6_CHECKER_TYPE,
17598  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_6_WIDTH },
17599  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_7_CHECKER_TYPE,
17600  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_7_WIDTH },
17601  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_8_CHECKER_TYPE,
17602  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_8_WIDTH },
17603  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_9_CHECKER_TYPE,
17604  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_9_WIDTH },
17605  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_10_CHECKER_TYPE,
17606  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_10_WIDTH },
17607  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_11_CHECKER_TYPE,
17608  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_11_WIDTH },
17609  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_12_CHECKER_TYPE,
17610  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_12_WIDTH },
17611  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_13_CHECKER_TYPE,
17612  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_13_WIDTH },
17613  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_14_CHECKER_TYPE,
17614  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_14_WIDTH },
17615  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_15_CHECKER_TYPE,
17616  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_15_WIDTH },
17617  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_16_CHECKER_TYPE,
17618  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_16_WIDTH },
17619  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_17_CHECKER_TYPE,
17620  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_17_WIDTH },
17621  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_18_CHECKER_TYPE,
17622  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_18_WIDTH },
17623  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_19_CHECKER_TYPE,
17624  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_19_WIDTH },
17625  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_20_CHECKER_TYPE,
17626  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_20_WIDTH },
17627  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_21_CHECKER_TYPE,
17628  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_21_WIDTH },
17629  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_22_CHECKER_TYPE,
17630  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_22_WIDTH },
17631  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_23_CHECKER_TYPE,
17632  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_23_WIDTH },
17633  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_24_CHECKER_TYPE,
17634  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_24_WIDTH },
17635  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_25_CHECKER_TYPE,
17636  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_25_WIDTH },
17637  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_26_CHECKER_TYPE,
17638  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_26_WIDTH },
17639  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_27_CHECKER_TYPE,
17640  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_27_WIDTH },
17641  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_28_CHECKER_TYPE,
17642  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_28_WIDTH },
17643  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_29_CHECKER_TYPE,
17644  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_29_WIDTH },
17645  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_30_CHECKER_TYPE,
17646  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_30_WIDTH },
17647  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_31_CHECKER_TYPE,
17648  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_31_WIDTH },
17649  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_32_CHECKER_TYPE,
17650  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_32_WIDTH },
17651  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_33_CHECKER_TYPE,
17652  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_33_WIDTH },
17653  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_34_CHECKER_TYPE,
17654  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_34_WIDTH },
17655  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_35_CHECKER_TYPE,
17656  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_35_WIDTH },
17657  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_36_CHECKER_TYPE,
17658  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_36_WIDTH },
17659  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_37_CHECKER_TYPE,
17660  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_37_WIDTH },
17661  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_38_CHECKER_TYPE,
17662  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_38_WIDTH },
17663  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_39_CHECKER_TYPE,
17664  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_39_WIDTH },
17665  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_40_CHECKER_TYPE,
17666  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_40_WIDTH },
17667  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_41_CHECKER_TYPE,
17668  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_41_WIDTH },
17669  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_42_CHECKER_TYPE,
17670  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_42_WIDTH },
17671 };
17672 
17678 static const SDL_GrpChkConfig_t SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_groupEntries[SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS] =
17679 {
17680  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
17681  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
17682  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
17683  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
17684  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
17685  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
17686  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
17687  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
17688  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
17689  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
17690  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_5_CHECKER_TYPE,
17691  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_5_WIDTH },
17692  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_6_CHECKER_TYPE,
17693  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_6_WIDTH },
17694  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_7_CHECKER_TYPE,
17695  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_7_WIDTH },
17696  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_8_CHECKER_TYPE,
17697  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_8_WIDTH },
17698  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_9_CHECKER_TYPE,
17699  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_9_WIDTH },
17700  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_10_CHECKER_TYPE,
17701  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_10_WIDTH },
17702  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_11_CHECKER_TYPE,
17703  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_11_WIDTH },
17704  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_12_CHECKER_TYPE,
17705  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_12_WIDTH },
17706  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_13_CHECKER_TYPE,
17707  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_13_WIDTH },
17708  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_14_CHECKER_TYPE,
17709  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_14_WIDTH },
17710  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_15_CHECKER_TYPE,
17711  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_15_WIDTH },
17712  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_16_CHECKER_TYPE,
17713  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_16_WIDTH },
17714  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_17_CHECKER_TYPE,
17715  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_17_WIDTH },
17716  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_18_CHECKER_TYPE,
17717  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_18_WIDTH },
17718  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_19_CHECKER_TYPE,
17719  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_19_WIDTH },
17720  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_20_CHECKER_TYPE,
17721  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_20_WIDTH },
17722  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_21_CHECKER_TYPE,
17723  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_21_WIDTH },
17724  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_22_CHECKER_TYPE,
17725  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_22_WIDTH },
17726  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_23_CHECKER_TYPE,
17727  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_23_WIDTH },
17728  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_24_CHECKER_TYPE,
17729  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_24_WIDTH },
17730  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_25_CHECKER_TYPE,
17731  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_25_WIDTH },
17732  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_26_CHECKER_TYPE,
17733  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_26_WIDTH },
17734  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_27_CHECKER_TYPE,
17735  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_27_WIDTH },
17736  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_28_CHECKER_TYPE,
17737  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_28_WIDTH },
17738  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_29_CHECKER_TYPE,
17739  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_29_WIDTH },
17740  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_30_CHECKER_TYPE,
17741  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_30_WIDTH },
17742  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_31_CHECKER_TYPE,
17743  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_31_WIDTH },
17744  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_32_CHECKER_TYPE,
17745  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_32_WIDTH },
17746  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_33_CHECKER_TYPE,
17747  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_33_WIDTH },
17748  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_34_CHECKER_TYPE,
17749  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_34_WIDTH },
17750  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_35_CHECKER_TYPE,
17751  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_35_WIDTH },
17752  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_36_CHECKER_TYPE,
17753  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_36_WIDTH },
17754  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_37_CHECKER_TYPE,
17755  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_37_WIDTH },
17756  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_38_CHECKER_TYPE,
17757  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_38_WIDTH },
17758  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_39_CHECKER_TYPE,
17759  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_39_WIDTH },
17760  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_40_CHECKER_TYPE,
17761  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_40_WIDTH },
17762  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_41_CHECKER_TYPE,
17763  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_41_WIDTH },
17764  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_42_CHECKER_TYPE,
17765  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_42_WIDTH },
17766  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_43_CHECKER_TYPE,
17767  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_43_WIDTH },
17768  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_44_CHECKER_TYPE,
17769  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_44_WIDTH },
17770  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_45_CHECKER_TYPE,
17771  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_45_WIDTH },
17772  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_46_CHECKER_TYPE,
17773  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_46_WIDTH },
17774  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_47_CHECKER_TYPE,
17775  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_47_WIDTH },
17776  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_48_CHECKER_TYPE,
17777  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_48_WIDTH },
17778  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_49_CHECKER_TYPE,
17779  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_49_WIDTH },
17780  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_50_CHECKER_TYPE,
17781  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_50_WIDTH },
17782  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_51_CHECKER_TYPE,
17783  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_51_WIDTH },
17784  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_52_CHECKER_TYPE,
17785  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_52_WIDTH },
17786  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_53_CHECKER_TYPE,
17787  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_53_WIDTH },
17788  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_54_CHECKER_TYPE,
17789  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_54_WIDTH },
17790  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_55_CHECKER_TYPE,
17791  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_55_WIDTH },
17792  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_56_CHECKER_TYPE,
17793  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_56_WIDTH },
17794  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_57_CHECKER_TYPE,
17795  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_57_WIDTH },
17796  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_58_CHECKER_TYPE,
17797  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_58_WIDTH },
17798  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_59_CHECKER_TYPE,
17799  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_59_WIDTH },
17800  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_60_CHECKER_TYPE,
17801  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_60_WIDTH },
17802  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_61_CHECKER_TYPE,
17803  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_61_WIDTH },
17804  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_62_CHECKER_TYPE,
17805  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_62_WIDTH },
17806 };
17807 
17813 static const SDL_GrpChkConfig_t SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_DEFAULT_MMRS_SMS_TIFS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_groupEntries[SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_DEFAULT_MMRS_SMS_TIFS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS] =
17814 {
17815  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_DEFAULT_MMRS_SMS_TIFS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
17816  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_DEFAULT_MMRS_SMS_TIFS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
17817  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_DEFAULT_MMRS_SMS_TIFS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
17818  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_DEFAULT_MMRS_SMS_TIFS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
17819  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_DEFAULT_MMRS_SMS_TIFS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
17820  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_DEFAULT_MMRS_SMS_TIFS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
17821  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_DEFAULT_MMRS_SMS_TIFS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
17822  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_DEFAULT_MMRS_SMS_TIFS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
17823  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_DEFAULT_MMRS_SMS_TIFS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
17824  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_DEFAULT_MMRS_SMS_TIFS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
17825  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_DEFAULT_MMRS_SMS_TIFS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_5_CHECKER_TYPE,
17826  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_DEFAULT_MMRS_SMS_TIFS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_5_WIDTH },
17827  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_DEFAULT_MMRS_SMS_TIFS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_6_CHECKER_TYPE,
17828  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_DEFAULT_MMRS_SMS_TIFS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_6_WIDTH },
17829  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_DEFAULT_MMRS_SMS_TIFS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_7_CHECKER_TYPE,
17830  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_DEFAULT_MMRS_SMS_TIFS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_7_WIDTH },
17831 };
17832 
17838 static const SDL_GrpChkConfig_t SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_groupEntries[SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS] =
17839 {
17840  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
17841  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
17842  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
17843  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
17844  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
17845  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
17846  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
17847  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
17848  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
17849  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
17850  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_5_CHECKER_TYPE,
17851  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_5_WIDTH },
17852  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_6_CHECKER_TYPE,
17853  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_6_WIDTH },
17854  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_7_CHECKER_TYPE,
17855  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_7_WIDTH },
17856  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_8_CHECKER_TYPE,
17857  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_8_WIDTH },
17858  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_9_CHECKER_TYPE,
17859  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_9_WIDTH },
17860  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_10_CHECKER_TYPE,
17861  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_10_WIDTH },
17862  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_11_CHECKER_TYPE,
17863  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_11_WIDTH },
17864  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_12_CHECKER_TYPE,
17865  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_12_WIDTH },
17866  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_13_CHECKER_TYPE,
17867  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_13_WIDTH },
17868  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_14_CHECKER_TYPE,
17869  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_14_WIDTH },
17870  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_15_CHECKER_TYPE,
17871  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_15_WIDTH },
17872  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_16_CHECKER_TYPE,
17873  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_16_WIDTH },
17874  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_17_CHECKER_TYPE,
17875  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_17_WIDTH },
17876  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_18_CHECKER_TYPE,
17877  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_18_WIDTH },
17878  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_19_CHECKER_TYPE,
17879  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_19_WIDTH },
17880  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_20_CHECKER_TYPE,
17881  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_20_WIDTH },
17882  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_21_CHECKER_TYPE,
17883  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_21_WIDTH },
17884  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_22_CHECKER_TYPE,
17885  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_22_WIDTH },
17886  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_23_CHECKER_TYPE,
17887  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_23_WIDTH },
17888  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_24_CHECKER_TYPE,
17889  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_24_WIDTH },
17890  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_25_CHECKER_TYPE,
17891  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_25_WIDTH },
17892  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_26_CHECKER_TYPE,
17893  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_26_WIDTH },
17894  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_27_CHECKER_TYPE,
17895  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_27_WIDTH },
17896  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_28_CHECKER_TYPE,
17897  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_28_WIDTH },
17898  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_29_CHECKER_TYPE,
17899  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_29_WIDTH },
17900  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_30_CHECKER_TYPE,
17901  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_30_WIDTH },
17902  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_31_CHECKER_TYPE,
17903  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_31_WIDTH },
17904  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_32_CHECKER_TYPE,
17905  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_32_WIDTH },
17906  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_33_CHECKER_TYPE,
17907  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_33_WIDTH },
17908  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_34_CHECKER_TYPE,
17909  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_34_WIDTH },
17910  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_35_CHECKER_TYPE,
17911  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_35_WIDTH },
17912  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_36_CHECKER_TYPE,
17913  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_36_WIDTH },
17914  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_37_CHECKER_TYPE,
17915  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_37_WIDTH },
17916  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_38_CHECKER_TYPE,
17917  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_38_WIDTH },
17918  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_39_CHECKER_TYPE,
17919  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_39_WIDTH },
17920  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_40_CHECKER_TYPE,
17921  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_40_WIDTH },
17922  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_41_CHECKER_TYPE,
17923  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_41_WIDTH },
17924 };
17925 
17931 static const SDL_GrpChkConfig_t SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_groupEntries[SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_MAX_NUM_CHECKERS] =
17932 {
17933  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_0_CHECKER_TYPE,
17934  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_0_WIDTH },
17935  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_1_CHECKER_TYPE,
17936  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_1_WIDTH },
17937  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_2_CHECKER_TYPE,
17938  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_2_WIDTH },
17939  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_3_CHECKER_TYPE,
17940  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_3_WIDTH },
17941  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_4_CHECKER_TYPE,
17942  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_4_WIDTH },
17943  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_5_CHECKER_TYPE,
17944  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_5_WIDTH },
17945  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_6_CHECKER_TYPE,
17946  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_6_WIDTH },
17947  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_7_CHECKER_TYPE,
17948  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_7_WIDTH },
17949  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_8_CHECKER_TYPE,
17950  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_8_WIDTH },
17951  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_9_CHECKER_TYPE,
17952  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_9_WIDTH },
17953  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_10_CHECKER_TYPE,
17954  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_10_WIDTH },
17955  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_11_CHECKER_TYPE,
17956  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_11_WIDTH },
17957  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_12_CHECKER_TYPE,
17958  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_12_WIDTH },
17959  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_13_CHECKER_TYPE,
17960  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_13_WIDTH },
17961  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_14_CHECKER_TYPE,
17962  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_14_WIDTH },
17963  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_15_CHECKER_TYPE,
17964  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_15_WIDTH },
17965  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_16_CHECKER_TYPE,
17966  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_16_WIDTH },
17967  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_17_CHECKER_TYPE,
17968  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_17_WIDTH },
17969  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_18_CHECKER_TYPE,
17970  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_18_WIDTH },
17971 };
17972 
17978 static const SDL_GrpChkConfig_t SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_groupEntries[SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS] =
17979 {
17980  { SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
17981  SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
17982  { SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
17983  SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
17984  { SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
17985  SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
17986  { SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
17987  SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
17988  { SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
17989  SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
17990  { SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_5_CHECKER_TYPE,
17991  SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_5_WIDTH },
17992  { SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_6_CHECKER_TYPE,
17993  SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_6_WIDTH },
17994  { SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_7_CHECKER_TYPE,
17995  SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_7_WIDTH },
17996  { SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_8_CHECKER_TYPE,
17997  SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_8_WIDTH },
17998  { SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_9_CHECKER_TYPE,
17999  SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_9_WIDTH },
18000  { SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_10_CHECKER_TYPE,
18001  SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_10_WIDTH },
18002  { SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_11_CHECKER_TYPE,
18003  SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_11_WIDTH },
18004  { SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_12_CHECKER_TYPE,
18005  SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_12_WIDTH },
18006  { SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_13_CHECKER_TYPE,
18007  SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_13_WIDTH },
18008  { SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_14_CHECKER_TYPE,
18009  SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_14_WIDTH },
18010  { SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_15_CHECKER_TYPE,
18011  SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_15_WIDTH },
18012  { SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_16_CHECKER_TYPE,
18013  SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_16_WIDTH },
18014  { SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_17_CHECKER_TYPE,
18015  SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_17_WIDTH },
18016  { SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_18_CHECKER_TYPE,
18017  SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_18_WIDTH },
18018  { SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_19_CHECKER_TYPE,
18019  SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_19_WIDTH },
18020  { SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_20_CHECKER_TYPE,
18021  SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_20_WIDTH },
18022  { SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_21_CHECKER_TYPE,
18023  SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_21_WIDTH },
18024  { SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_22_CHECKER_TYPE,
18025  SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_22_WIDTH },
18026  { SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_23_CHECKER_TYPE,
18027  SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_23_WIDTH },
18028  { SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_24_CHECKER_TYPE,
18029  SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_24_WIDTH },
18030  { SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_25_CHECKER_TYPE,
18031  SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_25_WIDTH },
18032  { SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_26_CHECKER_TYPE,
18033  SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_26_WIDTH },
18034  { SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_27_CHECKER_TYPE,
18035  SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_27_WIDTH },
18036  { SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_28_CHECKER_TYPE,
18037  SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_28_WIDTH },
18038  { SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_29_CHECKER_TYPE,
18039  SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_29_WIDTH },
18040  { SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_30_CHECKER_TYPE,
18041  SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_30_WIDTH },
18042  { SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_31_CHECKER_TYPE,
18043  SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_31_WIDTH },
18044  { SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_32_CHECKER_TYPE,
18045  SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_32_WIDTH },
18046  { SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_33_CHECKER_TYPE,
18047  SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_33_WIDTH },
18048  { SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_34_CHECKER_TYPE,
18049  SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_34_WIDTH },
18050  { SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_35_CHECKER_TYPE,
18051  SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_35_WIDTH },
18052  { SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_36_CHECKER_TYPE,
18053  SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_36_WIDTH },
18054  { SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_37_CHECKER_TYPE,
18055  SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_37_WIDTH },
18056  { SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_38_CHECKER_TYPE,
18057  SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_38_WIDTH },
18058  { SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_39_CHECKER_TYPE,
18059  SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_39_WIDTH },
18060  { SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_40_CHECKER_TYPE,
18061  SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_40_WIDTH },
18062  { SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_41_CHECKER_TYPE,
18063  SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_41_WIDTH },
18064  { SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_42_CHECKER_TYPE,
18065  SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_42_WIDTH },
18066  { SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_43_CHECKER_TYPE,
18067  SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_43_WIDTH },
18068  { SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_44_CHECKER_TYPE,
18069  SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_44_WIDTH },
18070  { SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_45_CHECKER_TYPE,
18071  SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_45_WIDTH },
18072  { SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_46_CHECKER_TYPE,
18073  SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_46_WIDTH },
18074  { SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_47_CHECKER_TYPE,
18075  SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_47_WIDTH },
18076  { SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_48_CHECKER_TYPE,
18077  SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_48_WIDTH },
18078  { SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_49_CHECKER_TYPE,
18079  SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_49_WIDTH },
18080  { SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_50_CHECKER_TYPE,
18081  SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_50_WIDTH },
18082  { SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_51_CHECKER_TYPE,
18083  SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_51_WIDTH },
18084  { SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_52_CHECKER_TYPE,
18085  SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_52_WIDTH },
18086  { SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_53_CHECKER_TYPE,
18087  SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_53_WIDTH },
18088  { SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_54_CHECKER_TYPE,
18089  SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_54_WIDTH },
18090  { SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_55_CHECKER_TYPE,
18091  SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_55_WIDTH },
18092  { SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_56_CHECKER_TYPE,
18093  SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_56_WIDTH },
18094  { SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_57_CHECKER_TYPE,
18095  SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_57_WIDTH },
18096  { SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_58_CHECKER_TYPE,
18097  SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_58_WIDTH },
18098  { SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_59_CHECKER_TYPE,
18099  SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_59_WIDTH },
18100  { SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_60_CHECKER_TYPE,
18101  SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_60_WIDTH },
18102  { SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_61_CHECKER_TYPE,
18103  SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_61_WIDTH },
18104  { SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_62_CHECKER_TYPE,
18105  SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_62_WIDTH },
18106  { SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_63_CHECKER_TYPE,
18107  SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_63_WIDTH },
18108  { SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_64_CHECKER_TYPE,
18109  SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_64_WIDTH },
18110  { SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_65_CHECKER_TYPE,
18111  SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_65_WIDTH },
18112 };
18113 
18119 static const SDL_GrpChkConfig_t SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_DMSS_HSM_P2P_BRIDGE_SMS_DMSS_HSM_BRIDGE_BUSECC_groupEntries[SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_DMSS_HSM_P2P_BRIDGE_SMS_DMSS_HSM_BRIDGE_BUSECC_MAX_NUM_CHECKERS] =
18120 {
18121  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_DMSS_HSM_P2P_BRIDGE_SMS_DMSS_HSM_BRIDGE_BUSECC_GROUP_0_CHECKER_TYPE,
18122  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_DMSS_HSM_P2P_BRIDGE_SMS_DMSS_HSM_BRIDGE_BUSECC_GROUP_0_WIDTH },
18123  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_DMSS_HSM_P2P_BRIDGE_SMS_DMSS_HSM_BRIDGE_BUSECC_GROUP_1_CHECKER_TYPE,
18124  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_DMSS_HSM_P2P_BRIDGE_SMS_DMSS_HSM_BRIDGE_BUSECC_GROUP_1_WIDTH },
18125  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_DMSS_HSM_P2P_BRIDGE_SMS_DMSS_HSM_BRIDGE_BUSECC_GROUP_2_CHECKER_TYPE,
18126  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_DMSS_HSM_P2P_BRIDGE_SMS_DMSS_HSM_BRIDGE_BUSECC_GROUP_2_WIDTH },
18127  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_DMSS_HSM_P2P_BRIDGE_SMS_DMSS_HSM_BRIDGE_BUSECC_GROUP_3_CHECKER_TYPE,
18128  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_DMSS_HSM_P2P_BRIDGE_SMS_DMSS_HSM_BRIDGE_BUSECC_GROUP_3_WIDTH },
18129  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_DMSS_HSM_P2P_BRIDGE_SMS_DMSS_HSM_BRIDGE_BUSECC_GROUP_4_CHECKER_TYPE,
18130  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_DMSS_HSM_P2P_BRIDGE_SMS_DMSS_HSM_BRIDGE_BUSECC_GROUP_4_WIDTH },
18131  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_DMSS_HSM_P2P_BRIDGE_SMS_DMSS_HSM_BRIDGE_BUSECC_GROUP_5_CHECKER_TYPE,
18132  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_DMSS_HSM_P2P_BRIDGE_SMS_DMSS_HSM_BRIDGE_BUSECC_GROUP_5_WIDTH },
18133  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_DMSS_HSM_P2P_BRIDGE_SMS_DMSS_HSM_BRIDGE_BUSECC_GROUP_6_CHECKER_TYPE,
18134  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_DMSS_HSM_P2P_BRIDGE_SMS_DMSS_HSM_BRIDGE_BUSECC_GROUP_6_WIDTH },
18135  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_DMSS_HSM_P2P_BRIDGE_SMS_DMSS_HSM_BRIDGE_BUSECC_GROUP_7_CHECKER_TYPE,
18136  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_DMSS_HSM_P2P_BRIDGE_SMS_DMSS_HSM_BRIDGE_BUSECC_GROUP_7_WIDTH },
18137  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_DMSS_HSM_P2P_BRIDGE_SMS_DMSS_HSM_BRIDGE_BUSECC_GROUP_8_CHECKER_TYPE,
18138  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_DMSS_HSM_P2P_BRIDGE_SMS_DMSS_HSM_BRIDGE_BUSECC_GROUP_8_WIDTH },
18139  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_DMSS_HSM_P2P_BRIDGE_SMS_DMSS_HSM_BRIDGE_BUSECC_GROUP_9_CHECKER_TYPE,
18140  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_DMSS_HSM_P2P_BRIDGE_SMS_DMSS_HSM_BRIDGE_BUSECC_GROUP_9_WIDTH },
18141  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_DMSS_HSM_P2P_BRIDGE_SMS_DMSS_HSM_BRIDGE_BUSECC_GROUP_10_CHECKER_TYPE,
18142  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_DMSS_HSM_P2P_BRIDGE_SMS_DMSS_HSM_BRIDGE_BUSECC_GROUP_10_WIDTH },
18143  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_DMSS_HSM_P2P_BRIDGE_SMS_DMSS_HSM_BRIDGE_BUSECC_GROUP_11_CHECKER_TYPE,
18144  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_DMSS_HSM_P2P_BRIDGE_SMS_DMSS_HSM_BRIDGE_BUSECC_GROUP_11_WIDTH },
18145  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_DMSS_HSM_P2P_BRIDGE_SMS_DMSS_HSM_BRIDGE_BUSECC_GROUP_12_CHECKER_TYPE,
18146  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_DMSS_HSM_P2P_BRIDGE_SMS_DMSS_HSM_BRIDGE_BUSECC_GROUP_12_WIDTH },
18147 };
18148 
18154 static const SDL_GrpChkConfig_t SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_WWRTI_CM_EDC_CTRL_BUSECC_groupEntries[SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_WWRTI_CM_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS] =
18155 {
18156  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_WWRTI_CM_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
18157  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_WWRTI_CM_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
18158  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_WWRTI_CM_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
18159  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_WWRTI_CM_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
18160  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_WWRTI_CM_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
18161  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_WWRTI_CM_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
18162  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_WWRTI_CM_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
18163  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_WWRTI_CM_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
18164  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_WWRTI_CM_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
18165  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_WWRTI_CM_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
18166  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_WWRTI_CM_EDC_CTRL_BUSECC_GROUP_5_CHECKER_TYPE,
18167  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_WWRTI_CM_EDC_CTRL_BUSECC_GROUP_5_WIDTH },
18168 };
18169 
18175 static const SDL_GrpChkConfig_t SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CM_EDC_CTRL_BUSECC_groupEntries[SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CM_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS] =
18176 {
18177  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CM_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
18178  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CM_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
18179  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CM_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
18180  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CM_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
18181  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CM_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
18182  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CM_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
18183  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CM_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
18184  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CM_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
18185  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CM_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
18186  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CM_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
18187  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CM_EDC_CTRL_BUSECC_GROUP_5_CHECKER_TYPE,
18188  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CM_EDC_CTRL_BUSECC_GROUP_5_WIDTH },
18189  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CM_EDC_CTRL_BUSECC_GROUP_6_CHECKER_TYPE,
18190  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CM_EDC_CTRL_BUSECC_GROUP_6_WIDTH },
18191  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CM_EDC_CTRL_BUSECC_GROUP_7_CHECKER_TYPE,
18192  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CM_EDC_CTRL_BUSECC_GROUP_7_WIDTH },
18193  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CM_EDC_CTRL_BUSECC_GROUP_8_CHECKER_TYPE,
18194  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CM_EDC_CTRL_BUSECC_GROUP_8_WIDTH },
18195  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CM_EDC_CTRL_BUSECC_GROUP_9_CHECKER_TYPE,
18196  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CM_EDC_CTRL_BUSECC_GROUP_9_WIDTH },
18197  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CM_EDC_CTRL_BUSECC_GROUP_10_CHECKER_TYPE,
18198  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CM_EDC_CTRL_BUSECC_GROUP_10_WIDTH },
18199  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CM_EDC_CTRL_BUSECC_GROUP_11_CHECKER_TYPE,
18200  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CM_EDC_CTRL_BUSECC_GROUP_11_WIDTH },
18201  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CM_EDC_CTRL_BUSECC_GROUP_12_CHECKER_TYPE,
18202  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CM_EDC_CTRL_BUSECC_GROUP_12_WIDTH },
18203  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CM_EDC_CTRL_BUSECC_GROUP_13_CHECKER_TYPE,
18204  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CM_EDC_CTRL_BUSECC_GROUP_13_WIDTH },
18205  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CM_EDC_CTRL_BUSECC_GROUP_14_CHECKER_TYPE,
18206  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CM_EDC_CTRL_BUSECC_GROUP_14_WIDTH },
18207  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CM_EDC_CTRL_BUSECC_GROUP_15_CHECKER_TYPE,
18208  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CM_EDC_CTRL_BUSECC_GROUP_15_WIDTH },
18209  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CM_EDC_CTRL_BUSECC_GROUP_16_CHECKER_TYPE,
18210  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CM_EDC_CTRL_BUSECC_GROUP_16_WIDTH },
18211  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CM_EDC_CTRL_BUSECC_GROUP_17_CHECKER_TYPE,
18212  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CM_EDC_CTRL_BUSECC_GROUP_17_WIDTH },
18213  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CM_EDC_CTRL_BUSECC_GROUP_18_CHECKER_TYPE,
18214  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CM_EDC_CTRL_BUSECC_GROUP_18_WIDTH },
18215  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CM_EDC_CTRL_BUSECC_GROUP_19_CHECKER_TYPE,
18216  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CM_EDC_CTRL_BUSECC_GROUP_19_WIDTH },
18217  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CM_EDC_CTRL_BUSECC_GROUP_20_CHECKER_TYPE,
18218  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CM_EDC_CTRL_BUSECC_GROUP_20_WIDTH },
18219  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CM_EDC_CTRL_BUSECC_GROUP_21_CHECKER_TYPE,
18220  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CM_EDC_CTRL_BUSECC_GROUP_21_WIDTH },
18221  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CM_EDC_CTRL_BUSECC_GROUP_22_CHECKER_TYPE,
18222  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CM_EDC_CTRL_BUSECC_GROUP_22_WIDTH },
18223  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CM_EDC_CTRL_BUSECC_GROUP_23_CHECKER_TYPE,
18224  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CM_EDC_CTRL_BUSECC_GROUP_23_WIDTH },
18225  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CM_EDC_CTRL_BUSECC_GROUP_24_CHECKER_TYPE,
18226  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CM_EDC_CTRL_BUSECC_GROUP_24_WIDTH },
18227  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CM_EDC_CTRL_BUSECC_GROUP_25_CHECKER_TYPE,
18228  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CM_EDC_CTRL_BUSECC_GROUP_25_WIDTH },
18229  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CM_EDC_CTRL_BUSECC_GROUP_26_CHECKER_TYPE,
18230  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CM_EDC_CTRL_BUSECC_GROUP_26_WIDTH },
18231  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CM_EDC_CTRL_BUSECC_GROUP_27_CHECKER_TYPE,
18232  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CM_EDC_CTRL_BUSECC_GROUP_27_WIDTH },
18233  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CM_EDC_CTRL_BUSECC_GROUP_28_CHECKER_TYPE,
18234  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CM_EDC_CTRL_BUSECC_GROUP_28_WIDTH },
18235  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CM_EDC_CTRL_BUSECC_GROUP_29_CHECKER_TYPE,
18236  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CM_EDC_CTRL_BUSECC_GROUP_29_WIDTH },
18237  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CM_EDC_CTRL_BUSECC_GROUP_30_CHECKER_TYPE,
18238  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CM_EDC_CTRL_BUSECC_GROUP_30_WIDTH },
18239  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CM_EDC_CTRL_BUSECC_GROUP_31_CHECKER_TYPE,
18240  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CM_EDC_CTRL_BUSECC_GROUP_31_WIDTH },
18241  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CM_EDC_CTRL_BUSECC_GROUP_32_CHECKER_TYPE,
18242  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CM_EDC_CTRL_BUSECC_GROUP_32_WIDTH },
18243  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CM_EDC_CTRL_BUSECC_GROUP_33_CHECKER_TYPE,
18244  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CM_EDC_CTRL_BUSECC_GROUP_33_WIDTH },
18245  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CM_EDC_CTRL_BUSECC_GROUP_34_CHECKER_TYPE,
18246  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CM_EDC_CTRL_BUSECC_GROUP_34_WIDTH },
18247  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CM_EDC_CTRL_BUSECC_GROUP_35_CHECKER_TYPE,
18248  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CM_EDC_CTRL_BUSECC_GROUP_35_WIDTH },
18249 };
18250 
18256 static const SDL_GrpChkConfig_t SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_SEC_CM_EDC_CTRL_BUSECC_groupEntries[SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_SEC_CM_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS] =
18257 {
18258  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_SEC_CM_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
18259  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_SEC_CM_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
18260  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_SEC_CM_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
18261  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_SEC_CM_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
18262  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_SEC_CM_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
18263  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_SEC_CM_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
18264  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_SEC_CM_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
18265  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_SEC_CM_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
18266  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_SEC_CM_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
18267  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_SEC_CM_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
18268  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_SEC_CM_EDC_CTRL_BUSECC_GROUP_5_CHECKER_TYPE,
18269  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_SEC_CM_EDC_CTRL_BUSECC_GROUP_5_WIDTH },
18270  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_SEC_CM_EDC_CTRL_BUSECC_GROUP_6_CHECKER_TYPE,
18271  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_SEC_CM_EDC_CTRL_BUSECC_GROUP_6_WIDTH },
18272  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_SEC_CM_EDC_CTRL_BUSECC_GROUP_7_CHECKER_TYPE,
18273  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_SEC_CM_EDC_CTRL_BUSECC_GROUP_7_WIDTH },
18274  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_SEC_CM_EDC_CTRL_BUSECC_GROUP_8_CHECKER_TYPE,
18275  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_SEC_CM_EDC_CTRL_BUSECC_GROUP_8_WIDTH },
18276  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_SEC_CM_EDC_CTRL_BUSECC_GROUP_9_CHECKER_TYPE,
18277  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_SEC_CM_EDC_CTRL_BUSECC_GROUP_9_WIDTH },
18278  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_SEC_CM_EDC_CTRL_BUSECC_GROUP_10_CHECKER_TYPE,
18279  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_SEC_CM_EDC_CTRL_BUSECC_GROUP_10_WIDTH },
18280  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_SEC_CM_EDC_CTRL_BUSECC_GROUP_11_CHECKER_TYPE,
18281  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_SEC_CM_EDC_CTRL_BUSECC_GROUP_11_WIDTH },
18282  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_SEC_CM_EDC_CTRL_BUSECC_GROUP_12_CHECKER_TYPE,
18283  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_SEC_CM_EDC_CTRL_BUSECC_GROUP_12_WIDTH },
18284  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_SEC_CM_EDC_CTRL_BUSECC_GROUP_13_CHECKER_TYPE,
18285  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_SEC_CM_EDC_CTRL_BUSECC_GROUP_13_WIDTH },
18286  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_SEC_CM_EDC_CTRL_BUSECC_GROUP_14_CHECKER_TYPE,
18287  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_SEC_CM_EDC_CTRL_BUSECC_GROUP_14_WIDTH },
18288  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_SEC_CM_EDC_CTRL_BUSECC_GROUP_15_CHECKER_TYPE,
18289  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_SEC_CM_EDC_CTRL_BUSECC_GROUP_15_WIDTH },
18290  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_SEC_CM_EDC_CTRL_BUSECC_GROUP_16_CHECKER_TYPE,
18291  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_SEC_CM_EDC_CTRL_BUSECC_GROUP_16_WIDTH },
18292  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_SEC_CM_EDC_CTRL_BUSECC_GROUP_17_CHECKER_TYPE,
18293  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_SEC_CM_EDC_CTRL_BUSECC_GROUP_17_WIDTH },
18294  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_SEC_CM_EDC_CTRL_BUSECC_GROUP_18_CHECKER_TYPE,
18295  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_SEC_CM_EDC_CTRL_BUSECC_GROUP_18_WIDTH },
18296  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_SEC_CM_EDC_CTRL_BUSECC_GROUP_19_CHECKER_TYPE,
18297  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_SEC_CM_EDC_CTRL_BUSECC_GROUP_19_WIDTH },
18298  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_SEC_CM_EDC_CTRL_BUSECC_GROUP_20_CHECKER_TYPE,
18299  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_SEC_CM_EDC_CTRL_BUSECC_GROUP_20_WIDTH },
18300  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_SEC_CM_EDC_CTRL_BUSECC_GROUP_21_CHECKER_TYPE,
18301  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_SEC_CM_EDC_CTRL_BUSECC_GROUP_21_WIDTH },
18302  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_SEC_CM_EDC_CTRL_BUSECC_GROUP_22_CHECKER_TYPE,
18303  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_SEC_CM_EDC_CTRL_BUSECC_GROUP_22_WIDTH },
18304  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_SEC_CM_EDC_CTRL_BUSECC_GROUP_23_CHECKER_TYPE,
18305  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_SEC_CM_EDC_CTRL_BUSECC_GROUP_23_WIDTH },
18306  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_SEC_CM_EDC_CTRL_BUSECC_GROUP_24_CHECKER_TYPE,
18307  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_SEC_CM_EDC_CTRL_BUSECC_GROUP_24_WIDTH },
18308  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_SEC_CM_EDC_CTRL_BUSECC_GROUP_25_CHECKER_TYPE,
18309  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_SEC_CM_EDC_CTRL_BUSECC_GROUP_25_WIDTH },
18310  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_SEC_CM_EDC_CTRL_BUSECC_GROUP_26_CHECKER_TYPE,
18311  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_SEC_CM_EDC_CTRL_BUSECC_GROUP_26_WIDTH },
18312  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_SEC_CM_EDC_CTRL_BUSECC_GROUP_27_CHECKER_TYPE,
18313  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_SEC_CM_EDC_CTRL_BUSECC_GROUP_27_WIDTH },
18314  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_SEC_CM_EDC_CTRL_BUSECC_GROUP_28_CHECKER_TYPE,
18315  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_SEC_CM_EDC_CTRL_BUSECC_GROUP_28_WIDTH },
18316  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_SEC_CM_EDC_CTRL_BUSECC_GROUP_29_CHECKER_TYPE,
18317  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_SEC_CM_EDC_CTRL_BUSECC_GROUP_29_WIDTH },
18318  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_SEC_CM_EDC_CTRL_BUSECC_GROUP_30_CHECKER_TYPE,
18319  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_SEC_CM_EDC_CTRL_BUSECC_GROUP_30_WIDTH },
18320  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_SEC_CM_EDC_CTRL_BUSECC_GROUP_31_CHECKER_TYPE,
18321  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_SEC_CM_EDC_CTRL_BUSECC_GROUP_31_WIDTH },
18322  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_SEC_CM_EDC_CTRL_BUSECC_GROUP_32_CHECKER_TYPE,
18323  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_SEC_CM_EDC_CTRL_BUSECC_GROUP_32_WIDTH },
18324  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_SEC_CM_EDC_CTRL_BUSECC_GROUP_33_CHECKER_TYPE,
18325  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_SEC_CM_EDC_CTRL_BUSECC_GROUP_33_WIDTH },
18326  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_SEC_CM_EDC_CTRL_BUSECC_GROUP_34_CHECKER_TYPE,
18327  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_SEC_CM_EDC_CTRL_BUSECC_GROUP_34_WIDTH },
18328  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_SEC_CM_EDC_CTRL_BUSECC_GROUP_35_CHECKER_TYPE,
18329  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_SEC_CM_EDC_CTRL_BUSECC_GROUP_35_WIDTH },
18330  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_SEC_CM_EDC_CTRL_BUSECC_GROUP_36_CHECKER_TYPE,
18331  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_SEC_CM_EDC_CTRL_BUSECC_GROUP_36_WIDTH },
18332 };
18333 
18339 static const SDL_GrpChkConfig_t SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_ECC_EDC_CTRL_groupEntries[SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_ECC_EDC_CTRL_MAX_NUM_CHECKERS] =
18340 {
18341  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_ECC_EDC_CTRL_GROUP_0_CHECKER_TYPE,
18342  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_ECC_EDC_CTRL_GROUP_0_WIDTH },
18343  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_ECC_EDC_CTRL_GROUP_1_CHECKER_TYPE,
18344  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_ECC_EDC_CTRL_GROUP_1_WIDTH },
18345  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_ECC_EDC_CTRL_GROUP_2_CHECKER_TYPE,
18346  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_ECC_EDC_CTRL_GROUP_2_WIDTH },
18347  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_ECC_EDC_CTRL_GROUP_3_CHECKER_TYPE,
18348  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_ECC_EDC_CTRL_GROUP_3_WIDTH },
18349  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_ECC_EDC_CTRL_GROUP_4_CHECKER_TYPE,
18350  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_ECC_EDC_CTRL_GROUP_4_WIDTH },
18351  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_ECC_EDC_CTRL_GROUP_5_CHECKER_TYPE,
18352  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_ECC_EDC_CTRL_GROUP_5_WIDTH },
18353 };
18354 
18360 static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_groupEntries[SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_MAX_NUM_CHECKERS] =
18361 {
18362  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_0_CHECKER_TYPE,
18363  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_0_WIDTH },
18364  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_1_CHECKER_TYPE,
18365  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_1_WIDTH },
18366  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_2_CHECKER_TYPE,
18367  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_2_WIDTH },
18368  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_3_CHECKER_TYPE,
18369  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_3_WIDTH },
18370  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_4_CHECKER_TYPE,
18371  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_4_WIDTH },
18372  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_5_CHECKER_TYPE,
18373  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_5_WIDTH },
18374  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_6_CHECKER_TYPE,
18375  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_6_WIDTH },
18376  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_7_CHECKER_TYPE,
18377  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_7_WIDTH },
18378  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_8_CHECKER_TYPE,
18379  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_8_WIDTH },
18380  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_9_CHECKER_TYPE,
18381  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_9_WIDTH },
18382  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_10_CHECKER_TYPE,
18383  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_10_WIDTH },
18384  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_11_CHECKER_TYPE,
18385  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_11_WIDTH },
18386  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_12_CHECKER_TYPE,
18387  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_12_WIDTH },
18388  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_13_CHECKER_TYPE,
18389  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_13_WIDTH },
18390  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_14_CHECKER_TYPE,
18391  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_14_WIDTH },
18392  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_15_CHECKER_TYPE,
18393  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_15_WIDTH },
18394  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_16_CHECKER_TYPE,
18395  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_16_WIDTH },
18396  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_17_CHECKER_TYPE,
18397  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_17_WIDTH },
18398  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_18_CHECKER_TYPE,
18399  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_18_WIDTH },
18400  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_19_CHECKER_TYPE,
18401  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_19_WIDTH },
18402  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_20_CHECKER_TYPE,
18403  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_20_WIDTH },
18404  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_21_CHECKER_TYPE,
18405  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_21_WIDTH },
18406  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_22_CHECKER_TYPE,
18407  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_22_WIDTH },
18408  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_23_CHECKER_TYPE,
18409  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_23_WIDTH },
18410  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_24_CHECKER_TYPE,
18411  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_24_WIDTH },
18412  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_25_CHECKER_TYPE,
18413  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_25_WIDTH },
18414  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_26_CHECKER_TYPE,
18415  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_26_WIDTH },
18416  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_27_CHECKER_TYPE,
18417  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_27_WIDTH },
18418  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_28_CHECKER_TYPE,
18419  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_28_WIDTH },
18420  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_29_CHECKER_TYPE,
18421  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_29_WIDTH },
18422  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_30_CHECKER_TYPE,
18423  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_30_WIDTH },
18424  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_31_CHECKER_TYPE,
18425  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_31_WIDTH },
18426  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_32_CHECKER_TYPE,
18427  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_32_WIDTH },
18428  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_33_CHECKER_TYPE,
18429  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_33_WIDTH },
18430  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_34_CHECKER_TYPE,
18431  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_34_WIDTH },
18432  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_35_CHECKER_TYPE,
18433  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_35_WIDTH },
18434  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_36_CHECKER_TYPE,
18435  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_36_WIDTH },
18436  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_37_CHECKER_TYPE,
18437  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_37_WIDTH },
18438  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_38_CHECKER_TYPE,
18439  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_38_WIDTH },
18440  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_39_CHECKER_TYPE,
18441  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_39_WIDTH },
18442  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_40_CHECKER_TYPE,
18443  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_40_WIDTH },
18444  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_41_CHECKER_TYPE,
18445  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_41_WIDTH },
18446  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_42_CHECKER_TYPE,
18447  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_42_WIDTH },
18448  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_43_CHECKER_TYPE,
18449  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_43_WIDTH },
18450  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_44_CHECKER_TYPE,
18451  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_44_WIDTH },
18452  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_45_CHECKER_TYPE,
18453  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_45_WIDTH },
18454  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_46_CHECKER_TYPE,
18455  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_46_WIDTH },
18456  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_47_CHECKER_TYPE,
18457  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_47_WIDTH },
18458  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_48_CHECKER_TYPE,
18459  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_48_WIDTH },
18460  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_49_CHECKER_TYPE,
18461  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_49_WIDTH },
18462  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_50_CHECKER_TYPE,
18463  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_50_WIDTH },
18464  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_51_CHECKER_TYPE,
18465  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_51_WIDTH },
18466  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_52_CHECKER_TYPE,
18467  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_52_WIDTH },
18468  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_53_CHECKER_TYPE,
18469  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_53_WIDTH },
18470  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_54_CHECKER_TYPE,
18471  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_54_WIDTH },
18472  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_55_CHECKER_TYPE,
18473  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_55_WIDTH },
18474  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_56_CHECKER_TYPE,
18475  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_56_WIDTH },
18476  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_57_CHECKER_TYPE,
18477  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_57_WIDTH },
18478  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_58_CHECKER_TYPE,
18479  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_58_WIDTH },
18480  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_59_CHECKER_TYPE,
18481  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_59_WIDTH },
18482  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_60_CHECKER_TYPE,
18483  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_60_WIDTH },
18484  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_61_CHECKER_TYPE,
18485  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_61_WIDTH },
18486  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_62_CHECKER_TYPE,
18487  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_62_WIDTH },
18488  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_63_CHECKER_TYPE,
18489  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_63_WIDTH },
18490  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_64_CHECKER_TYPE,
18491  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_64_WIDTH },
18492  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_65_CHECKER_TYPE,
18493  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_65_WIDTH },
18494  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_66_CHECKER_TYPE,
18495  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_66_WIDTH },
18496  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_67_CHECKER_TYPE,
18497  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_67_WIDTH },
18498  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_68_CHECKER_TYPE,
18499  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_68_WIDTH },
18500 };
18501 
18507 static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_groupEntries[SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_MAX_NUM_CHECKERS] =
18508 {
18509  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_0_CHECKER_TYPE,
18510  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_0_WIDTH },
18511  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_1_CHECKER_TYPE,
18512  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_1_WIDTH },
18513  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_2_CHECKER_TYPE,
18514  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_2_WIDTH },
18515  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_3_CHECKER_TYPE,
18516  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_3_WIDTH },
18517  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_4_CHECKER_TYPE,
18518  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_4_WIDTH },
18519  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_5_CHECKER_TYPE,
18520  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_5_WIDTH },
18521  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_6_CHECKER_TYPE,
18522  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_6_WIDTH },
18523  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_7_CHECKER_TYPE,
18524  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_7_WIDTH },
18525  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_8_CHECKER_TYPE,
18526  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_8_WIDTH },
18527  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_9_CHECKER_TYPE,
18528  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_9_WIDTH },
18529  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_10_CHECKER_TYPE,
18530  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_10_WIDTH },
18531  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_11_CHECKER_TYPE,
18532  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_11_WIDTH },
18533  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_12_CHECKER_TYPE,
18534  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_12_WIDTH },
18535  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_13_CHECKER_TYPE,
18536  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_13_WIDTH },
18537  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_14_CHECKER_TYPE,
18538  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_14_WIDTH },
18539  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_15_CHECKER_TYPE,
18540  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_15_WIDTH },
18541  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_16_CHECKER_TYPE,
18542  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_16_WIDTH },
18543  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_17_CHECKER_TYPE,
18544  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_17_WIDTH },
18545  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_18_CHECKER_TYPE,
18546  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_18_WIDTH },
18547  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_19_CHECKER_TYPE,
18548  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_19_WIDTH },
18549  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_20_CHECKER_TYPE,
18550  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_20_WIDTH },
18551  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_21_CHECKER_TYPE,
18552  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_21_WIDTH },
18553  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_22_CHECKER_TYPE,
18554  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_22_WIDTH },
18555  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_23_CHECKER_TYPE,
18556  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_23_WIDTH },
18557  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_24_CHECKER_TYPE,
18558  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_24_WIDTH },
18559  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_25_CHECKER_TYPE,
18560  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_25_WIDTH },
18561  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_26_CHECKER_TYPE,
18562  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_26_WIDTH },
18563  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_27_CHECKER_TYPE,
18564  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_27_WIDTH },
18565  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_28_CHECKER_TYPE,
18566  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_28_WIDTH },
18567  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_29_CHECKER_TYPE,
18568  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_29_WIDTH },
18569  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_30_CHECKER_TYPE,
18570  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_30_WIDTH },
18571  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_31_CHECKER_TYPE,
18572  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_31_WIDTH },
18573  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_32_CHECKER_TYPE,
18574  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_32_WIDTH },
18575  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_33_CHECKER_TYPE,
18576  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_33_WIDTH },
18577  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_34_CHECKER_TYPE,
18578  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_34_WIDTH },
18579  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_35_CHECKER_TYPE,
18580  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_35_WIDTH },
18581  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_36_CHECKER_TYPE,
18582  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_36_WIDTH },
18583  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_37_CHECKER_TYPE,
18584  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_37_WIDTH },
18585  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_38_CHECKER_TYPE,
18586  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_38_WIDTH },
18587  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_39_CHECKER_TYPE,
18588  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_39_WIDTH },
18589  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_40_CHECKER_TYPE,
18590  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_40_WIDTH },
18591  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_41_CHECKER_TYPE,
18592  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_41_WIDTH },
18593  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_42_CHECKER_TYPE,
18594  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_42_WIDTH },
18595  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_43_CHECKER_TYPE,
18596  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_43_WIDTH },
18597  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_44_CHECKER_TYPE,
18598  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_44_WIDTH },
18599  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_45_CHECKER_TYPE,
18600  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_45_WIDTH },
18601  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_46_CHECKER_TYPE,
18602  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_46_WIDTH },
18603  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_47_CHECKER_TYPE,
18604  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_47_WIDTH },
18605  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_48_CHECKER_TYPE,
18606  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_48_WIDTH },
18607  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_49_CHECKER_TYPE,
18608  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_49_WIDTH },
18609  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_50_CHECKER_TYPE,
18610  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_50_WIDTH },
18611  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_51_CHECKER_TYPE,
18612  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_51_WIDTH },
18613  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_52_CHECKER_TYPE,
18614  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_52_WIDTH },
18615  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_53_CHECKER_TYPE,
18616  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_53_WIDTH },
18617  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_54_CHECKER_TYPE,
18618  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_54_WIDTH },
18619  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_55_CHECKER_TYPE,
18620  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_55_WIDTH },
18621  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_56_CHECKER_TYPE,
18622  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_56_WIDTH },
18623  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_57_CHECKER_TYPE,
18624  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_57_WIDTH },
18625  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_58_CHECKER_TYPE,
18626  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_58_WIDTH },
18627  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_59_CHECKER_TYPE,
18628  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_59_WIDTH },
18629  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_60_CHECKER_TYPE,
18630  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_60_WIDTH },
18631  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_61_CHECKER_TYPE,
18632  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_61_WIDTH },
18633  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_62_CHECKER_TYPE,
18634  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_62_WIDTH },
18635  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_63_CHECKER_TYPE,
18636  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_63_WIDTH },
18637  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_64_CHECKER_TYPE,
18638  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_64_WIDTH },
18639 };
18640 
18646 static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_groupEntries[SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_MAX_NUM_CHECKERS] =
18647 {
18648  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_0_CHECKER_TYPE,
18649  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_0_WIDTH },
18650  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_1_CHECKER_TYPE,
18651  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_1_WIDTH },
18652  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_2_CHECKER_TYPE,
18653  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_2_WIDTH },
18654  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_3_CHECKER_TYPE,
18655  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_3_WIDTH },
18656  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_4_CHECKER_TYPE,
18657  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_4_WIDTH },
18658  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_5_CHECKER_TYPE,
18659  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_5_WIDTH },
18660  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_6_CHECKER_TYPE,
18661  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_6_WIDTH },
18662  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_7_CHECKER_TYPE,
18663  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_7_WIDTH },
18664  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_8_CHECKER_TYPE,
18665  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_8_WIDTH },
18666  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_9_CHECKER_TYPE,
18667  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_9_WIDTH },
18668  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_10_CHECKER_TYPE,
18669  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_10_WIDTH },
18670  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_11_CHECKER_TYPE,
18671  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_11_WIDTH },
18672  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_12_CHECKER_TYPE,
18673  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_12_WIDTH },
18674  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_13_CHECKER_TYPE,
18675  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_13_WIDTH },
18676  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_14_CHECKER_TYPE,
18677  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_14_WIDTH },
18678  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_15_CHECKER_TYPE,
18679  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_15_WIDTH },
18680  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_16_CHECKER_TYPE,
18681  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_16_WIDTH },
18682  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_17_CHECKER_TYPE,
18683  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_17_WIDTH },
18684  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_18_CHECKER_TYPE,
18685  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_18_WIDTH },
18686  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_19_CHECKER_TYPE,
18687  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_19_WIDTH },
18688  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_20_CHECKER_TYPE,
18689  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_20_WIDTH },
18690  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_21_CHECKER_TYPE,
18691  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_21_WIDTH },
18692  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_22_CHECKER_TYPE,
18693  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_22_WIDTH },
18694  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_23_CHECKER_TYPE,
18695  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_23_WIDTH },
18696  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_24_CHECKER_TYPE,
18697  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_24_WIDTH },
18698  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_25_CHECKER_TYPE,
18699  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_25_WIDTH },
18700  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_26_CHECKER_TYPE,
18701  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_26_WIDTH },
18702  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_27_CHECKER_TYPE,
18703  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_27_WIDTH },
18704  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_28_CHECKER_TYPE,
18705  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_28_WIDTH },
18706  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_29_CHECKER_TYPE,
18707  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_29_WIDTH },
18708  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_30_CHECKER_TYPE,
18709  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_30_WIDTH },
18710  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_31_CHECKER_TYPE,
18711  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_31_WIDTH },
18712  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_32_CHECKER_TYPE,
18713  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_32_WIDTH },
18714  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_33_CHECKER_TYPE,
18715  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_33_WIDTH },
18716  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_34_CHECKER_TYPE,
18717  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_34_WIDTH },
18718  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_35_CHECKER_TYPE,
18719  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_35_WIDTH },
18720  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_36_CHECKER_TYPE,
18721  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_36_WIDTH },
18722  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_37_CHECKER_TYPE,
18723  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_37_WIDTH },
18724  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_38_CHECKER_TYPE,
18725  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_38_WIDTH },
18726  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_39_CHECKER_TYPE,
18727  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_39_WIDTH },
18728  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_40_CHECKER_TYPE,
18729  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_40_WIDTH },
18730  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_41_CHECKER_TYPE,
18731  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_41_WIDTH },
18732  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_42_CHECKER_TYPE,
18733  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_42_WIDTH },
18734  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_43_CHECKER_TYPE,
18735  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_43_WIDTH },
18736  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_44_CHECKER_TYPE,
18737  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_44_WIDTH },
18738  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_45_CHECKER_TYPE,
18739  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_45_WIDTH },
18740  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_46_CHECKER_TYPE,
18741  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_46_WIDTH },
18742  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_47_CHECKER_TYPE,
18743  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_47_WIDTH },
18744  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_48_CHECKER_TYPE,
18745  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_48_WIDTH },
18746  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_49_CHECKER_TYPE,
18747  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_49_WIDTH },
18748  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_50_CHECKER_TYPE,
18749  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_50_WIDTH },
18750  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_51_CHECKER_TYPE,
18751  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_51_WIDTH },
18752  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_52_CHECKER_TYPE,
18753  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_52_WIDTH },
18754  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_53_CHECKER_TYPE,
18755  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_53_WIDTH },
18756  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_54_CHECKER_TYPE,
18757  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_54_WIDTH },
18758  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_55_CHECKER_TYPE,
18759  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_55_WIDTH },
18760  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_56_CHECKER_TYPE,
18761  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_56_WIDTH },
18762  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_57_CHECKER_TYPE,
18763  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_57_WIDTH },
18764  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_58_CHECKER_TYPE,
18765  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_58_WIDTH },
18766  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_59_CHECKER_TYPE,
18767  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_59_WIDTH },
18768  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_60_CHECKER_TYPE,
18769  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_60_WIDTH },
18770  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_61_CHECKER_TYPE,
18771  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_61_WIDTH },
18772  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_62_CHECKER_TYPE,
18773  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_62_WIDTH },
18774  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_63_CHECKER_TYPE,
18775  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_63_WIDTH },
18776  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_64_CHECKER_TYPE,
18777  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_64_WIDTH },
18778  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_65_CHECKER_TYPE,
18779  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_65_WIDTH },
18780  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_66_CHECKER_TYPE,
18781  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_66_WIDTH },
18782  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_67_CHECKER_TYPE,
18783  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_67_WIDTH },
18784  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_68_CHECKER_TYPE,
18785  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_68_WIDTH },
18786 };
18787 
18793 static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_CFG_SLV_DST_BUSECC_groupEntries[SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_CFG_SLV_DST_BUSECC_MAX_NUM_CHECKERS] =
18794 {
18795  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_CFG_SLV_DST_BUSECC_GROUP_0_CHECKER_TYPE,
18796  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_CFG_SLV_DST_BUSECC_GROUP_0_WIDTH },
18797  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_CFG_SLV_DST_BUSECC_GROUP_1_CHECKER_TYPE,
18798  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_CFG_SLV_DST_BUSECC_GROUP_1_WIDTH },
18799  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_CFG_SLV_DST_BUSECC_GROUP_2_CHECKER_TYPE,
18800  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_CFG_SLV_DST_BUSECC_GROUP_2_WIDTH },
18801  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_CFG_SLV_DST_BUSECC_GROUP_3_CHECKER_TYPE,
18802  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_CFG_SLV_DST_BUSECC_GROUP_3_WIDTH },
18803 };
18804 
18810 static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_PMST_SRC_BUSECC_groupEntries[SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_PMST_SRC_BUSECC_MAX_NUM_CHECKERS] =
18811 {
18812  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_PMST_SRC_BUSECC_GROUP_0_CHECKER_TYPE,
18813  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_PMST_SRC_BUSECC_GROUP_0_WIDTH },
18814  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_PMST_SRC_BUSECC_GROUP_1_CHECKER_TYPE,
18815  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_PMST_SRC_BUSECC_GROUP_1_WIDTH },
18816  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_PMST_SRC_BUSECC_GROUP_2_CHECKER_TYPE,
18817  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_PMST_SRC_BUSECC_GROUP_2_WIDTH },
18818  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_PMST_SRC_BUSECC_GROUP_3_CHECKER_TYPE,
18819  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_PMST_SRC_BUSECC_GROUP_3_WIDTH },
18820  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_PMST_SRC_BUSECC_GROUP_4_CHECKER_TYPE,
18821  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_PMST_SRC_BUSECC_GROUP_4_WIDTH },
18822  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_PMST_SRC_BUSECC_GROUP_5_CHECKER_TYPE,
18823  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_PMST_SRC_BUSECC_GROUP_5_WIDTH },
18824  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_PMST_SRC_BUSECC_GROUP_6_CHECKER_TYPE,
18825  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_PMST_SRC_BUSECC_GROUP_6_WIDTH },
18826  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_PMST_SRC_BUSECC_GROUP_7_CHECKER_TYPE,
18827  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_PMST_SRC_BUSECC_GROUP_7_WIDTH },
18828  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_PMST_SRC_BUSECC_GROUP_8_CHECKER_TYPE,
18829  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_PMST_SRC_BUSECC_GROUP_8_WIDTH },
18830  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_PMST_SRC_BUSECC_GROUP_9_CHECKER_TYPE,
18831  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_PMST_SRC_BUSECC_GROUP_9_WIDTH },
18832  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_PMST_SRC_BUSECC_GROUP_10_CHECKER_TYPE,
18833  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_PMST_SRC_BUSECC_GROUP_10_WIDTH },
18834  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_PMST_SRC_BUSECC_GROUP_11_CHECKER_TYPE,
18835  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_PMST_SRC_BUSECC_GROUP_11_WIDTH },
18836  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_PMST_SRC_BUSECC_GROUP_12_CHECKER_TYPE,
18837  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_PMST_SRC_BUSECC_GROUP_12_WIDTH },
18838  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_PMST_SRC_BUSECC_GROUP_13_CHECKER_TYPE,
18839  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_PMST_SRC_BUSECC_GROUP_13_WIDTH },
18840  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_PMST_SRC_BUSECC_GROUP_14_CHECKER_TYPE,
18841  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_PMST_SRC_BUSECC_GROUP_14_WIDTH },
18842 };
18843 
18849 static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__IECC_AGGR_CFG_DST_BUSECC_groupEntries[SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__IECC_AGGR_CFG_DST_BUSECC_MAX_NUM_CHECKERS] =
18850 {
18851  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__IECC_AGGR_CFG_DST_BUSECC_GROUP_0_CHECKER_TYPE,
18852  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__IECC_AGGR_CFG_DST_BUSECC_GROUP_0_WIDTH },
18853  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__IECC_AGGR_CFG_DST_BUSECC_GROUP_1_CHECKER_TYPE,
18854  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__IECC_AGGR_CFG_DST_BUSECC_GROUP_1_WIDTH },
18855  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__IECC_AGGR_CFG_DST_BUSECC_GROUP_2_CHECKER_TYPE,
18856  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__IECC_AGGR_CFG_DST_BUSECC_GROUP_2_WIDTH },
18857  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__IECC_AGGR_CFG_DST_BUSECC_GROUP_3_CHECKER_TYPE,
18858  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__IECC_AGGR_CFG_DST_BUSECC_GROUP_3_WIDTH },
18859 };
18860 
18866 static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_SAM62A_MCU_PULSAR_UL_ECC_AGGR_EDC_CTRL_groupEntries[SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_SAM62A_MCU_PULSAR_UL_ECC_AGGR_EDC_CTRL_MAX_NUM_CHECKERS] =
18867 {
18868  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_SAM62A_MCU_PULSAR_UL_ECC_AGGR_EDC_CTRL_GROUP_0_CHECKER_TYPE,
18869  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_SAM62A_MCU_PULSAR_UL_ECC_AGGR_EDC_CTRL_GROUP_0_WIDTH },
18870  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_SAM62A_MCU_PULSAR_UL_ECC_AGGR_EDC_CTRL_GROUP_1_CHECKER_TYPE,
18871  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_SAM62A_MCU_PULSAR_UL_ECC_AGGR_EDC_CTRL_GROUP_1_WIDTH },
18872  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_SAM62A_MCU_PULSAR_UL_ECC_AGGR_EDC_CTRL_GROUP_2_CHECKER_TYPE,
18873  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_SAM62A_MCU_PULSAR_UL_ECC_AGGR_EDC_CTRL_GROUP_2_WIDTH },
18874  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_SAM62A_MCU_PULSAR_UL_ECC_AGGR_EDC_CTRL_GROUP_3_CHECKER_TYPE,
18875  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_SAM62A_MCU_PULSAR_UL_ECC_AGGR_EDC_CTRL_GROUP_3_WIDTH },
18876  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_SAM62A_MCU_PULSAR_UL_ECC_AGGR_EDC_CTRL_GROUP_4_CHECKER_TYPE,
18877  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_SAM62A_MCU_PULSAR_UL_ECC_AGGR_EDC_CTRL_GROUP_4_WIDTH },
18878  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_SAM62A_MCU_PULSAR_UL_ECC_AGGR_EDC_CTRL_GROUP_5_CHECKER_TYPE,
18879  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_SAM62A_MCU_PULSAR_UL_ECC_AGGR_EDC_CTRL_GROUP_5_WIDTH },
18880 };
18881 
18886 static const SDL_MemConfig_t SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_MemEntries[SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES] =
18887 {
18888  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_SAM62A_C7XV_CLEC_CLEC_SRAM_RAM_ID, 0u,
18889  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_SAM62A_C7XV_CLEC_CLEC_SRAM_RAM_SIZE, 4u,
18890  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_SAM62A_C7XV_CLEC_CLEC_SRAM_ROW_WIDTH, ((bool)false) },
18891 };
18892 
18898 static const SDL_GrpChkConfig_t SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_AC71_PMC_WRAP_PMC_PMC_MEMWRAP_EDC_CTRL_PARITY_0_groupEntries[SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_AC71_PMC_WRAP_PMC_PMC_MEMWRAP_EDC_CTRL_PARITY_0_MAX_NUM_CHECKERS] =
18899 {
18900  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_AC71_PMC_WRAP_PMC_PMC_MEMWRAP_EDC_CTRL_PARITY_0_GROUP_0_CHECKER_TYPE,
18901  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_AC71_PMC_WRAP_PMC_PMC_MEMWRAP_EDC_CTRL_PARITY_0_GROUP_0_WIDTH },
18902  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_AC71_PMC_WRAP_PMC_PMC_MEMWRAP_EDC_CTRL_PARITY_0_GROUP_1_CHECKER_TYPE,
18903  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_AC71_PMC_WRAP_PMC_PMC_MEMWRAP_EDC_CTRL_PARITY_0_GROUP_1_WIDTH },
18904  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_AC71_PMC_WRAP_PMC_PMC_MEMWRAP_EDC_CTRL_PARITY_0_GROUP_2_CHECKER_TYPE,
18905  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_AC71_PMC_WRAP_PMC_PMC_MEMWRAP_EDC_CTRL_PARITY_0_GROUP_2_WIDTH },
18906  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_AC71_PMC_WRAP_PMC_PMC_MEMWRAP_EDC_CTRL_PARITY_0_GROUP_3_CHECKER_TYPE,
18907  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_AC71_PMC_WRAP_PMC_PMC_MEMWRAP_EDC_CTRL_PARITY_0_GROUP_3_WIDTH },
18908 };
18909 
18915 static const SDL_GrpChkConfig_t SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_TAG_CTL_TOP_DMC_TAG_CTL_EDC_CTRL_0_groupEntries[SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_TAG_CTL_TOP_DMC_TAG_CTL_EDC_CTRL_0_MAX_NUM_CHECKERS] =
18916 {
18917  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_TAG_CTL_TOP_DMC_TAG_CTL_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
18918  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_TAG_CTL_TOP_DMC_TAG_CTL_EDC_CTRL_0_GROUP_0_WIDTH },
18919  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_TAG_CTL_TOP_DMC_TAG_CTL_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
18920  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_TAG_CTL_TOP_DMC_TAG_CTL_EDC_CTRL_0_GROUP_1_WIDTH },
18921 };
18922 
18928 static const SDL_GrpChkConfig_t SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_groupEntries[SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_MAX_NUM_CHECKERS] =
18929 {
18930  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
18931  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_0_WIDTH },
18932  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
18933  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_1_WIDTH },
18934  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
18935  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_2_WIDTH },
18936  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
18937  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_3_WIDTH },
18938  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
18939  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_4_WIDTH },
18940  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
18941  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_5_WIDTH },
18942  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
18943  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_6_WIDTH },
18944  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
18945  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_7_WIDTH },
18946  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
18947  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_8_WIDTH },
18948  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
18949  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_9_WIDTH },
18950  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
18951  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_10_WIDTH },
18952  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
18953  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_11_WIDTH },
18954  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
18955  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_12_WIDTH },
18956  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
18957  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_13_WIDTH },
18958  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
18959  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_14_WIDTH },
18960  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
18961  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_15_WIDTH },
18962  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
18963  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_16_WIDTH },
18964  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
18965  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_17_WIDTH },
18966  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
18967  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_18_WIDTH },
18968  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
18969  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_19_WIDTH },
18970  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
18971  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_20_WIDTH },
18972  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
18973  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_21_WIDTH },
18974  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
18975  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_22_WIDTH },
18976  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
18977  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_23_WIDTH },
18978  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
18979  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_24_WIDTH },
18980  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
18981  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_25_WIDTH },
18982  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
18983  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_26_WIDTH },
18984  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
18985  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_27_WIDTH },
18986  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
18987  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_28_WIDTH },
18988  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
18989  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_29_WIDTH },
18990  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
18991  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_30_WIDTH },
18992  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
18993  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_31_WIDTH },
18994  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
18995  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_32_WIDTH },
18996  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_33_CHECKER_TYPE,
18997  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_33_WIDTH },
18998  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_34_CHECKER_TYPE,
18999  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_34_WIDTH },
19000  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_35_CHECKER_TYPE,
19001  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_35_WIDTH },
19002  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_36_CHECKER_TYPE,
19003  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_36_WIDTH },
19004  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_37_CHECKER_TYPE,
19005  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_37_WIDTH },
19006  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_38_CHECKER_TYPE,
19007  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_38_WIDTH },
19008  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_39_CHECKER_TYPE,
19009  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_39_WIDTH },
19010  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_40_CHECKER_TYPE,
19011  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_40_WIDTH },
19012  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_41_CHECKER_TYPE,
19013  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_41_WIDTH },
19014  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_42_CHECKER_TYPE,
19015  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_42_WIDTH },
19016  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_43_CHECKER_TYPE,
19017  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_43_WIDTH },
19018  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_44_CHECKER_TYPE,
19019  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_44_WIDTH },
19020  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_45_CHECKER_TYPE,
19021  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_45_WIDTH },
19022  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_46_CHECKER_TYPE,
19023  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_46_WIDTH },
19024  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_47_CHECKER_TYPE,
19025  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_47_WIDTH },
19026  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_48_CHECKER_TYPE,
19027  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_48_WIDTH },
19028  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_49_CHECKER_TYPE,
19029  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_49_WIDTH },
19030  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_50_CHECKER_TYPE,
19031  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_50_WIDTH },
19032  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_51_CHECKER_TYPE,
19033  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_51_WIDTH },
19034  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_52_CHECKER_TYPE,
19035  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_52_WIDTH },
19036  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_53_CHECKER_TYPE,
19037  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_53_WIDTH },
19038  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_54_CHECKER_TYPE,
19039  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_54_WIDTH },
19040  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_55_CHECKER_TYPE,
19041  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_55_WIDTH },
19042  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_56_CHECKER_TYPE,
19043  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_56_WIDTH },
19044  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_57_CHECKER_TYPE,
19045  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_57_WIDTH },
19046  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_58_CHECKER_TYPE,
19047  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_58_WIDTH },
19048  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_59_CHECKER_TYPE,
19049  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_59_WIDTH },
19050  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_60_CHECKER_TYPE,
19051  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_60_WIDTH },
19052  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_61_CHECKER_TYPE,
19053  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_61_WIDTH },
19054  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_62_CHECKER_TYPE,
19055  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_62_WIDTH },
19056  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_63_CHECKER_TYPE,
19057  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_63_WIDTH },
19058  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_64_CHECKER_TYPE,
19059  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_64_WIDTH },
19060  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_65_CHECKER_TYPE,
19061  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_65_WIDTH },
19062  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_66_CHECKER_TYPE,
19063  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_66_WIDTH },
19064  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_67_CHECKER_TYPE,
19065  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_67_WIDTH },
19066  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_68_CHECKER_TYPE,
19067  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_68_WIDTH },
19068  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_69_CHECKER_TYPE,
19069  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_69_WIDTH },
19070  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_70_CHECKER_TYPE,
19071  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_70_WIDTH },
19072  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_71_CHECKER_TYPE,
19073  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_71_WIDTH },
19074  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_72_CHECKER_TYPE,
19075  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_72_WIDTH },
19076  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_73_CHECKER_TYPE,
19077  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_73_WIDTH },
19078  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_74_CHECKER_TYPE,
19079  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_74_WIDTH },
19080  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_75_CHECKER_TYPE,
19081  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_75_WIDTH },
19082  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_76_CHECKER_TYPE,
19083  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_76_WIDTH },
19084  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_77_CHECKER_TYPE,
19085  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_77_WIDTH },
19086  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_78_CHECKER_TYPE,
19087  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_78_WIDTH },
19088  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_79_CHECKER_TYPE,
19089  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_79_WIDTH },
19090  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_80_CHECKER_TYPE,
19091  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_80_WIDTH },
19092  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_81_CHECKER_TYPE,
19093  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_81_WIDTH },
19094  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_82_CHECKER_TYPE,
19095  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_82_WIDTH },
19096  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_83_CHECKER_TYPE,
19097  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_83_WIDTH },
19098  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_84_CHECKER_TYPE,
19099  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_84_WIDTH },
19100  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_85_CHECKER_TYPE,
19101  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_85_WIDTH },
19102  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_86_CHECKER_TYPE,
19103  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_86_WIDTH },
19104  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_87_CHECKER_TYPE,
19105  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_87_WIDTH },
19106  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_88_CHECKER_TYPE,
19107  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_88_WIDTH },
19108  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_89_CHECKER_TYPE,
19109  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_89_WIDTH },
19110  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_90_CHECKER_TYPE,
19111  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_90_WIDTH },
19112  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_91_CHECKER_TYPE,
19113  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_91_WIDTH },
19114  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_92_CHECKER_TYPE,
19115  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_92_WIDTH },
19116  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_93_CHECKER_TYPE,
19117  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_93_WIDTH },
19118  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_94_CHECKER_TYPE,
19119  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_94_WIDTH },
19120  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_95_CHECKER_TYPE,
19121  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_95_WIDTH },
19122  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_96_CHECKER_TYPE,
19123  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_96_WIDTH },
19124  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_97_CHECKER_TYPE,
19125  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_97_WIDTH },
19126  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_98_CHECKER_TYPE,
19127  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_98_WIDTH },
19128  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_99_CHECKER_TYPE,
19129  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_99_WIDTH },
19130  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_100_CHECKER_TYPE,
19131  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_100_WIDTH },
19132  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_101_CHECKER_TYPE,
19133  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_101_WIDTH },
19134  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_102_CHECKER_TYPE,
19135  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_102_WIDTH },
19136  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_103_CHECKER_TYPE,
19137  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_103_WIDTH },
19138  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_104_CHECKER_TYPE,
19139  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_104_WIDTH },
19140  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_105_CHECKER_TYPE,
19141  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_105_WIDTH },
19142  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_106_CHECKER_TYPE,
19143  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_106_WIDTH },
19144  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_107_CHECKER_TYPE,
19145  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_107_WIDTH },
19146  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_108_CHECKER_TYPE,
19147  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_108_WIDTH },
19148  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_109_CHECKER_TYPE,
19149  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_109_WIDTH },
19150  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_110_CHECKER_TYPE,
19151  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_110_WIDTH },
19152  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_111_CHECKER_TYPE,
19153  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_111_WIDTH },
19154  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_112_CHECKER_TYPE,
19155  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_112_WIDTH },
19156  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_113_CHECKER_TYPE,
19157  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_113_WIDTH },
19158  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_114_CHECKER_TYPE,
19159  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_114_WIDTH },
19160  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_115_CHECKER_TYPE,
19161  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_115_WIDTH },
19162  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_116_CHECKER_TYPE,
19163  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_116_WIDTH },
19164  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_117_CHECKER_TYPE,
19165  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_117_WIDTH },
19166  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_118_CHECKER_TYPE,
19167  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_118_WIDTH },
19168  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_119_CHECKER_TYPE,
19169  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_119_WIDTH },
19170  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_120_CHECKER_TYPE,
19171  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_120_WIDTH },
19172  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_121_CHECKER_TYPE,
19173  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_121_WIDTH },
19174  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_122_CHECKER_TYPE,
19175  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_122_WIDTH },
19176  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_123_CHECKER_TYPE,
19177  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_123_WIDTH },
19178  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_124_CHECKER_TYPE,
19179  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_124_WIDTH },
19180  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_125_CHECKER_TYPE,
19181  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_125_WIDTH },
19182  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_126_CHECKER_TYPE,
19183  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_126_WIDTH },
19184  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_127_CHECKER_TYPE,
19185  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_127_WIDTH },
19186  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_128_CHECKER_TYPE,
19187  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_128_WIDTH },
19188  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_129_CHECKER_TYPE,
19189  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_129_WIDTH },
19190  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_130_CHECKER_TYPE,
19191  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_130_WIDTH },
19192  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_131_CHECKER_TYPE,
19193  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_131_WIDTH },
19194  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_132_CHECKER_TYPE,
19195  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_132_WIDTH },
19196  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_133_CHECKER_TYPE,
19197  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_133_WIDTH },
19198  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_134_CHECKER_TYPE,
19199  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_134_WIDTH },
19200  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_135_CHECKER_TYPE,
19201  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_135_WIDTH },
19202  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_136_CHECKER_TYPE,
19203  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_136_WIDTH },
19204  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_137_CHECKER_TYPE,
19205  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_137_WIDTH },
19206  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_138_CHECKER_TYPE,
19207  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_138_WIDTH },
19208  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_139_CHECKER_TYPE,
19209  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_139_WIDTH },
19210  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_140_CHECKER_TYPE,
19211  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_140_WIDTH },
19212  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_141_CHECKER_TYPE,
19213  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_141_WIDTH },
19214  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_142_CHECKER_TYPE,
19215  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_142_WIDTH },
19216  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_143_CHECKER_TYPE,
19217  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_143_WIDTH },
19218  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_144_CHECKER_TYPE,
19219  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_144_WIDTH },
19220  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_145_CHECKER_TYPE,
19221  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_145_WIDTH },
19222  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_146_CHECKER_TYPE,
19223  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_146_WIDTH },
19224  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_147_CHECKER_TYPE,
19225  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_147_WIDTH },
19226  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_148_CHECKER_TYPE,
19227  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_148_WIDTH },
19228  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_149_CHECKER_TYPE,
19229  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_149_WIDTH },
19230  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_150_CHECKER_TYPE,
19231  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_150_WIDTH },
19232  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_151_CHECKER_TYPE,
19233  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_151_WIDTH },
19234  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_152_CHECKER_TYPE,
19235  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_152_WIDTH },
19236  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_153_CHECKER_TYPE,
19237  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_153_WIDTH },
19238  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_154_CHECKER_TYPE,
19239  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_154_WIDTH },
19240  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_155_CHECKER_TYPE,
19241  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_155_WIDTH },
19242  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_156_CHECKER_TYPE,
19243  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_156_WIDTH },
19244  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_157_CHECKER_TYPE,
19245  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_157_WIDTH },
19246  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_158_CHECKER_TYPE,
19247  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_158_WIDTH },
19248  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_159_CHECKER_TYPE,
19249  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_159_WIDTH },
19250  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_160_CHECKER_TYPE,
19251  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_160_WIDTH },
19252  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_161_CHECKER_TYPE,
19253  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_161_WIDTH },
19254  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_162_CHECKER_TYPE,
19255  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_162_WIDTH },
19256  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_163_CHECKER_TYPE,
19257  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_163_WIDTH },
19258  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_164_CHECKER_TYPE,
19259  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_164_WIDTH },
19260  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_165_CHECKER_TYPE,
19261  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_165_WIDTH },
19262  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_166_CHECKER_TYPE,
19263  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_166_WIDTH },
19264  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_167_CHECKER_TYPE,
19265  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_167_WIDTH },
19266 };
19267 
19273 static const SDL_GrpChkConfig_t SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_DRU_R30_C_R_CORE_QUEUE_CMD_EDC_CTRL_0_groupEntries[SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_DRU_R30_C_R_CORE_QUEUE_CMD_EDC_CTRL_0_MAX_NUM_CHECKERS] =
19274 {
19275  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_DRU_R30_C_R_CORE_QUEUE_CMD_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
19276  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_DRU_R30_C_R_CORE_QUEUE_CMD_EDC_CTRL_0_GROUP_0_WIDTH },
19277  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_DRU_R30_C_R_CORE_QUEUE_CMD_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
19278  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_DRU_R30_C_R_CORE_QUEUE_CMD_EDC_CTRL_0_GROUP_1_WIDTH },
19279  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_DRU_R30_C_R_CORE_QUEUE_CMD_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
19280  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_DRU_R30_C_R_CORE_QUEUE_CMD_EDC_CTRL_0_GROUP_2_WIDTH },
19281  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_DRU_R30_C_R_CORE_QUEUE_CMD_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
19282  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_DRU_R30_C_R_CORE_QUEUE_CMD_EDC_CTRL_0_GROUP_3_WIDTH },
19283 };
19284 
19290 static const SDL_GrpChkConfig_t SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_DRU_R30_C_R_CORE_RD_BUFFER_CMD_EDC_CTRL_0_groupEntries[SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_DRU_R30_C_R_CORE_RD_BUFFER_CMD_EDC_CTRL_0_MAX_NUM_CHECKERS] =
19291 {
19292  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_DRU_R30_C_R_CORE_RD_BUFFER_CMD_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
19293  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_DRU_R30_C_R_CORE_RD_BUFFER_CMD_EDC_CTRL_0_GROUP_0_WIDTH },
19294 };
19295 
19301 static const SDL_GrpChkConfig_t SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_DRU_R30_C_R_CORE_CH_LOGIC_RING_MEM_RING_EDC_CTRL_0_groupEntries[SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_DRU_R30_C_R_CORE_CH_LOGIC_RING_MEM_RING_EDC_CTRL_0_MAX_NUM_CHECKERS] =
19302 {
19303  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_DRU_R30_C_R_CORE_CH_LOGIC_RING_MEM_RING_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
19304  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_DRU_R30_C_R_CORE_CH_LOGIC_RING_MEM_RING_EDC_CTRL_0_GROUP_0_WIDTH },
19305 };
19306 
19312 static const SDL_GrpChkConfig_t SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_UMC_WRAP_C7XV_EL2_C7XV_EL2_CORE_C7XV_EL2_EDC_CTL_0_groupEntries[SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_UMC_WRAP_C7XV_EL2_C7XV_EL2_CORE_C7XV_EL2_EDC_CTL_0_MAX_NUM_CHECKERS] =
19313 {
19314  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_UMC_WRAP_C7XV_EL2_C7XV_EL2_CORE_C7XV_EL2_EDC_CTL_0_GROUP_0_CHECKER_TYPE,
19315  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_UMC_WRAP_C7XV_EL2_C7XV_EL2_CORE_C7XV_EL2_EDC_CTL_0_GROUP_0_WIDTH },
19316  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_UMC_WRAP_C7XV_EL2_C7XV_EL2_CORE_C7XV_EL2_EDC_CTL_0_GROUP_1_CHECKER_TYPE,
19317  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_UMC_WRAP_C7XV_EL2_C7XV_EL2_CORE_C7XV_EL2_EDC_CTL_0_GROUP_1_WIDTH },
19318  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_UMC_WRAP_C7XV_EL2_C7XV_EL2_CORE_C7XV_EL2_EDC_CTL_0_GROUP_2_CHECKER_TYPE,
19319  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_UMC_WRAP_C7XV_EL2_C7XV_EL2_CORE_C7XV_EL2_EDC_CTL_0_GROUP_2_WIDTH },
19320  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_UMC_WRAP_C7XV_EL2_C7XV_EL2_CORE_C7XV_EL2_EDC_CTL_0_GROUP_3_CHECKER_TYPE,
19321  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_UMC_WRAP_C7XV_EL2_C7XV_EL2_CORE_C7XV_EL2_EDC_CTL_0_GROUP_3_WIDTH },
19322  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_UMC_WRAP_C7XV_EL2_C7XV_EL2_CORE_C7XV_EL2_EDC_CTL_0_GROUP_4_CHECKER_TYPE,
19323  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_UMC_WRAP_C7XV_EL2_C7XV_EL2_CORE_C7XV_EL2_EDC_CTL_0_GROUP_4_WIDTH },
19324  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_UMC_WRAP_C7XV_EL2_C7XV_EL2_CORE_C7XV_EL2_EDC_CTL_0_GROUP_5_CHECKER_TYPE,
19325  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_UMC_WRAP_C7XV_EL2_C7XV_EL2_CORE_C7XV_EL2_EDC_CTL_0_GROUP_5_WIDTH },
19326  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_UMC_WRAP_C7XV_EL2_C7XV_EL2_CORE_C7XV_EL2_EDC_CTL_0_GROUP_6_CHECKER_TYPE,
19327  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_UMC_WRAP_C7XV_EL2_C7XV_EL2_CORE_C7XV_EL2_EDC_CTL_0_GROUP_6_WIDTH },
19328  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_UMC_WRAP_C7XV_EL2_C7XV_EL2_CORE_C7XV_EL2_EDC_CTL_0_GROUP_7_CHECKER_TYPE,
19329  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_UMC_WRAP_C7XV_EL2_C7XV_EL2_CORE_C7XV_EL2_EDC_CTL_0_GROUP_7_WIDTH },
19330  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_UMC_WRAP_C7XV_EL2_C7XV_EL2_CORE_C7XV_EL2_EDC_CTL_0_GROUP_8_CHECKER_TYPE,
19331  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_UMC_WRAP_C7XV_EL2_C7XV_EL2_CORE_C7XV_EL2_EDC_CTL_0_GROUP_8_WIDTH },
19332  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_UMC_WRAP_C7XV_EL2_C7XV_EL2_CORE_C7XV_EL2_EDC_CTL_0_GROUP_9_CHECKER_TYPE,
19333  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_UMC_WRAP_C7XV_EL2_C7XV_EL2_CORE_C7XV_EL2_EDC_CTL_0_GROUP_9_WIDTH },
19334  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_UMC_WRAP_C7XV_EL2_C7XV_EL2_CORE_C7XV_EL2_EDC_CTL_0_GROUP_10_CHECKER_TYPE,
19335  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_UMC_WRAP_C7XV_EL2_C7XV_EL2_CORE_C7XV_EL2_EDC_CTL_0_GROUP_10_WIDTH },
19336  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_UMC_WRAP_C7XV_EL2_C7XV_EL2_CORE_C7XV_EL2_EDC_CTL_0_GROUP_11_CHECKER_TYPE,
19337  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_UMC_WRAP_C7XV_EL2_C7XV_EL2_CORE_C7XV_EL2_EDC_CTL_0_GROUP_11_WIDTH },
19338  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_UMC_WRAP_C7XV_EL2_C7XV_EL2_CORE_C7XV_EL2_EDC_CTL_0_GROUP_12_CHECKER_TYPE,
19339  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_UMC_WRAP_C7XV_EL2_C7XV_EL2_CORE_C7XV_EL2_EDC_CTL_0_GROUP_12_WIDTH },
19340  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_UMC_WRAP_C7XV_EL2_C7XV_EL2_CORE_C7XV_EL2_EDC_CTL_0_GROUP_13_CHECKER_TYPE,
19341  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_UMC_WRAP_C7XV_EL2_C7XV_EL2_CORE_C7XV_EL2_EDC_CTL_0_GROUP_13_WIDTH },
19342  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_UMC_WRAP_C7XV_EL2_C7XV_EL2_CORE_C7XV_EL2_EDC_CTL_0_GROUP_14_CHECKER_TYPE,
19343  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_UMC_WRAP_C7XV_EL2_C7XV_EL2_CORE_C7XV_EL2_EDC_CTL_0_GROUP_14_WIDTH },
19344  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_UMC_WRAP_C7XV_EL2_C7XV_EL2_CORE_C7XV_EL2_EDC_CTL_0_GROUP_15_CHECKER_TYPE,
19345  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_UMC_WRAP_C7XV_EL2_C7XV_EL2_CORE_C7XV_EL2_EDC_CTL_0_GROUP_15_WIDTH },
19346 };
19347 
19352 static const SDL_MemConfig_t SDL_USB1_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_MemEntries[SDL_USB1_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES] =
19353 {
19354  { SDL_USB1_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_USB2SS_16FFC_USB2SS_CORE_AXI2VBUSM_MST_KSBUS_AXI2VBUSM_R_RDATA_BUFFER_RAM_ID, 0u,
19355  SDL_USB1_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_USB2SS_16FFC_USB2SS_CORE_AXI2VBUSM_MST_KSBUS_AXI2VBUSM_R_RDATA_BUFFER_RAM_SIZE, 9u,
19356  SDL_USB1_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_USB2SS_16FFC_USB2SS_CORE_AXI2VBUSM_MST_KSBUS_AXI2VBUSM_R_RDATA_BUFFER_ROW_WIDTH, ((bool)false) },
19357  { SDL_USB1_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_USB2SS_16FFC_USB2SS_CORE_RAMS_MEM_CTRL_RAM0_RAM_ID, 0u,
19358  SDL_USB1_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_USB2SS_16FFC_USB2SS_CORE_RAMS_MEM_CTRL_RAM0_RAM_SIZE, 8u,
19359  SDL_USB1_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_USB2SS_16FFC_USB2SS_CORE_RAMS_MEM_CTRL_RAM0_ROW_WIDTH, ((bool)false) },
19360 };
19361 
19366 static const SDL_MemConfig_t SDL_USB0_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_MemEntries[SDL_USB0_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES] =
19367 {
19368  { SDL_USB0_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_USB2SS_16FFC_USB2SS_CORE_AXI2VBUSM_MST_KSBUS_AXI2VBUSM_R_RDATA_BUFFER_RAM_ID, 0u,
19369  SDL_USB0_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_USB2SS_16FFC_USB2SS_CORE_AXI2VBUSM_MST_KSBUS_AXI2VBUSM_R_RDATA_BUFFER_RAM_SIZE, 9u,
19370  SDL_USB0_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_USB2SS_16FFC_USB2SS_CORE_AXI2VBUSM_MST_KSBUS_AXI2VBUSM_R_RDATA_BUFFER_ROW_WIDTH, ((bool)false) },
19371  { SDL_USB0_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_USB2SS_16FFC_USB2SS_CORE_RAMS_MEM_CTRL_RAM0_RAM_ID, 0u,
19372  SDL_USB0_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_USB2SS_16FFC_USB2SS_CORE_RAMS_MEM_CTRL_RAM0_RAM_SIZE, 8u,
19373  SDL_USB0_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_USB2SS_16FFC_USB2SS_CORE_RAMS_MEM_CTRL_RAM0_ROW_WIDTH, ((bool)false) },
19374 };
19375 
19380 static const SDL_MemConfig_t SDL_WKUP_PSRAMECC_8K0_PSRAM8KX32E_ECC_AGGR_MemEntries[SDL_WKUP_PSRAMECC_8K0_PSRAM8KX32E_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES] =
19381 {
19382  { SDL_WKUP_PSRAMECC_8K0_PSRAM8KX32E_ECC_AGGR_PSRAM8KX32E_PSRAM0_ECC_RAM_ID, 0x0041880000u,
19383  SDL_WKUP_PSRAMECC_8K0_PSRAM8KX32E_ECC_AGGR_PSRAM8KX32E_PSRAM0_ECC_RAM_SIZE, 4u,
19384  SDL_WKUP_PSRAMECC_8K0_PSRAM8KX32E_ECC_AGGR_PSRAM8KX32E_PSRAM0_ECC_ROW_WIDTH, ((bool)true) },
19385 };
19386 
19391 static const SDL_MemConfig_t SDL_PDMA0_SAM62_PDMA_SPI_ECCAGGR_MemEntries[SDL_PDMA0_SAM62_PDMA_SPI_ECCAGGR_RAM_IDS_TOTAL_ENTRIES] =
19392 {
19393  { SDL_PDMA0_SAM62_PDMA_SPI_ECCAGGR_SAM62_PDMA_SPI_PDMA_CORE_TF0_F0_TPRAM_60X128_SBW_SR_RAM_ID, 0u,
19394  SDL_PDMA0_SAM62_PDMA_SPI_ECCAGGR_SAM62_PDMA_SPI_PDMA_CORE_TF0_F0_TPRAM_60X128_SBW_SR_RAM_SIZE, 16u,
19395  SDL_PDMA0_SAM62_PDMA_SPI_ECCAGGR_SAM62_PDMA_SPI_PDMA_CORE_TF0_F0_TPRAM_60X128_SBW_SR_ROW_WIDTH, ((bool)false) },
19396  { SDL_PDMA0_SAM62_PDMA_SPI_ECCAGGR_SAM62_PDMA_SPI_PDMA_CORE_TF0_F1_TPRAM_60X128_SBW_SR_RAM_ID, 0u,
19397  SDL_PDMA0_SAM62_PDMA_SPI_ECCAGGR_SAM62_PDMA_SPI_PDMA_CORE_TF0_F1_TPRAM_60X128_SBW_SR_RAM_SIZE, 16u,
19398  SDL_PDMA0_SAM62_PDMA_SPI_ECCAGGR_SAM62_PDMA_SPI_PDMA_CORE_TF0_F1_TPRAM_60X128_SBW_SR_ROW_WIDTH, ((bool)false) },
19399  { SDL_PDMA0_SAM62_PDMA_SPI_ECCAGGR_SAM62_PDMA_SPI_PDMA_CORE_RF0_F0_TPRAM_60X144_SBW_SR_RAM_ID, 0u,
19400  SDL_PDMA0_SAM62_PDMA_SPI_ECCAGGR_SAM62_PDMA_SPI_PDMA_CORE_RF0_F0_TPRAM_60X144_SBW_SR_RAM_SIZE, 18u,
19401  SDL_PDMA0_SAM62_PDMA_SPI_ECCAGGR_SAM62_PDMA_SPI_PDMA_CORE_RF0_F0_TPRAM_60X144_SBW_SR_ROW_WIDTH, ((bool)false) },
19402  { SDL_PDMA0_SAM62_PDMA_SPI_ECCAGGR_SAM62_PDMA_SPI_PDMA_CORE_RF0_F1_TPRAM_60X144_SBW_SR_RAM_ID, 0u,
19403  SDL_PDMA0_SAM62_PDMA_SPI_ECCAGGR_SAM62_PDMA_SPI_PDMA_CORE_RF0_F1_TPRAM_60X144_SBW_SR_RAM_SIZE, 18u,
19404  SDL_PDMA0_SAM62_PDMA_SPI_ECCAGGR_SAM62_PDMA_SPI_PDMA_CORE_RF0_F1_TPRAM_60X144_SBW_SR_ROW_WIDTH, ((bool)false) },
19405 };
19406 
19412 static const SDL_GrpChkConfig_t SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_groupEntries[SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_MAX_NUM_CHECKERS] =
19413 {
19414  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_0_CHECKER_TYPE,
19415  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_0_WIDTH },
19416  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_1_CHECKER_TYPE,
19417  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_1_WIDTH },
19418  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_2_CHECKER_TYPE,
19419  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_2_WIDTH },
19420  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_3_CHECKER_TYPE,
19421  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_3_WIDTH },
19422  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_4_CHECKER_TYPE,
19423  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_4_WIDTH },
19424  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_5_CHECKER_TYPE,
19425  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_5_WIDTH },
19426  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_6_CHECKER_TYPE,
19427  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_6_WIDTH },
19428  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_7_CHECKER_TYPE,
19429  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_7_WIDTH },
19430  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_8_CHECKER_TYPE,
19431  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_8_WIDTH },
19432  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_9_CHECKER_TYPE,
19433  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_9_WIDTH },
19434  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_10_CHECKER_TYPE,
19435  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_10_WIDTH },
19436  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_11_CHECKER_TYPE,
19437  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_11_WIDTH },
19438  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_12_CHECKER_TYPE,
19439  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_12_WIDTH },
19440  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_13_CHECKER_TYPE,
19441  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_13_WIDTH },
19442  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_14_CHECKER_TYPE,
19443  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_14_WIDTH },
19444  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_15_CHECKER_TYPE,
19445  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_15_WIDTH },
19446  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_16_CHECKER_TYPE,
19447  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_16_WIDTH },
19448  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_17_CHECKER_TYPE,
19449  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_17_WIDTH },
19450  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_18_CHECKER_TYPE,
19451  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_18_WIDTH },
19452  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_19_CHECKER_TYPE,
19453  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_19_WIDTH },
19454  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_20_CHECKER_TYPE,
19455  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_20_WIDTH },
19456  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_21_CHECKER_TYPE,
19457  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_21_WIDTH },
19458  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_22_CHECKER_TYPE,
19459  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_22_WIDTH },
19460  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_23_CHECKER_TYPE,
19461  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_23_WIDTH },
19462  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_24_CHECKER_TYPE,
19463  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_24_WIDTH },
19464  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_25_CHECKER_TYPE,
19465  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_25_WIDTH },
19466  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_26_CHECKER_TYPE,
19467  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_26_WIDTH },
19468  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_27_CHECKER_TYPE,
19469  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_27_WIDTH },
19470  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_28_CHECKER_TYPE,
19471  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_28_WIDTH },
19472  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_29_CHECKER_TYPE,
19473  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_29_WIDTH },
19474  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_30_CHECKER_TYPE,
19475  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_30_WIDTH },
19476  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_31_CHECKER_TYPE,
19477  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_31_WIDTH },
19478  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_32_CHECKER_TYPE,
19479  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_32_WIDTH },
19480  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_33_CHECKER_TYPE,
19481  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_33_WIDTH },
19482  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_34_CHECKER_TYPE,
19483  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_34_WIDTH },
19484  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_35_CHECKER_TYPE,
19485  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_35_WIDTH },
19486  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_36_CHECKER_TYPE,
19487  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_36_WIDTH },
19488  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_37_CHECKER_TYPE,
19489  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_37_WIDTH },
19490  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_38_CHECKER_TYPE,
19491  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_38_WIDTH },
19492  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_39_CHECKER_TYPE,
19493  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_39_WIDTH },
19494  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_40_CHECKER_TYPE,
19495  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_40_WIDTH },
19496  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_41_CHECKER_TYPE,
19497  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_41_WIDTH },
19498  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_42_CHECKER_TYPE,
19499  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_42_WIDTH },
19500  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_43_CHECKER_TYPE,
19501  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_43_WIDTH },
19502  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_44_CHECKER_TYPE,
19503  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_44_WIDTH },
19504  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_45_CHECKER_TYPE,
19505  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_45_WIDTH },
19506  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_46_CHECKER_TYPE,
19507  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_46_WIDTH },
19508  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_47_CHECKER_TYPE,
19509  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_47_WIDTH },
19510  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_48_CHECKER_TYPE,
19511  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_48_WIDTH },
19512  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_49_CHECKER_TYPE,
19513  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_49_WIDTH },
19514  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_50_CHECKER_TYPE,
19515  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_50_WIDTH },
19516  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_51_CHECKER_TYPE,
19517  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_51_WIDTH },
19518  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_52_CHECKER_TYPE,
19519  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_52_WIDTH },
19520  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_53_CHECKER_TYPE,
19521  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_53_WIDTH },
19522  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_54_CHECKER_TYPE,
19523  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_54_WIDTH },
19524  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_55_CHECKER_TYPE,
19525  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_55_WIDTH },
19526  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_56_CHECKER_TYPE,
19527  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_56_WIDTH },
19528  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_57_CHECKER_TYPE,
19529  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_57_WIDTH },
19530  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_58_CHECKER_TYPE,
19531  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_58_WIDTH },
19532  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_59_CHECKER_TYPE,
19533  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_59_WIDTH },
19534  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_60_CHECKER_TYPE,
19535  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_60_WIDTH },
19536  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_61_CHECKER_TYPE,
19537  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_61_WIDTH },
19538  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_62_CHECKER_TYPE,
19539  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_62_WIDTH },
19540  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_63_CHECKER_TYPE,
19541  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_63_WIDTH },
19542  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_64_CHECKER_TYPE,
19543  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_64_WIDTH },
19544  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_65_CHECKER_TYPE,
19545  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_65_WIDTH },
19546  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_66_CHECKER_TYPE,
19547  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_66_WIDTH },
19548  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_67_CHECKER_TYPE,
19549  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_67_WIDTH },
19550  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_68_CHECKER_TYPE,
19551  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_68_WIDTH },
19552  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_69_CHECKER_TYPE,
19553  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_69_WIDTH },
19554  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_70_CHECKER_TYPE,
19555  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_70_WIDTH },
19556  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_71_CHECKER_TYPE,
19557  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_71_WIDTH },
19558  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_72_CHECKER_TYPE,
19559  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_72_WIDTH },
19560  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_73_CHECKER_TYPE,
19561  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_73_WIDTH },
19562  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_74_CHECKER_TYPE,
19563  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_74_WIDTH },
19564  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_75_CHECKER_TYPE,
19565  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_75_WIDTH },
19566  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_76_CHECKER_TYPE,
19567  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_76_WIDTH },
19568  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_77_CHECKER_TYPE,
19569  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_77_WIDTH },
19570 };
19571 
19577 static const SDL_GrpChkConfig_t SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_groupEntries[SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_MAX_NUM_CHECKERS] =
19578 {
19579  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_0_CHECKER_TYPE,
19580  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_0_WIDTH },
19581  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_1_CHECKER_TYPE,
19582  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_1_WIDTH },
19583  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_2_CHECKER_TYPE,
19584  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_2_WIDTH },
19585  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_3_CHECKER_TYPE,
19586  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_3_WIDTH },
19587  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_4_CHECKER_TYPE,
19588  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_4_WIDTH },
19589  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_5_CHECKER_TYPE,
19590  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_5_WIDTH },
19591  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_6_CHECKER_TYPE,
19592  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_6_WIDTH },
19593  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_7_CHECKER_TYPE,
19594  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_7_WIDTH },
19595  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_8_CHECKER_TYPE,
19596  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_8_WIDTH },
19597  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_9_CHECKER_TYPE,
19598  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_9_WIDTH },
19599  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_10_CHECKER_TYPE,
19600  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_10_WIDTH },
19601  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_11_CHECKER_TYPE,
19602  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_11_WIDTH },
19603  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_12_CHECKER_TYPE,
19604  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_12_WIDTH },
19605  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_13_CHECKER_TYPE,
19606  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_13_WIDTH },
19607  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_14_CHECKER_TYPE,
19608  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_14_WIDTH },
19609  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_15_CHECKER_TYPE,
19610  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_15_WIDTH },
19611  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_16_CHECKER_TYPE,
19612  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_16_WIDTH },
19613  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_17_CHECKER_TYPE,
19614  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_17_WIDTH },
19615  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_18_CHECKER_TYPE,
19616  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_18_WIDTH },
19617  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_19_CHECKER_TYPE,
19618  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_19_WIDTH },
19619  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_20_CHECKER_TYPE,
19620  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_20_WIDTH },
19621  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_21_CHECKER_TYPE,
19622  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_21_WIDTH },
19623  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_22_CHECKER_TYPE,
19624  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_22_WIDTH },
19625  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_23_CHECKER_TYPE,
19626  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_23_WIDTH },
19627  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_24_CHECKER_TYPE,
19628  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_24_WIDTH },
19629  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_25_CHECKER_TYPE,
19630  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_25_WIDTH },
19631  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_26_CHECKER_TYPE,
19632  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_26_WIDTH },
19633  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_27_CHECKER_TYPE,
19634  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_27_WIDTH },
19635  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_28_CHECKER_TYPE,
19636  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_28_WIDTH },
19637  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_29_CHECKER_TYPE,
19638  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_29_WIDTH },
19639  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_30_CHECKER_TYPE,
19640  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_30_WIDTH },
19641  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_31_CHECKER_TYPE,
19642  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_31_WIDTH },
19643  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_32_CHECKER_TYPE,
19644  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_32_WIDTH },
19645 };
19646 
19652 static const SDL_GrpChkConfig_t SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_IK3VTM_N16FFC_WKUP_0_VBUSP_P2P_BRIDGE_IK3VTM_N16FFC_WKUP_0_VBUSP_BRIDGE_BUSECC_groupEntries[SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_IK3VTM_N16FFC_WKUP_0_VBUSP_P2P_BRIDGE_IK3VTM_N16FFC_WKUP_0_VBUSP_BRIDGE_BUSECC_MAX_NUM_CHECKERS] =
19653 {
19654  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_IK3VTM_N16FFC_WKUP_0_VBUSP_P2P_BRIDGE_IK3VTM_N16FFC_WKUP_0_VBUSP_BRIDGE_BUSECC_GROUP_0_CHECKER_TYPE,
19655  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_IK3VTM_N16FFC_WKUP_0_VBUSP_P2P_BRIDGE_IK3VTM_N16FFC_WKUP_0_VBUSP_BRIDGE_BUSECC_GROUP_0_WIDTH },
19656  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_IK3VTM_N16FFC_WKUP_0_VBUSP_P2P_BRIDGE_IK3VTM_N16FFC_WKUP_0_VBUSP_BRIDGE_BUSECC_GROUP_1_CHECKER_TYPE,
19657  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_IK3VTM_N16FFC_WKUP_0_VBUSP_P2P_BRIDGE_IK3VTM_N16FFC_WKUP_0_VBUSP_BRIDGE_BUSECC_GROUP_1_WIDTH },
19658  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_IK3VTM_N16FFC_WKUP_0_VBUSP_P2P_BRIDGE_IK3VTM_N16FFC_WKUP_0_VBUSP_BRIDGE_BUSECC_GROUP_2_CHECKER_TYPE,
19659  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_IK3VTM_N16FFC_WKUP_0_VBUSP_P2P_BRIDGE_IK3VTM_N16FFC_WKUP_0_VBUSP_BRIDGE_BUSECC_GROUP_2_WIDTH },
19660  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_IK3VTM_N16FFC_WKUP_0_VBUSP_P2P_BRIDGE_IK3VTM_N16FFC_WKUP_0_VBUSP_BRIDGE_BUSECC_GROUP_3_CHECKER_TYPE,
19661  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_IK3VTM_N16FFC_WKUP_0_VBUSP_P2P_BRIDGE_IK3VTM_N16FFC_WKUP_0_VBUSP_BRIDGE_BUSECC_GROUP_3_WIDTH },
19662  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_IK3VTM_N16FFC_WKUP_0_VBUSP_P2P_BRIDGE_IK3VTM_N16FFC_WKUP_0_VBUSP_BRIDGE_BUSECC_GROUP_4_CHECKER_TYPE,
19663  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_IK3VTM_N16FFC_WKUP_0_VBUSP_P2P_BRIDGE_IK3VTM_N16FFC_WKUP_0_VBUSP_BRIDGE_BUSECC_GROUP_4_WIDTH },
19664  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_IK3VTM_N16FFC_WKUP_0_VBUSP_P2P_BRIDGE_IK3VTM_N16FFC_WKUP_0_VBUSP_BRIDGE_BUSECC_GROUP_5_CHECKER_TYPE,
19665  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_IK3VTM_N16FFC_WKUP_0_VBUSP_P2P_BRIDGE_IK3VTM_N16FFC_WKUP_0_VBUSP_BRIDGE_BUSECC_GROUP_5_WIDTH },
19666  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_IK3VTM_N16FFC_WKUP_0_VBUSP_P2P_BRIDGE_IK3VTM_N16FFC_WKUP_0_VBUSP_BRIDGE_BUSECC_GROUP_6_CHECKER_TYPE,
19667  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_IK3VTM_N16FFC_WKUP_0_VBUSP_P2P_BRIDGE_IK3VTM_N16FFC_WKUP_0_VBUSP_BRIDGE_BUSECC_GROUP_6_WIDTH },
19668  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_IK3VTM_N16FFC_WKUP_0_VBUSP_P2P_BRIDGE_IK3VTM_N16FFC_WKUP_0_VBUSP_BRIDGE_BUSECC_GROUP_7_CHECKER_TYPE,
19669  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_IK3VTM_N16FFC_WKUP_0_VBUSP_P2P_BRIDGE_IK3VTM_N16FFC_WKUP_0_VBUSP_BRIDGE_BUSECC_GROUP_7_WIDTH },
19670  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_IK3VTM_N16FFC_WKUP_0_VBUSP_P2P_BRIDGE_IK3VTM_N16FFC_WKUP_0_VBUSP_BRIDGE_BUSECC_GROUP_8_CHECKER_TYPE,
19671  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_IK3VTM_N16FFC_WKUP_0_VBUSP_P2P_BRIDGE_IK3VTM_N16FFC_WKUP_0_VBUSP_BRIDGE_BUSECC_GROUP_8_WIDTH },
19672  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_IK3VTM_N16FFC_WKUP_0_VBUSP_P2P_BRIDGE_IK3VTM_N16FFC_WKUP_0_VBUSP_BRIDGE_BUSECC_GROUP_9_CHECKER_TYPE,
19673  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_IK3VTM_N16FFC_WKUP_0_VBUSP_P2P_BRIDGE_IK3VTM_N16FFC_WKUP_0_VBUSP_BRIDGE_BUSECC_GROUP_9_WIDTH },
19674  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_IK3VTM_N16FFC_WKUP_0_VBUSP_P2P_BRIDGE_IK3VTM_N16FFC_WKUP_0_VBUSP_BRIDGE_BUSECC_GROUP_10_CHECKER_TYPE,
19675  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_IK3VTM_N16FFC_WKUP_0_VBUSP_P2P_BRIDGE_IK3VTM_N16FFC_WKUP_0_VBUSP_BRIDGE_BUSECC_GROUP_10_WIDTH },
19676  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_IK3VTM_N16FFC_WKUP_0_VBUSP_P2P_BRIDGE_IK3VTM_N16FFC_WKUP_0_VBUSP_BRIDGE_BUSECC_GROUP_11_CHECKER_TYPE,
19677  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_IK3VTM_N16FFC_WKUP_0_VBUSP_P2P_BRIDGE_IK3VTM_N16FFC_WKUP_0_VBUSP_BRIDGE_BUSECC_GROUP_11_WIDTH },
19678  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_IK3VTM_N16FFC_WKUP_0_VBUSP_P2P_BRIDGE_IK3VTM_N16FFC_WKUP_0_VBUSP_BRIDGE_BUSECC_GROUP_12_CHECKER_TYPE,
19679  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_IK3VTM_N16FFC_WKUP_0_VBUSP_P2P_BRIDGE_IK3VTM_N16FFC_WKUP_0_VBUSP_BRIDGE_BUSECC_GROUP_12_WIDTH },
19680 };
19681 
19687 static const SDL_GrpChkConfig_t SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_groupEntries[SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS] =
19688 {
19689  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
19690  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
19691  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
19692  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
19693  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
19694  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
19695  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
19696  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
19697  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
19698  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
19699  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_5_CHECKER_TYPE,
19700  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_5_WIDTH },
19701  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_6_CHECKER_TYPE,
19702  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_6_WIDTH },
19703  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_7_CHECKER_TYPE,
19704  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_7_WIDTH },
19705  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_8_CHECKER_TYPE,
19706  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_8_WIDTH },
19707  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_9_CHECKER_TYPE,
19708  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_9_WIDTH },
19709  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_10_CHECKER_TYPE,
19710  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_10_WIDTH },
19711  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_11_CHECKER_TYPE,
19712  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_11_WIDTH },
19713  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_12_CHECKER_TYPE,
19714  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_12_WIDTH },
19715  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_13_CHECKER_TYPE,
19716  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_13_WIDTH },
19717  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_14_CHECKER_TYPE,
19718  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_14_WIDTH },
19719  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_15_CHECKER_TYPE,
19720  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_15_WIDTH },
19721  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_16_CHECKER_TYPE,
19722  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_16_WIDTH },
19723  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_17_CHECKER_TYPE,
19724  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_17_WIDTH },
19725  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_18_CHECKER_TYPE,
19726  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_18_WIDTH },
19727  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_19_CHECKER_TYPE,
19728  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_19_WIDTH },
19729  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_20_CHECKER_TYPE,
19730  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_20_WIDTH },
19731  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_21_CHECKER_TYPE,
19732  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_21_WIDTH },
19733  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_22_CHECKER_TYPE,
19734  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_22_WIDTH },
19735  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_23_CHECKER_TYPE,
19736  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_23_WIDTH },
19737  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_24_CHECKER_TYPE,
19738  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_24_WIDTH },
19739  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_25_CHECKER_TYPE,
19740  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_25_WIDTH },
19741  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_26_CHECKER_TYPE,
19742  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_26_WIDTH },
19743  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_27_CHECKER_TYPE,
19744  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_27_WIDTH },
19745  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_28_CHECKER_TYPE,
19746  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_28_WIDTH },
19747  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_29_CHECKER_TYPE,
19748  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_29_WIDTH },
19749  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_30_CHECKER_TYPE,
19750  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_30_WIDTH },
19751  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_31_CHECKER_TYPE,
19752  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_31_WIDTH },
19753  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_32_CHECKER_TYPE,
19754  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_32_WIDTH },
19755  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_33_CHECKER_TYPE,
19756  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_33_WIDTH },
19757  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_34_CHECKER_TYPE,
19758  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_34_WIDTH },
19759  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_35_CHECKER_TYPE,
19760  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_35_WIDTH },
19761  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_36_CHECKER_TYPE,
19762  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_36_WIDTH },
19763  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_37_CHECKER_TYPE,
19764  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_37_WIDTH },
19765  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_38_CHECKER_TYPE,
19766  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_38_WIDTH },
19767  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_39_CHECKER_TYPE,
19768  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_39_WIDTH },
19769  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_40_CHECKER_TYPE,
19770  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_40_WIDTH },
19771  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_41_CHECKER_TYPE,
19772  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_41_WIDTH },
19773  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_42_CHECKER_TYPE,
19774  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_42_WIDTH },
19775  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_43_CHECKER_TYPE,
19776  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_43_WIDTH },
19777  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_44_CHECKER_TYPE,
19778  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_44_WIDTH },
19779  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_45_CHECKER_TYPE,
19780  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_45_WIDTH },
19781  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_46_CHECKER_TYPE,
19782  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_46_WIDTH },
19783  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_47_CHECKER_TYPE,
19784  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_47_WIDTH },
19785  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_48_CHECKER_TYPE,
19786  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_48_WIDTH },
19787  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_49_CHECKER_TYPE,
19788  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_49_WIDTH },
19789  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_50_CHECKER_TYPE,
19790  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_50_WIDTH },
19791  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_51_CHECKER_TYPE,
19792  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_51_WIDTH },
19793  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_52_CHECKER_TYPE,
19794  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_52_WIDTH },
19795  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_53_CHECKER_TYPE,
19796  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_53_WIDTH },
19797  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_54_CHECKER_TYPE,
19798  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_54_WIDTH },
19799  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_55_CHECKER_TYPE,
19800  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_55_WIDTH },
19801  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_56_CHECKER_TYPE,
19802  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_56_WIDTH },
19803  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_57_CHECKER_TYPE,
19804  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_57_WIDTH },
19805  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_58_CHECKER_TYPE,
19806  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_58_WIDTH },
19807  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_59_CHECKER_TYPE,
19808  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_59_WIDTH },
19809  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_60_CHECKER_TYPE,
19810  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_60_WIDTH },
19811  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_61_CHECKER_TYPE,
19812  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_61_WIDTH },
19813  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_62_CHECKER_TYPE,
19814  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_62_WIDTH },
19815  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_63_CHECKER_TYPE,
19816  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_63_WIDTH },
19817  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_64_CHECKER_TYPE,
19818  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_64_WIDTH },
19819  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_65_CHECKER_TYPE,
19820  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_65_WIDTH },
19821  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_66_CHECKER_TYPE,
19822  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_66_WIDTH },
19823  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_67_CHECKER_TYPE,
19824  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_67_WIDTH },
19825  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_68_CHECKER_TYPE,
19826  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_68_WIDTH },
19827  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_69_CHECKER_TYPE,
19828  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_69_WIDTH },
19829  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_70_CHECKER_TYPE,
19830  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_70_WIDTH },
19831  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_71_CHECKER_TYPE,
19832  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_71_WIDTH },
19833  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_72_CHECKER_TYPE,
19834  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_72_WIDTH },
19835 };
19836 
19842 static const SDL_GrpChkConfig_t SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS] =
19843 {
19844  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
19845  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
19846  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
19847  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
19848  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
19849  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
19850  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
19851  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
19852  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
19853  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
19854  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_5_CHECKER_TYPE,
19855  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_5_WIDTH },
19856  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_6_CHECKER_TYPE,
19857  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_6_WIDTH },
19858  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_7_CHECKER_TYPE,
19859  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_7_WIDTH },
19860  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_8_CHECKER_TYPE,
19861  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_8_WIDTH },
19862  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_9_CHECKER_TYPE,
19863  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_9_WIDTH },
19864  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_10_CHECKER_TYPE,
19865  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_10_WIDTH },
19866  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_11_CHECKER_TYPE,
19867  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_11_WIDTH },
19868  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_12_CHECKER_TYPE,
19869  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_12_WIDTH },
19870  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_13_CHECKER_TYPE,
19871  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_13_WIDTH },
19872  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_14_CHECKER_TYPE,
19873  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_14_WIDTH },
19874  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_15_CHECKER_TYPE,
19875  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_15_WIDTH },
19876  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_16_CHECKER_TYPE,
19877  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_16_WIDTH },
19878  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_17_CHECKER_TYPE,
19879  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_17_WIDTH },
19880  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_18_CHECKER_TYPE,
19881  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_18_WIDTH },
19882  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_19_CHECKER_TYPE,
19883  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_19_WIDTH },
19884  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_20_CHECKER_TYPE,
19885  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_20_WIDTH },
19886  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_21_CHECKER_TYPE,
19887  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_21_WIDTH },
19888  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_22_CHECKER_TYPE,
19889  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_22_WIDTH },
19890  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_23_CHECKER_TYPE,
19891  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_23_WIDTH },
19892  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_24_CHECKER_TYPE,
19893  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_24_WIDTH },
19894  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_25_CHECKER_TYPE,
19895  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_25_WIDTH },
19896  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_26_CHECKER_TYPE,
19897  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_26_WIDTH },
19898  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_27_CHECKER_TYPE,
19899  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_27_WIDTH },
19900  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_28_CHECKER_TYPE,
19901  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_28_WIDTH },
19902  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_29_CHECKER_TYPE,
19903  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_29_WIDTH },
19904  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_30_CHECKER_TYPE,
19905  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_30_WIDTH },
19906  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_31_CHECKER_TYPE,
19907  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_31_WIDTH },
19908  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_32_CHECKER_TYPE,
19909  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_32_WIDTH },
19910  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_33_CHECKER_TYPE,
19911  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_33_WIDTH },
19912  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_34_CHECKER_TYPE,
19913  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_34_WIDTH },
19914  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_35_CHECKER_TYPE,
19915  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_35_WIDTH },
19916  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_36_CHECKER_TYPE,
19917  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_36_WIDTH },
19918  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_37_CHECKER_TYPE,
19919  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_37_WIDTH },
19920  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_38_CHECKER_TYPE,
19921  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_38_WIDTH },
19922  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_39_CHECKER_TYPE,
19923  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_39_WIDTH },
19924  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_40_CHECKER_TYPE,
19925  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_40_WIDTH },
19926  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_41_CHECKER_TYPE,
19927  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_41_WIDTH },
19928  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_42_CHECKER_TYPE,
19929  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_42_WIDTH },
19930  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_43_CHECKER_TYPE,
19931  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_43_WIDTH },
19932  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_44_CHECKER_TYPE,
19933  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_44_WIDTH },
19934  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_45_CHECKER_TYPE,
19935  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_45_WIDTH },
19936  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_46_CHECKER_TYPE,
19937  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_46_WIDTH },
19938  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_47_CHECKER_TYPE,
19939  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_47_WIDTH },
19940  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_48_CHECKER_TYPE,
19941  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_48_WIDTH },
19942  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_49_CHECKER_TYPE,
19943  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_49_WIDTH },
19944  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_50_CHECKER_TYPE,
19945  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_50_WIDTH },
19946  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_51_CHECKER_TYPE,
19947  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_51_WIDTH },
19948  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_52_CHECKER_TYPE,
19949  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_52_WIDTH },
19950  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_53_CHECKER_TYPE,
19951  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_53_WIDTH },
19952  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_54_CHECKER_TYPE,
19953  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_54_WIDTH },
19954  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_55_CHECKER_TYPE,
19955  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_55_WIDTH },
19956  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_56_CHECKER_TYPE,
19957  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_56_WIDTH },
19958  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_57_CHECKER_TYPE,
19959  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_57_WIDTH },
19960  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_58_CHECKER_TYPE,
19961  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_58_WIDTH },
19962  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_59_CHECKER_TYPE,
19963  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_59_WIDTH },
19964  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_60_CHECKER_TYPE,
19965  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_60_WIDTH },
19966  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_61_CHECKER_TYPE,
19967  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_61_WIDTH },
19968  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_62_CHECKER_TYPE,
19969  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_62_WIDTH },
19970  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_63_CHECKER_TYPE,
19971  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_63_WIDTH },
19972  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_64_CHECKER_TYPE,
19973  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_64_WIDTH },
19974  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_65_CHECKER_TYPE,
19975  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_65_WIDTH },
19976  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_66_CHECKER_TYPE,
19977  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_66_WIDTH },
19978  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_67_CHECKER_TYPE,
19979  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_67_WIDTH },
19980  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_68_CHECKER_TYPE,
19981  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_68_WIDTH },
19982  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_69_CHECKER_TYPE,
19983  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_69_WIDTH },
19984  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_70_CHECKER_TYPE,
19985  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_70_WIDTH },
19986  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_71_CHECKER_TYPE,
19987  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_71_WIDTH },
19988 };
19989 
19995 static const SDL_GrpChkConfig_t SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISAM62A_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM62A_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_DST_BUSECC_groupEntries[SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISAM62A_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM62A_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS] =
19996 {
19997  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISAM62A_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM62A_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_DST_BUSECC_GROUP_0_CHECKER_TYPE,
19998  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISAM62A_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM62A_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_DST_BUSECC_GROUP_0_WIDTH },
19999  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISAM62A_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM62A_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_DST_BUSECC_GROUP_1_CHECKER_TYPE,
20000  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISAM62A_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM62A_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_DST_BUSECC_GROUP_1_WIDTH },
20001  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISAM62A_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM62A_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_DST_BUSECC_GROUP_2_CHECKER_TYPE,
20002  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISAM62A_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM62A_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_DST_BUSECC_GROUP_2_WIDTH },
20003  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISAM62A_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM62A_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_DST_BUSECC_GROUP_3_CHECKER_TYPE,
20004  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISAM62A_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM62A_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_DST_BUSECC_GROUP_3_WIDTH },
20005  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISAM62A_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM62A_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_DST_BUSECC_GROUP_4_CHECKER_TYPE,
20006  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISAM62A_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM62A_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_DST_BUSECC_GROUP_4_WIDTH },
20007  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISAM62A_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM62A_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_DST_BUSECC_GROUP_5_CHECKER_TYPE,
20008  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISAM62A_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM62A_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_DST_BUSECC_GROUP_5_WIDTH },
20009  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISAM62A_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM62A_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_DST_BUSECC_GROUP_6_CHECKER_TYPE,
20010  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISAM62A_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM62A_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_DST_BUSECC_GROUP_6_WIDTH },
20011 };
20012 
20018 static const SDL_GrpChkConfig_t SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISAM62A_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM62A_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_SRC_BUSECC_groupEntries[SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISAM62A_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM62A_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS] =
20019 {
20020  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISAM62A_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM62A_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_SRC_BUSECC_GROUP_0_CHECKER_TYPE,
20021  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISAM62A_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM62A_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_SRC_BUSECC_GROUP_0_WIDTH },
20022  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISAM62A_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM62A_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_SRC_BUSECC_GROUP_1_CHECKER_TYPE,
20023  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISAM62A_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM62A_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_SRC_BUSECC_GROUP_1_WIDTH },
20024  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISAM62A_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM62A_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_SRC_BUSECC_GROUP_2_CHECKER_TYPE,
20025  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISAM62A_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM62A_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_SRC_BUSECC_GROUP_2_WIDTH },
20026  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISAM62A_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM62A_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_SRC_BUSECC_GROUP_3_CHECKER_TYPE,
20027  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISAM62A_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM62A_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_SRC_BUSECC_GROUP_3_WIDTH },
20028  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISAM62A_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM62A_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_SRC_BUSECC_GROUP_4_CHECKER_TYPE,
20029  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISAM62A_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM62A_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_SRC_BUSECC_GROUP_4_WIDTH },
20030  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISAM62A_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM62A_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_SRC_BUSECC_GROUP_5_CHECKER_TYPE,
20031  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISAM62A_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM62A_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_SRC_BUSECC_GROUP_5_WIDTH },
20032  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISAM62A_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM62A_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_SRC_BUSECC_GROUP_6_CHECKER_TYPE,
20033  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISAM62A_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM62A_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_SRC_BUSECC_GROUP_6_WIDTH },
20034  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISAM62A_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM62A_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_SRC_BUSECC_GROUP_7_CHECKER_TYPE,
20035  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISAM62A_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM62A_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_SRC_BUSECC_GROUP_7_WIDTH },
20036  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISAM62A_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM62A_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_SRC_BUSECC_GROUP_8_CHECKER_TYPE,
20037  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISAM62A_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM62A_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_SRC_BUSECC_GROUP_8_WIDTH },
20038  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISAM62A_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM62A_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_SRC_BUSECC_GROUP_9_CHECKER_TYPE,
20039  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISAM62A_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM62A_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_SRC_BUSECC_GROUP_9_WIDTH },
20040  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISAM62A_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM62A_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_SRC_BUSECC_GROUP_10_CHECKER_TYPE,
20041  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISAM62A_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM62A_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_SRC_BUSECC_GROUP_10_WIDTH },
20042  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISAM62A_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM62A_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_SRC_BUSECC_GROUP_11_CHECKER_TYPE,
20043  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISAM62A_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM62A_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_SRC_BUSECC_GROUP_11_WIDTH },
20044  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISAM62A_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM62A_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_SRC_BUSECC_GROUP_12_CHECKER_TYPE,
20045  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISAM62A_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM62A_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_SRC_BUSECC_GROUP_12_WIDTH },
20046  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISAM62A_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM62A_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_SRC_BUSECC_GROUP_13_CHECKER_TYPE,
20047  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISAM62A_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM62A_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_SRC_BUSECC_GROUP_13_WIDTH },
20048  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISAM62A_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM62A_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_SRC_BUSECC_GROUP_14_CHECKER_TYPE,
20049  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISAM62A_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM62A_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_SRC_BUSECC_GROUP_14_WIDTH },
20050  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISAM62A_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM62A_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_SRC_BUSECC_GROUP_15_CHECKER_TYPE,
20051  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISAM62A_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM62A_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_SRC_BUSECC_GROUP_15_WIDTH },
20052  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISAM62A_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM62A_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_SRC_BUSECC_GROUP_16_CHECKER_TYPE,
20053  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISAM62A_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM62A_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_SRC_BUSECC_GROUP_16_WIDTH },
20054 };
20055 
20061 static const SDL_GrpChkConfig_t SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISAM62A_DM_MCU_ECC_AGGR_WKUP_1_CFG_P2P_BRIDGE_ISAM62A_DM_MCU_ECC_AGGR_WKUP_1_CFG_BRIDGE_SRC_BUSECC_groupEntries[SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISAM62A_DM_MCU_ECC_AGGR_WKUP_1_CFG_P2P_BRIDGE_ISAM62A_DM_MCU_ECC_AGGR_WKUP_1_CFG_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS] =
20062 {
20063  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISAM62A_DM_MCU_ECC_AGGR_WKUP_1_CFG_P2P_BRIDGE_ISAM62A_DM_MCU_ECC_AGGR_WKUP_1_CFG_BRIDGE_SRC_BUSECC_GROUP_0_CHECKER_TYPE,
20064  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISAM62A_DM_MCU_ECC_AGGR_WKUP_1_CFG_P2P_BRIDGE_ISAM62A_DM_MCU_ECC_AGGR_WKUP_1_CFG_BRIDGE_SRC_BUSECC_GROUP_0_WIDTH },
20065  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISAM62A_DM_MCU_ECC_AGGR_WKUP_1_CFG_P2P_BRIDGE_ISAM62A_DM_MCU_ECC_AGGR_WKUP_1_CFG_BRIDGE_SRC_BUSECC_GROUP_1_CHECKER_TYPE,
20066  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISAM62A_DM_MCU_ECC_AGGR_WKUP_1_CFG_P2P_BRIDGE_ISAM62A_DM_MCU_ECC_AGGR_WKUP_1_CFG_BRIDGE_SRC_BUSECC_GROUP_1_WIDTH },
20067  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISAM62A_DM_MCU_ECC_AGGR_WKUP_1_CFG_P2P_BRIDGE_ISAM62A_DM_MCU_ECC_AGGR_WKUP_1_CFG_BRIDGE_SRC_BUSECC_GROUP_2_CHECKER_TYPE,
20068  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISAM62A_DM_MCU_ECC_AGGR_WKUP_1_CFG_P2P_BRIDGE_ISAM62A_DM_MCU_ECC_AGGR_WKUP_1_CFG_BRIDGE_SRC_BUSECC_GROUP_2_WIDTH },
20069  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISAM62A_DM_MCU_ECC_AGGR_WKUP_1_CFG_P2P_BRIDGE_ISAM62A_DM_MCU_ECC_AGGR_WKUP_1_CFG_BRIDGE_SRC_BUSECC_GROUP_3_CHECKER_TYPE,
20070  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISAM62A_DM_MCU_ECC_AGGR_WKUP_1_CFG_P2P_BRIDGE_ISAM62A_DM_MCU_ECC_AGGR_WKUP_1_CFG_BRIDGE_SRC_BUSECC_GROUP_3_WIDTH },
20071  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISAM62A_DM_MCU_ECC_AGGR_WKUP_1_CFG_P2P_BRIDGE_ISAM62A_DM_MCU_ECC_AGGR_WKUP_1_CFG_BRIDGE_SRC_BUSECC_GROUP_4_CHECKER_TYPE,
20072  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISAM62A_DM_MCU_ECC_AGGR_WKUP_1_CFG_P2P_BRIDGE_ISAM62A_DM_MCU_ECC_AGGR_WKUP_1_CFG_BRIDGE_SRC_BUSECC_GROUP_4_WIDTH },
20073  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISAM62A_DM_MCU_ECC_AGGR_WKUP_1_CFG_P2P_BRIDGE_ISAM62A_DM_MCU_ECC_AGGR_WKUP_1_CFG_BRIDGE_SRC_BUSECC_GROUP_5_CHECKER_TYPE,
20074  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISAM62A_DM_MCU_ECC_AGGR_WKUP_1_CFG_P2P_BRIDGE_ISAM62A_DM_MCU_ECC_AGGR_WKUP_1_CFG_BRIDGE_SRC_BUSECC_GROUP_5_WIDTH },
20075  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISAM62A_DM_MCU_ECC_AGGR_WKUP_1_CFG_P2P_BRIDGE_ISAM62A_DM_MCU_ECC_AGGR_WKUP_1_CFG_BRIDGE_SRC_BUSECC_GROUP_6_CHECKER_TYPE,
20076  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISAM62A_DM_MCU_ECC_AGGR_WKUP_1_CFG_P2P_BRIDGE_ISAM62A_DM_MCU_ECC_AGGR_WKUP_1_CFG_BRIDGE_SRC_BUSECC_GROUP_6_WIDTH },
20077  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISAM62A_DM_MCU_ECC_AGGR_WKUP_1_CFG_P2P_BRIDGE_ISAM62A_DM_MCU_ECC_AGGR_WKUP_1_CFG_BRIDGE_SRC_BUSECC_GROUP_7_CHECKER_TYPE,
20078  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISAM62A_DM_MCU_ECC_AGGR_WKUP_1_CFG_P2P_BRIDGE_ISAM62A_DM_MCU_ECC_AGGR_WKUP_1_CFG_BRIDGE_SRC_BUSECC_GROUP_7_WIDTH },
20079  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISAM62A_DM_MCU_ECC_AGGR_WKUP_1_CFG_P2P_BRIDGE_ISAM62A_DM_MCU_ECC_AGGR_WKUP_1_CFG_BRIDGE_SRC_BUSECC_GROUP_8_CHECKER_TYPE,
20080  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISAM62A_DM_MCU_ECC_AGGR_WKUP_1_CFG_P2P_BRIDGE_ISAM62A_DM_MCU_ECC_AGGR_WKUP_1_CFG_BRIDGE_SRC_BUSECC_GROUP_8_WIDTH },
20081  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISAM62A_DM_MCU_ECC_AGGR_WKUP_1_CFG_P2P_BRIDGE_ISAM62A_DM_MCU_ECC_AGGR_WKUP_1_CFG_BRIDGE_SRC_BUSECC_GROUP_9_CHECKER_TYPE,
20082  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISAM62A_DM_MCU_ECC_AGGR_WKUP_1_CFG_P2P_BRIDGE_ISAM62A_DM_MCU_ECC_AGGR_WKUP_1_CFG_BRIDGE_SRC_BUSECC_GROUP_9_WIDTH },
20083  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISAM62A_DM_MCU_ECC_AGGR_WKUP_1_CFG_P2P_BRIDGE_ISAM62A_DM_MCU_ECC_AGGR_WKUP_1_CFG_BRIDGE_SRC_BUSECC_GROUP_10_CHECKER_TYPE,
20084  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISAM62A_DM_MCU_ECC_AGGR_WKUP_1_CFG_P2P_BRIDGE_ISAM62A_DM_MCU_ECC_AGGR_WKUP_1_CFG_BRIDGE_SRC_BUSECC_GROUP_10_WIDTH },
20085  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISAM62A_DM_MCU_ECC_AGGR_WKUP_1_CFG_P2P_BRIDGE_ISAM62A_DM_MCU_ECC_AGGR_WKUP_1_CFG_BRIDGE_SRC_BUSECC_GROUP_11_CHECKER_TYPE,
20086  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISAM62A_DM_MCU_ECC_AGGR_WKUP_1_CFG_P2P_BRIDGE_ISAM62A_DM_MCU_ECC_AGGR_WKUP_1_CFG_BRIDGE_SRC_BUSECC_GROUP_11_WIDTH },
20087  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISAM62A_DM_MCU_ECC_AGGR_WKUP_1_CFG_P2P_BRIDGE_ISAM62A_DM_MCU_ECC_AGGR_WKUP_1_CFG_BRIDGE_SRC_BUSECC_GROUP_12_CHECKER_TYPE,
20088  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISAM62A_DM_MCU_ECC_AGGR_WKUP_1_CFG_P2P_BRIDGE_ISAM62A_DM_MCU_ECC_AGGR_WKUP_1_CFG_BRIDGE_SRC_BUSECC_GROUP_12_WIDTH },
20089  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISAM62A_DM_MCU_ECC_AGGR_WKUP_1_CFG_P2P_BRIDGE_ISAM62A_DM_MCU_ECC_AGGR_WKUP_1_CFG_BRIDGE_SRC_BUSECC_GROUP_13_CHECKER_TYPE,
20090  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISAM62A_DM_MCU_ECC_AGGR_WKUP_1_CFG_P2P_BRIDGE_ISAM62A_DM_MCU_ECC_AGGR_WKUP_1_CFG_BRIDGE_SRC_BUSECC_GROUP_13_WIDTH },
20091  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISAM62A_DM_MCU_ECC_AGGR_WKUP_1_CFG_P2P_BRIDGE_ISAM62A_DM_MCU_ECC_AGGR_WKUP_1_CFG_BRIDGE_SRC_BUSECC_GROUP_14_CHECKER_TYPE,
20092  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISAM62A_DM_MCU_ECC_AGGR_WKUP_1_CFG_P2P_BRIDGE_ISAM62A_DM_MCU_ECC_AGGR_WKUP_1_CFG_BRIDGE_SRC_BUSECC_GROUP_14_WIDTH },
20093  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISAM62A_DM_MCU_ECC_AGGR_WKUP_1_CFG_P2P_BRIDGE_ISAM62A_DM_MCU_ECC_AGGR_WKUP_1_CFG_BRIDGE_SRC_BUSECC_GROUP_15_CHECKER_TYPE,
20094  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISAM62A_DM_MCU_ECC_AGGR_WKUP_1_CFG_P2P_BRIDGE_ISAM62A_DM_MCU_ECC_AGGR_WKUP_1_CFG_BRIDGE_SRC_BUSECC_GROUP_15_WIDTH },
20095  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISAM62A_DM_MCU_ECC_AGGR_WKUP_1_CFG_P2P_BRIDGE_ISAM62A_DM_MCU_ECC_AGGR_WKUP_1_CFG_BRIDGE_SRC_BUSECC_GROUP_16_CHECKER_TYPE,
20096  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISAM62A_DM_MCU_ECC_AGGR_WKUP_1_CFG_P2P_BRIDGE_ISAM62A_DM_MCU_ECC_AGGR_WKUP_1_CFG_BRIDGE_SRC_BUSECC_GROUP_16_WIDTH },
20097 };
20098 
20104 static const SDL_GrpChkConfig_t SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS] =
20105 {
20106  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
20107  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
20108  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
20109  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
20110  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
20111  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
20112  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
20113  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
20114  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
20115  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
20116  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_5_CHECKER_TYPE,
20117  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_5_WIDTH },
20118  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_6_CHECKER_TYPE,
20119  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_6_WIDTH },
20120  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_7_CHECKER_TYPE,
20121  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_7_WIDTH },
20122  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_8_CHECKER_TYPE,
20123  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_8_WIDTH },
20124  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_9_CHECKER_TYPE,
20125  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_9_WIDTH },
20126  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_10_CHECKER_TYPE,
20127  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_10_WIDTH },
20128  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_11_CHECKER_TYPE,
20129  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_11_WIDTH },
20130  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_12_CHECKER_TYPE,
20131  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_12_WIDTH },
20132  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_13_CHECKER_TYPE,
20133  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_13_WIDTH },
20134  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_14_CHECKER_TYPE,
20135  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_14_WIDTH },
20136  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_15_CHECKER_TYPE,
20137  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_15_WIDTH },
20138  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_16_CHECKER_TYPE,
20139  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_16_WIDTH },
20140  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_17_CHECKER_TYPE,
20141  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_17_WIDTH },
20142  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_18_CHECKER_TYPE,
20143  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_18_WIDTH },
20144  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_19_CHECKER_TYPE,
20145  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_19_WIDTH },
20146  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_20_CHECKER_TYPE,
20147  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_20_WIDTH },
20148  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_21_CHECKER_TYPE,
20149  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_21_WIDTH },
20150  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_22_CHECKER_TYPE,
20151  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_22_WIDTH },
20152  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_23_CHECKER_TYPE,
20153  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_23_WIDTH },
20154  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_24_CHECKER_TYPE,
20155  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_24_WIDTH },
20156  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_25_CHECKER_TYPE,
20157  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_25_WIDTH },
20158  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_26_CHECKER_TYPE,
20159  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_26_WIDTH },
20160  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_27_CHECKER_TYPE,
20161  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_27_WIDTH },
20162  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_28_CHECKER_TYPE,
20163  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_28_WIDTH },
20164  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_29_CHECKER_TYPE,
20165  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_29_WIDTH },
20166  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_30_CHECKER_TYPE,
20167  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_30_WIDTH },
20168  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_31_CHECKER_TYPE,
20169  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_31_WIDTH },
20170  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_32_CHECKER_TYPE,
20171  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_32_WIDTH },
20172  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_33_CHECKER_TYPE,
20173  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_33_WIDTH },
20174  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_34_CHECKER_TYPE,
20175  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_34_WIDTH },
20176  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_35_CHECKER_TYPE,
20177  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_35_WIDTH },
20178  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_36_CHECKER_TYPE,
20179  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_36_WIDTH },
20180  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_37_CHECKER_TYPE,
20181  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_37_WIDTH },
20182  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_38_CHECKER_TYPE,
20183  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_38_WIDTH },
20184  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_39_CHECKER_TYPE,
20185  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_39_WIDTH },
20186  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_40_CHECKER_TYPE,
20187  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_40_WIDTH },
20188  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_41_CHECKER_TYPE,
20189  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_41_WIDTH },
20190  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_42_CHECKER_TYPE,
20191  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_42_WIDTH },
20192  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_43_CHECKER_TYPE,
20193  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_43_WIDTH },
20194  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_44_CHECKER_TYPE,
20195  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_44_WIDTH },
20196  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_45_CHECKER_TYPE,
20197  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_45_WIDTH },
20198  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_46_CHECKER_TYPE,
20199  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_46_WIDTH },
20200  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_47_CHECKER_TYPE,
20201  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_47_WIDTH },
20202  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_48_CHECKER_TYPE,
20203  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_48_WIDTH },
20204  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_49_CHECKER_TYPE,
20205  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_49_WIDTH },
20206  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_50_CHECKER_TYPE,
20207  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_50_WIDTH },
20208  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_51_CHECKER_TYPE,
20209  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_51_WIDTH },
20210  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_52_CHECKER_TYPE,
20211  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_52_WIDTH },
20212  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_53_CHECKER_TYPE,
20213  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_53_WIDTH },
20214  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_54_CHECKER_TYPE,
20215  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_54_WIDTH },
20216  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_55_CHECKER_TYPE,
20217  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_55_WIDTH },
20218  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_56_CHECKER_TYPE,
20219  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_56_WIDTH },
20220  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_57_CHECKER_TYPE,
20221  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_57_WIDTH },
20222  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_58_CHECKER_TYPE,
20223  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_58_WIDTH },
20224  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_59_CHECKER_TYPE,
20225  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_59_WIDTH },
20226  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_60_CHECKER_TYPE,
20227  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_60_WIDTH },
20228  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_61_CHECKER_TYPE,
20229  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_61_WIDTH },
20230  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_62_CHECKER_TYPE,
20231  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_62_WIDTH },
20232  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_63_CHECKER_TYPE,
20233  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_63_WIDTH },
20234  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_64_CHECKER_TYPE,
20235  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_64_WIDTH },
20236  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_65_CHECKER_TYPE,
20237  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_65_WIDTH },
20238  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_66_CHECKER_TYPE,
20239  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_66_WIDTH },
20240  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_67_CHECKER_TYPE,
20241  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_67_WIDTH },
20242  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_68_CHECKER_TYPE,
20243  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_68_WIDTH },
20244  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_69_CHECKER_TYPE,
20245  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_69_WIDTH },
20246 };
20247 
20253 static const SDL_GrpChkConfig_t SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS] =
20254 {
20255  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
20256  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
20257  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
20258  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
20259  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
20260  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
20261  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
20262  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
20263  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
20264  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
20265  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_5_CHECKER_TYPE,
20266  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_5_WIDTH },
20267  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_6_CHECKER_TYPE,
20268  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_6_WIDTH },
20269  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_7_CHECKER_TYPE,
20270  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_7_WIDTH },
20271  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_8_CHECKER_TYPE,
20272  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_8_WIDTH },
20273  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_9_CHECKER_TYPE,
20274  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_9_WIDTH },
20275  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_10_CHECKER_TYPE,
20276  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_10_WIDTH },
20277  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_11_CHECKER_TYPE,
20278  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_11_WIDTH },
20279  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_12_CHECKER_TYPE,
20280  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_12_WIDTH },
20281  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_13_CHECKER_TYPE,
20282  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_13_WIDTH },
20283  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_14_CHECKER_TYPE,
20284  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_14_WIDTH },
20285  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_15_CHECKER_TYPE,
20286  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_15_WIDTH },
20287  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_16_CHECKER_TYPE,
20288  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_16_WIDTH },
20289  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_17_CHECKER_TYPE,
20290  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_17_WIDTH },
20291  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_18_CHECKER_TYPE,
20292  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_18_WIDTH },
20293  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_19_CHECKER_TYPE,
20294  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_19_WIDTH },
20295  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_20_CHECKER_TYPE,
20296  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_20_WIDTH },
20297  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_21_CHECKER_TYPE,
20298  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_21_WIDTH },
20299  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_22_CHECKER_TYPE,
20300  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_22_WIDTH },
20301  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_23_CHECKER_TYPE,
20302  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_23_WIDTH },
20303  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_24_CHECKER_TYPE,
20304  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_24_WIDTH },
20305  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_25_CHECKER_TYPE,
20306  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_25_WIDTH },
20307  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_26_CHECKER_TYPE,
20308  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_26_WIDTH },
20309  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_27_CHECKER_TYPE,
20310  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_27_WIDTH },
20311  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_28_CHECKER_TYPE,
20312  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_28_WIDTH },
20313  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_29_CHECKER_TYPE,
20314  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_29_WIDTH },
20315  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_30_CHECKER_TYPE,
20316  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_30_WIDTH },
20317  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_31_CHECKER_TYPE,
20318  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_31_WIDTH },
20319  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_32_CHECKER_TYPE,
20320  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_32_WIDTH },
20321  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_33_CHECKER_TYPE,
20322  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_33_WIDTH },
20323  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_34_CHECKER_TYPE,
20324  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_34_WIDTH },
20325  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_35_CHECKER_TYPE,
20326  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_35_WIDTH },
20327  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_36_CHECKER_TYPE,
20328  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_36_WIDTH },
20329  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_37_CHECKER_TYPE,
20330  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_37_WIDTH },
20331  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_38_CHECKER_TYPE,
20332  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_38_WIDTH },
20333  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_39_CHECKER_TYPE,
20334  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_39_WIDTH },
20335  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_40_CHECKER_TYPE,
20336  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_40_WIDTH },
20337  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_41_CHECKER_TYPE,
20338  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_41_WIDTH },
20339  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_42_CHECKER_TYPE,
20340  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_42_WIDTH },
20341  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_43_CHECKER_TYPE,
20342  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_43_WIDTH },
20343  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_44_CHECKER_TYPE,
20344  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_44_WIDTH },
20345  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_45_CHECKER_TYPE,
20346  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_45_WIDTH },
20347  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_46_CHECKER_TYPE,
20348  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_46_WIDTH },
20349  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_47_CHECKER_TYPE,
20350  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_47_WIDTH },
20351  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_48_CHECKER_TYPE,
20352  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_48_WIDTH },
20353  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_49_CHECKER_TYPE,
20354  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_49_WIDTH },
20355  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_50_CHECKER_TYPE,
20356  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_50_WIDTH },
20357  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_51_CHECKER_TYPE,
20358  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_51_WIDTH },
20359  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_52_CHECKER_TYPE,
20360  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_52_WIDTH },
20361  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_53_CHECKER_TYPE,
20362  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_53_WIDTH },
20363  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_54_CHECKER_TYPE,
20364  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_54_WIDTH },
20365  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_55_CHECKER_TYPE,
20366  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_55_WIDTH },
20367  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_56_CHECKER_TYPE,
20368  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_56_WIDTH },
20369  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_57_CHECKER_TYPE,
20370  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_57_WIDTH },
20371  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_58_CHECKER_TYPE,
20372  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_58_WIDTH },
20373  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_59_CHECKER_TYPE,
20374  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_59_WIDTH },
20375  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_60_CHECKER_TYPE,
20376  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_60_WIDTH },
20377  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_61_CHECKER_TYPE,
20378  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_61_WIDTH },
20379  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_62_CHECKER_TYPE,
20380  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_62_WIDTH },
20381  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_63_CHECKER_TYPE,
20382  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_63_WIDTH },
20383  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_64_CHECKER_TYPE,
20384  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_64_WIDTH },
20385  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_65_CHECKER_TYPE,
20386  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_65_WIDTH },
20387 };
20388 
20394 static const SDL_GrpChkConfig_t SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_SAM62A_DM_DM_ECC_AGGR_EDC_CTRL_groupEntries[SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_SAM62A_DM_DM_ECC_AGGR_EDC_CTRL_MAX_NUM_CHECKERS] =
20395 {
20396  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_SAM62A_DM_DM_ECC_AGGR_EDC_CTRL_GROUP_0_CHECKER_TYPE,
20397  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_SAM62A_DM_DM_ECC_AGGR_EDC_CTRL_GROUP_0_WIDTH },
20398  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_SAM62A_DM_DM_ECC_AGGR_EDC_CTRL_GROUP_1_CHECKER_TYPE,
20399  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_SAM62A_DM_DM_ECC_AGGR_EDC_CTRL_GROUP_1_WIDTH },
20400  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_SAM62A_DM_DM_ECC_AGGR_EDC_CTRL_GROUP_2_CHECKER_TYPE,
20401  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_SAM62A_DM_DM_ECC_AGGR_EDC_CTRL_GROUP_2_WIDTH },
20402  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_SAM62A_DM_DM_ECC_AGGR_EDC_CTRL_GROUP_3_CHECKER_TYPE,
20403  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_SAM62A_DM_DM_ECC_AGGR_EDC_CTRL_GROUP_3_WIDTH },
20404  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_SAM62A_DM_DM_ECC_AGGR_EDC_CTRL_GROUP_4_CHECKER_TYPE,
20405  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_SAM62A_DM_DM_ECC_AGGR_EDC_CTRL_GROUP_4_WIDTH },
20406  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_SAM62A_DM_DM_ECC_AGGR_EDC_CTRL_GROUP_5_CHECKER_TYPE,
20407  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_SAM62A_DM_DM_ECC_AGGR_EDC_CTRL_GROUP_5_WIDTH },
20408 };
20409 
20414 static const SDL_MemConfig_t SDL_PDMA1_SAM62_PDMA_UART_ECCAGGR_MemEntries[SDL_PDMA1_SAM62_PDMA_UART_ECCAGGR_RAM_IDS_TOTAL_ENTRIES] =
20415 {
20416  { SDL_PDMA1_SAM62_PDMA_UART_ECCAGGR_SAM62_PDMA_UART_PDMA_CORE_TF0_F0_TPRAM_28X128_SBW_SR_RAM_ID, 0u,
20417  SDL_PDMA1_SAM62_PDMA_UART_ECCAGGR_SAM62_PDMA_UART_PDMA_CORE_TF0_F0_TPRAM_28X128_SBW_SR_RAM_SIZE, 16u,
20418  SDL_PDMA1_SAM62_PDMA_UART_ECCAGGR_SAM62_PDMA_UART_PDMA_CORE_TF0_F0_TPRAM_28X128_SBW_SR_ROW_WIDTH, ((bool)false) },
20419  { SDL_PDMA1_SAM62_PDMA_UART_ECCAGGR_SAM62_PDMA_UART_PDMA_CORE_TF0_F1_TPRAM_28X128_SBW_SR_RAM_ID, 0u,
20420  SDL_PDMA1_SAM62_PDMA_UART_ECCAGGR_SAM62_PDMA_UART_PDMA_CORE_TF0_F1_TPRAM_28X128_SBW_SR_RAM_SIZE, 16u,
20421  SDL_PDMA1_SAM62_PDMA_UART_ECCAGGR_SAM62_PDMA_UART_PDMA_CORE_TF0_F1_TPRAM_28X128_SBW_SR_ROW_WIDTH, ((bool)false) },
20422  { SDL_PDMA1_SAM62_PDMA_UART_ECCAGGR_SAM62_PDMA_UART_PDMA_CORE_RF0_F0_TPRAM_28X144_SBW_SR_RAM_ID, 0u,
20423  SDL_PDMA1_SAM62_PDMA_UART_ECCAGGR_SAM62_PDMA_UART_PDMA_CORE_RF0_F0_TPRAM_28X144_SBW_SR_RAM_SIZE, 18u,
20424  SDL_PDMA1_SAM62_PDMA_UART_ECCAGGR_SAM62_PDMA_UART_PDMA_CORE_RF0_F0_TPRAM_28X144_SBW_SR_ROW_WIDTH, ((bool)false) },
20425  { SDL_PDMA1_SAM62_PDMA_UART_ECCAGGR_SAM62_PDMA_UART_PDMA_CORE_RF0_F1_TPRAM_28X144_SBW_SR_RAM_ID, 0u,
20426  SDL_PDMA1_SAM62_PDMA_UART_ECCAGGR_SAM62_PDMA_UART_PDMA_CORE_RF0_F1_TPRAM_28X144_SBW_SR_RAM_SIZE, 18u,
20427  SDL_PDMA1_SAM62_PDMA_UART_ECCAGGR_SAM62_PDMA_UART_PDMA_CORE_RF0_F1_TPRAM_28X144_SBW_SR_ROW_WIDTH, ((bool)false) },
20428 };
20429 
20434 static const SDL_MemConfig_t SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_MemEntries[SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES] =
20435 {
20436  { SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_ID, 0x0020708000u,
20437  SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_SIZE, 4u,
20438  SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_ROW_WIDTH, ((bool)true) },
20439 };
20440 
20446 static const SDL_GrpChkConfig_t SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_groupEntries[SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_MAX_NUM_CHECKERS] =
20447 {
20448  { SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_GROUP_0_CHECKER_TYPE,
20449  SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_GROUP_0_WIDTH },
20450 };
20451 
20456 static const SDL_MemConfig_t SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_MemEntries[SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_RAM_IDS_TOTAL_ENTRIES] =
20457 {
20458  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_IDATA_SPRAM_BANK0_LO_ECC_SVBUS_RAM_ID, 0u,
20459  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_IDATA_SPRAM_BANK0_LO_ECC_SVBUS_RAM_SIZE, 6u,
20460  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_IDATA_SPRAM_BANK0_LO_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
20461  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_IDATA_SPRAM_BANK0_HI_ECC_SVBUS_RAM_ID, 0u,
20462  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_IDATA_SPRAM_BANK0_HI_ECC_SVBUS_RAM_SIZE, 6u,
20463  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_IDATA_SPRAM_BANK0_HI_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
20464  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_IDATA_SPRAM_BANK1_LO_ECC_SVBUS_RAM_ID, 0u,
20465  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_IDATA_SPRAM_BANK1_LO_ECC_SVBUS_RAM_SIZE, 6u,
20466  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_IDATA_SPRAM_BANK1_LO_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
20467  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_IDATA_SPRAM_BANK1_HI_ECC_SVBUS_RAM_ID, 0u,
20468  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_IDATA_SPRAM_BANK1_HI_ECC_SVBUS_RAM_SIZE, 6u,
20469  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_IDATA_SPRAM_BANK1_HI_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
20470  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_ITAG_SPRAM_RAM0_ECC_SVBUS_RAM_ID, 0u,
20471  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_ITAG_SPRAM_RAM0_ECC_SVBUS_RAM_SIZE, 4u,
20472  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_ITAG_SPRAM_RAM0_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
20473  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_ITAG_SPRAM_RAM1_ECC_SVBUS_RAM_ID, 0u,
20474  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_ITAG_SPRAM_RAM1_ECC_SVBUS_RAM_SIZE, 4u,
20475  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_ITAG_SPRAM_RAM1_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
20476  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DDATA_SPRAM_BANK0_ECC_SVBUS_RAM_ID, 0u,
20477  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DDATA_SPRAM_BANK0_ECC_SVBUS_RAM_SIZE, 5u,
20478  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DDATA_SPRAM_BANK0_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
20479  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DDATA_SPRAM_BANK1_ECC_SVBUS_RAM_ID, 0u,
20480  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DDATA_SPRAM_BANK1_ECC_SVBUS_RAM_SIZE, 5u,
20481  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DDATA_SPRAM_BANK1_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
20482  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DDATA_SPRAM_BANK2_ECC_SVBUS_RAM_ID, 0u,
20483  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DDATA_SPRAM_BANK2_ECC_SVBUS_RAM_SIZE, 5u,
20484  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DDATA_SPRAM_BANK2_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
20485  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DDATA_SPRAM_BANK3_ECC_SVBUS_RAM_ID, 0u,
20486  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DDATA_SPRAM_BANK3_ECC_SVBUS_RAM_SIZE, 5u,
20487  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DDATA_SPRAM_BANK3_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
20488  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DDATA_SPRAM_BANK4_ECC_SVBUS_RAM_ID, 0u,
20489  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DDATA_SPRAM_BANK4_ECC_SVBUS_RAM_SIZE, 5u,
20490  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DDATA_SPRAM_BANK4_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
20491  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DDATA_SPRAM_BANK5_ECC_SVBUS_RAM_ID, 0u,
20492  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DDATA_SPRAM_BANK5_ECC_SVBUS_RAM_SIZE, 5u,
20493  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DDATA_SPRAM_BANK5_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
20494  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DDATA_SPRAM_BANK6_ECC_SVBUS_RAM_ID, 0u,
20495  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DDATA_SPRAM_BANK6_ECC_SVBUS_RAM_SIZE, 5u,
20496  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DDATA_SPRAM_BANK6_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
20497  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DDATA_SPRAM_BANK7_ECC_SVBUS_RAM_ID, 0u,
20498  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DDATA_SPRAM_BANK7_ECC_SVBUS_RAM_SIZE, 5u,
20499  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DDATA_SPRAM_BANK7_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
20500  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DTAG_SPRAM_BANK0_ECC_SVBUS_RAM_ID, 0u,
20501  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DTAG_SPRAM_BANK0_ECC_SVBUS_RAM_SIZE, 4u,
20502  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DTAG_SPRAM_BANK0_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
20503  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DTAG_SPRAM_BANK1_ECC_SVBUS_RAM_ID, 0u,
20504  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DTAG_SPRAM_BANK1_ECC_SVBUS_RAM_SIZE, 4u,
20505  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DTAG_SPRAM_BANK1_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
20506  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DTAG_SPRAM_BANK2_ECC_SVBUS_RAM_ID, 0u,
20507  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DTAG_SPRAM_BANK2_ECC_SVBUS_RAM_SIZE, 4u,
20508  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DTAG_SPRAM_BANK2_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
20509  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DTAG_SPRAM_BANK3_ECC_SVBUS_RAM_ID, 0u,
20510  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DTAG_SPRAM_BANK3_ECC_SVBUS_RAM_SIZE, 4u,
20511  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DTAG_SPRAM_BANK3_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
20512  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DDIRTY_SPRAM_ECC_SVBUS_RAM_ID, 0u,
20513  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DDIRTY_SPRAM_ECC_SVBUS_RAM_SIZE, 4u,
20514  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DDIRTY_SPRAM_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
20515  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_TLB_SPRAM_BANK0_ECC_SVBUS_RAM_ID, 0u,
20516  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_TLB_SPRAM_BANK0_ECC_SVBUS_RAM_SIZE, 15u,
20517  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_TLB_SPRAM_BANK0_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
20518  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_TLB_SPRAM_BANK1_ECC_SVBUS_RAM_ID, 0u,
20519  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_TLB_SPRAM_BANK1_ECC_SVBUS_RAM_SIZE, 15u,
20520  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_TLB_SPRAM_BANK1_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
20521  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_TLB_SPRAM_BANK2_ECC_SVBUS_RAM_ID, 0u,
20522  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_TLB_SPRAM_BANK2_ECC_SVBUS_RAM_SIZE, 15u,
20523  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_TLB_SPRAM_BANK2_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
20524  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_TLB_SPRAM_BANK3_ECC_SVBUS_RAM_ID, 0u,
20525  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_TLB_SPRAM_BANK3_ECC_SVBUS_RAM_SIZE, 15u,
20526  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_TLB_SPRAM_BANK3_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
20527  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY0_ECC_SVBUS_RAM_ID, 0u,
20528  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY0_ECC_SVBUS_RAM_SIZE, 5u,
20529  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY0_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
20530  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY1_ECC_SVBUS_RAM_ID, 0u,
20531  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY1_ECC_SVBUS_RAM_SIZE, 5u,
20532  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY1_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
20533  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY2_ECC_SVBUS_RAM_ID, 0u,
20534  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY2_ECC_SVBUS_RAM_SIZE, 5u,
20535  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY2_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
20536  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY3_ECC_SVBUS_RAM_ID, 0u,
20537  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY3_ECC_SVBUS_RAM_SIZE, 5u,
20538  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY3_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
20539 };
20540 
20545 static const SDL_MemConfig_t SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_MemEntries[SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_RAM_IDS_TOTAL_ENTRIES] =
20546 {
20547  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_IDATA_SPRAM_BANK0_LO_ECC_SVBUS_RAM_ID, 0u,
20548  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_IDATA_SPRAM_BANK0_LO_ECC_SVBUS_RAM_SIZE, 6u,
20549  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_IDATA_SPRAM_BANK0_LO_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
20550  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_IDATA_SPRAM_BANK0_HI_ECC_SVBUS_RAM_ID, 0u,
20551  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_IDATA_SPRAM_BANK0_HI_ECC_SVBUS_RAM_SIZE, 6u,
20552  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_IDATA_SPRAM_BANK0_HI_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
20553  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_IDATA_SPRAM_BANK1_LO_ECC_SVBUS_RAM_ID, 0u,
20554  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_IDATA_SPRAM_BANK1_LO_ECC_SVBUS_RAM_SIZE, 6u,
20555  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_IDATA_SPRAM_BANK1_LO_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
20556  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_IDATA_SPRAM_BANK1_HI_ECC_SVBUS_RAM_ID, 0u,
20557  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_IDATA_SPRAM_BANK1_HI_ECC_SVBUS_RAM_SIZE, 6u,
20558  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_IDATA_SPRAM_BANK1_HI_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
20559  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_ITAG_SPRAM_RAM0_ECC_SVBUS_RAM_ID, 0u,
20560  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_ITAG_SPRAM_RAM0_ECC_SVBUS_RAM_SIZE, 4u,
20561  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_ITAG_SPRAM_RAM0_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
20562  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_ITAG_SPRAM_RAM1_ECC_SVBUS_RAM_ID, 0u,
20563  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_ITAG_SPRAM_RAM1_ECC_SVBUS_RAM_SIZE, 4u,
20564  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_ITAG_SPRAM_RAM1_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
20565  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DDATA_SPRAM_BANK0_ECC_SVBUS_RAM_ID, 0u,
20566  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DDATA_SPRAM_BANK0_ECC_SVBUS_RAM_SIZE, 5u,
20567  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DDATA_SPRAM_BANK0_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
20568  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DDATA_SPRAM_BANK1_ECC_SVBUS_RAM_ID, 0u,
20569  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DDATA_SPRAM_BANK1_ECC_SVBUS_RAM_SIZE, 5u,
20570  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DDATA_SPRAM_BANK1_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
20571  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DDATA_SPRAM_BANK2_ECC_SVBUS_RAM_ID, 0u,
20572  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DDATA_SPRAM_BANK2_ECC_SVBUS_RAM_SIZE, 5u,
20573  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DDATA_SPRAM_BANK2_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
20574  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DDATA_SPRAM_BANK3_ECC_SVBUS_RAM_ID, 0u,
20575  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DDATA_SPRAM_BANK3_ECC_SVBUS_RAM_SIZE, 5u,
20576  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DDATA_SPRAM_BANK3_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
20577  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DDATA_SPRAM_BANK4_ECC_SVBUS_RAM_ID, 0u,
20578  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DDATA_SPRAM_BANK4_ECC_SVBUS_RAM_SIZE, 5u,
20579  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DDATA_SPRAM_BANK4_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
20580  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DDATA_SPRAM_BANK5_ECC_SVBUS_RAM_ID, 0u,
20581  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DDATA_SPRAM_BANK5_ECC_SVBUS_RAM_SIZE, 5u,
20582  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DDATA_SPRAM_BANK5_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
20583  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DDATA_SPRAM_BANK6_ECC_SVBUS_RAM_ID, 0u,
20584  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DDATA_SPRAM_BANK6_ECC_SVBUS_RAM_SIZE, 5u,
20585  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DDATA_SPRAM_BANK6_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
20586  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DDATA_SPRAM_BANK7_ECC_SVBUS_RAM_ID, 0u,
20587  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DDATA_SPRAM_BANK7_ECC_SVBUS_RAM_SIZE, 5u,
20588  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DDATA_SPRAM_BANK7_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
20589  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DTAG_SPRAM_BANK0_ECC_SVBUS_RAM_ID, 0u,
20590  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DTAG_SPRAM_BANK0_ECC_SVBUS_RAM_SIZE, 4u,
20591  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DTAG_SPRAM_BANK0_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
20592  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DTAG_SPRAM_BANK1_ECC_SVBUS_RAM_ID, 0u,
20593  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DTAG_SPRAM_BANK1_ECC_SVBUS_RAM_SIZE, 4u,
20594  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DTAG_SPRAM_BANK1_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
20595  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DTAG_SPRAM_BANK2_ECC_SVBUS_RAM_ID, 0u,
20596  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DTAG_SPRAM_BANK2_ECC_SVBUS_RAM_SIZE, 4u,
20597  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DTAG_SPRAM_BANK2_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
20598  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DTAG_SPRAM_BANK3_ECC_SVBUS_RAM_ID, 0u,
20599  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DTAG_SPRAM_BANK3_ECC_SVBUS_RAM_SIZE, 4u,
20600  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DTAG_SPRAM_BANK3_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
20601  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DDIRTY_SPRAM_ECC_SVBUS_RAM_ID, 0u,
20602  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DDIRTY_SPRAM_ECC_SVBUS_RAM_SIZE, 4u,
20603  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DDIRTY_SPRAM_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
20604  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_TLB_SPRAM_BANK0_ECC_SVBUS_RAM_ID, 0u,
20605  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_TLB_SPRAM_BANK0_ECC_SVBUS_RAM_SIZE, 15u,
20606  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_TLB_SPRAM_BANK0_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
20607  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_TLB_SPRAM_BANK1_ECC_SVBUS_RAM_ID, 0u,
20608  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_TLB_SPRAM_BANK1_ECC_SVBUS_RAM_SIZE, 15u,
20609  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_TLB_SPRAM_BANK1_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
20610  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_TLB_SPRAM_BANK2_ECC_SVBUS_RAM_ID, 0u,
20611  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_TLB_SPRAM_BANK2_ECC_SVBUS_RAM_SIZE, 15u,
20612  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_TLB_SPRAM_BANK2_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
20613  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_TLB_SPRAM_BANK3_ECC_SVBUS_RAM_ID, 0u,
20614  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_TLB_SPRAM_BANK3_ECC_SVBUS_RAM_SIZE, 15u,
20615  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_TLB_SPRAM_BANK3_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
20616  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY0_ECC_SVBUS_RAM_ID, 0u,
20617  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY0_ECC_SVBUS_RAM_SIZE, 5u,
20618  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY0_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
20619  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY1_ECC_SVBUS_RAM_ID, 0u,
20620  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY1_ECC_SVBUS_RAM_SIZE, 5u,
20621  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY1_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
20622  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY2_ECC_SVBUS_RAM_ID, 0u,
20623  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY2_ECC_SVBUS_RAM_SIZE, 5u,
20624  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY2_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
20625  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY3_ECC_SVBUS_RAM_ID, 0u,
20626  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY3_ECC_SVBUS_RAM_SIZE, 5u,
20627  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY3_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
20628 };
20629 
20634 static const SDL_MemConfig_t SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_MemEntries[SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_RAM_IDS_TOTAL_ENTRIES] =
20635 {
20636  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_IDATA_SPRAM_BANK0_LO_ECC_SVBUS_RAM_ID, 0u,
20637  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_IDATA_SPRAM_BANK0_LO_ECC_SVBUS_RAM_SIZE, 6u,
20638  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_IDATA_SPRAM_BANK0_LO_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
20639  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_IDATA_SPRAM_BANK0_HI_ECC_SVBUS_RAM_ID, 0u,
20640  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_IDATA_SPRAM_BANK0_HI_ECC_SVBUS_RAM_SIZE, 6u,
20641  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_IDATA_SPRAM_BANK0_HI_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
20642  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_IDATA_SPRAM_BANK1_LO_ECC_SVBUS_RAM_ID, 0u,
20643  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_IDATA_SPRAM_BANK1_LO_ECC_SVBUS_RAM_SIZE, 6u,
20644  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_IDATA_SPRAM_BANK1_LO_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
20645  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_IDATA_SPRAM_BANK1_HI_ECC_SVBUS_RAM_ID, 0u,
20646  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_IDATA_SPRAM_BANK1_HI_ECC_SVBUS_RAM_SIZE, 6u,
20647  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_IDATA_SPRAM_BANK1_HI_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
20648  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_ITAG_SPRAM_RAM0_ECC_SVBUS_RAM_ID, 0u,
20649  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_ITAG_SPRAM_RAM0_ECC_SVBUS_RAM_SIZE, 4u,
20650  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_ITAG_SPRAM_RAM0_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
20651  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_ITAG_SPRAM_RAM1_ECC_SVBUS_RAM_ID, 0u,
20652  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_ITAG_SPRAM_RAM1_ECC_SVBUS_RAM_SIZE, 4u,
20653  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_ITAG_SPRAM_RAM1_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
20654  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DDATA_SPRAM_BANK0_ECC_SVBUS_RAM_ID, 0u,
20655  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DDATA_SPRAM_BANK0_ECC_SVBUS_RAM_SIZE, 5u,
20656  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DDATA_SPRAM_BANK0_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
20657  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DDATA_SPRAM_BANK1_ECC_SVBUS_RAM_ID, 0u,
20658  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DDATA_SPRAM_BANK1_ECC_SVBUS_RAM_SIZE, 5u,
20659  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DDATA_SPRAM_BANK1_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
20660  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DDATA_SPRAM_BANK2_ECC_SVBUS_RAM_ID, 0u,
20661  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DDATA_SPRAM_BANK2_ECC_SVBUS_RAM_SIZE, 5u,
20662  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DDATA_SPRAM_BANK2_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
20663  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DDATA_SPRAM_BANK3_ECC_SVBUS_RAM_ID, 0u,
20664  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DDATA_SPRAM_BANK3_ECC_SVBUS_RAM_SIZE, 5u,
20665  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DDATA_SPRAM_BANK3_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
20666  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DDATA_SPRAM_BANK4_ECC_SVBUS_RAM_ID, 0u,
20667  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DDATA_SPRAM_BANK4_ECC_SVBUS_RAM_SIZE, 5u,
20668  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DDATA_SPRAM_BANK4_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
20669  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DDATA_SPRAM_BANK5_ECC_SVBUS_RAM_ID, 0u,
20670  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DDATA_SPRAM_BANK5_ECC_SVBUS_RAM_SIZE, 5u,
20671  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DDATA_SPRAM_BANK5_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
20672  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DDATA_SPRAM_BANK6_ECC_SVBUS_RAM_ID, 0u,
20673  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DDATA_SPRAM_BANK6_ECC_SVBUS_RAM_SIZE, 5u,
20674  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DDATA_SPRAM_BANK6_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
20675  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DDATA_SPRAM_BANK7_ECC_SVBUS_RAM_ID, 0u,
20676  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DDATA_SPRAM_BANK7_ECC_SVBUS_RAM_SIZE, 5u,
20677  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DDATA_SPRAM_BANK7_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
20678  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DTAG_SPRAM_BANK0_ECC_SVBUS_RAM_ID, 0u,
20679  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DTAG_SPRAM_BANK0_ECC_SVBUS_RAM_SIZE, 4u,
20680  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DTAG_SPRAM_BANK0_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
20681  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DTAG_SPRAM_BANK1_ECC_SVBUS_RAM_ID, 0u,
20682  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DTAG_SPRAM_BANK1_ECC_SVBUS_RAM_SIZE, 4u,
20683  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DTAG_SPRAM_BANK1_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
20684  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DTAG_SPRAM_BANK2_ECC_SVBUS_RAM_ID, 0u,
20685  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DTAG_SPRAM_BANK2_ECC_SVBUS_RAM_SIZE, 4u,
20686  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DTAG_SPRAM_BANK2_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
20687  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DTAG_SPRAM_BANK3_ECC_SVBUS_RAM_ID, 0u,
20688  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DTAG_SPRAM_BANK3_ECC_SVBUS_RAM_SIZE, 4u,
20689  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DTAG_SPRAM_BANK3_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
20690  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DDIRTY_SPRAM_ECC_SVBUS_RAM_ID, 0u,
20691  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DDIRTY_SPRAM_ECC_SVBUS_RAM_SIZE, 4u,
20692  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DDIRTY_SPRAM_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
20693  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_TLB_SPRAM_BANK0_ECC_SVBUS_RAM_ID, 0u,
20694  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_TLB_SPRAM_BANK0_ECC_SVBUS_RAM_SIZE, 15u,
20695  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_TLB_SPRAM_BANK0_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
20696  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_TLB_SPRAM_BANK1_ECC_SVBUS_RAM_ID, 0u,
20697  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_TLB_SPRAM_BANK1_ECC_SVBUS_RAM_SIZE, 15u,
20698  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_TLB_SPRAM_BANK1_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
20699  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_TLB_SPRAM_BANK2_ECC_SVBUS_RAM_ID, 0u,
20700  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_TLB_SPRAM_BANK2_ECC_SVBUS_RAM_SIZE, 15u,
20701  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_TLB_SPRAM_BANK2_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
20702  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_TLB_SPRAM_BANK3_ECC_SVBUS_RAM_ID, 0u,
20703  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_TLB_SPRAM_BANK3_ECC_SVBUS_RAM_SIZE, 15u,
20704  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_TLB_SPRAM_BANK3_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
20705  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY0_ECC_SVBUS_RAM_ID, 0u,
20706  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY0_ECC_SVBUS_RAM_SIZE, 5u,
20707  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY0_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
20708  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY1_ECC_SVBUS_RAM_ID, 0u,
20709  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY1_ECC_SVBUS_RAM_SIZE, 5u,
20710  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY1_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
20711  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY2_ECC_SVBUS_RAM_ID, 0u,
20712  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY2_ECC_SVBUS_RAM_SIZE, 5u,
20713  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY2_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
20714  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY3_ECC_SVBUS_RAM_ID, 0u,
20715  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY3_ECC_SVBUS_RAM_SIZE, 5u,
20716  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY3_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
20717 };
20718 
20723 static const SDL_MemConfig_t SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_MemEntries[SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_RAM_IDS_TOTAL_ENTRIES] =
20724 {
20725  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_IDATA_SPRAM_BANK0_LO_ECC_SVBUS_RAM_ID, 0u,
20726  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_IDATA_SPRAM_BANK0_LO_ECC_SVBUS_RAM_SIZE, 6u,
20727  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_IDATA_SPRAM_BANK0_LO_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
20728  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_IDATA_SPRAM_BANK0_HI_ECC_SVBUS_RAM_ID, 0u,
20729  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_IDATA_SPRAM_BANK0_HI_ECC_SVBUS_RAM_SIZE, 6u,
20730  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_IDATA_SPRAM_BANK0_HI_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
20731  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_IDATA_SPRAM_BANK1_LO_ECC_SVBUS_RAM_ID, 0u,
20732  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_IDATA_SPRAM_BANK1_LO_ECC_SVBUS_RAM_SIZE, 6u,
20733  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_IDATA_SPRAM_BANK1_LO_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
20734  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_IDATA_SPRAM_BANK1_HI_ECC_SVBUS_RAM_ID, 0u,
20735  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_IDATA_SPRAM_BANK1_HI_ECC_SVBUS_RAM_SIZE, 6u,
20736  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_IDATA_SPRAM_BANK1_HI_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
20737  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_ITAG_SPRAM_RAM0_ECC_SVBUS_RAM_ID, 0u,
20738  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_ITAG_SPRAM_RAM0_ECC_SVBUS_RAM_SIZE, 4u,
20739  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_ITAG_SPRAM_RAM0_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
20740  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_ITAG_SPRAM_RAM1_ECC_SVBUS_RAM_ID, 0u,
20741  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_ITAG_SPRAM_RAM1_ECC_SVBUS_RAM_SIZE, 4u,
20742  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_ITAG_SPRAM_RAM1_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
20743  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DDATA_SPRAM_BANK0_ECC_SVBUS_RAM_ID, 0u,
20744  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DDATA_SPRAM_BANK0_ECC_SVBUS_RAM_SIZE, 5u,
20745  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DDATA_SPRAM_BANK0_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
20746  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DDATA_SPRAM_BANK1_ECC_SVBUS_RAM_ID, 0u,
20747  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DDATA_SPRAM_BANK1_ECC_SVBUS_RAM_SIZE, 5u,
20748  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DDATA_SPRAM_BANK1_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
20749  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DDATA_SPRAM_BANK2_ECC_SVBUS_RAM_ID, 0u,
20750  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DDATA_SPRAM_BANK2_ECC_SVBUS_RAM_SIZE, 5u,
20751  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DDATA_SPRAM_BANK2_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
20752  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DDATA_SPRAM_BANK3_ECC_SVBUS_RAM_ID, 0u,
20753  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DDATA_SPRAM_BANK3_ECC_SVBUS_RAM_SIZE, 5u,
20754  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DDATA_SPRAM_BANK3_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
20755  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DDATA_SPRAM_BANK4_ECC_SVBUS_RAM_ID, 0u,
20756  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DDATA_SPRAM_BANK4_ECC_SVBUS_RAM_SIZE, 5u,
20757  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DDATA_SPRAM_BANK4_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
20758  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DDATA_SPRAM_BANK5_ECC_SVBUS_RAM_ID, 0u,
20759  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DDATA_SPRAM_BANK5_ECC_SVBUS_RAM_SIZE, 5u,
20760  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DDATA_SPRAM_BANK5_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
20761  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DDATA_SPRAM_BANK6_ECC_SVBUS_RAM_ID, 0u,
20762  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DDATA_SPRAM_BANK6_ECC_SVBUS_RAM_SIZE, 5u,
20763  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DDATA_SPRAM_BANK6_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
20764  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DDATA_SPRAM_BANK7_ECC_SVBUS_RAM_ID, 0u,
20765  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DDATA_SPRAM_BANK7_ECC_SVBUS_RAM_SIZE, 5u,
20766  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DDATA_SPRAM_BANK7_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
20767  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DTAG_SPRAM_BANK0_ECC_SVBUS_RAM_ID, 0u,
20768  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DTAG_SPRAM_BANK0_ECC_SVBUS_RAM_SIZE, 4u,
20769  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DTAG_SPRAM_BANK0_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
20770  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DTAG_SPRAM_BANK1_ECC_SVBUS_RAM_ID, 0u,
20771  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DTAG_SPRAM_BANK1_ECC_SVBUS_RAM_SIZE, 4u,
20772  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DTAG_SPRAM_BANK1_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
20773  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DTAG_SPRAM_BANK2_ECC_SVBUS_RAM_ID, 0u,
20774  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DTAG_SPRAM_BANK2_ECC_SVBUS_RAM_SIZE, 4u,
20775  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DTAG_SPRAM_BANK2_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
20776  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DTAG_SPRAM_BANK3_ECC_SVBUS_RAM_ID, 0u,
20777  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DTAG_SPRAM_BANK3_ECC_SVBUS_RAM_SIZE, 4u,
20778  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DTAG_SPRAM_BANK3_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
20779  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DDIRTY_SPRAM_ECC_SVBUS_RAM_ID, 0u,
20780  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DDIRTY_SPRAM_ECC_SVBUS_RAM_SIZE, 4u,
20781  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DDIRTY_SPRAM_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
20782  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_TLB_SPRAM_BANK0_ECC_SVBUS_RAM_ID, 0u,
20783  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_TLB_SPRAM_BANK0_ECC_SVBUS_RAM_SIZE, 15u,
20784  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_TLB_SPRAM_BANK0_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
20785  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_TLB_SPRAM_BANK1_ECC_SVBUS_RAM_ID, 0u,
20786  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_TLB_SPRAM_BANK1_ECC_SVBUS_RAM_SIZE, 15u,
20787  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_TLB_SPRAM_BANK1_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
20788  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_TLB_SPRAM_BANK2_ECC_SVBUS_RAM_ID, 0u,
20789  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_TLB_SPRAM_BANK2_ECC_SVBUS_RAM_SIZE, 15u,
20790  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_TLB_SPRAM_BANK2_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
20791  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_TLB_SPRAM_BANK3_ECC_SVBUS_RAM_ID, 0u,
20792  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_TLB_SPRAM_BANK3_ECC_SVBUS_RAM_SIZE, 15u,
20793  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_TLB_SPRAM_BANK3_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
20794  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY0_ECC_SVBUS_RAM_ID, 0u,
20795  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY0_ECC_SVBUS_RAM_SIZE, 5u,
20796  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY0_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
20797  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY1_ECC_SVBUS_RAM_ID, 0u,
20798  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY1_ECC_SVBUS_RAM_SIZE, 5u,
20799  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY1_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
20800  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY2_ECC_SVBUS_RAM_ID, 0u,
20801  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY2_ECC_SVBUS_RAM_SIZE, 5u,
20802  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY2_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
20803  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY3_ECC_SVBUS_RAM_ID, 0u,
20804  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY3_ECC_SVBUS_RAM_SIZE, 5u,
20805  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY3_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
20806 };
20807 
20812 static const SDL_MemConfig_t SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_MemEntries[SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_RAM_IDS_TOTAL_ENTRIES] =
20813 {
20814  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY0_ECC_SVBUS_RAM_ID, 0u,
20815  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY0_ECC_SVBUS_RAM_SIZE, 5u,
20816  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY0_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
20817  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY1_ECC_SVBUS_RAM_ID, 0u,
20818  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY1_ECC_SVBUS_RAM_SIZE, 5u,
20819  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY1_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
20820  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY2_ECC_SVBUS_RAM_ID, 0u,
20821  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY2_ECC_SVBUS_RAM_SIZE, 5u,
20822  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY2_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
20823  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY3_ECC_SVBUS_RAM_ID, 0u,
20824  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY3_ECC_SVBUS_RAM_SIZE, 5u,
20825  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY3_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
20826  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY4_ECC_SVBUS_RAM_ID, 0u,
20827  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY4_ECC_SVBUS_RAM_SIZE, 5u,
20828  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY4_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
20829  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY5_ECC_SVBUS_RAM_ID, 0u,
20830  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY5_ECC_SVBUS_RAM_SIZE, 5u,
20831  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY5_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
20832  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY6_ECC_SVBUS_RAM_ID, 0u,
20833  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY6_ECC_SVBUS_RAM_SIZE, 5u,
20834  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY6_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
20835  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY7_ECC_SVBUS_RAM_ID, 0u,
20836  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY7_ECC_SVBUS_RAM_SIZE, 5u,
20837  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY7_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
20838  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY8_ECC_SVBUS_RAM_ID, 0u,
20839  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY8_ECC_SVBUS_RAM_SIZE, 5u,
20840  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY8_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
20841  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY9_ECC_SVBUS_RAM_ID, 0u,
20842  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY9_ECC_SVBUS_RAM_SIZE, 5u,
20843  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY9_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
20844  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY10_ECC_SVBUS_RAM_ID, 0u,
20845  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY10_ECC_SVBUS_RAM_SIZE, 5u,
20846  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY10_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
20847  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY11_ECC_SVBUS_RAM_ID, 0u,
20848  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY11_ECC_SVBUS_RAM_SIZE, 5u,
20849  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY11_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
20850  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY12_ECC_SVBUS_RAM_ID, 0u,
20851  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY12_ECC_SVBUS_RAM_SIZE, 5u,
20852  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY12_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
20853  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY13_ECC_SVBUS_RAM_ID, 0u,
20854  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY13_ECC_SVBUS_RAM_SIZE, 5u,
20855  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY13_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
20856  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY14_ECC_SVBUS_RAM_ID, 0u,
20857  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY14_ECC_SVBUS_RAM_SIZE, 5u,
20858  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY14_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
20859  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY15_ECC_SVBUS_RAM_ID, 0u,
20860  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY15_ECC_SVBUS_RAM_SIZE, 5u,
20861  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY15_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
20862  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_DATARAM_SPRAM_0_ECC_SVBUS_RAM_ID, 0u,
20863  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_DATARAM_SPRAM_0_ECC_SVBUS_RAM_SIZE, 9u,
20864  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_DATARAM_SPRAM_0_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
20865  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_DATARAM_SPRAM_1_ECC_SVBUS_RAM_ID, 0u,
20866  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_DATARAM_SPRAM_1_ECC_SVBUS_RAM_SIZE, 9u,
20867  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_DATARAM_SPRAM_1_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
20868  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_DATARAM_SPRAM_2_ECC_SVBUS_RAM_ID, 0u,
20869  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_DATARAM_SPRAM_2_ECC_SVBUS_RAM_SIZE, 9u,
20870  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_DATARAM_SPRAM_2_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
20871  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_DATARAM_SPRAM_3_ECC_SVBUS_RAM_ID, 0u,
20872  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_DATARAM_SPRAM_3_ECC_SVBUS_RAM_SIZE, 9u,
20873  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_DATARAM_SPRAM_3_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
20874  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_DATARAM_SPRAM_4_ECC_SVBUS_RAM_ID, 0u,
20875  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_DATARAM_SPRAM_4_ECC_SVBUS_RAM_SIZE, 9u,
20876  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_DATARAM_SPRAM_4_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
20877  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_DATARAM_SPRAM_5_ECC_SVBUS_RAM_ID, 0u,
20878  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_DATARAM_SPRAM_5_ECC_SVBUS_RAM_SIZE, 9u,
20879  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_DATARAM_SPRAM_5_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
20880  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_DATARAM_SPRAM_6_ECC_SVBUS_RAM_ID, 0u,
20881  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_DATARAM_SPRAM_6_ECC_SVBUS_RAM_SIZE, 9u,
20882  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_DATARAM_SPRAM_6_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
20883  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_DATARAM_SPRAM_7_ECC_SVBUS_RAM_ID, 0u,
20884  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_DATARAM_SPRAM_7_ECC_SVBUS_RAM_SIZE, 9u,
20885  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_DATARAM_SPRAM_7_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
20886 };
20887 
20892 static const SDL_MemConfig_t SDL_MCU_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_MemEntries[SDL_MCU_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES] =
20893 {
20894  { SDL_MCU_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_ID, 0x0004E00000u,
20895  SDL_MCU_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_SIZE, 4u,
20896  SDL_MCU_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_ROW_WIDTH, ((bool)true) },
20897 };
20898 
20904 static const SDL_GrpChkConfig_t SDL_MCU_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_groupEntries[SDL_MCU_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_MAX_NUM_CHECKERS] =
20905 {
20906  { SDL_MCU_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_GROUP_0_CHECKER_TYPE,
20907  SDL_MCU_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_GROUP_0_WIDTH },
20908 };
20909 
20914 static const SDL_MemConfig_t SDL_MCU_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_MemEntries[SDL_MCU_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES] =
20915 {
20916  { SDL_MCU_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_ID, 0x0004E10000u,
20917  SDL_MCU_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_SIZE, 4u,
20918  SDL_MCU_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_ROW_WIDTH, ((bool)true) },
20919 };
20920 
20926 static const SDL_GrpChkConfig_t SDL_MCU_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_groupEntries[SDL_MCU_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_MAX_NUM_CHECKERS] =
20927 {
20928  { SDL_MCU_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_GROUP_0_CHECKER_TYPE,
20929  SDL_MCU_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_GROUP_0_WIDTH },
20930 };
20931 
20936 static const SDL_MemConfig_t SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_MemEntries[SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES] =
20937 {
20938  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_IMAILBOX4_MAIN_0_RAMECC_RAM_ID, 0u,
20939  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_IMAILBOX4_MAIN_0_RAMECC_RAM_SIZE, 4u,
20940  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_IMAILBOX4_MAIN_0_RAMECC_ROW_WIDTH, ((bool)false) },
20941 };
20942 
20948 static const SDL_GrpChkConfig_t SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_groupEntries[SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_MAX_NUM_CHECKERS] =
20949 {
20950  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_0_CHECKER_TYPE,
20951  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_0_WIDTH },
20952  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_1_CHECKER_TYPE,
20953  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_1_WIDTH },
20954  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_2_CHECKER_TYPE,
20955  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_2_WIDTH },
20956  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_3_CHECKER_TYPE,
20957  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_3_WIDTH },
20958  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_4_CHECKER_TYPE,
20959  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_4_WIDTH },
20960  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_5_CHECKER_TYPE,
20961  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_5_WIDTH },
20962  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_6_CHECKER_TYPE,
20963  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_6_WIDTH },
20964  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_7_CHECKER_TYPE,
20965  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_7_WIDTH },
20966  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_8_CHECKER_TYPE,
20967  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_8_WIDTH },
20968  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_9_CHECKER_TYPE,
20969  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_9_WIDTH },
20970  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_10_CHECKER_TYPE,
20971  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_10_WIDTH },
20972  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_11_CHECKER_TYPE,
20973  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_11_WIDTH },
20974  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_12_CHECKER_TYPE,
20975  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_12_WIDTH },
20976  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_13_CHECKER_TYPE,
20977  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_13_WIDTH },
20978  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_14_CHECKER_TYPE,
20979  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_14_WIDTH },
20980  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_15_CHECKER_TYPE,
20981  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_15_WIDTH },
20982  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_16_CHECKER_TYPE,
20983  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_16_WIDTH },
20984  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_17_CHECKER_TYPE,
20985  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_17_WIDTH },
20986  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_18_CHECKER_TYPE,
20987  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_18_WIDTH },
20988  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_19_CHECKER_TYPE,
20989  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_19_WIDTH },
20990  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_20_CHECKER_TYPE,
20991  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_20_WIDTH },
20992  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_21_CHECKER_TYPE,
20993  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_21_WIDTH },
20994  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_22_CHECKER_TYPE,
20995  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_22_WIDTH },
20996  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_23_CHECKER_TYPE,
20997  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_23_WIDTH },
20998  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_24_CHECKER_TYPE,
20999  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_24_WIDTH },
21000  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_25_CHECKER_TYPE,
21001  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_25_WIDTH },
21002  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_26_CHECKER_TYPE,
21003  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_26_WIDTH },
21004  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_27_CHECKER_TYPE,
21005  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_27_WIDTH },
21006  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_28_CHECKER_TYPE,
21007  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_28_WIDTH },
21008  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_29_CHECKER_TYPE,
21009  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_29_WIDTH },
21010  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_30_CHECKER_TYPE,
21011  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_30_WIDTH },
21012  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_31_CHECKER_TYPE,
21013  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_31_WIDTH },
21014  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_32_CHECKER_TYPE,
21015  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_32_WIDTH },
21016  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_33_CHECKER_TYPE,
21017  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_33_WIDTH },
21018  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_34_CHECKER_TYPE,
21019  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_34_WIDTH },
21020  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_35_CHECKER_TYPE,
21021  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_35_WIDTH },
21022  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_36_CHECKER_TYPE,
21023  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_36_WIDTH },
21024  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_37_CHECKER_TYPE,
21025  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_37_WIDTH },
21026  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_38_CHECKER_TYPE,
21027  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_38_WIDTH },
21028  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_39_CHECKER_TYPE,
21029  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_39_WIDTH },
21030  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_40_CHECKER_TYPE,
21031  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_40_WIDTH },
21032  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_41_CHECKER_TYPE,
21033  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_41_WIDTH },
21034  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_42_CHECKER_TYPE,
21035  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_42_WIDTH },
21036  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_43_CHECKER_TYPE,
21037  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_43_WIDTH },
21038  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_44_CHECKER_TYPE,
21039  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_44_WIDTH },
21040  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_45_CHECKER_TYPE,
21041  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_45_WIDTH },
21042  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_46_CHECKER_TYPE,
21043  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_46_WIDTH },
21044  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_47_CHECKER_TYPE,
21045  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_47_WIDTH },
21046  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_48_CHECKER_TYPE,
21047  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_48_WIDTH },
21048  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_49_CHECKER_TYPE,
21049  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_49_WIDTH },
21050  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_50_CHECKER_TYPE,
21051  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_50_WIDTH },
21052  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_51_CHECKER_TYPE,
21053  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_51_WIDTH },
21054  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_52_CHECKER_TYPE,
21055  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_52_WIDTH },
21056  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_53_CHECKER_TYPE,
21057  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_53_WIDTH },
21058  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_54_CHECKER_TYPE,
21059  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_54_WIDTH },
21060  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_55_CHECKER_TYPE,
21061  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_55_WIDTH },
21062  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_56_CHECKER_TYPE,
21063  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_56_WIDTH },
21064  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_57_CHECKER_TYPE,
21065  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_57_WIDTH },
21066  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_58_CHECKER_TYPE,
21067  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_58_WIDTH },
21068  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_59_CHECKER_TYPE,
21069  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_59_WIDTH },
21070  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_60_CHECKER_TYPE,
21071  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_60_WIDTH },
21072  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_61_CHECKER_TYPE,
21073  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_61_WIDTH },
21074 };
21075 
21081 static const SDL_GrpChkConfig_t SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_HSM_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_HSM_VBUSP_S_BRIDGE_BUSECC_groupEntries[SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_HSM_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_HSM_VBUSP_S_BRIDGE_BUSECC_MAX_NUM_CHECKERS] =
21082 {
21083  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_HSM_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_HSM_VBUSP_S_BRIDGE_BUSECC_GROUP_0_CHECKER_TYPE,
21084  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_HSM_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_HSM_VBUSP_S_BRIDGE_BUSECC_GROUP_0_WIDTH },
21085  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_HSM_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_HSM_VBUSP_S_BRIDGE_BUSECC_GROUP_1_CHECKER_TYPE,
21086  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_HSM_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_HSM_VBUSP_S_BRIDGE_BUSECC_GROUP_1_WIDTH },
21087  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_HSM_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_HSM_VBUSP_S_BRIDGE_BUSECC_GROUP_2_CHECKER_TYPE,
21088  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_HSM_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_HSM_VBUSP_S_BRIDGE_BUSECC_GROUP_2_WIDTH },
21089  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_HSM_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_HSM_VBUSP_S_BRIDGE_BUSECC_GROUP_3_CHECKER_TYPE,
21090  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_HSM_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_HSM_VBUSP_S_BRIDGE_BUSECC_GROUP_3_WIDTH },
21091  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_HSM_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_HSM_VBUSP_S_BRIDGE_BUSECC_GROUP_4_CHECKER_TYPE,
21092  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_HSM_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_HSM_VBUSP_S_BRIDGE_BUSECC_GROUP_4_WIDTH },
21093  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_HSM_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_HSM_VBUSP_S_BRIDGE_BUSECC_GROUP_5_CHECKER_TYPE,
21094  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_HSM_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_HSM_VBUSP_S_BRIDGE_BUSECC_GROUP_5_WIDTH },
21095  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_HSM_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_HSM_VBUSP_S_BRIDGE_BUSECC_GROUP_6_CHECKER_TYPE,
21096  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_HSM_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_HSM_VBUSP_S_BRIDGE_BUSECC_GROUP_6_WIDTH },
21097  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_HSM_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_HSM_VBUSP_S_BRIDGE_BUSECC_GROUP_7_CHECKER_TYPE,
21098  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_HSM_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_HSM_VBUSP_S_BRIDGE_BUSECC_GROUP_7_WIDTH },
21099  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_HSM_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_HSM_VBUSP_S_BRIDGE_BUSECC_GROUP_8_CHECKER_TYPE,
21100  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_HSM_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_HSM_VBUSP_S_BRIDGE_BUSECC_GROUP_8_WIDTH },
21101  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_HSM_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_HSM_VBUSP_S_BRIDGE_BUSECC_GROUP_9_CHECKER_TYPE,
21102  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_HSM_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_HSM_VBUSP_S_BRIDGE_BUSECC_GROUP_9_WIDTH },
21103  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_HSM_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_HSM_VBUSP_S_BRIDGE_BUSECC_GROUP_10_CHECKER_TYPE,
21104  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_HSM_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_HSM_VBUSP_S_BRIDGE_BUSECC_GROUP_10_WIDTH },
21105  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_HSM_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_HSM_VBUSP_S_BRIDGE_BUSECC_GROUP_11_CHECKER_TYPE,
21106  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_HSM_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_HSM_VBUSP_S_BRIDGE_BUSECC_GROUP_11_WIDTH },
21107  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_HSM_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_HSM_VBUSP_S_BRIDGE_BUSECC_GROUP_12_CHECKER_TYPE,
21108  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_HSM_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_HSM_VBUSP_S_BRIDGE_BUSECC_GROUP_12_WIDTH },
21109 };
21110 
21116 static const SDL_GrpChkConfig_t SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_TIFS_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_TIFS_VBUSP_S_BRIDGE_BUSECC_groupEntries[SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_TIFS_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_TIFS_VBUSP_S_BRIDGE_BUSECC_MAX_NUM_CHECKERS] =
21117 {
21118  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_TIFS_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_TIFS_VBUSP_S_BRIDGE_BUSECC_GROUP_0_CHECKER_TYPE,
21119  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_TIFS_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_TIFS_VBUSP_S_BRIDGE_BUSECC_GROUP_0_WIDTH },
21120  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_TIFS_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_TIFS_VBUSP_S_BRIDGE_BUSECC_GROUP_1_CHECKER_TYPE,
21121  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_TIFS_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_TIFS_VBUSP_S_BRIDGE_BUSECC_GROUP_1_WIDTH },
21122  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_TIFS_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_TIFS_VBUSP_S_BRIDGE_BUSECC_GROUP_2_CHECKER_TYPE,
21123  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_TIFS_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_TIFS_VBUSP_S_BRIDGE_BUSECC_GROUP_2_WIDTH },
21124  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_TIFS_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_TIFS_VBUSP_S_BRIDGE_BUSECC_GROUP_3_CHECKER_TYPE,
21125  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_TIFS_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_TIFS_VBUSP_S_BRIDGE_BUSECC_GROUP_3_WIDTH },
21126  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_TIFS_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_TIFS_VBUSP_S_BRIDGE_BUSECC_GROUP_4_CHECKER_TYPE,
21127  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_TIFS_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_TIFS_VBUSP_S_BRIDGE_BUSECC_GROUP_4_WIDTH },
21128  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_TIFS_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_TIFS_VBUSP_S_BRIDGE_BUSECC_GROUP_5_CHECKER_TYPE,
21129  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_TIFS_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_TIFS_VBUSP_S_BRIDGE_BUSECC_GROUP_5_WIDTH },
21130  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_TIFS_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_TIFS_VBUSP_S_BRIDGE_BUSECC_GROUP_6_CHECKER_TYPE,
21131  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_TIFS_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_TIFS_VBUSP_S_BRIDGE_BUSECC_GROUP_6_WIDTH },
21132  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_TIFS_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_TIFS_VBUSP_S_BRIDGE_BUSECC_GROUP_7_CHECKER_TYPE,
21133  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_TIFS_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_TIFS_VBUSP_S_BRIDGE_BUSECC_GROUP_7_WIDTH },
21134  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_TIFS_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_TIFS_VBUSP_S_BRIDGE_BUSECC_GROUP_8_CHECKER_TYPE,
21135  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_TIFS_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_TIFS_VBUSP_S_BRIDGE_BUSECC_GROUP_8_WIDTH },
21136  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_TIFS_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_TIFS_VBUSP_S_BRIDGE_BUSECC_GROUP_9_CHECKER_TYPE,
21137  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_TIFS_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_TIFS_VBUSP_S_BRIDGE_BUSECC_GROUP_9_WIDTH },
21138  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_TIFS_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_TIFS_VBUSP_S_BRIDGE_BUSECC_GROUP_10_CHECKER_TYPE,
21139  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_TIFS_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_TIFS_VBUSP_S_BRIDGE_BUSECC_GROUP_10_WIDTH },
21140  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_TIFS_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_TIFS_VBUSP_S_BRIDGE_BUSECC_GROUP_11_CHECKER_TYPE,
21141  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_TIFS_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_TIFS_VBUSP_S_BRIDGE_BUSECC_GROUP_11_WIDTH },
21142  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_TIFS_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_TIFS_VBUSP_S_BRIDGE_BUSECC_GROUP_12_CHECKER_TYPE,
21143  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_TIFS_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_TIFS_VBUSP_S_BRIDGE_BUSECC_GROUP_12_WIDTH },
21144 };
21145 
21151 static const SDL_GrpChkConfig_t SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_groupEntries[SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_MAX_NUM_CHECKERS] =
21152 {
21153  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_0_CHECKER_TYPE,
21154  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_0_WIDTH },
21155  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_1_CHECKER_TYPE,
21156  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_1_WIDTH },
21157  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_2_CHECKER_TYPE,
21158  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_2_WIDTH },
21159  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_3_CHECKER_TYPE,
21160  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_3_WIDTH },
21161  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_4_CHECKER_TYPE,
21162  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_4_WIDTH },
21163  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_5_CHECKER_TYPE,
21164  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_5_WIDTH },
21165  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_6_CHECKER_TYPE,
21166  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_6_WIDTH },
21167  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_7_CHECKER_TYPE,
21168  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_7_WIDTH },
21169  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_8_CHECKER_TYPE,
21170  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_8_WIDTH },
21171  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_9_CHECKER_TYPE,
21172  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_9_WIDTH },
21173  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_10_CHECKER_TYPE,
21174  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_10_WIDTH },
21175  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_11_CHECKER_TYPE,
21176  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_11_WIDTH },
21177  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_12_CHECKER_TYPE,
21178  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_12_WIDTH },
21179  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_13_CHECKER_TYPE,
21180  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_13_WIDTH },
21181  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_14_CHECKER_TYPE,
21182  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_14_WIDTH },
21183  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_15_CHECKER_TYPE,
21184  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_15_WIDTH },
21185  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_16_CHECKER_TYPE,
21186  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_16_WIDTH },
21187  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_17_CHECKER_TYPE,
21188  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_17_WIDTH },
21189  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_18_CHECKER_TYPE,
21190  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_18_WIDTH },
21191  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_19_CHECKER_TYPE,
21192  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_19_WIDTH },
21193  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_20_CHECKER_TYPE,
21194  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_20_WIDTH },
21195  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_21_CHECKER_TYPE,
21196  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_21_WIDTH },
21197  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_22_CHECKER_TYPE,
21198  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_22_WIDTH },
21199  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_23_CHECKER_TYPE,
21200  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_23_WIDTH },
21201  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_24_CHECKER_TYPE,
21202  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_24_WIDTH },
21203  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_25_CHECKER_TYPE,
21204  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_25_WIDTH },
21205 };
21206 
21212 static const SDL_GrpChkConfig_t SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_FW_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_groupEntries[SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_FW_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_MAX_NUM_CHECKERS] =
21213 {
21214  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_FW_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_0_CHECKER_TYPE,
21215  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_FW_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_0_WIDTH },
21216  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_FW_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_1_CHECKER_TYPE,
21217  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_FW_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_1_WIDTH },
21218  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_FW_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_2_CHECKER_TYPE,
21219  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_FW_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_2_WIDTH },
21220  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_FW_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_3_CHECKER_TYPE,
21221  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_FW_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_3_WIDTH },
21222  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_FW_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_4_CHECKER_TYPE,
21223  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_FW_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_4_WIDTH },
21224  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_FW_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_5_CHECKER_TYPE,
21225  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_FW_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_5_WIDTH },
21226  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_FW_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_6_CHECKER_TYPE,
21227  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_FW_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_6_WIDTH },
21228  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_FW_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_7_CHECKER_TYPE,
21229  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_FW_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_7_WIDTH },
21230  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_FW_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_8_CHECKER_TYPE,
21231  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_FW_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_8_WIDTH },
21232  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_FW_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_9_CHECKER_TYPE,
21233  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_FW_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_9_WIDTH },
21234  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_FW_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_10_CHECKER_TYPE,
21235  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_FW_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_10_WIDTH },
21236  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_FW_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_11_CHECKER_TYPE,
21237  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_FW_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_11_WIDTH },
21238  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_FW_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_12_CHECKER_TYPE,
21239  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_FW_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_12_WIDTH },
21240  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_FW_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_13_CHECKER_TYPE,
21241  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_FW_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_13_WIDTH },
21242  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_FW_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_14_CHECKER_TYPE,
21243  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_FW_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_14_WIDTH },
21244 };
21245 
21251 static const SDL_GrpChkConfig_t SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_FW_CBASS_IAM62A_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM62A_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_groupEntries[SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_FW_CBASS_IAM62A_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM62A_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS] =
21252 {
21253  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_FW_CBASS_IAM62A_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM62A_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_0_CHECKER_TYPE,
21254  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_FW_CBASS_IAM62A_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM62A_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_0_WIDTH },
21255  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_FW_CBASS_IAM62A_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM62A_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_1_CHECKER_TYPE,
21256  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_FW_CBASS_IAM62A_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM62A_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_1_WIDTH },
21257  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_FW_CBASS_IAM62A_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM62A_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_2_CHECKER_TYPE,
21258  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_FW_CBASS_IAM62A_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM62A_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_2_WIDTH },
21259  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_FW_CBASS_IAM62A_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM62A_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_3_CHECKER_TYPE,
21260  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_FW_CBASS_IAM62A_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM62A_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_3_WIDTH },
21261  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_FW_CBASS_IAM62A_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM62A_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_4_CHECKER_TYPE,
21262  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_FW_CBASS_IAM62A_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM62A_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_4_WIDTH },
21263  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_FW_CBASS_IAM62A_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM62A_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_5_CHECKER_TYPE,
21264  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_FW_CBASS_IAM62A_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM62A_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_5_WIDTH },
21265  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_FW_CBASS_IAM62A_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM62A_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_6_CHECKER_TYPE,
21266  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_FW_CBASS_IAM62A_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM62A_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_6_WIDTH },
21267  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_FW_CBASS_IAM62A_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM62A_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_7_CHECKER_TYPE,
21268  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_FW_CBASS_IAM62A_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM62A_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_7_WIDTH },
21269  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_FW_CBASS_IAM62A_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM62A_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_8_CHECKER_TYPE,
21270  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_FW_CBASS_IAM62A_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM62A_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_8_WIDTH },
21271  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_FW_CBASS_IAM62A_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM62A_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_9_CHECKER_TYPE,
21272  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_FW_CBASS_IAM62A_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM62A_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_9_WIDTH },
21273  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_FW_CBASS_IAM62A_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM62A_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_10_CHECKER_TYPE,
21274  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_FW_CBASS_IAM62A_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM62A_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_10_WIDTH },
21275  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_FW_CBASS_IAM62A_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM62A_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_11_CHECKER_TYPE,
21276  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_FW_CBASS_IAM62A_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM62A_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_11_WIDTH },
21277  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_FW_CBASS_IAM62A_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM62A_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_12_CHECKER_TYPE,
21278  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_FW_CBASS_IAM62A_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM62A_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_12_WIDTH },
21279  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_FW_CBASS_IAM62A_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM62A_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_13_CHECKER_TYPE,
21280  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_FW_CBASS_IAM62A_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM62A_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_13_WIDTH },
21281  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_FW_CBASS_IAM62A_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM62A_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_14_CHECKER_TYPE,
21282  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_FW_CBASS_IAM62A_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM62A_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_14_WIDTH },
21283 };
21284 
21290 static const SDL_GrpChkConfig_t SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_DST_BUSECC_groupEntries[SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS] =
21291 {
21292  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_DST_BUSECC_GROUP_0_CHECKER_TYPE,
21293  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_DST_BUSECC_GROUP_0_WIDTH },
21294  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_DST_BUSECC_GROUP_1_CHECKER_TYPE,
21295  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_DST_BUSECC_GROUP_1_WIDTH },
21296  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_DST_BUSECC_GROUP_2_CHECKER_TYPE,
21297  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_DST_BUSECC_GROUP_2_WIDTH },
21298  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_DST_BUSECC_GROUP_3_CHECKER_TYPE,
21299  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_DST_BUSECC_GROUP_3_WIDTH },
21300 };
21301 
21307 static const SDL_GrpChkConfig_t SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_SRC_BUSECC_groupEntries[SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS] =
21308 {
21309  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_SRC_BUSECC_GROUP_0_CHECKER_TYPE,
21310  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_SRC_BUSECC_GROUP_0_WIDTH },
21311  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_SRC_BUSECC_GROUP_1_CHECKER_TYPE,
21312  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_SRC_BUSECC_GROUP_1_WIDTH },
21313  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_SRC_BUSECC_GROUP_2_CHECKER_TYPE,
21314  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_SRC_BUSECC_GROUP_2_WIDTH },
21315  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_SRC_BUSECC_GROUP_3_CHECKER_TYPE,
21316  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_SRC_BUSECC_GROUP_3_WIDTH },
21317  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_SRC_BUSECC_GROUP_4_CHECKER_TYPE,
21318  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_SRC_BUSECC_GROUP_4_WIDTH },
21319  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_SRC_BUSECC_GROUP_5_CHECKER_TYPE,
21320  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_SRC_BUSECC_GROUP_5_WIDTH },
21321  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_SRC_BUSECC_GROUP_6_CHECKER_TYPE,
21322  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_SRC_BUSECC_GROUP_6_WIDTH },
21323  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_SRC_BUSECC_GROUP_7_CHECKER_TYPE,
21324  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_SRC_BUSECC_GROUP_7_WIDTH },
21325  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_SRC_BUSECC_GROUP_8_CHECKER_TYPE,
21326  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_SRC_BUSECC_GROUP_8_WIDTH },
21327  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_SRC_BUSECC_GROUP_9_CHECKER_TYPE,
21328  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_SRC_BUSECC_GROUP_9_WIDTH },
21329  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_SRC_BUSECC_GROUP_10_CHECKER_TYPE,
21330  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_SRC_BUSECC_GROUP_10_WIDTH },
21331  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_SRC_BUSECC_GROUP_11_CHECKER_TYPE,
21332  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_SRC_BUSECC_GROUP_11_WIDTH },
21333  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_SRC_BUSECC_GROUP_12_CHECKER_TYPE,
21334  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_SRC_BUSECC_GROUP_12_WIDTH },
21335  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_SRC_BUSECC_GROUP_13_CHECKER_TYPE,
21336  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_SRC_BUSECC_GROUP_13_WIDTH },
21337  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_SRC_BUSECC_GROUP_14_CHECKER_TYPE,
21338  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_SRC_BUSECC_GROUP_14_WIDTH },
21339 };
21340 
21346 static const SDL_GrpChkConfig_t SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_DMSS_CFG_DST_BUSECC_groupEntries[SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_DMSS_CFG_DST_BUSECC_MAX_NUM_CHECKERS] =
21347 {
21348  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_DMSS_CFG_DST_BUSECC_GROUP_0_CHECKER_TYPE,
21349  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_DMSS_CFG_DST_BUSECC_GROUP_0_WIDTH },
21350  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_DMSS_CFG_DST_BUSECC_GROUP_1_CHECKER_TYPE,
21351  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_DMSS_CFG_DST_BUSECC_GROUP_1_WIDTH },
21352  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_DMSS_CFG_DST_BUSECC_GROUP_2_CHECKER_TYPE,
21353  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_DMSS_CFG_DST_BUSECC_GROUP_2_WIDTH },
21354  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_DMSS_CFG_DST_BUSECC_GROUP_3_CHECKER_TYPE,
21355  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_DMSS_CFG_DST_BUSECC_GROUP_3_WIDTH },
21356 };
21357 
21363 static const SDL_GrpChkConfig_t SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_DMSS_CFG_SRC_BUSECC_groupEntries[SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_DMSS_CFG_SRC_BUSECC_MAX_NUM_CHECKERS] =
21364 {
21365  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_DMSS_CFG_SRC_BUSECC_GROUP_0_CHECKER_TYPE,
21366  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_DMSS_CFG_SRC_BUSECC_GROUP_0_WIDTH },
21367  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_DMSS_CFG_SRC_BUSECC_GROUP_1_CHECKER_TYPE,
21368  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_DMSS_CFG_SRC_BUSECC_GROUP_1_WIDTH },
21369  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_DMSS_CFG_SRC_BUSECC_GROUP_2_CHECKER_TYPE,
21370  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_DMSS_CFG_SRC_BUSECC_GROUP_2_WIDTH },
21371  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_DMSS_CFG_SRC_BUSECC_GROUP_3_CHECKER_TYPE,
21372  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_DMSS_CFG_SRC_BUSECC_GROUP_3_WIDTH },
21373  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_DMSS_CFG_SRC_BUSECC_GROUP_4_CHECKER_TYPE,
21374  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_DMSS_CFG_SRC_BUSECC_GROUP_4_WIDTH },
21375  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_DMSS_CFG_SRC_BUSECC_GROUP_5_CHECKER_TYPE,
21376  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_DMSS_CFG_SRC_BUSECC_GROUP_5_WIDTH },
21377  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_DMSS_CFG_SRC_BUSECC_GROUP_6_CHECKER_TYPE,
21378  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_DMSS_CFG_SRC_BUSECC_GROUP_6_WIDTH },
21379  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_DMSS_CFG_SRC_BUSECC_GROUP_7_CHECKER_TYPE,
21380  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_DMSS_CFG_SRC_BUSECC_GROUP_7_WIDTH },
21381  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_DMSS_CFG_SRC_BUSECC_GROUP_8_CHECKER_TYPE,
21382  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_DMSS_CFG_SRC_BUSECC_GROUP_8_WIDTH },
21383  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_DMSS_CFG_SRC_BUSECC_GROUP_9_CHECKER_TYPE,
21384  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_DMSS_CFG_SRC_BUSECC_GROUP_9_WIDTH },
21385  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_DMSS_CFG_SRC_BUSECC_GROUP_10_CHECKER_TYPE,
21386  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_DMSS_CFG_SRC_BUSECC_GROUP_10_WIDTH },
21387  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_DMSS_CFG_SRC_BUSECC_GROUP_11_CHECKER_TYPE,
21388  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_DMSS_CFG_SRC_BUSECC_GROUP_11_WIDTH },
21389  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_DMSS_CFG_SRC_BUSECC_GROUP_12_CHECKER_TYPE,
21390  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_DMSS_CFG_SRC_BUSECC_GROUP_12_WIDTH },
21391  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_DMSS_CFG_SRC_BUSECC_GROUP_13_CHECKER_TYPE,
21392  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_DMSS_CFG_SRC_BUSECC_GROUP_13_WIDTH },
21393  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_DMSS_CFG_SRC_BUSECC_GROUP_14_CHECKER_TYPE,
21394  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_DMSS_CFG_SRC_BUSECC_GROUP_14_WIDTH },
21395 };
21396 
21402 static const SDL_GrpChkConfig_t SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_PKTDMA_CRED_DST_BUSECC_groupEntries[SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_PKTDMA_CRED_DST_BUSECC_MAX_NUM_CHECKERS] =
21403 {
21404  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_PKTDMA_CRED_DST_BUSECC_GROUP_0_CHECKER_TYPE,
21405  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_PKTDMA_CRED_DST_BUSECC_GROUP_0_WIDTH },
21406  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_PKTDMA_CRED_DST_BUSECC_GROUP_1_CHECKER_TYPE,
21407  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_PKTDMA_CRED_DST_BUSECC_GROUP_1_WIDTH },
21408  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_PKTDMA_CRED_DST_BUSECC_GROUP_2_CHECKER_TYPE,
21409  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_PKTDMA_CRED_DST_BUSECC_GROUP_2_WIDTH },
21410  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_PKTDMA_CRED_DST_BUSECC_GROUP_3_CHECKER_TYPE,
21411  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_PKTDMA_CRED_DST_BUSECC_GROUP_3_WIDTH },
21412 };
21413 
21419 static const SDL_GrpChkConfig_t SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_PKTDMA_CRED_SRC_BUSECC_groupEntries[SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_PKTDMA_CRED_SRC_BUSECC_MAX_NUM_CHECKERS] =
21420 {
21421  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_PKTDMA_CRED_SRC_BUSECC_GROUP_0_CHECKER_TYPE,
21422  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_PKTDMA_CRED_SRC_BUSECC_GROUP_0_WIDTH },
21423  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_PKTDMA_CRED_SRC_BUSECC_GROUP_1_CHECKER_TYPE,
21424  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_PKTDMA_CRED_SRC_BUSECC_GROUP_1_WIDTH },
21425  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_PKTDMA_CRED_SRC_BUSECC_GROUP_2_CHECKER_TYPE,
21426  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_PKTDMA_CRED_SRC_BUSECC_GROUP_2_WIDTH },
21427  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_PKTDMA_CRED_SRC_BUSECC_GROUP_3_CHECKER_TYPE,
21428  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_PKTDMA_CRED_SRC_BUSECC_GROUP_3_WIDTH },
21429  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_PKTDMA_CRED_SRC_BUSECC_GROUP_4_CHECKER_TYPE,
21430  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_PKTDMA_CRED_SRC_BUSECC_GROUP_4_WIDTH },
21431  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_PKTDMA_CRED_SRC_BUSECC_GROUP_5_CHECKER_TYPE,
21432  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_PKTDMA_CRED_SRC_BUSECC_GROUP_5_WIDTH },
21433  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_PKTDMA_CRED_SRC_BUSECC_GROUP_6_CHECKER_TYPE,
21434  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_PKTDMA_CRED_SRC_BUSECC_GROUP_6_WIDTH },
21435  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_PKTDMA_CRED_SRC_BUSECC_GROUP_7_CHECKER_TYPE,
21436  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_PKTDMA_CRED_SRC_BUSECC_GROUP_7_WIDTH },
21437  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_PKTDMA_CRED_SRC_BUSECC_GROUP_8_CHECKER_TYPE,
21438  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_PKTDMA_CRED_SRC_BUSECC_GROUP_8_WIDTH },
21439  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_PKTDMA_CRED_SRC_BUSECC_GROUP_9_CHECKER_TYPE,
21440  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_PKTDMA_CRED_SRC_BUSECC_GROUP_9_WIDTH },
21441  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_PKTDMA_CRED_SRC_BUSECC_GROUP_10_CHECKER_TYPE,
21442  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_PKTDMA_CRED_SRC_BUSECC_GROUP_10_WIDTH },
21443  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_PKTDMA_CRED_SRC_BUSECC_GROUP_11_CHECKER_TYPE,
21444  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_PKTDMA_CRED_SRC_BUSECC_GROUP_11_WIDTH },
21445  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_PKTDMA_CRED_SRC_BUSECC_GROUP_12_CHECKER_TYPE,
21446  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_PKTDMA_CRED_SRC_BUSECC_GROUP_12_WIDTH },
21447  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_PKTDMA_CRED_SRC_BUSECC_GROUP_13_CHECKER_TYPE,
21448  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_PKTDMA_CRED_SRC_BUSECC_GROUP_13_WIDTH },
21449  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_PKTDMA_CRED_SRC_BUSECC_GROUP_14_CHECKER_TYPE,
21450  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_PKTDMA_CRED_SRC_BUSECC_GROUP_14_WIDTH },
21451 };
21456 static const SDL_RAMIdEntry_t SDL_PSCSS0_SAM62A_MAIN_PSC_WRAP_ECC_AGGR_RamIdTable[SDL_PSCSS0_SAM62A_MAIN_PSC_WRAP_ECC_AGGR_NUM_RAMS] =
21457 {
21458  { SDL_PSCSS0_SAM62A_MAIN_PSC_WRAP_ECC_AGGR_AM62A_PSC_CHFW_CBASS_DST_FW_CH_VBUSP_TABLE_RAM_ID,
21459  SDL_PSCSS0_SAM62A_MAIN_PSC_WRAP_ECC_AGGR_AM62A_PSC_CHFW_CBASS_DST_FW_CH_VBUSP_TABLE_INJECT_TYPE,
21460  SDL_PSCSS0_SAM62A_MAIN_PSC_WRAP_ECC_AGGR_AM62A_PSC_CHFW_CBASS_DST_FW_CH_VBUSP_TABLE_ECC_TYPE,
21461  0u,
21462  NULL },
21463 };
21464 
21469 static const SDL_RAMIdEntry_t SDL_PSRAMECC0_PSRAM256X32E_ECC_AGGR_RamIdTable[SDL_PSRAMECC0_PSRAM256X32E_ECC_AGGR_NUM_RAMS] =
21470 {
21471  { SDL_PSRAMECC0_PSRAM256X32E_ECC_AGGR_PSRAM256X32E_PSRAM0_ECC_RAM_ID,
21472  SDL_PSRAMECC0_PSRAM256X32E_ECC_AGGR_PSRAM256X32E_PSRAM0_ECC_INJECT_TYPE,
21473  SDL_PSRAMECC0_PSRAM256X32E_ECC_AGGR_PSRAM256X32E_PSRAM0_ECC_ECC_TYPE,
21474  0u,
21475  NULL },
21476 };
21477 
21482 static const SDL_RAMIdEntry_t SDL_PSRAMECC1_PSRAM256X32E_ECC_AGGR_RamIdTable[SDL_PSRAMECC1_PSRAM256X32E_ECC_AGGR_NUM_RAMS] =
21483 {
21484  { SDL_PSRAMECC1_PSRAM256X32E_ECC_AGGR_PSRAM256X32E_PSRAM0_ECC_RAM_ID,
21485  SDL_PSRAMECC1_PSRAM256X32E_ECC_AGGR_PSRAM256X32E_PSRAM0_ECC_INJECT_TYPE,
21486  SDL_PSRAMECC1_PSRAM256X32E_ECC_AGGR_PSRAM256X32E_PSRAM0_ECC_ECC_TYPE,
21487  0u,
21488  NULL },
21489 };
21490 
21495 static const SDL_RAMIdEntry_t SDL_MSRAM_64K0_MSRAM2KX256E_ECC_AGGR_RamIdTable[SDL_MSRAM_64K0_MSRAM2KX256E_ECC_AGGR_NUM_RAMS] =
21496 {
21497  { SDL_MSRAM_64K0_MSRAM2KX256E_ECC_AGGR_MSRAM2KX256E_MSRAM0_ECC0_RAM_ID,
21498  SDL_MSRAM_64K0_MSRAM2KX256E_ECC_AGGR_MSRAM2KX256E_MSRAM0_ECC0_INJECT_TYPE,
21499  SDL_MSRAM_64K0_MSRAM2KX256E_ECC_AGGR_MSRAM2KX256E_MSRAM0_ECC0_ECC_TYPE,
21500  0u,
21501  NULL },
21502 };
21503 
21508 static const SDL_RAMIdEntry_t SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_RamIdTable[SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_NUM_RAMS] =
21509 {
21510  { SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISAM62A_DM_MCU_ECC_AGGR_WKUP_1_CFG_P2P_BRIDGE_ISAM62A_DM_MCU_ECC_AGGR_WKUP_1_CFG_BRIDGE_DST_BUSECC_RAM_ID,
21511  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISAM62A_DM_MCU_ECC_AGGR_WKUP_1_CFG_P2P_BRIDGE_ISAM62A_DM_MCU_ECC_AGGR_WKUP_1_CFG_BRIDGE_DST_BUSECC_INJECT_TYPE,
21512  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISAM62A_DM_MCU_ECC_AGGR_WKUP_1_CFG_P2P_BRIDGE_ISAM62A_DM_MCU_ECC_AGGR_WKUP_1_CFG_BRIDGE_DST_BUSECC_ECC_TYPE,
21513  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISAM62A_DM_MCU_ECC_AGGR_WKUP_1_CFG_P2P_BRIDGE_ISAM62A_DM_MCU_ECC_AGGR_WKUP_1_CFG_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS,
21514  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISAM62A_DM_MCU_ECC_AGGR_WKUP_1_CFG_P2P_BRIDGE_ISAM62A_DM_MCU_ECC_AGGR_WKUP_1_CFG_BRIDGE_DST_BUSECC_groupEntries },
21515  { SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_RAM_ID,
21516  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_INJECT_TYPE,
21517  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_ECC_TYPE,
21518  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
21519  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_groupEntries },
21520 { SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_RAM_ID,
21521  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_INJECT_TYPE,
21522  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_ECC_TYPE,
21523  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
21524  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_groupEntries },
21525  { SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_SAM62A_DM_MCU_ECC_AGGR_EDC_CTRL_RAM_ID,
21526  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_SAM62A_DM_MCU_ECC_AGGR_EDC_CTRL_INJECT_TYPE,
21527  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_SAM62A_DM_MCU_ECC_AGGR_EDC_CTRL_ECC_TYPE,
21528  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_SAM62A_DM_MCU_ECC_AGGR_EDC_CTRL_MAX_NUM_CHECKERS,
21529  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_SAM62A_DM_MCU_ECC_AGGR_EDC_CTRL_groupEntries },
21530 };
21531 
21536 static const SDL_RAMIdEntry_t SDL_DMASS1_DMSS_CSI_AM62A_ECCAGGR_RamIdTable[SDL_DMASS1_DMSS_CSI_AM62A_ECCAGGR_NUM_RAMS] =
21537 {
21538  { SDL_DMASS1_DMSS_CSI_AM62A_ECCAGGR_DMSS_CSI_AM62A_BCDMA_CFG_CONFIG_RAM_ID,
21539  SDL_DMASS1_DMSS_CSI_AM62A_ECCAGGR_DMSS_CSI_AM62A_BCDMA_CFG_CONFIG_INJECT_TYPE,
21540  SDL_DMASS1_DMSS_CSI_AM62A_ECCAGGR_DMSS_CSI_AM62A_BCDMA_CFG_CONFIG_ECC_TYPE,
21541  0u,
21542  NULL },
21543  { SDL_DMASS1_DMSS_CSI_AM62A_ECCAGGR_DMSS_CSI_AM62A_BCDMA_CFG_STATE_RAM_ID,
21544  SDL_DMASS1_DMSS_CSI_AM62A_ECCAGGR_DMSS_CSI_AM62A_BCDMA_CFG_STATE_INJECT_TYPE,
21545  SDL_DMASS1_DMSS_CSI_AM62A_ECCAGGR_DMSS_CSI_AM62A_BCDMA_CFG_STATE_ECC_TYPE,
21546  0u,
21547  NULL },
21548  { SDL_DMASS1_DMSS_CSI_AM62A_ECCAGGR_DMSS_CSI_AM62A_BCDMA_RPCFIFO_F0_RAM_ID,
21549  SDL_DMASS1_DMSS_CSI_AM62A_ECCAGGR_DMSS_CSI_AM62A_BCDMA_RPCFIFO_F0_INJECT_TYPE,
21550  SDL_DMASS1_DMSS_CSI_AM62A_ECCAGGR_DMSS_CSI_AM62A_BCDMA_RPCFIFO_F0_ECC_TYPE,
21551  0u,
21552  NULL },
21553  { SDL_DMASS1_DMSS_CSI_AM62A_ECCAGGR_DMSS_CSI_AM62A_BCDMA_RPCFIFO_F1_RAM_ID,
21554  SDL_DMASS1_DMSS_CSI_AM62A_ECCAGGR_DMSS_CSI_AM62A_BCDMA_RPCFIFO_F1_INJECT_TYPE,
21555  SDL_DMASS1_DMSS_CSI_AM62A_ECCAGGR_DMSS_CSI_AM62A_BCDMA_RPCFIFO_F1_ECC_TYPE,
21556  0u,
21557  NULL },
21558  { SDL_DMASS1_DMSS_CSI_AM62A_ECCAGGR_DMSS_CSI_AM62A_BCDMA_RPCFIFO_WC_RAM_ID,
21559  SDL_DMASS1_DMSS_CSI_AM62A_ECCAGGR_DMSS_CSI_AM62A_BCDMA_RPCFIFO_WC_INJECT_TYPE,
21560  SDL_DMASS1_DMSS_CSI_AM62A_ECCAGGR_DMSS_CSI_AM62A_BCDMA_RPCFIFO_WC_ECC_TYPE,
21561  0u,
21562  NULL },
21563  { SDL_DMASS1_DMSS_CSI_AM62A_ECCAGGR_DMSS_CSI_AM62A_BCDMA_STATS_STSR0_RAM_ID,
21564  SDL_DMASS1_DMSS_CSI_AM62A_ECCAGGR_DMSS_CSI_AM62A_BCDMA_STATS_STSR0_INJECT_TYPE,
21565  SDL_DMASS1_DMSS_CSI_AM62A_ECCAGGR_DMSS_CSI_AM62A_BCDMA_STATS_STSR0_ECC_TYPE,
21566  0u,
21567  NULL },
21568  { SDL_DMASS1_DMSS_CSI_AM62A_ECCAGGR_DMSS_CSI_AM62A_BCDMA_RINGOCC_CNTR_RAM_ID,
21569  SDL_DMASS1_DMSS_CSI_AM62A_ECCAGGR_DMSS_CSI_AM62A_BCDMA_RINGOCC_CNTR_INJECT_TYPE,
21570  SDL_DMASS1_DMSS_CSI_AM62A_ECCAGGR_DMSS_CSI_AM62A_BCDMA_RINGOCC_CNTR_ECC_TYPE,
21571  0u,
21572  NULL },
21573  { SDL_DMASS1_DMSS_CSI_AM62A_ECCAGGR_DMSS_CSI_AM62A_INTAGGR_STATREG_SR_SPRAM_8X128_SWW_SR_RAM_ID,
21574  SDL_DMASS1_DMSS_CSI_AM62A_ECCAGGR_DMSS_CSI_AM62A_INTAGGR_STATREG_SR_SPRAM_8X128_SWW_SR_INJECT_TYPE,
21575  SDL_DMASS1_DMSS_CSI_AM62A_ECCAGGR_DMSS_CSI_AM62A_INTAGGR_STATREG_SR_SPRAM_8X128_SWW_SR_ECC_TYPE,
21576  0u,
21577  NULL },
21578  { SDL_DMASS1_DMSS_CSI_AM62A_ECCAGGR_DMSS_CSI_AM62A_INTAGGR_COMMON_IM_TPRAM_153X34_SWW_SR_RAM_ID,
21579  SDL_DMASS1_DMSS_CSI_AM62A_ECCAGGR_DMSS_CSI_AM62A_INTAGGR_COMMON_IM_TPRAM_153X34_SWW_SR_INJECT_TYPE,
21580  SDL_DMASS1_DMSS_CSI_AM62A_ECCAGGR_DMSS_CSI_AM62A_INTAGGR_COMMON_IM_TPRAM_153X34_SWW_SR_ECC_TYPE,
21581  0u,
21582  NULL },
21583 };
21584 
21589 static const SDL_RAMIdEntry_t SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_RamIdTable[SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_NUM_RAMS] =
21590 {
21591  { SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_ECC0_RAM_ID,
21592  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_ECC0_INJECT_TYPE,
21593  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_ECC0_ECC_TYPE,
21594  0u,
21595  NULL },
21596  { SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_RAM_ID,
21597  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_INJECT_TYPE,
21598  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_ECC_TYPE,
21599  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_MAX_NUM_CHECKERS,
21600  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_groupEntries },
21601  { SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_ECC_AGGR_EDC_CTRL_RAM_ID,
21602  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_ECC_AGGR_EDC_CTRL_INJECT_TYPE,
21603  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_ECC_AGGR_EDC_CTRL_ECC_TYPE,
21604  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_ECC_AGGR_EDC_CTRL_MAX_NUM_CHECKERS,
21605  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_ECC_AGGR_EDC_CTRL_groupEntries },
21606 };
21607 
21612 static const SDL_RAMIdEntry_t SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_RamIdTable[SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_NUM_RAMS] =
21613 {
21614  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_ECCAGGR_EDC_CTRL_RAM_ID,
21615  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_ECCAGGR_EDC_CTRL_INJECT_TYPE,
21616  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_ECCAGGR_EDC_CTRL_ECC_TYPE,
21617  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_ECCAGGR_EDC_CTRL_MAX_NUM_CHECKERS,
21618  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_ECCAGGR_EDC_CTRL_groupEntries },
21619  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_RAM_ID,
21620  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_INJECT_TYPE,
21621  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_ECC_TYPE,
21622  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_MAX_NUM_CHECKERS,
21623  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_groupEntries },
21624  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_VBUSP_P2P_BRIDGE_EDC_CTRL_0_RAM_ID,
21625  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_VBUSP_P2P_BRIDGE_EDC_CTRL_0_INJECT_TYPE,
21626  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_VBUSP_P2P_BRIDGE_EDC_CTRL_0_ECC_TYPE,
21627  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_VBUSP_P2P_BRIDGE_EDC_CTRL_0_MAX_NUM_CHECKERS,
21628  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_VBUSP_P2P_BRIDGE_EDC_CTRL_0_groupEntries },
21629  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_RAM_ID,
21630  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_INJECT_TYPE,
21631  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_ECC_TYPE,
21632  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_MAX_NUM_CHECKERS,
21633  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_groupEntries },
21634 };
21635 
21640 static const SDL_RAMIdEntry_t SDL_FSS0_FSS_UL_OSPI0_OSPI_WRAP_ECC_AGGR_RamIdTable[SDL_FSS0_FSS_UL_OSPI0_OSPI_WRAP_ECC_AGGR_NUM_RAMS] =
21641 {
21642  { SDL_FSS0_FSS_UL_OSPI0_OSPI_WRAP_ECC_AGGR_OSPI_OSPI_WRAP_SRAM_RAM_ID,
21643  SDL_FSS0_FSS_UL_OSPI0_OSPI_WRAP_ECC_AGGR_OSPI_OSPI_WRAP_SRAM_INJECT_TYPE,
21644  SDL_FSS0_FSS_UL_OSPI0_OSPI_WRAP_ECC_AGGR_OSPI_OSPI_WRAP_SRAM_ECC_TYPE,
21645  0u,
21646  NULL },
21647 };
21648 
21653 static const SDL_RAMIdEntry_t SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_RamIdTable[SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_NUM_RAMS] =
21654 {
21655  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_ITAG_RAM0_RAM_ID,
21656  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_ITAG_RAM0_INJECT_TYPE,
21657  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_ITAG_RAM0_ECC_TYPE,
21658  0u,
21659  NULL },
21660  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_ITAG_RAM1_RAM_ID,
21661  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_ITAG_RAM1_INJECT_TYPE,
21662  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_ITAG_RAM1_ECC_TYPE,
21663  0u,
21664  NULL },
21665  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_ITAG_RAM2_RAM_ID,
21666  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_ITAG_RAM2_INJECT_TYPE,
21667  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_ITAG_RAM2_ECC_TYPE,
21668  0u,
21669  NULL },
21670  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_ITAG_RAM3_RAM_ID,
21671  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_ITAG_RAM3_INJECT_TYPE,
21672  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_ITAG_RAM3_ECC_TYPE,
21673  0u,
21674  NULL },
21675  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_IDATA_BANK0_RAM_ID,
21676  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_IDATA_BANK0_INJECT_TYPE,
21677  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_IDATA_BANK0_ECC_TYPE,
21678  0u,
21679  NULL },
21680  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_IDATA_BANK1_RAM_ID,
21681  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_IDATA_BANK1_INJECT_TYPE,
21682  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_IDATA_BANK1_ECC_TYPE,
21683  0u,
21684  NULL },
21685  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_IDATA_BANK2_RAM_ID,
21686  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_IDATA_BANK2_INJECT_TYPE,
21687  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_IDATA_BANK2_ECC_TYPE,
21688  0u,
21689  NULL },
21690  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_IDATA_BANK3_RAM_ID,
21691  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_IDATA_BANK3_INJECT_TYPE,
21692  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_IDATA_BANK3_ECC_TYPE,
21693  0u,
21694  NULL },
21695  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_DTAG_RAM0_RAM_ID,
21696  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_DTAG_RAM0_INJECT_TYPE,
21697  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_DTAG_RAM0_ECC_TYPE,
21698  0u,
21699  NULL },
21700  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_DTAG_RAM1_RAM_ID,
21701  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_DTAG_RAM1_INJECT_TYPE,
21702  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_DTAG_RAM1_ECC_TYPE,
21703  0u,
21704  NULL },
21705  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_DTAG_RAM2_RAM_ID,
21706  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_DTAG_RAM2_INJECT_TYPE,
21707  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_DTAG_RAM2_ECC_TYPE,
21708  0u,
21709  NULL },
21710  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_DTAG_RAM3_RAM_ID,
21711  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_DTAG_RAM3_INJECT_TYPE,
21712  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_DTAG_RAM3_ECC_TYPE,
21713  0u,
21714  NULL },
21715  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_DDIRTY_RAM_RAM_ID,
21716  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_DDIRTY_RAM_INJECT_TYPE,
21717  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_DDIRTY_RAM_ECC_TYPE,
21718  0u,
21719  NULL },
21720  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_DDATA_RAM0_RAM_ID,
21721  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_DDATA_RAM0_INJECT_TYPE,
21722  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_DDATA_RAM0_ECC_TYPE,
21723  0u,
21724  NULL },
21725  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_DDATA_RAM1_RAM_ID,
21726  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_DDATA_RAM1_INJECT_TYPE,
21727  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_DDATA_RAM1_ECC_TYPE,
21728  0u,
21729  NULL },
21730  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_DDATA_RAM2_RAM_ID,
21731  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_DDATA_RAM2_INJECT_TYPE,
21732  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_DDATA_RAM2_ECC_TYPE,
21733  0u,
21734  NULL },
21735  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_DDATA_RAM3_RAM_ID,
21736  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_DDATA_RAM3_INJECT_TYPE,
21737  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_DDATA_RAM3_ECC_TYPE,
21738  0u,
21739  NULL },
21740  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_DDATA_RAM4_RAM_ID,
21741  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_DDATA_RAM4_INJECT_TYPE,
21742  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_DDATA_RAM4_ECC_TYPE,
21743  0u,
21744  NULL },
21745  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_DDATA_RAM5_RAM_ID,
21746  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_DDATA_RAM5_INJECT_TYPE,
21747  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_DDATA_RAM5_ECC_TYPE,
21748  0u,
21749  NULL },
21750  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_DDATA_RAM6_RAM_ID,
21751  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_DDATA_RAM6_INJECT_TYPE,
21752  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_DDATA_RAM6_ECC_TYPE,
21753  0u,
21754  NULL },
21755  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_DDATA_RAM7_RAM_ID,
21756  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_DDATA_RAM7_INJECT_TYPE,
21757  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_DDATA_RAM7_ECC_TYPE,
21758  0u,
21759  NULL },
21760  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_ATCM0_BANK0_RAM_ID,
21761  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_ATCM0_BANK0_INJECT_TYPE,
21762  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_ATCM0_BANK0_ECC_TYPE,
21763  0u,
21764  NULL },
21765  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_ATCM0_BANK1_RAM_ID,
21766  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_ATCM0_BANK1_INJECT_TYPE,
21767  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_ATCM0_BANK1_ECC_TYPE,
21768  0u,
21769  NULL },
21770  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_B0TCM0_BANK0_RAM_ID,
21771  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_B0TCM0_BANK0_INJECT_TYPE,
21772  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_B0TCM0_BANK0_ECC_TYPE,
21773  0u,
21774  NULL },
21775  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_B0TCM0_BANK1_RAM_ID,
21776  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_B0TCM0_BANK1_INJECT_TYPE,
21777  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_B0TCM0_BANK1_ECC_TYPE,
21778  0u,
21779  NULL },
21780  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_B1TCM0_BANK0_RAM_ID,
21781  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_B1TCM0_BANK0_INJECT_TYPE,
21782  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_B1TCM0_BANK0_ECC_TYPE,
21783  0u,
21784  NULL },
21785  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_B1TCM0_BANK1_RAM_ID,
21786  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_B1TCM0_BANK1_INJECT_TYPE,
21787  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_B1TCM0_BANK1_ECC_TYPE,
21788  0u,
21789  NULL },
21790  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_KS_VIM_RAMECC_RAM_ID,
21791  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_KS_VIM_RAMECC_INJECT_TYPE,
21792  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_KS_VIM_RAMECC_ECC_TYPE,
21793  0u,
21794  NULL },
21795  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_VBUSM2AXI_EDC_RAM_ID,
21796  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_VBUSM2AXI_EDC_INJECT_TYPE,
21797  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_VBUSM2AXI_EDC_ECC_TYPE,
21798  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_VBUSM2AXI_EDC_MAX_NUM_CHECKERS,
21799  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_VBUSM2AXI_EDC_groupEntries },
21800  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_AXI2VBUSM_MEM_MST_RAMECC_RAM_ID,
21801  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_AXI2VBUSM_MEM_MST_RAMECC_INJECT_TYPE,
21802  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_AXI2VBUSM_MEM_MST_RAMECC_ECC_TYPE,
21803  0u,
21804  NULL },
21805  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_RAM_ID,
21806  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_INJECT_TYPE,
21807  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_ECC_TYPE,
21808  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_MAX_NUM_CHECKERS,
21809  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_groupEntries },
21810  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_0_RAM_ID,
21811  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_0_INJECT_TYPE,
21812  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_0_ECC_TYPE,
21813  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_0_MAX_NUM_CHECKERS,
21814  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_0_groupEntries },
21815  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_SCRP_EDC_RAM_ID,
21816  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_SCRP_EDC_INJECT_TYPE,
21817  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_SCRP_EDC_ECC_TYPE,
21818  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_SCRP_EDC_MAX_NUM_CHECKERS,
21819  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_SCRP_EDC_groupEntries },
21820  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_RAM_ID,
21821  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_INJECT_TYPE,
21822  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_ECC_TYPE,
21823  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
21824  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_groupEntries },
21825  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_ECC_AGGR_EDC_CTRL_RAM_ID,
21826  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_ECC_AGGR_EDC_CTRL_INJECT_TYPE,
21827  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_ECC_AGGR_EDC_CTRL_ECC_TYPE,
21828  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_ECC_AGGR_EDC_CTRL_MAX_NUM_CHECKERS,
21829  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_ECC_AGGR_EDC_CTRL_groupEntries },
21830 };
21831 
21836 static const SDL_RAMIdEntry_t SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR_RamIdTable[SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR_NUM_RAMS] =
21837 {
21838  { SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR_ALE_RAM_RAM_ID,
21839  SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR_ALE_RAM_INJECT_TYPE,
21840  SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR_ALE_RAM_ECC_TYPE,
21841  0u,
21842  NULL },
21843  { SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR_CPSW_3GU_CORE_ECC_ECC_CTRL1_RAM_ID,
21844  SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR_CPSW_3GU_CORE_ECC_ECC_CTRL1_INJECT_TYPE,
21845  SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR_CPSW_3GU_CORE_ECC_ECC_CTRL1_ECC_TYPE,
21846  0u,
21847  NULL },
21848  { SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR_CPSW_3GU_CORE_ECC_ECC_CTRL2_RAM_ID,
21849  SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR_CPSW_3GU_CORE_ECC_ECC_CTRL2_INJECT_TYPE,
21850  SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR_CPSW_3GU_CORE_ECC_ECC_CTRL2_ECC_TYPE,
21851  0u,
21852  NULL },
21853  { SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR_CPSW_3GU_CORE_ECC_ECC_CTRL3_RAM_ID,
21854  SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR_CPSW_3GU_CORE_ECC_ECC_CTRL3_INJECT_TYPE,
21855  SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR_CPSW_3GU_CORE_ECC_ECC_CTRL3_ECC_TYPE,
21856  0u,
21857  NULL },
21858  { SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR_CPSW_3GU_CORE_ECC_ECC_CTRL4_RAM_ID,
21859  SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR_CPSW_3GU_CORE_ECC_ECC_CTRL4_INJECT_TYPE,
21860  SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR_CPSW_3GU_CORE_ECC_ECC_CTRL4_ECC_TYPE,
21861  0u,
21862  NULL },
21863  { SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR_CPSW_3GU_CORE_ECC_ECC_CTRL5_RAM_ID,
21864  SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR_CPSW_3GU_CORE_ECC_ECC_CTRL5_INJECT_TYPE,
21865  SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR_CPSW_3GU_CORE_ECC_ECC_CTRL5_ECC_TYPE,
21866  0u,
21867  NULL },
21868  { SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR_CPSW_3GU_CORE_ECC_ECC_CTRL6_RAM_ID,
21869  SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR_CPSW_3GU_CORE_ECC_ECC_CTRL6_INJECT_TYPE,
21870  SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR_CPSW_3GU_CORE_ECC_ECC_CTRL6_ECC_TYPE,
21871  0u,
21872  NULL },
21873  { SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR_EST_RAM_RAM_ID,
21874  SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR_EST_RAM_INJECT_TYPE,
21875  SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR_EST_RAM_ECC_TYPE,
21876  0u,
21877  NULL },
21878 };
21879 
21884 static const SDL_RAMIdEntry_t SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_RamIdTable[SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_NUM_RAMS] =
21885 {
21886  { SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_ECC0_RAM_ID,
21887  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_ECC0_INJECT_TYPE,
21888  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_ECC0_ECC_TYPE,
21889  0u,
21890  NULL },
21891  { SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_RAM_ID,
21892  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_INJECT_TYPE,
21893  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_ECC_TYPE,
21894  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_MAX_NUM_CHECKERS,
21895  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_groupEntries },
21896  { SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_ECC_AGGR_EDC_CTRL_RAM_ID,
21897  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_ECC_AGGR_EDC_CTRL_INJECT_TYPE,
21898  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_ECC_AGGR_EDC_CTRL_ECC_TYPE,
21899  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_ECC_AGGR_EDC_CTRL_MAX_NUM_CHECKERS,
21900  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_ECC_AGGR_EDC_CTRL_groupEntries },
21901 };
21902 
21907 static const SDL_RAMIdEntry_t SDL_GICSS0_GIC500SS_1_4_ECC_AGGR_RamIdTable[SDL_GICSS0_GIC500SS_1_4_ECC_AGGR_NUM_RAMS] =
21908 {
21909  { SDL_GICSS0_GIC500SS_1_4_ECC_AGGR_ICB_RAMECC_RAM_ID,
21910  SDL_GICSS0_GIC500SS_1_4_ECC_AGGR_ICB_RAMECC_INJECT_TYPE,
21911  SDL_GICSS0_GIC500SS_1_4_ECC_AGGR_ICB_RAMECC_ECC_TYPE,
21912  0u,
21913  NULL },
21914  { SDL_GICSS0_GIC500SS_1_4_ECC_AGGR_ITE_RAMECC_RAM_ID,
21915  SDL_GICSS0_GIC500SS_1_4_ECC_AGGR_ITE_RAMECC_INJECT_TYPE,
21916  SDL_GICSS0_GIC500SS_1_4_ECC_AGGR_ITE_RAMECC_ECC_TYPE,
21917  0u,
21918  NULL },
21919  { SDL_GICSS0_GIC500SS_1_4_ECC_AGGR_LPI_RAMECC_RAM_ID,
21920  SDL_GICSS0_GIC500SS_1_4_ECC_AGGR_LPI_RAMECC_INJECT_TYPE,
21921  SDL_GICSS0_GIC500SS_1_4_ECC_AGGR_LPI_RAMECC_ECC_TYPE,
21922  0u,
21923  NULL },
21924 };
21925 
21930 static const SDL_RAMIdEntry_t SDL_ECC_AGGR1_SAM62A_SEC_MCU_ECC_AGGR_RamIdTable[SDL_ECC_AGGR1_SAM62A_SEC_MCU_ECC_AGGR_NUM_RAMS] =
21931 {
21932  { SDL_ECC_AGGR1_SAM62A_SEC_MCU_ECC_AGGR_AM62A_MAIN_FW_CBASS_IAM62A_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM62A_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_RAM_ID,
21933  SDL_ECC_AGGR1_SAM62A_SEC_MCU_ECC_AGGR_AM62A_MAIN_FW_CBASS_IAM62A_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM62A_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_INJECT_TYPE,
21934  SDL_ECC_AGGR1_SAM62A_SEC_MCU_ECC_AGGR_AM62A_MAIN_FW_CBASS_IAM62A_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM62A_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_ECC_TYPE,
21935  SDL_ECC_AGGR1_SAM62A_SEC_MCU_ECC_AGGR_AM62A_MAIN_FW_CBASS_IAM62A_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM62A_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS,
21936  SDL_ECC_AGGR1_SAM62A_SEC_MCU_ECC_AGGR_AM62A_MAIN_FW_CBASS_IAM62A_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM62A_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_groupEntries },
21937 };
21938 
21943 static const SDL_RAMIdEntry_t SDL_DMASS0_DMSS_AM62A_ECCAGGR_RamIdTable[SDL_DMASS0_DMSS_AM62A_ECCAGGR_NUM_RAMS] =
21944 {
21945  { SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_PKTDMA_CFG_CONFIG_RAM_ID,
21946  SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_PKTDMA_CFG_CONFIG_INJECT_TYPE,
21947  SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_PKTDMA_CFG_CONFIG_ECC_TYPE,
21948  0u,
21949  NULL },
21950  { SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_PKTDMA_CFG_STATE_RAM_ID,
21951  SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_PKTDMA_CFG_STATE_INJECT_TYPE,
21952  SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_PKTDMA_CFG_STATE_ECC_TYPE,
21953  0u,
21954  NULL },
21955  { SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_PKTDMA_TPCFIFO_F0_RAM_ID,
21956  SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_PKTDMA_TPCFIFO_F0_INJECT_TYPE,
21957  SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_PKTDMA_TPCFIFO_F0_ECC_TYPE,
21958  0u,
21959  NULL },
21960  { SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_PKTDMA_TPCFIFO_F1_RAM_ID,
21961  SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_PKTDMA_TPCFIFO_F1_INJECT_TYPE,
21962  SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_PKTDMA_TPCFIFO_F1_ECC_TYPE,
21963  0u,
21964  NULL },
21965  { SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_PKTDMA_RPCFIFO_F0_RAM_ID,
21966  SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_PKTDMA_RPCFIFO_F0_INJECT_TYPE,
21967  SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_PKTDMA_RPCFIFO_F0_ECC_TYPE,
21968  0u,
21969  NULL },
21970  { SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_PKTDMA_RPCFIFO_F1_RAM_ID,
21971  SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_PKTDMA_RPCFIFO_F1_INJECT_TYPE,
21972  SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_PKTDMA_RPCFIFO_F1_ECC_TYPE,
21973  0u,
21974  NULL },
21975  { SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_PKTDMA_RPCFIFO_WC_RAM_ID,
21976  SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_PKTDMA_RPCFIFO_WC_INJECT_TYPE,
21977  SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_PKTDMA_RPCFIFO_WC_ECC_TYPE,
21978  0u,
21979  NULL },
21980  { SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_PKTDMA_STATS_STST0_RAM_ID,
21981  SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_PKTDMA_STATS_STST0_INJECT_TYPE,
21982  SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_PKTDMA_STATS_STST0_ECC_TYPE,
21983  0u,
21984  NULL },
21985  { SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_PKTDMA_STATS_STSR0_RAM_ID,
21986  SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_PKTDMA_STATS_STSR0_INJECT_TYPE,
21987  SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_PKTDMA_STATS_STSR0_ECC_TYPE,
21988  0u,
21989  NULL },
21990  { SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_PKTDMA_RINGOCC_CNTR_RAM_ID,
21991  SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_PKTDMA_RINGOCC_CNTR_INJECT_TYPE,
21992  SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_PKTDMA_RINGOCC_CNTR_ECC_TYPE,
21993  0u,
21994  NULL },
21995  { SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_BCDMA_CFG_CONFIG_RAM_ID,
21996  SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_BCDMA_CFG_CONFIG_INJECT_TYPE,
21997  SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_BCDMA_CFG_CONFIG_ECC_TYPE,
21998  0u,
21999  NULL },
22000  { SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_BCDMA_CFG_STATE_RAM_ID,
22001  SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_BCDMA_CFG_STATE_INJECT_TYPE,
22002  SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_BCDMA_CFG_STATE_ECC_TYPE,
22003  0u,
22004  NULL },
22005  { SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_BCDMA_PCFIFO_DFIFO_F0_RAM_ID,
22006  SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_BCDMA_PCFIFO_DFIFO_F0_INJECT_TYPE,
22007  SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_BCDMA_PCFIFO_DFIFO_F0_ECC_TYPE,
22008  0u,
22009  NULL },
22010  { SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_BCDMA_PCFIFO_DFIFO_F1_RAM_ID,
22011  SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_BCDMA_PCFIFO_DFIFO_F1_INJECT_TYPE,
22012  SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_BCDMA_PCFIFO_DFIFO_F1_ECC_TYPE,
22013  0u,
22014  NULL },
22015  { SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_BCDMA_TPCFIFO_F0_RAM_ID,
22016  SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_BCDMA_TPCFIFO_F0_INJECT_TYPE,
22017  SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_BCDMA_TPCFIFO_F0_ECC_TYPE,
22018  0u,
22019  NULL },
22020  { SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_BCDMA_TPCFIFO_F1_RAM_ID,
22021  SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_BCDMA_TPCFIFO_F1_INJECT_TYPE,
22022  SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_BCDMA_TPCFIFO_F1_ECC_TYPE,
22023  0u,
22024  NULL },
22025  { SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_BCDMA_RPCFIFO_F0_RAM_ID,
22026  SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_BCDMA_RPCFIFO_F0_INJECT_TYPE,
22027  SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_BCDMA_RPCFIFO_F0_ECC_TYPE,
22028  0u,
22029  NULL },
22030  { SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_BCDMA_RPCFIFO_F1_RAM_ID,
22031  SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_BCDMA_RPCFIFO_F1_INJECT_TYPE,
22032  SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_BCDMA_RPCFIFO_F1_ECC_TYPE,
22033  0u,
22034  NULL },
22035  { SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_BCDMA_RPCFIFO_WC_RAM_ID,
22036  SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_BCDMA_RPCFIFO_WC_INJECT_TYPE,
22037  SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_BCDMA_RPCFIFO_WC_ECC_TYPE,
22038  0u,
22039  NULL },
22040  { SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_BCDMA_STATS_STST0_RAM_ID,
22041  SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_BCDMA_STATS_STST0_INJECT_TYPE,
22042  SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_BCDMA_STATS_STST0_ECC_TYPE,
22043  0u,
22044  NULL },
22045  { SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_BCDMA_STATS_STSR0_RAM_ID,
22046  SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_BCDMA_STATS_STSR0_INJECT_TYPE,
22047  SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_BCDMA_STATS_STSR0_ECC_TYPE,
22048  0u,
22049  NULL },
22050  { SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_BCDMA_RINGOCC_CNTR_RAM_ID,
22051  SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_BCDMA_RINGOCC_CNTR_INJECT_TYPE,
22052  SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_BCDMA_RINGOCC_CNTR_ECC_TYPE,
22053  0u,
22054  NULL },
22055  { SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_INTAGGR_STATREG_SR_SPRAM_184X128_SWW_SR_RAM_ID,
22056  SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_INTAGGR_STATREG_SR_SPRAM_184X128_SWW_SR_INJECT_TYPE,
22057  SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_INTAGGR_STATREG_SR_SPRAM_184X128_SWW_SR_ECC_TYPE,
22058  0u,
22059  NULL },
22060  { SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_INTAGGR_COMMON_IM_TPRAM_1531X34_SWW_SR_RAM_ID,
22061  SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_INTAGGR_COMMON_IM_TPRAM_1531X34_SWW_SR_INJECT_TYPE,
22062  SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_INTAGGR_COMMON_IM_TPRAM_1531X34_SWW_SR_ECC_TYPE,
22063  0u,
22064  NULL },
22065  { SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_IPCSS_RINGACC_STRAM_RAM_ID,
22066  SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_IPCSS_RINGACC_STRAM_INJECT_TYPE,
22067  SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_IPCSS_RINGACC_STRAM_ECC_TYPE,
22068  0u,
22069  NULL },
22070  { SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_IPCSS_SEC_PROXY_BUF_STRAM_RAM_ID,
22071  SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_IPCSS_SEC_PROXY_BUF_STRAM_INJECT_TYPE,
22072  SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_IPCSS_SEC_PROXY_BUF_STRAM_ECC_TYPE,
22073  0u,
22074  NULL },
22075  { SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_IPCSS_SEC_PROXY_BUF_BUFRAM_RAM_ID,
22076  SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_IPCSS_SEC_PROXY_BUF_BUFRAM_INJECT_TYPE,
22077  SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_IPCSS_SEC_PROXY_BUF_BUFRAM_ECC_TYPE,
22078  0u,
22079  NULL },
22080  { SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_IPCSS_MSRAM_ECC0_RAM_ID,
22081  SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_IPCSS_MSRAM_ECC0_INJECT_TYPE,
22082  SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_IPCSS_MSRAM_ECC0_ECC_TYPE,
22083  0u,
22084  NULL },
22085 };
22086 
22091 static const SDL_RAMIdEntry_t SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_RXMEM_RamIdTable[SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_RXMEM_NUM_RAMS] =
22092 {
22093  { SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_RXMEM_EMMCSD4SS_SDHC_WRAP_RXMEM_RAM_ID,
22094  SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_RXMEM_EMMCSD4SS_SDHC_WRAP_RXMEM_INJECT_TYPE,
22095  SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_RXMEM_EMMCSD4SS_SDHC_WRAP_RXMEM_ECC_TYPE,
22096  0u,
22097  NULL },
22098 };
22099 
22104 static const SDL_RAMIdEntry_t SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_TXMEM_RamIdTable[SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_TXMEM_NUM_RAMS] =
22105 {
22106  { SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_TXMEM_EMMCSD4SS_SDHC_WRAP_TXMEM_RAM_ID,
22107  SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_TXMEM_EMMCSD4SS_SDHC_WRAP_TXMEM_INJECT_TYPE,
22108  SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_TXMEM_EMMCSD4SS_SDHC_WRAP_TXMEM_ECC_TYPE,
22109  0u,
22110  NULL },
22111 };
22112 
22117 static const SDL_RAMIdEntry_t SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_RXMEM_RamIdTable[SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_RXMEM_NUM_RAMS] =
22118 {
22119  { SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_RXMEM_EMMCSD4SS_SDHC_WRAP_RXMEM_RAM_ID,
22120  SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_RXMEM_EMMCSD4SS_SDHC_WRAP_RXMEM_INJECT_TYPE,
22121  SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_RXMEM_EMMCSD4SS_SDHC_WRAP_RXMEM_ECC_TYPE,
22122  0u,
22123  NULL },
22124 };
22125 
22130 static const SDL_RAMIdEntry_t SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_TXMEM_RamIdTable[SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_TXMEM_NUM_RAMS] =
22131 {
22132  { SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_TXMEM_EMMCSD4SS_SDHC_WRAP_TXMEM_RAM_ID,
22133  SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_TXMEM_EMMCSD4SS_SDHC_WRAP_TXMEM_INJECT_TYPE,
22134  SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_TXMEM_EMMCSD4SS_SDHC_WRAP_TXMEM_ECC_TYPE,
22135  0u,
22136  NULL },
22137 };
22138 
22143 static const SDL_RAMIdEntry_t SDL_MMCSD0_EMMCSD8SS_ECC_AGGR_TXMEM_RamIdTable[SDL_MMCSD0_EMMCSD8SS_ECC_AGGR_TXMEM_NUM_RAMS] =
22144 {
22145  { SDL_MMCSD0_EMMCSD8SS_ECC_AGGR_TXMEM_EMMCSD8SS_SDHC_WRAP_TXMEM_RAM_ID,
22146  SDL_MMCSD0_EMMCSD8SS_ECC_AGGR_TXMEM_EMMCSD8SS_SDHC_WRAP_TXMEM_INJECT_TYPE,
22147  SDL_MMCSD0_EMMCSD8SS_ECC_AGGR_TXMEM_EMMCSD8SS_SDHC_WRAP_TXMEM_ECC_TYPE,
22148  0u,
22149  NULL },
22150 };
22151 
22156 static const SDL_RAMIdEntry_t SDL_MMCSD0_EMMCSD8SS_ECC_AGGR_RXMEM_RamIdTable[SDL_MMCSD0_EMMCSD8SS_ECC_AGGR_RXMEM_NUM_RAMS] =
22157 {
22158  { SDL_MMCSD0_EMMCSD8SS_ECC_AGGR_RXMEM_EMMCSD8SS_SDHC_WRAP_RXMEM_RAM_ID,
22159  SDL_MMCSD0_EMMCSD8SS_ECC_AGGR_RXMEM_EMMCSD8SS_SDHC_WRAP_RXMEM_INJECT_TYPE,
22160  SDL_MMCSD0_EMMCSD8SS_ECC_AGGR_RXMEM_EMMCSD8SS_SDHC_WRAP_RXMEM_ECC_TYPE,
22161  0u,
22162  NULL },
22163 };
22164 
22169 static const SDL_RAMIdEntry_t SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_RamIdTable[SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_NUM_RAMS] =
22170 {
22171  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_RAM_ID,
22172  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_INJECT_TYPE,
22173  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_ECC_TYPE,
22174  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_MAX_NUM_CHECKERS,
22175  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_groupEntries },
22176  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_RAM_ID,
22177  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_INJECT_TYPE,
22178  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_ECC_TYPE,
22179  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_MAX_NUM_CHECKERS,
22180  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_groupEntries },
22181  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_RAM_ID,
22182  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_INJECT_TYPE,
22183  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_ECC_TYPE,
22184  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_MAX_NUM_CHECKERS,
22185  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_groupEntries },
22186  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_CFG_SLV_SRC_BUSECC_RAM_ID,
22187  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_CFG_SLV_SRC_BUSECC_INJECT_TYPE,
22188  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_CFG_SLV_SRC_BUSECC_ECC_TYPE,
22189  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_CFG_SLV_SRC_BUSECC_MAX_NUM_CHECKERS,
22190  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_CFG_SLV_SRC_BUSECC_groupEntries },
22191  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_PMST_DST_BUSECC_RAM_ID,
22192  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_PMST_DST_BUSECC_INJECT_TYPE,
22193  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_PMST_DST_BUSECC_ECC_TYPE,
22194  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_PMST_DST_BUSECC_MAX_NUM_CHECKERS,
22195  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_PMST_DST_BUSECC_groupEntries },
22196  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__IECC_AGGR_CFG_SRC_BUSECC_RAM_ID,
22197  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__IECC_AGGR_CFG_SRC_BUSECC_INJECT_TYPE,
22198  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__IECC_AGGR_CFG_SRC_BUSECC_ECC_TYPE,
22199  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__IECC_AGGR_CFG_SRC_BUSECC_MAX_NUM_CHECKERS,
22200  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__IECC_AGGR_CFG_SRC_BUSECC_groupEntries },
22201  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_DM2MCU_VBUSM_GASKET_MCU_0_EDC_CTRL_RAM_ID,
22202  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_DM2MCU_VBUSM_GASKET_MCU_0_EDC_CTRL_INJECT_TYPE,
22203  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_DM2MCU_VBUSM_GASKET_MCU_0_EDC_CTRL_ECC_TYPE,
22204  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_DM2MCU_VBUSM_GASKET_MCU_0_EDC_CTRL_MAX_NUM_CHECKERS,
22205  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_DM2MCU_VBUSM_GASKET_MCU_0_EDC_CTRL_groupEntries },
22206  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_RAM_ID,
22207  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_INJECT_TYPE,
22208  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_ECC_TYPE,
22209  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_MAX_NUM_CHECKERS,
22210  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_groupEntries },
22211  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_RD_RAMECC_RAM_ID,
22212  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_RD_RAMECC_INJECT_TYPE,
22213  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_RD_RAMECC_ECC_TYPE,
22214  0u,
22215  NULL },
22216  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_WR_RAMECC_RAM_ID,
22217  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_WR_RAMECC_INJECT_TYPE,
22218  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_WR_RAMECC_ECC_TYPE,
22219  0u,
22220  NULL },
22221  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IAM62A_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM62A_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_RAM_ID,
22222  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IAM62A_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM62A_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_INJECT_TYPE,
22223  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IAM62A_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM62A_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_ECC_TYPE,
22224  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IAM62A_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM62A_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS,
22225  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IAM62A_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM62A_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_groupEntries },
22226  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IAM62A_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM62A_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_RAM_ID,
22227  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IAM62A_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM62A_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_INJECT_TYPE,
22228  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IAM62A_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM62A_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_ECC_TYPE,
22229  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IAM62A_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM62A_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS,
22230  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IAM62A_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM62A_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_groupEntries },
22231  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IMSRAM32KX64E_MCU_0_CFG_P2P_BRIDGE_IMSRAM32KX64E_MCU_0_CFG_BRIDGE_BUSECC_RAM_ID,
22232  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IMSRAM32KX64E_MCU_0_CFG_P2P_BRIDGE_IMSRAM32KX64E_MCU_0_CFG_BRIDGE_BUSECC_INJECT_TYPE,
22233  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IMSRAM32KX64E_MCU_0_CFG_P2P_BRIDGE_IMSRAM32KX64E_MCU_0_CFG_BRIDGE_BUSECC_ECC_TYPE,
22234  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IMSRAM32KX64E_MCU_0_CFG_P2P_BRIDGE_IMSRAM32KX64E_MCU_0_CFG_BRIDGE_BUSECC_MAX_NUM_CHECKERS,
22235  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IMSRAM32KX64E_MCU_0_CFG_P2P_BRIDGE_IMSRAM32KX64E_MCU_0_CFG_BRIDGE_BUSECC_groupEntries },
22236  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IMSRAM32KX64E_MCU_1_CFG_P2P_BRIDGE_IMSRAM32KX64E_MCU_1_CFG_BRIDGE_BUSECC_RAM_ID,
22237  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IMSRAM32KX64E_MCU_1_CFG_P2P_BRIDGE_IMSRAM32KX64E_MCU_1_CFG_BRIDGE_BUSECC_INJECT_TYPE,
22238  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IMSRAM32KX64E_MCU_1_CFG_P2P_BRIDGE_IMSRAM32KX64E_MCU_1_CFG_BRIDGE_BUSECC_ECC_TYPE,
22239  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IMSRAM32KX64E_MCU_1_CFG_P2P_BRIDGE_IMSRAM32KX64E_MCU_1_CFG_BRIDGE_BUSECC_MAX_NUM_CHECKERS,
22240  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IMSRAM32KX64E_MCU_1_CFG_P2P_BRIDGE_IMSRAM32KX64E_MCU_1_CFG_BRIDGE_BUSECC_groupEntries },
22241  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IPULSAR_ULS_MCU_0_CPU0_CFG_SLV_P2P_BRIDGE_IPULSAR_ULS_MCU_0_CPU0_CFG_SLV_BRIDGE_BUSECC_RAM_ID,
22242  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IPULSAR_ULS_MCU_0_CPU0_CFG_SLV_P2P_BRIDGE_IPULSAR_ULS_MCU_0_CPU0_CFG_SLV_BRIDGE_BUSECC_INJECT_TYPE,
22243  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IPULSAR_ULS_MCU_0_CPU0_CFG_SLV_P2P_BRIDGE_IPULSAR_ULS_MCU_0_CPU0_CFG_SLV_BRIDGE_BUSECC_ECC_TYPE,
22244  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IPULSAR_ULS_MCU_0_CPU0_CFG_SLV_P2P_BRIDGE_IPULSAR_ULS_MCU_0_CPU0_CFG_SLV_BRIDGE_BUSECC_MAX_NUM_CHECKERS,
22245  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IPULSAR_ULS_MCU_0_CPU0_CFG_SLV_P2P_BRIDGE_IPULSAR_ULS_MCU_0_CPU0_CFG_SLV_BRIDGE_BUSECC_groupEntries },
22246  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_CFG_P2P_BRIDGE_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_CFG_BRIDGE_DST_BUSECC_RAM_ID,
22247  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_CFG_P2P_BRIDGE_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_CFG_BRIDGE_DST_BUSECC_INJECT_TYPE,
22248  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_CFG_P2P_BRIDGE_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_CFG_BRIDGE_DST_BUSECC_ECC_TYPE,
22249  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_CFG_P2P_BRIDGE_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_CFG_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS,
22250  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_CFG_P2P_BRIDGE_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_CFG_BRIDGE_DST_BUSECC_groupEntries },
22251  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_CFG_P2P_BRIDGE_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_CFG_BRIDGE_SRC_BUSECC_RAM_ID,
22252  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_CFG_P2P_BRIDGE_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_CFG_BRIDGE_SRC_BUSECC_INJECT_TYPE,
22253  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_CFG_P2P_BRIDGE_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_CFG_BRIDGE_SRC_BUSECC_ECC_TYPE,
22254  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_CFG_P2P_BRIDGE_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_CFG_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS,
22255  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_CFG_P2P_BRIDGE_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_CFG_BRIDGE_SRC_BUSECC_groupEntries },
22256  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ISAM62A_MCU_MCU_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM62A_MCU_MCU_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_RAM_ID,
22257  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ISAM62A_MCU_MCU_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM62A_MCU_MCU_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_INJECT_TYPE,
22258  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ISAM62A_MCU_MCU_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM62A_MCU_MCU_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_ECC_TYPE,
22259  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ISAM62A_MCU_MCU_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM62A_MCU_MCU_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_MAX_NUM_CHECKERS,
22260  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ISAM62A_MCU_MCU_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM62A_MCU_MCU_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_groupEntries },
22261  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ISAM62A_MCU_PULSAR_UL_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM62A_MCU_PULSAR_UL_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_RAM_ID,
22262  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ISAM62A_MCU_PULSAR_UL_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM62A_MCU_PULSAR_UL_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_INJECT_TYPE,
22263  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ISAM62A_MCU_PULSAR_UL_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM62A_MCU_PULSAR_UL_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_ECC_TYPE,
22264  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ISAM62A_MCU_PULSAR_UL_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM62A_MCU_PULSAR_UL_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_MAX_NUM_CHECKERS,
22265  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ISAM62A_MCU_PULSAR_UL_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM62A_MCU_PULSAR_UL_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_groupEntries },
22266  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_RAM_ID,
22267  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_INJECT_TYPE,
22268  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_ECC_TYPE,
22269  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_MAX_NUM_CHECKERS,
22270  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_groupEntries },
22271  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_RAM_ID,
22272  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_INJECT_TYPE,
22273  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_ECC_TYPE,
22274  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_MAX_NUM_CHECKERS,
22275  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_groupEntries },
22276  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_RAM_ID,
22277  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_INJECT_TYPE,
22278  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_ECC_TYPE,
22279  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_MAX_NUM_CHECKERS,
22280  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_groupEntries },
22281  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_RAM_ID,
22282  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_INJECT_TYPE,
22283  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_ECC_TYPE,
22284  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_MAX_NUM_CHECKERS,
22285  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_groupEntries },
22286  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_RAM_ID,
22287  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_INJECT_TYPE,
22288  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_ECC_TYPE,
22289  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_MAX_NUM_CHECKERS,
22290  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_groupEntries },
22291  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_RAM_ID,
22292  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_INJECT_TYPE,
22293  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_ECC_TYPE,
22294  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_MAX_NUM_CHECKERS,
22295  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_groupEntries },
22296  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_RAM_ID,
22297  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_INJECT_TYPE,
22298  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_ECC_TYPE,
22299  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_MAX_NUM_CHECKERS,
22300  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_groupEntries },
22301  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_RAM_ID,
22302  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_INJECT_TYPE,
22303  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_ECC_TYPE,
22304  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_MAX_NUM_CHECKERS,
22305  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_groupEntries },
22306  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_RAM_ID,
22307  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_INJECT_TYPE,
22308  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_ECC_TYPE,
22309  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_MAX_NUM_CHECKERS,
22310  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_groupEntries },
22311  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_BRIDGE_DST_BUSECC_RAM_ID,
22312  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_BRIDGE_DST_BUSECC_INJECT_TYPE,
22313  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_BRIDGE_DST_BUSECC_ECC_TYPE,
22314  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS,
22315  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_BRIDGE_DST_BUSECC_groupEntries },
22316  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_BRIDGE_SRC_BUSECC_RAM_ID,
22317  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_BRIDGE_SRC_BUSECC_INJECT_TYPE,
22318  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_BRIDGE_SRC_BUSECC_ECC_TYPE,
22319  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS,
22320  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_BRIDGE_SRC_BUSECC_groupEntries },
22321  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_P2M_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_BRIDGE_DST_BUSECC_RAM_ID,
22322  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_P2M_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_BRIDGE_DST_BUSECC_INJECT_TYPE,
22323  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_P2M_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_BRIDGE_DST_BUSECC_ECC_TYPE,
22324  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_P2M_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS,
22325  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_P2M_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_BRIDGE_DST_BUSECC_groupEntries },
22326  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_P2M_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_BRIDGE_SRC_BUSECC_RAM_ID,
22327  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_P2M_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_BRIDGE_SRC_BUSECC_INJECT_TYPE,
22328  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_P2M_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_BRIDGE_SRC_BUSECC_ECC_TYPE,
22329  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_P2M_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS,
22330  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_P2M_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_BRIDGE_SRC_BUSECC_groupEntries },
22331  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_P2P_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_BRIDGE_DST_BUSECC_RAM_ID,
22332  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_P2P_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_BRIDGE_DST_BUSECC_INJECT_TYPE,
22333  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_P2P_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_BRIDGE_DST_BUSECC_ECC_TYPE,
22334  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_P2P_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS,
22335  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_P2P_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_BRIDGE_DST_BUSECC_groupEntries },
22336  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_P2P_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_BRIDGE_SRC_BUSECC_RAM_ID,
22337  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_P2P_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_BRIDGE_SRC_BUSECC_INJECT_TYPE,
22338  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_P2P_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_BRIDGE_SRC_BUSECC_ECC_TYPE,
22339  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_P2P_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS,
22340  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_P2P_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_BRIDGE_SRC_BUSECC_groupEntries },
22341  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_CBASS_DEFAULT_ERR_AM62A_MCU_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_RAM_ID,
22342  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_CBASS_DEFAULT_ERR_AM62A_MCU_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_INJECT_TYPE,
22343  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_CBASS_DEFAULT_ERR_AM62A_MCU_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_ECC_TYPE,
22344  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_CBASS_DEFAULT_ERR_AM62A_MCU_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
22345  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_CBASS_DEFAULT_ERR_AM62A_MCU_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_groupEntries },
22346  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_CBASS_DEFAULT_MMRS_AM62A_MCU_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_RAM_ID,
22347  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_CBASS_DEFAULT_MMRS_AM62A_MCU_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_INJECT_TYPE,
22348  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_CBASS_DEFAULT_MMRS_AM62A_MCU_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_ECC_TYPE,
22349  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_CBASS_DEFAULT_MMRS_AM62A_MCU_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
22350  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_CBASS_DEFAULT_MMRS_AM62A_MCU_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_groupEntries },
22351  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_RAM_ID,
22352  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_INJECT_TYPE,
22353  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_ECC_TYPE,
22354  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
22355  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_groupEntries },
22356  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_RAM_ID,
22357  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_INJECT_TYPE,
22358  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_ECC_TYPE,
22359  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_MAX_NUM_CHECKERS,
22360  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_groupEntries },
22361  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ERR_SCR_AM62A_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_RAM_ID,
22362  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ERR_SCR_AM62A_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_INJECT_TYPE,
22363  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ERR_SCR_AM62A_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_ECC_TYPE,
22364  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ERR_SCR_AM62A_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
22365  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ERR_SCR_AM62A_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_groupEntries },
22366  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_RAM_ID,
22367  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_INJECT_TYPE,
22368  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_ECC_TYPE,
22369  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_MAX_NUM_CHECKERS,
22370  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_groupEntries },
22371  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_DST_BUSECC_RAM_ID,
22372  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_DST_BUSECC_INJECT_TYPE,
22373  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_DST_BUSECC_ECC_TYPE,
22374  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS,
22375  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_DST_BUSECC_groupEntries },
22376  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_SRC_BUSECC_RAM_ID,
22377  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_SRC_BUSECC_INJECT_TYPE,
22378  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_SRC_BUSECC_ECC_TYPE,
22379  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS,
22380  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_SRC_BUSECC_groupEntries },
22381  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_SAM62A_MCU_MCU_ECC_AGGR_EDC_CTRL_RAM_ID,
22382  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_SAM62A_MCU_MCU_ECC_AGGR_EDC_CTRL_INJECT_TYPE,
22383  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_SAM62A_MCU_MCU_ECC_AGGR_EDC_CTRL_ECC_TYPE,
22384  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_SAM62A_MCU_MCU_ECC_AGGR_EDC_CTRL_MAX_NUM_CHECKERS,
22385  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_SAM62A_MCU_MCU_ECC_AGGR_EDC_CTRL_groupEntries },
22386 };
22387 
22392 static const SDL_RAMIdEntry_t SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_RamIdTable[SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_NUM_RAMS] =
22393 {
22394  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_ECCAGGR_EDC_CTRL_RAM_ID,
22395  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_ECCAGGR_EDC_CTRL_INJECT_TYPE,
22396  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_ECCAGGR_EDC_CTRL_ECC_TYPE,
22397  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_ECCAGGR_EDC_CTRL_MAX_NUM_CHECKERS,
22398  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_ECCAGGR_EDC_CTRL_groupEntries },
22399  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_CFG_CONFIG_RAM_ID,
22400  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_CFG_CONFIG_INJECT_TYPE,
22401  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_CFG_CONFIG_ECC_TYPE,
22402  0u,
22403  NULL },
22404  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_CFG_STATE_RAM_ID,
22405  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_CFG_STATE_INJECT_TYPE,
22406  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_CFG_STATE_ECC_TYPE,
22407  0u,
22408  NULL },
22409  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_TPCFIFO_F0_RAM_ID,
22410  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_TPCFIFO_F0_INJECT_TYPE,
22411  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_TPCFIFO_F0_ECC_TYPE,
22412  0u,
22413  NULL },
22414  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_TPCFIFO_F1_RAM_ID,
22415  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_TPCFIFO_F1_INJECT_TYPE,
22416  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_TPCFIFO_F1_ECC_TYPE,
22417  0u,
22418  NULL },
22419  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_RPCFIFO_F0_RAM_ID,
22420  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_RPCFIFO_F0_INJECT_TYPE,
22421  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_RPCFIFO_F0_ECC_TYPE,
22422  0u,
22423  NULL },
22424  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_RPCFIFO_F1_RAM_ID,
22425  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_RPCFIFO_F1_INJECT_TYPE,
22426  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_RPCFIFO_F1_ECC_TYPE,
22427  0u,
22428  NULL },
22429  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_RPCFIFO_WC_RAM_ID,
22430  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_RPCFIFO_WC_INJECT_TYPE,
22431  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_RPCFIFO_WC_ECC_TYPE,
22432  0u,
22433  NULL },
22434  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_STATS_STST0_RAM_ID,
22435  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_STATS_STST0_INJECT_TYPE,
22436  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_STATS_STST0_ECC_TYPE,
22437  0u,
22438  NULL },
22439  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_STATS_STSR0_RAM_ID,
22440  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_STATS_STSR0_INJECT_TYPE,
22441  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_STATS_STSR0_ECC_TYPE,
22442  0u,
22443  NULL },
22444  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_RINGOCC_CNTR_RAM_ID,
22445  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_RINGOCC_CNTR_INJECT_TYPE,
22446  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_RINGOCC_CNTR_ECC_TYPE,
22447  0u,
22448  NULL },
22449  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_RAM_ID,
22450  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_INJECT_TYPE,
22451  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_ECC_TYPE,
22452  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_MAX_NUM_CHECKERS,
22453  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_groupEntries },
22454  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_EDC_CTRL_0_RAM_ID,
22455  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_EDC_CTRL_0_INJECT_TYPE,
22456  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_EDC_CTRL_0_ECC_TYPE,
22457  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_EDC_CTRL_0_MAX_NUM_CHECKERS,
22458  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_EDC_CTRL_0_groupEntries },
22459  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_STATREG_SR_SPRAM_8X128_SWW_SR_RAM_ID,
22460  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_STATREG_SR_SPRAM_8X128_SWW_SR_INJECT_TYPE,
22461  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_STATREG_SR_SPRAM_8X128_SWW_SR_ECC_TYPE,
22462  0u,
22463  NULL },
22464  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_COMMON_IM_TPRAM_158X34_SWW_SR_RAM_ID,
22465  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_COMMON_IM_TPRAM_158X34_SWW_SR_INJECT_TYPE,
22466  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_COMMON_IM_TPRAM_158X34_SWW_SR_ECC_TYPE,
22467  0u,
22468  NULL },
22469  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_RAM_ID,
22470  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_INJECT_TYPE,
22471  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_ECC_TYPE,
22472  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_MAX_NUM_CHECKERS,
22473  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_groupEntries },
22474  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_RAM_ID,
22475  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_INJECT_TYPE,
22476  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_ECC_TYPE,
22477  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_MAX_NUM_CHECKERS,
22478  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_groupEntries },
22479  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_STRAM_RAM_ID,
22480  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_STRAM_INJECT_TYPE,
22481  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_STRAM_ECC_TYPE,
22482  0u,
22483  NULL },
22484  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_BUF_STRAM_RAM_ID,
22485  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_BUF_STRAM_INJECT_TYPE,
22486  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_BUF_STRAM_ECC_TYPE,
22487  0u,
22488  NULL },
22489  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_BUF_BUFRAM_RAM_ID,
22490  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_BUF_BUFRAM_INJECT_TYPE,
22491  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_BUF_BUFRAM_ECC_TYPE,
22492  0u,
22493  NULL },
22494  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_RAM_ID,
22495  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_INJECT_TYPE,
22496  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_ECC_TYPE,
22497  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_MAX_NUM_CHECKERS,
22498  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_groupEntries },
22499  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_RAM_ID,
22500  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_INJECT_TYPE,
22501  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_ECC_TYPE,
22502  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS,
22503  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries },
22504  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_RAM_ID,
22505  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_INJECT_TYPE,
22506  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_ECC_TYPE,
22507  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_MAX_NUM_CHECKERS,
22508  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_groupEntries },
22509  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_VD2GCLK_EDC_CTRL_0_RAM_ID,
22510  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_VD2GCLK_EDC_CTRL_0_INJECT_TYPE,
22511  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_VD2GCLK_EDC_CTRL_0_ECC_TYPE,
22512  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_VD2GCLK_EDC_CTRL_0_MAX_NUM_CHECKERS,
22513  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_VD2GCLK_EDC_CTRL_0_groupEntries },
22514  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_ECC0_RAM_ID,
22515  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_ECC0_INJECT_TYPE,
22516  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_ECC0_ECC_TYPE,
22517  0u,
22518  NULL },
22519  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_RAM_ID,
22520  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_INJECT_TYPE,
22521  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_ECC_TYPE,
22522  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_MAX_NUM_CHECKERS,
22523  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_groupEntries },
22524  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_RAM_ID,
22525  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_INJECT_TYPE,
22526  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_ECC_TYPE,
22527  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_MAX_NUM_CHECKERS,
22528  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_groupEntries },
22529  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_RAM_ID,
22530  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_INJECT_TYPE,
22531  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_ECC_TYPE,
22532  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_MAX_NUM_CHECKERS,
22533  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_groupEntries },
22534  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_RAM_ID,
22535  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_INJECT_TYPE,
22536  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_ECC_TYPE,
22537  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_MAX_NUM_CHECKERS,
22538  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_groupEntries },
22539  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_RAM_ID,
22540  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_INJECT_TYPE,
22541  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_ECC_TYPE,
22542  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_MAX_NUM_CHECKERS,
22543  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_groupEntries },
22544  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_RAM_ID,
22545  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_INJECT_TYPE,
22546  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_ECC_TYPE,
22547  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_MAX_NUM_CHECKERS,
22548  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_groupEntries },
22549  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_RAM_ID,
22550  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_INJECT_TYPE,
22551  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_ECC_TYPE,
22552  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_MAX_NUM_CHECKERS,
22553  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_groupEntries },
22554  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_RAM_ID,
22555  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_INJECT_TYPE,
22556  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_ECC_TYPE,
22557  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_MAX_NUM_CHECKERS,
22558  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_groupEntries },
22559  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_RAM_ID,
22560  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_INJECT_TYPE,
22561  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_ECC_TYPE,
22562  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_MAX_NUM_CHECKERS,
22563  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_groupEntries },
22564  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_RAM_ID,
22565  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_INJECT_TYPE,
22566  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_ECC_TYPE,
22567  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_MAX_NUM_CHECKERS,
22568  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_groupEntries },
22569  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_INTAGGR_EVT_EDC_CTRL_0_RAM_ID,
22570  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_INTAGGR_EVT_EDC_CTRL_0_INJECT_TYPE,
22571  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_INTAGGR_EVT_EDC_CTRL_0_ECC_TYPE,
22572  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_INTAGGR_EVT_EDC_CTRL_0_MAX_NUM_CHECKERS,
22573  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_INTAGGR_EVT_EDC_CTRL_0_groupEntries },
22574  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_INTAGGR_CEVT_EDC_CTRL_0_RAM_ID,
22575  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_INTAGGR_CEVT_EDC_CTRL_0_INJECT_TYPE,
22576  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_INTAGGR_CEVT_EDC_CTRL_0_ECC_TYPE,
22577  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_INTAGGR_CEVT_EDC_CTRL_0_MAX_NUM_CHECKERS,
22578  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_INTAGGR_CEVT_EDC_CTRL_0_groupEntries },
22579  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_INTAGGR_MEVT_IN_EDC_CTRL_0_RAM_ID,
22580  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_INTAGGR_MEVT_IN_EDC_CTRL_0_INJECT_TYPE,
22581  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_INTAGGR_MEVT_IN_EDC_CTRL_0_ECC_TYPE,
22582  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_INTAGGR_MEVT_IN_EDC_CTRL_0_MAX_NUM_CHECKERS,
22583  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_INTAGGR_MEVT_IN_EDC_CTRL_0_groupEntries },
22584  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_RAM_ID,
22585  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_INJECT_TYPE,
22586  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_ECC_TYPE,
22587  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_MAX_NUM_CHECKERS,
22588  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_groupEntries },
22589  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CFG_EDC_CTRL_0_RAM_ID,
22590  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CFG_EDC_CTRL_0_INJECT_TYPE,
22591  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CFG_EDC_CTRL_0_ECC_TYPE,
22592  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CFG_EDC_CTRL_0_MAX_NUM_CHECKERS,
22593  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CFG_EDC_CTRL_0_groupEntries },
22594  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_RAM_ID,
22595  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_INJECT_TYPE,
22596  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_ECC_TYPE,
22597  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_MAX_NUM_CHECKERS,
22598  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_groupEntries },
22599  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_RAM_ID,
22600  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_INJECT_TYPE,
22601  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_ECC_TYPE,
22602  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_MAX_NUM_CHECKERS,
22603  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_groupEntries },
22604  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_RAM_ID,
22605  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_INJECT_TYPE,
22606  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_ECC_TYPE,
22607  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_MAX_NUM_CHECKERS,
22608  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_groupEntries },
22609  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_VD2GCLK_EDC_CTRL_0_RAM_ID,
22610  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_VD2GCLK_EDC_CTRL_0_INJECT_TYPE,
22611  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_VD2GCLK_EDC_CTRL_0_ECC_TYPE,
22612  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_VD2GCLK_EDC_CTRL_0_MAX_NUM_CHECKERS,
22613  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_VD2GCLK_EDC_CTRL_0_groupEntries },
22614  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_DMSS_CFG_P2P_BRIDGE_EDC_CTRL_0_RAM_ID,
22615  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_DMSS_CFG_P2P_BRIDGE_EDC_CTRL_0_INJECT_TYPE,
22616  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_DMSS_CFG_P2P_BRIDGE_EDC_CTRL_0_ECC_TYPE,
22617  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_DMSS_CFG_P2P_BRIDGE_EDC_CTRL_0_MAX_NUM_CHECKERS,
22618  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_DMSS_CFG_P2P_BRIDGE_EDC_CTRL_0_groupEntries },
22619  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_RAM_ID,
22620  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_INJECT_TYPE,
22621  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_ECC_TYPE,
22622  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_MAX_NUM_CHECKERS,
22623  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_groupEntries },
22624  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_RAM_ID,
22625  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_INJECT_TYPE,
22626  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_ECC_TYPE,
22627  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_MAX_NUM_CHECKERS,
22628  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_groupEntries },
22629 };
22630 
22635 static const SDL_RAMIdEntry_t SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_RamIdTable[SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_NUM_RAMS] =
22636 {
22637  { SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_PKTRAM0_ECC_RAM_ID,
22638  SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_PKTRAM0_ECC_INJECT_TYPE,
22639  SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_PKTRAM0_ECC_ECC_TYPE,
22640  0u,
22641  NULL },
22642  { SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_PKTRAM1_ECC_RAM_ID,
22643  SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_PKTRAM1_ECC_INJECT_TYPE,
22644  SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_PKTRAM1_ECC_ECC_TYPE,
22645  0u,
22646  NULL },
22647  { SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_PKA_PROG_RAM_ECC_RAM_ID,
22648  SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_PKA_PROG_RAM_ECC_INJECT_TYPE,
22649  SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_PKA_PROG_RAM_ECC_ECC_TYPE,
22650  0u,
22651  NULL },
22652  { SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_ENCR_CTXRAM_BANK01_ECC_RAM_ID,
22653  SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_ENCR_CTXRAM_BANK01_ECC_INJECT_TYPE,
22654  SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_ENCR_CTXRAM_BANK01_ECC_ECC_TYPE,
22655  0u,
22656  NULL },
22657  { SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_ENCR_CTXRAM_BANK23_ECC_RAM_ID,
22658  SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_ENCR_CTXRAM_BANK23_ECC_INJECT_TYPE,
22659  SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_ENCR_CTXRAM_BANK23_ECC_ECC_TYPE,
22660  0u,
22661  NULL },
22662  { SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_ENCR_CTXRAM_BANK4_ECC_RAM_ID,
22663  SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_ENCR_CTXRAM_BANK4_ECC_INJECT_TYPE,
22664  SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_ENCR_CTXRAM_BANK4_ECC_ECC_TYPE,
22665  0u,
22666  NULL },
22667  { SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_AUTH_CTXRAM_BANK01_ECC_RAM_ID,
22668  SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_AUTH_CTXRAM_BANK01_ECC_INJECT_TYPE,
22669  SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_AUTH_CTXRAM_BANK01_ECC_ECC_TYPE,
22670  0u,
22671  NULL },
22672  { SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_AUTH_CTXRAM_BANK23_ECC_RAM_ID,
22673  SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_AUTH_CTXRAM_BANK23_ECC_INJECT_TYPE,
22674  SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_AUTH_CTXRAM_BANK23_ECC_ECC_TYPE,
22675  0u,
22676  NULL },
22677  { SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_AUTH_CTXRAM_BANK45_ECC_RAM_ID,
22678  SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_AUTH_CTXRAM_BANK45_ECC_INJECT_TYPE,
22679  SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_AUTH_CTXRAM_BANK45_ECC_ECC_TYPE,
22680  0u,
22681  NULL },
22682  { SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_AUTH_CTXRAM_BANK67_ECC_RAM_ID,
22683  SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_AUTH_CTXRAM_BANK67_ECC_INJECT_TYPE,
22684  SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_AUTH_CTXRAM_BANK67_ECC_ECC_TYPE,
22685  0u,
22686  NULL },
22687  { SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_AUTH_CTXRAM_BANK89_ECC_RAM_ID,
22688  SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_AUTH_CTXRAM_BANK89_ECC_INJECT_TYPE,
22689  SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_AUTH_CTXRAM_BANK89_ECC_ECC_TYPE,
22690  0u,
22691  NULL },
22692  { SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_AUTH_CTXRAM_BANK10_ECC_RAM_ID,
22693  SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_AUTH_CTXRAM_BANK10_ECC_INJECT_TYPE,
22694  SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_AUTH_CTXRAM_BANK10_ECC_ECC_TYPE,
22695  0u,
22696  NULL },
22697 };
22698 
22703 static const SDL_RAMIdEntry_t SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_RamIdTable[SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_NUM_RAMS] =
22704 {
22705  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_RAM_ID,
22706  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_INJECT_TYPE,
22707  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_ECC_TYPE,
22708  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_MAX_NUM_CHECKERS,
22709  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_groupEntries },
22710  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_RAM_ID,
22711  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_INJECT_TYPE,
22712  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_ECC_TYPE,
22713  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_MAX_NUM_CHECKERS,
22714  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_groupEntries },
22715  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_PLL_MMR_EDC_CTRL_BUSECC_RAM_ID,
22716  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_PLL_MMR_EDC_CTRL_BUSECC_INJECT_TYPE,
22717  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_PLL_MMR_EDC_CTRL_BUSECC_ECC_TYPE,
22718  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_PLL_MMR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
22719  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_PLL_MMR_EDC_CTRL_BUSECC_groupEntries },
22720  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_RAM_ID,
22721  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_INJECT_TYPE,
22722  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_ECC_TYPE,
22723  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_MAX_NUM_CHECKERS,
22724  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_groupEntries },
22725  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_RAM_ID,
22726  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_INJECT_TYPE,
22727  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_ECC_TYPE,
22728  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_MAX_NUM_CHECKERS,
22729  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_groupEntries },
22730  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_RAM_ID,
22731  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_INJECT_TYPE,
22732  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_ECC_TYPE,
22733  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_MAX_NUM_CHECKERS,
22734  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_groupEntries },
22735  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_ISAM62A_DM2WS_VBUSM_GASKET_MCU_0_EDC_CTRL_RAM_ID,
22736  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_ISAM62A_DM2WS_VBUSM_GASKET_MCU_0_EDC_CTRL_INJECT_TYPE,
22737  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_ISAM62A_DM2WS_VBUSM_GASKET_MCU_0_EDC_CTRL_ECC_TYPE,
22738  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_ISAM62A_DM2WS_VBUSM_GASKET_MCU_0_EDC_CTRL_MAX_NUM_CHECKERS,
22739  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_ISAM62A_DM2WS_VBUSM_GASKET_MCU_0_EDC_CTRL_groupEntries },
22740  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_IAM62A_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM62A_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_BRIDGE_BUSECC_RAM_ID,
22741  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_IAM62A_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM62A_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_BRIDGE_BUSECC_INJECT_TYPE,
22742  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_IAM62A_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM62A_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_BRIDGE_BUSECC_ECC_TYPE,
22743  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_IAM62A_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM62A_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_BRIDGE_BUSECC_MAX_NUM_CHECKERS,
22744  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_IAM62A_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM62A_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_BRIDGE_BUSECC_groupEntries },
22745  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ISAM62A_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM62A_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_BRIDGE_BUSECC_RAM_ID,
22746  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ISAM62A_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM62A_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_BRIDGE_BUSECC_INJECT_TYPE,
22747  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ISAM62A_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM62A_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_BRIDGE_BUSECC_ECC_TYPE,
22748  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ISAM62A_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM62A_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_BRIDGE_BUSECC_MAX_NUM_CHECKERS,
22749  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ISAM62A_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM62A_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_BRIDGE_BUSECC_groupEntries },
22750  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_RAM_ID,
22751  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_INJECT_TYPE,
22752  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_ECC_TYPE,
22753  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_MAX_NUM_CHECKERS,
22754  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_groupEntries },
22755  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_RAM_ID,
22756  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_INJECT_TYPE,
22757  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_ECC_TYPE,
22758  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_MAX_NUM_CHECKERS,
22759  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_groupEntries },
22760  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_RAM_ID,
22761  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_INJECT_TYPE,
22762  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_ECC_TYPE,
22763  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_MAX_NUM_CHECKERS,
22764  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_groupEntries },
22765  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_CBASS_DEFAULT_ERR_AM62A_WKUP_SAFE_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_RAM_ID,
22766  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_CBASS_DEFAULT_ERR_AM62A_WKUP_SAFE_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_INJECT_TYPE,
22767  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_CBASS_DEFAULT_ERR_AM62A_WKUP_SAFE_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_ECC_TYPE,
22768  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_CBASS_DEFAULT_ERR_AM62A_WKUP_SAFE_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
22769  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_CBASS_DEFAULT_ERR_AM62A_WKUP_SAFE_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_groupEntries },
22770  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_RAM_ID,
22771  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_INJECT_TYPE,
22772  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_ECC_TYPE,
22773  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
22774  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_groupEntries },
22775  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_RAM_ID,
22776  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_INJECT_TYPE,
22777  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_ECC_TYPE,
22778  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_MAX_NUM_CHECKERS,
22779  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_groupEntries },
22780  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_RAM_ID,
22781  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_INJECT_TYPE,
22782  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_ECC_TYPE,
22783  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_MAX_NUM_CHECKERS,
22784  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_groupEntries },
22785  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_SAM62A_WKUP_SAFE_ECC_AGGR_EDC_CTRL_RAM_ID,
22786  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_SAM62A_WKUP_SAFE_ECC_AGGR_EDC_CTRL_INJECT_TYPE,
22787  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_SAM62A_WKUP_SAFE_ECC_AGGR_EDC_CTRL_ECC_TYPE,
22788  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_SAM62A_WKUP_SAFE_ECC_AGGR_EDC_CTRL_MAX_NUM_CHECKERS,
22789  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_SAM62A_WKUP_SAFE_ECC_AGGR_EDC_CTRL_groupEntries },
22790 };
22791 
22796 static const SDL_RAMIdEntry_t SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_RamIdTable[SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_NUM_RAMS] =
22797 {
22798  { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_ITAG_RAM0_RAM_ID,
22799  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_ITAG_RAM0_INJECT_TYPE,
22800  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_ITAG_RAM0_ECC_TYPE,
22801  0u,
22802  NULL },
22803  { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_ITAG_RAM1_RAM_ID,
22804  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_ITAG_RAM1_INJECT_TYPE,
22805  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_ITAG_RAM1_ECC_TYPE,
22806  0u,
22807  NULL },
22808  { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_ITAG_RAM2_RAM_ID,
22809  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_ITAG_RAM2_INJECT_TYPE,
22810  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_ITAG_RAM2_ECC_TYPE,
22811  0u,
22812  NULL },
22813  { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_ITAG_RAM3_RAM_ID,
22814  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_ITAG_RAM3_INJECT_TYPE,
22815  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_ITAG_RAM3_ECC_TYPE,
22816  0u,
22817  NULL },
22818  { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_IDATA_BANK0_RAM_ID,
22819  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_IDATA_BANK0_INJECT_TYPE,
22820  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_IDATA_BANK0_ECC_TYPE,
22821  0u,
22822  NULL },
22823  { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_IDATA_BANK1_RAM_ID,
22824  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_IDATA_BANK1_INJECT_TYPE,
22825  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_IDATA_BANK1_ECC_TYPE,
22826  0u,
22827  NULL },
22828  { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_IDATA_BANK2_RAM_ID,
22829  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_IDATA_BANK2_INJECT_TYPE,
22830  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_IDATA_BANK2_ECC_TYPE,
22831  0u,
22832  NULL },
22833  { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_IDATA_BANK3_RAM_ID,
22834  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_IDATA_BANK3_INJECT_TYPE,
22835  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_IDATA_BANK3_ECC_TYPE,
22836  0u,
22837  NULL },
22838  { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DTAG_RAM0_RAM_ID,
22839  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DTAG_RAM0_INJECT_TYPE,
22840  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DTAG_RAM0_ECC_TYPE,
22841  0u,
22842  NULL },
22843  { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DTAG_RAM1_RAM_ID,
22844  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DTAG_RAM1_INJECT_TYPE,
22845  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DTAG_RAM1_ECC_TYPE,
22846  0u,
22847  NULL },
22848  { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DTAG_RAM2_RAM_ID,
22849  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DTAG_RAM2_INJECT_TYPE,
22850  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DTAG_RAM2_ECC_TYPE,
22851  0u,
22852  NULL },
22853  { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DTAG_RAM3_RAM_ID,
22854  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DTAG_RAM3_INJECT_TYPE,
22855  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DTAG_RAM3_ECC_TYPE,
22856  0u,
22857  NULL },
22858  { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDIRTY_RAM_RAM_ID,
22859  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDIRTY_RAM_INJECT_TYPE,
22860  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDIRTY_RAM_ECC_TYPE,
22861  0u,
22862  NULL },
22863  { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM0_RAM_ID,
22864  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM0_INJECT_TYPE,
22865  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM0_ECC_TYPE,
22866  0u,
22867  NULL },
22868  { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM1_RAM_ID,
22869  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM1_INJECT_TYPE,
22870  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM1_ECC_TYPE,
22871  0u,
22872  NULL },
22873  { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM2_RAM_ID,
22874  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM2_INJECT_TYPE,
22875  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM2_ECC_TYPE,
22876  0u,
22877  NULL },
22878  { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM3_RAM_ID,
22879  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM3_INJECT_TYPE,
22880  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM3_ECC_TYPE,
22881  0u,
22882  NULL },
22883  { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM4_RAM_ID,
22884  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM4_INJECT_TYPE,
22885  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM4_ECC_TYPE,
22886  0u,
22887  NULL },
22888  { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM5_RAM_ID,
22889  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM5_INJECT_TYPE,
22890  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM5_ECC_TYPE,
22891  0u,
22892  NULL },
22893  { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM6_RAM_ID,
22894  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM6_INJECT_TYPE,
22895  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM6_ECC_TYPE,
22896  0u,
22897  NULL },
22898  { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM7_RAM_ID,
22899  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM7_INJECT_TYPE,
22900  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM7_ECC_TYPE,
22901  0u,
22902  NULL },
22903  { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_ATCM0_BANK0_RAM_ID,
22904  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_ATCM0_BANK0_INJECT_TYPE,
22905  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_ATCM0_BANK0_ECC_TYPE,
22906  0u,
22907  NULL },
22908  { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_ATCM0_BANK1_RAM_ID,
22909  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_ATCM0_BANK1_INJECT_TYPE,
22910  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_ATCM0_BANK1_ECC_TYPE,
22911  0u,
22912  NULL },
22913  { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_B0TCM0_BANK0_RAM_ID,
22914  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_B0TCM0_BANK0_INJECT_TYPE,
22915  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_B0TCM0_BANK0_ECC_TYPE,
22916  0u,
22917  NULL },
22918  { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_B0TCM0_BANK1_RAM_ID,
22919  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_B0TCM0_BANK1_INJECT_TYPE,
22920  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_B0TCM0_BANK1_ECC_TYPE,
22921  0u,
22922  NULL },
22923  { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_B1TCM0_BANK0_RAM_ID,
22924  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_B1TCM0_BANK0_INJECT_TYPE,
22925  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_B1TCM0_BANK0_ECC_TYPE,
22926  0u,
22927  NULL },
22928  { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_B1TCM0_BANK1_RAM_ID,
22929  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_B1TCM0_BANK1_INJECT_TYPE,
22930  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_B1TCM0_BANK1_ECC_TYPE,
22931  0u,
22932  NULL },
22933  { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_PULSAR_KS_VIM_COMMON_CORE0_RAM_RAM_ID,
22934  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_PULSAR_KS_VIM_COMMON_CORE0_RAM_INJECT_TYPE,
22935  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_PULSAR_KS_VIM_COMMON_CORE0_RAM_ECC_TYPE,
22936  0u,
22937  NULL },
22938  { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_MEM_MST0_KSBUS_AXI2VBUSM_R_RDATA_BUFFER_RAM_ID,
22939  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_MEM_MST0_KSBUS_AXI2VBUSM_R_RDATA_BUFFER_INJECT_TYPE,
22940  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_MEM_MST0_KSBUS_AXI2VBUSM_R_RDATA_BUFFER_ECC_TYPE,
22941  0u,
22942  NULL },
22943 };
22944 
22949 static const SDL_RAMIdEntry_t SDL_SMS0_SMS_HSM_ECC_RamIdTable[SDL_SMS0_SMS_HSM_ECC_NUM_RAMS] =
22950 {
22951  { SDL_SMS0_SMS_HSM_ECC_ISRAM0_RAMECC_RAM_ID,
22952  SDL_SMS0_SMS_HSM_ECC_ISRAM0_RAMECC_INJECT_TYPE,
22953  SDL_SMS0_SMS_HSM_ECC_ISRAM0_RAMECC_ECC_TYPE,
22954  0u,
22955  NULL },
22956  { SDL_SMS0_SMS_HSM_ECC_ISRAM1_RAMECC_RAM_ID,
22957  SDL_SMS0_SMS_HSM_ECC_ISRAM1_RAMECC_INJECT_TYPE,
22958  SDL_SMS0_SMS_HSM_ECC_ISRAM1_RAMECC_ECC_TYPE,
22959  0u,
22960  NULL },
22961  { SDL_SMS0_SMS_HSM_ECC_ISRAM0_BUSECC_RAM_ID,
22962  SDL_SMS0_SMS_HSM_ECC_ISRAM0_BUSECC_INJECT_TYPE,
22963  SDL_SMS0_SMS_HSM_ECC_ISRAM0_BUSECC_ECC_TYPE,
22964  SDL_SMS0_SMS_HSM_ECC_ISRAM0_BUSECC_MAX_NUM_CHECKERS,
22965  SDL_SMS0_SMS_HSM_ECC_ISRAM0_BUSECC_groupEntries },
22966  { SDL_SMS0_SMS_HSM_ECC_ISRAM1_BUSECC_RAM_ID,
22967  SDL_SMS0_SMS_HSM_ECC_ISRAM1_BUSECC_INJECT_TYPE,
22968  SDL_SMS0_SMS_HSM_ECC_ISRAM1_BUSECC_ECC_TYPE,
22969  SDL_SMS0_SMS_HSM_ECC_ISRAM1_BUSECC_MAX_NUM_CHECKERS,
22970  SDL_SMS0_SMS_HSM_ECC_ISRAM1_BUSECC_groupEntries },
22971  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_RAM_ID,
22972  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_INJECT_TYPE,
22973  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_ECC_TYPE,
22974  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_MAX_NUM_CHECKERS,
22975  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_groupEntries },
22976  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_RAM_ID,
22977  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_INJECT_TYPE,
22978  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_ECC_TYPE,
22979  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_MAX_NUM_CHECKERS,
22980  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_groupEntries },
22981  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_RAM_ID,
22982  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_INJECT_TYPE,
22983  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_ECC_TYPE,
22984  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
22985  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_groupEntries },
22986  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_RAM_ID,
22987  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_INJECT_TYPE,
22988  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_ECC_TYPE,
22989  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
22990  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_groupEntries },
22991  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_DEFAULT_MMRS_SMS_HSM_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_RAM_ID,
22992  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_DEFAULT_MMRS_SMS_HSM_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_INJECT_TYPE,
22993  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_DEFAULT_MMRS_SMS_HSM_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_ECC_TYPE,
22994  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_DEFAULT_MMRS_SMS_HSM_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
22995  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_DEFAULT_MMRS_SMS_HSM_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_groupEntries },
22996  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_RAM_ID,
22997  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_INJECT_TYPE,
22998  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_ECC_TYPE,
22999  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
23000  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_groupEntries },
23001  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_RAM_ID,
23002  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_INJECT_TYPE,
23003  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_ECC_TYPE,
23004  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_MAX_NUM_CHECKERS,
23005  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_groupEntries },
23006  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_WWRTI_CM_EDC_CTRL_BUSECC_RAM_ID,
23007  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_WWRTI_CM_EDC_CTRL_BUSECC_INJECT_TYPE,
23008  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_WWRTI_CM_EDC_CTRL_BUSECC_ECC_TYPE,
23009  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_WWRTI_CM_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
23010  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_WWRTI_CM_EDC_CTRL_BUSECC_groupEntries },
23011  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_ECC_EDC_CTRL_RAM_ID,
23012  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_ECC_EDC_CTRL_INJECT_TYPE,
23013  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_ECC_EDC_CTRL_ECC_TYPE,
23014  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_ECC_EDC_CTRL_MAX_NUM_CHECKERS,
23015  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_ECC_EDC_CTRL_groupEntries },
23016 };
23017 
23022 static const SDL_RAMIdEntry_t SDL_SMS0_SMS_TIFS_ECC_RamIdTable[SDL_SMS0_SMS_TIFS_ECC_NUM_RAMS] =
23023 {
23024  { SDL_SMS0_SMS_TIFS_ECC_ISRAM0_RAMECC_RAM_ID,
23025  SDL_SMS0_SMS_TIFS_ECC_ISRAM0_RAMECC_INJECT_TYPE,
23026  SDL_SMS0_SMS_TIFS_ECC_ISRAM0_RAMECC_ECC_TYPE,
23027  0u,
23028  NULL },
23029  { SDL_SMS0_SMS_TIFS_ECC_ISRAM1_RAMECC_RAM_ID,
23030  SDL_SMS0_SMS_TIFS_ECC_ISRAM1_RAMECC_INJECT_TYPE,
23031  SDL_SMS0_SMS_TIFS_ECC_ISRAM1_RAMECC_ECC_TYPE,
23032  0u,
23033  NULL },
23034  { SDL_SMS0_SMS_TIFS_ECC_ISRAM0_BUSECC_RAM_ID,
23035  SDL_SMS0_SMS_TIFS_ECC_ISRAM0_BUSECC_INJECT_TYPE,
23036  SDL_SMS0_SMS_TIFS_ECC_ISRAM0_BUSECC_ECC_TYPE,
23037  SDL_SMS0_SMS_TIFS_ECC_ISRAM0_BUSECC_MAX_NUM_CHECKERS,
23038  SDL_SMS0_SMS_TIFS_ECC_ISRAM0_BUSECC_groupEntries },
23039  { SDL_SMS0_SMS_TIFS_ECC_ISRAM1_BUSECC_RAM_ID,
23040  SDL_SMS0_SMS_TIFS_ECC_ISRAM1_BUSECC_INJECT_TYPE,
23041  SDL_SMS0_SMS_TIFS_ECC_ISRAM1_BUSECC_ECC_TYPE,
23042  SDL_SMS0_SMS_TIFS_ECC_ISRAM1_BUSECC_MAX_NUM_CHECKERS,
23043  SDL_SMS0_SMS_TIFS_ECC_ISRAM1_BUSECC_groupEntries },
23044  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_RAM_ID,
23045  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_INJECT_TYPE,
23046  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_ECC_TYPE,
23047  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_MAX_NUM_CHECKERS,
23048  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_groupEntries },
23049  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_RAM_ID,
23050  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_INJECT_TYPE,
23051  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_ECC_TYPE,
23052  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_MAX_NUM_CHECKERS,
23053  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_groupEntries },
23054  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_2_RAM_ID,
23055  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_2_INJECT_TYPE,
23056  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_2_ECC_TYPE,
23057  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_2_MAX_NUM_CHECKERS,
23058  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_2_groupEntries },
23059  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_RAM_ID,
23060  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_INJECT_TYPE,
23061  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_ECC_TYPE,
23062  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_MAX_NUM_CHECKERS,
23063  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_groupEntries },
23064  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IFWMGR_M_P2P_BRIDGE_IFWMGR_M_BRIDGE_BUSECC_RAM_ID,
23065  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IFWMGR_M_P2P_BRIDGE_IFWMGR_M_BRIDGE_BUSECC_INJECT_TYPE,
23066  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IFWMGR_M_P2P_BRIDGE_IFWMGR_M_BRIDGE_BUSECC_ECC_TYPE,
23067  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IFWMGR_M_P2P_BRIDGE_IFWMGR_M_BRIDGE_BUSECC_MAX_NUM_CHECKERS,
23068  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IFWMGR_M_P2P_BRIDGE_IFWMGR_M_BRIDGE_BUSECC_groupEntries },
23069  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_RAM_ID,
23070  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_INJECT_TYPE,
23071  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_ECC_TYPE,
23072  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_MAX_NUM_CHECKERS,
23073  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_groupEntries },
23074  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_RAM_ID,
23075  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_INJECT_TYPE,
23076  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_ECC_TYPE,
23077  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_MAX_NUM_CHECKERS,
23078  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_groupEntries },
23079  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_RAM_ID,
23080  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_INJECT_TYPE,
23081  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_ECC_TYPE,
23082  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
23083  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_groupEntries },
23084  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_DEFAULT_MMRS_SMS_TIFS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_RAM_ID,
23085  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_DEFAULT_MMRS_SMS_TIFS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_INJECT_TYPE,
23086  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_DEFAULT_MMRS_SMS_TIFS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_ECC_TYPE,
23087  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_DEFAULT_MMRS_SMS_TIFS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
23088  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_DEFAULT_MMRS_SMS_TIFS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_groupEntries },
23089  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_RAM_ID,
23090  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_INJECT_TYPE,
23091  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_ECC_TYPE,
23092  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
23093  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_groupEntries },
23094  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_RAM_ID,
23095  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_INJECT_TYPE,
23096  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_ECC_TYPE,
23097  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_MAX_NUM_CHECKERS,
23098  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_groupEntries },
23099  { SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_RAM_ID,
23100  SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_INJECT_TYPE,
23101  SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_ECC_TYPE,
23102  SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
23103  SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_groupEntries },
23104  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_DMSS_HSM_P2P_BRIDGE_SMS_DMSS_HSM_BRIDGE_BUSECC_RAM_ID,
23105  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_DMSS_HSM_P2P_BRIDGE_SMS_DMSS_HSM_BRIDGE_BUSECC_INJECT_TYPE,
23106  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_DMSS_HSM_P2P_BRIDGE_SMS_DMSS_HSM_BRIDGE_BUSECC_ECC_TYPE,
23107  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_DMSS_HSM_P2P_BRIDGE_SMS_DMSS_HSM_BRIDGE_BUSECC_MAX_NUM_CHECKERS,
23108  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_DMSS_HSM_P2P_BRIDGE_SMS_DMSS_HSM_BRIDGE_BUSECC_groupEntries },
23109  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_WWRTI_CM_EDC_CTRL_BUSECC_RAM_ID,
23110  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_WWRTI_CM_EDC_CTRL_BUSECC_INJECT_TYPE,
23111  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_WWRTI_CM_EDC_CTRL_BUSECC_ECC_TYPE,
23112  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_WWRTI_CM_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
23113  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_WWRTI_CM_EDC_CTRL_BUSECC_groupEntries },
23114  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CM_EDC_CTRL_BUSECC_RAM_ID,
23115  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CM_EDC_CTRL_BUSECC_INJECT_TYPE,
23116  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CM_EDC_CTRL_BUSECC_ECC_TYPE,
23117  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CM_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
23118  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CM_EDC_CTRL_BUSECC_groupEntries },
23119  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_SEC_CM_EDC_CTRL_BUSECC_RAM_ID,
23120  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_SEC_CM_EDC_CTRL_BUSECC_INJECT_TYPE,
23121  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_SEC_CM_EDC_CTRL_BUSECC_ECC_TYPE,
23122  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_SEC_CM_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
23123  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_SEC_CM_EDC_CTRL_BUSECC_groupEntries },
23124  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_ECC_EDC_CTRL_RAM_ID,
23125  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_ECC_EDC_CTRL_INJECT_TYPE,
23126  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_ECC_EDC_CTRL_ECC_TYPE,
23127  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_ECC_EDC_CTRL_MAX_NUM_CHECKERS,
23128  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_ECC_EDC_CTRL_groupEntries },
23129 };
23130 
23135 static const SDL_RAMIdEntry_t SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_RamIdTable[SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_NUM_RAMS] =
23136 {
23137  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_RAM_ID,
23138  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_INJECT_TYPE,
23139  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_ECC_TYPE,
23140  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_MAX_NUM_CHECKERS,
23141  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_groupEntries },
23142  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_RAM_ID,
23143  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_INJECT_TYPE,
23144  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_ECC_TYPE,
23145  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_MAX_NUM_CHECKERS,
23146  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_groupEntries },
23147  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_RAM_ID,
23148  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_INJECT_TYPE,
23149  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_ECC_TYPE,
23150  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_MAX_NUM_CHECKERS,
23151  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_groupEntries },
23152  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_CFG_SLV_DST_BUSECC_RAM_ID,
23153  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_CFG_SLV_DST_BUSECC_INJECT_TYPE,
23154  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_CFG_SLV_DST_BUSECC_ECC_TYPE,
23155  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_CFG_SLV_DST_BUSECC_MAX_NUM_CHECKERS,
23156  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_CFG_SLV_DST_BUSECC_groupEntries },
23157  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_PMST_SRC_BUSECC_RAM_ID,
23158  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_PMST_SRC_BUSECC_INJECT_TYPE,
23159  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_PMST_SRC_BUSECC_ECC_TYPE,
23160  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_PMST_SRC_BUSECC_MAX_NUM_CHECKERS,
23161  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_PMST_SRC_BUSECC_groupEntries },
23162  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__IECC_AGGR_CFG_DST_BUSECC_RAM_ID,
23163  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__IECC_AGGR_CFG_DST_BUSECC_INJECT_TYPE,
23164  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__IECC_AGGR_CFG_DST_BUSECC_ECC_TYPE,
23165  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__IECC_AGGR_CFG_DST_BUSECC_MAX_NUM_CHECKERS,
23166  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__IECC_AGGR_CFG_DST_BUSECC_groupEntries },
23167  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_SAM62A_MCU_PULSAR_UL_ECC_AGGR_EDC_CTRL_RAM_ID,
23168  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_SAM62A_MCU_PULSAR_UL_ECC_AGGR_EDC_CTRL_INJECT_TYPE,
23169  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_SAM62A_MCU_PULSAR_UL_ECC_AGGR_EDC_CTRL_ECC_TYPE,
23170  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_SAM62A_MCU_PULSAR_UL_ECC_AGGR_EDC_CTRL_MAX_NUM_CHECKERS,
23171  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_SAM62A_MCU_PULSAR_UL_ECC_AGGR_EDC_CTRL_groupEntries },
23172 };
23173 
23178 static const SDL_RAMIdEntry_t SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_RamIdTable[SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_NUM_RAMS] =
23179 {
23180  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_AC71_PMC_WRAP_PMC_PMC_MEMWRAP_EDC_CTRL_PARITY_0_RAM_ID,
23181  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_AC71_PMC_WRAP_PMC_PMC_MEMWRAP_EDC_CTRL_PARITY_0_INJECT_TYPE,
23182  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_AC71_PMC_WRAP_PMC_PMC_MEMWRAP_EDC_CTRL_PARITY_0_ECC_TYPE,
23183  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_AC71_PMC_WRAP_PMC_PMC_MEMWRAP_EDC_CTRL_PARITY_0_MAX_NUM_CHECKERS,
23184  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_AC71_PMC_WRAP_PMC_PMC_MEMWRAP_EDC_CTRL_PARITY_0_groupEntries },
23185  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_TAG_CTL_TOP_DMC_TAG_CTL_EDC_CTRL_0_RAM_ID,
23186  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_TAG_CTL_TOP_DMC_TAG_CTL_EDC_CTRL_0_INJECT_TYPE,
23187  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_TAG_CTL_TOP_DMC_TAG_CTL_EDC_CTRL_0_ECC_TYPE,
23188  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_TAG_CTL_TOP_DMC_TAG_CTL_EDC_CTRL_0_MAX_NUM_CHECKERS,
23189  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_TAG_CTL_TOP_DMC_TAG_CTL_EDC_CTRL_0_groupEntries },
23190  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_RAM_ID,
23191  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_INJECT_TYPE,
23192  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_ECC_TYPE,
23193  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_MAX_NUM_CHECKERS,
23194  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_groupEntries },
23195  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_DRU_R30_C_R_CORE_QUEUE_CMD_EDC_CTRL_0_RAM_ID,
23196  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_DRU_R30_C_R_CORE_QUEUE_CMD_EDC_CTRL_0_INJECT_TYPE,
23197  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_DRU_R30_C_R_CORE_QUEUE_CMD_EDC_CTRL_0_ECC_TYPE,
23198  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_DRU_R30_C_R_CORE_QUEUE_CMD_EDC_CTRL_0_MAX_NUM_CHECKERS,
23199  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_DRU_R30_C_R_CORE_QUEUE_CMD_EDC_CTRL_0_groupEntries },
23200  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_DRU_R30_C_R_CORE_RD_BUFFER_CMD_EDC_CTRL_0_RAM_ID,
23201  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_DRU_R30_C_R_CORE_RD_BUFFER_CMD_EDC_CTRL_0_INJECT_TYPE,
23202  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_DRU_R30_C_R_CORE_RD_BUFFER_CMD_EDC_CTRL_0_ECC_TYPE,
23203  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_DRU_R30_C_R_CORE_RD_BUFFER_CMD_EDC_CTRL_0_MAX_NUM_CHECKERS,
23204  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_DRU_R30_C_R_CORE_RD_BUFFER_CMD_EDC_CTRL_0_groupEntries },
23205  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_DRU_R30_C_R_CORE_CH_LOGIC_RING_MEM_RING_EDC_CTRL_0_RAM_ID,
23206  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_DRU_R30_C_R_CORE_CH_LOGIC_RING_MEM_RING_EDC_CTRL_0_INJECT_TYPE,
23207  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_DRU_R30_C_R_CORE_CH_LOGIC_RING_MEM_RING_EDC_CTRL_0_ECC_TYPE,
23208  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_DRU_R30_C_R_CORE_CH_LOGIC_RING_MEM_RING_EDC_CTRL_0_MAX_NUM_CHECKERS,
23209  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_DRU_R30_C_R_CORE_CH_LOGIC_RING_MEM_RING_EDC_CTRL_0_groupEntries },
23210  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_SAM62A_C7XV_CLEC_CLEC_SRAM_RAM_ID,
23211  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_SAM62A_C7XV_CLEC_CLEC_SRAM_INJECT_TYPE,
23212  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_SAM62A_C7XV_CLEC_CLEC_SRAM_ECC_TYPE,
23213  0u,
23214  NULL },
23215  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_UMC_WRAP_C7XV_EL2_C7XV_EL2_CORE_C7XV_EL2_EDC_CTL_0_RAM_ID,
23216  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_UMC_WRAP_C7XV_EL2_C7XV_EL2_CORE_C7XV_EL2_EDC_CTL_0_INJECT_TYPE,
23217  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_UMC_WRAP_C7XV_EL2_C7XV_EL2_CORE_C7XV_EL2_EDC_CTL_0_ECC_TYPE,
23218  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_UMC_WRAP_C7XV_EL2_C7XV_EL2_CORE_C7XV_EL2_EDC_CTL_0_MAX_NUM_CHECKERS,
23219  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_UMC_WRAP_C7XV_EL2_C7XV_EL2_CORE_C7XV_EL2_EDC_CTL_0_groupEntries },
23220 };
23221 
23226 static const SDL_RAMIdEntry_t SDL_USB1_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_RamIdTable[SDL_USB1_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_NUM_RAMS] =
23227 {
23228  { SDL_USB1_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_USB2SS_16FFC_USB2SS_CORE_AXI2VBUSM_MST_KSBUS_AXI2VBUSM_R_RDATA_BUFFER_RAM_ID,
23229  SDL_USB1_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_USB2SS_16FFC_USB2SS_CORE_AXI2VBUSM_MST_KSBUS_AXI2VBUSM_R_RDATA_BUFFER_INJECT_TYPE,
23230  SDL_USB1_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_USB2SS_16FFC_USB2SS_CORE_AXI2VBUSM_MST_KSBUS_AXI2VBUSM_R_RDATA_BUFFER_ECC_TYPE,
23231  0u,
23232  NULL },
23233  { SDL_USB1_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_USB2SS_16FFC_USB2SS_CORE_RAMS_MEM_CTRL_RAM0_RAM_ID,
23234  SDL_USB1_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_USB2SS_16FFC_USB2SS_CORE_RAMS_MEM_CTRL_RAM0_INJECT_TYPE,
23235  SDL_USB1_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_USB2SS_16FFC_USB2SS_CORE_RAMS_MEM_CTRL_RAM0_ECC_TYPE,
23236  0u,
23237  NULL },
23238 };
23239 
23244 static const SDL_RAMIdEntry_t SDL_USB0_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_RamIdTable[SDL_USB0_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_NUM_RAMS] =
23245 {
23246  { SDL_USB0_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_USB2SS_16FFC_USB2SS_CORE_AXI2VBUSM_MST_KSBUS_AXI2VBUSM_R_RDATA_BUFFER_RAM_ID,
23247  SDL_USB0_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_USB2SS_16FFC_USB2SS_CORE_AXI2VBUSM_MST_KSBUS_AXI2VBUSM_R_RDATA_BUFFER_INJECT_TYPE,
23248  SDL_USB0_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_USB2SS_16FFC_USB2SS_CORE_AXI2VBUSM_MST_KSBUS_AXI2VBUSM_R_RDATA_BUFFER_ECC_TYPE,
23249  0u,
23250  NULL },
23251  { SDL_USB0_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_USB2SS_16FFC_USB2SS_CORE_RAMS_MEM_CTRL_RAM0_RAM_ID,
23252  SDL_USB0_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_USB2SS_16FFC_USB2SS_CORE_RAMS_MEM_CTRL_RAM0_INJECT_TYPE,
23253  SDL_USB0_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_USB2SS_16FFC_USB2SS_CORE_RAMS_MEM_CTRL_RAM0_ECC_TYPE,
23254  0u,
23255  NULL },
23256 };
23257 
23262 static const SDL_RAMIdEntry_t SDL_WKUP_PSRAMECC_8K0_PSRAM8KX32E_ECC_AGGR_RamIdTable[SDL_WKUP_PSRAMECC_8K0_PSRAM8KX32E_ECC_AGGR_NUM_RAMS] =
23263 {
23264  { SDL_WKUP_PSRAMECC_8K0_PSRAM8KX32E_ECC_AGGR_PSRAM8KX32E_PSRAM0_ECC_RAM_ID,
23265  SDL_WKUP_PSRAMECC_8K0_PSRAM8KX32E_ECC_AGGR_PSRAM8KX32E_PSRAM0_ECC_INJECT_TYPE,
23266  SDL_WKUP_PSRAMECC_8K0_PSRAM8KX32E_ECC_AGGR_PSRAM8KX32E_PSRAM0_ECC_ECC_TYPE,
23267  0u,
23268  NULL },
23269 };
23270 
23275 static const SDL_RAMIdEntry_t SDL_PDMA0_SAM62_PDMA_SPI_ECCAGGR_RamIdTable[SDL_PDMA0_SAM62_PDMA_SPI_ECCAGGR_NUM_RAMS] =
23276 {
23277  { SDL_PDMA0_SAM62_PDMA_SPI_ECCAGGR_SAM62_PDMA_SPI_PDMA_CORE_TF0_F0_TPRAM_60X128_SBW_SR_RAM_ID,
23278  SDL_PDMA0_SAM62_PDMA_SPI_ECCAGGR_SAM62_PDMA_SPI_PDMA_CORE_TF0_F0_TPRAM_60X128_SBW_SR_INJECT_TYPE,
23279  SDL_PDMA0_SAM62_PDMA_SPI_ECCAGGR_SAM62_PDMA_SPI_PDMA_CORE_TF0_F0_TPRAM_60X128_SBW_SR_ECC_TYPE,
23280  0u,
23281  NULL },
23282  { SDL_PDMA0_SAM62_PDMA_SPI_ECCAGGR_SAM62_PDMA_SPI_PDMA_CORE_TF0_F1_TPRAM_60X128_SBW_SR_RAM_ID,
23283  SDL_PDMA0_SAM62_PDMA_SPI_ECCAGGR_SAM62_PDMA_SPI_PDMA_CORE_TF0_F1_TPRAM_60X128_SBW_SR_INJECT_TYPE,
23284  SDL_PDMA0_SAM62_PDMA_SPI_ECCAGGR_SAM62_PDMA_SPI_PDMA_CORE_TF0_F1_TPRAM_60X128_SBW_SR_ECC_TYPE,
23285  0u,
23286  NULL },
23287  { SDL_PDMA0_SAM62_PDMA_SPI_ECCAGGR_SAM62_PDMA_SPI_PDMA_CORE_RF0_F0_TPRAM_60X144_SBW_SR_RAM_ID,
23288  SDL_PDMA0_SAM62_PDMA_SPI_ECCAGGR_SAM62_PDMA_SPI_PDMA_CORE_RF0_F0_TPRAM_60X144_SBW_SR_INJECT_TYPE,
23289  SDL_PDMA0_SAM62_PDMA_SPI_ECCAGGR_SAM62_PDMA_SPI_PDMA_CORE_RF0_F0_TPRAM_60X144_SBW_SR_ECC_TYPE,
23290  0u,
23291  NULL },
23292  { SDL_PDMA0_SAM62_PDMA_SPI_ECCAGGR_SAM62_PDMA_SPI_PDMA_CORE_RF0_F1_TPRAM_60X144_SBW_SR_RAM_ID,
23293  SDL_PDMA0_SAM62_PDMA_SPI_ECCAGGR_SAM62_PDMA_SPI_PDMA_CORE_RF0_F1_TPRAM_60X144_SBW_SR_INJECT_TYPE,
23294  SDL_PDMA0_SAM62_PDMA_SPI_ECCAGGR_SAM62_PDMA_SPI_PDMA_CORE_RF0_F1_TPRAM_60X144_SBW_SR_ECC_TYPE,
23295  0u,
23296  NULL },
23297 };
23298 
23303 static const SDL_RAMIdEntry_t SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_RamIdTable[SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_NUM_RAMS] =
23304 {
23305  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_RAM_ID,
23306  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_INJECT_TYPE,
23307  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_ECC_TYPE,
23308  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_MAX_NUM_CHECKERS,
23309  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_groupEntries },
23310  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_RAM_ID,
23311  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_INJECT_TYPE,
23312  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_ECC_TYPE,
23313  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_MAX_NUM_CHECKERS,
23314  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_groupEntries },
23315  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_IK3VTM_N16FFC_WKUP_0_VBUSP_P2P_BRIDGE_IK3VTM_N16FFC_WKUP_0_VBUSP_BRIDGE_BUSECC_RAM_ID,
23316  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_IK3VTM_N16FFC_WKUP_0_VBUSP_P2P_BRIDGE_IK3VTM_N16FFC_WKUP_0_VBUSP_BRIDGE_BUSECC_INJECT_TYPE,
23317  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_IK3VTM_N16FFC_WKUP_0_VBUSP_P2P_BRIDGE_IK3VTM_N16FFC_WKUP_0_VBUSP_BRIDGE_BUSECC_ECC_TYPE,
23318  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_IK3VTM_N16FFC_WKUP_0_VBUSP_P2P_BRIDGE_IK3VTM_N16FFC_WKUP_0_VBUSP_BRIDGE_BUSECC_MAX_NUM_CHECKERS,
23319  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_IK3VTM_N16FFC_WKUP_0_VBUSP_P2P_BRIDGE_IK3VTM_N16FFC_WKUP_0_VBUSP_BRIDGE_BUSECC_groupEntries },
23320  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_RAM_ID,
23321  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_INJECT_TYPE,
23322  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_ECC_TYPE,
23323  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
23324  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_groupEntries },
23325  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_RAM_ID,
23326  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_INJECT_TYPE,
23327  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ECC_TYPE,
23328  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
23329  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries },
23330  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISAM62A_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM62A_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_DST_BUSECC_RAM_ID,
23331  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISAM62A_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM62A_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_DST_BUSECC_INJECT_TYPE,
23332  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISAM62A_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM62A_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_DST_BUSECC_ECC_TYPE,
23333  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISAM62A_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM62A_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS,
23334  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISAM62A_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM62A_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_DST_BUSECC_groupEntries },
23335  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISAM62A_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM62A_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_SRC_BUSECC_RAM_ID,
23336  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISAM62A_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM62A_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_SRC_BUSECC_INJECT_TYPE,
23337  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISAM62A_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM62A_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_SRC_BUSECC_ECC_TYPE,
23338  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISAM62A_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM62A_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS,
23339  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISAM62A_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM62A_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_SRC_BUSECC_groupEntries },
23340  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISAM62A_DM_MCU_ECC_AGGR_WKUP_1_CFG_P2P_BRIDGE_ISAM62A_DM_MCU_ECC_AGGR_WKUP_1_CFG_BRIDGE_SRC_BUSECC_RAM_ID,
23341  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISAM62A_DM_MCU_ECC_AGGR_WKUP_1_CFG_P2P_BRIDGE_ISAM62A_DM_MCU_ECC_AGGR_WKUP_1_CFG_BRIDGE_SRC_BUSECC_INJECT_TYPE,
23342  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISAM62A_DM_MCU_ECC_AGGR_WKUP_1_CFG_P2P_BRIDGE_ISAM62A_DM_MCU_ECC_AGGR_WKUP_1_CFG_BRIDGE_SRC_BUSECC_ECC_TYPE,
23343  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISAM62A_DM_MCU_ECC_AGGR_WKUP_1_CFG_P2P_BRIDGE_ISAM62A_DM_MCU_ECC_AGGR_WKUP_1_CFG_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS,
23344  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISAM62A_DM_MCU_ECC_AGGR_WKUP_1_CFG_P2P_BRIDGE_ISAM62A_DM_MCU_ECC_AGGR_WKUP_1_CFG_BRIDGE_SRC_BUSECC_groupEntries },
23345  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_RAM_ID,
23346  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_INJECT_TYPE,
23347  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ECC_TYPE,
23348  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
23349  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries },
23350  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_RAM_ID,
23351  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_INJECT_TYPE,
23352  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ECC_TYPE,
23353  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
23354  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries },
23355  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_SAM62A_DM_DM_ECC_AGGR_EDC_CTRL_RAM_ID,
23356  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_SAM62A_DM_DM_ECC_AGGR_EDC_CTRL_INJECT_TYPE,
23357  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_SAM62A_DM_DM_ECC_AGGR_EDC_CTRL_ECC_TYPE,
23358  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_SAM62A_DM_DM_ECC_AGGR_EDC_CTRL_MAX_NUM_CHECKERS,
23359  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_SAM62A_DM_DM_ECC_AGGR_EDC_CTRL_groupEntries },
23360 };
23361 
23366 static const SDL_RAMIdEntry_t SDL_PDMA1_SAM62_PDMA_UART_ECCAGGR_RamIdTable[SDL_PDMA1_SAM62_PDMA_UART_ECCAGGR_NUM_RAMS] =
23367 {
23368  { SDL_PDMA1_SAM62_PDMA_UART_ECCAGGR_SAM62_PDMA_UART_PDMA_CORE_TF0_F0_TPRAM_28X128_SBW_SR_RAM_ID,
23369  SDL_PDMA1_SAM62_PDMA_UART_ECCAGGR_SAM62_PDMA_UART_PDMA_CORE_TF0_F0_TPRAM_28X128_SBW_SR_INJECT_TYPE,
23370  SDL_PDMA1_SAM62_PDMA_UART_ECCAGGR_SAM62_PDMA_UART_PDMA_CORE_TF0_F0_TPRAM_28X128_SBW_SR_ECC_TYPE,
23371  0u,
23372  NULL },
23373  { SDL_PDMA1_SAM62_PDMA_UART_ECCAGGR_SAM62_PDMA_UART_PDMA_CORE_TF0_F1_TPRAM_28X128_SBW_SR_RAM_ID,
23374  SDL_PDMA1_SAM62_PDMA_UART_ECCAGGR_SAM62_PDMA_UART_PDMA_CORE_TF0_F1_TPRAM_28X128_SBW_SR_INJECT_TYPE,
23375  SDL_PDMA1_SAM62_PDMA_UART_ECCAGGR_SAM62_PDMA_UART_PDMA_CORE_TF0_F1_TPRAM_28X128_SBW_SR_ECC_TYPE,
23376  0u,
23377  NULL },
23378  { SDL_PDMA1_SAM62_PDMA_UART_ECCAGGR_SAM62_PDMA_UART_PDMA_CORE_RF0_F0_TPRAM_28X144_SBW_SR_RAM_ID,
23379  SDL_PDMA1_SAM62_PDMA_UART_ECCAGGR_SAM62_PDMA_UART_PDMA_CORE_RF0_F0_TPRAM_28X144_SBW_SR_INJECT_TYPE,
23380  SDL_PDMA1_SAM62_PDMA_UART_ECCAGGR_SAM62_PDMA_UART_PDMA_CORE_RF0_F0_TPRAM_28X144_SBW_SR_ECC_TYPE,
23381  0u,
23382  NULL },
23383  { SDL_PDMA1_SAM62_PDMA_UART_ECCAGGR_SAM62_PDMA_UART_PDMA_CORE_RF0_F1_TPRAM_28X144_SBW_SR_RAM_ID,
23384  SDL_PDMA1_SAM62_PDMA_UART_ECCAGGR_SAM62_PDMA_UART_PDMA_CORE_RF0_F1_TPRAM_28X144_SBW_SR_INJECT_TYPE,
23385  SDL_PDMA1_SAM62_PDMA_UART_ECCAGGR_SAM62_PDMA_UART_PDMA_CORE_RF0_F1_TPRAM_28X144_SBW_SR_ECC_TYPE,
23386  0u,
23387  NULL },
23388 };
23389 
23394 static const SDL_RAMIdEntry_t SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_RamIdTable[SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_NUM_RAMS] =
23395 {
23396  { SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_ID,
23397  SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_INJECT_TYPE,
23398  SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_ECC_TYPE,
23399  0u,
23400  NULL },
23401  { SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_RAM_ID,
23402  SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_INJECT_TYPE,
23403  SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_ECC_TYPE,
23404  SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_MAX_NUM_CHECKERS,
23405  SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_groupEntries },
23406 };
23407 
23412 static const SDL_RAMIdEntry_t SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_RamIdTable[SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_NUM_RAMS] =
23413 {
23414  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_IDATA_SPRAM_BANK0_LO_ECC_SVBUS_RAM_ID,
23415  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_IDATA_SPRAM_BANK0_LO_ECC_SVBUS_INJECT_TYPE,
23416  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_IDATA_SPRAM_BANK0_LO_ECC_SVBUS_ECC_TYPE,
23417  0u,
23418  NULL },
23419  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_IDATA_SPRAM_BANK0_HI_ECC_SVBUS_RAM_ID,
23420  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_IDATA_SPRAM_BANK0_HI_ECC_SVBUS_INJECT_TYPE,
23421  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_IDATA_SPRAM_BANK0_HI_ECC_SVBUS_ECC_TYPE,
23422  0u,
23423  NULL },
23424  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_IDATA_SPRAM_BANK1_LO_ECC_SVBUS_RAM_ID,
23425  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_IDATA_SPRAM_BANK1_LO_ECC_SVBUS_INJECT_TYPE,
23426  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_IDATA_SPRAM_BANK1_LO_ECC_SVBUS_ECC_TYPE,
23427  0u,
23428  NULL },
23429  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_IDATA_SPRAM_BANK1_HI_ECC_SVBUS_RAM_ID,
23430  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_IDATA_SPRAM_BANK1_HI_ECC_SVBUS_INJECT_TYPE,
23431  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_IDATA_SPRAM_BANK1_HI_ECC_SVBUS_ECC_TYPE,
23432  0u,
23433  NULL },
23434  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_ITAG_SPRAM_RAM0_ECC_SVBUS_RAM_ID,
23435  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_ITAG_SPRAM_RAM0_ECC_SVBUS_INJECT_TYPE,
23436  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_ITAG_SPRAM_RAM0_ECC_SVBUS_ECC_TYPE,
23437  0u,
23438  NULL },
23439  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_ITAG_SPRAM_RAM1_ECC_SVBUS_RAM_ID,
23440  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_ITAG_SPRAM_RAM1_ECC_SVBUS_INJECT_TYPE,
23441  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_ITAG_SPRAM_RAM1_ECC_SVBUS_ECC_TYPE,
23442  0u,
23443  NULL },
23444  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DDATA_SPRAM_BANK0_ECC_SVBUS_RAM_ID,
23445  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DDATA_SPRAM_BANK0_ECC_SVBUS_INJECT_TYPE,
23446  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DDATA_SPRAM_BANK0_ECC_SVBUS_ECC_TYPE,
23447  0u,
23448  NULL },
23449  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DDATA_SPRAM_BANK1_ECC_SVBUS_RAM_ID,
23450  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DDATA_SPRAM_BANK1_ECC_SVBUS_INJECT_TYPE,
23451  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DDATA_SPRAM_BANK1_ECC_SVBUS_ECC_TYPE,
23452  0u,
23453  NULL },
23454  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DDATA_SPRAM_BANK2_ECC_SVBUS_RAM_ID,
23455  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DDATA_SPRAM_BANK2_ECC_SVBUS_INJECT_TYPE,
23456  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DDATA_SPRAM_BANK2_ECC_SVBUS_ECC_TYPE,
23457  0u,
23458  NULL },
23459  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DDATA_SPRAM_BANK3_ECC_SVBUS_RAM_ID,
23460  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DDATA_SPRAM_BANK3_ECC_SVBUS_INJECT_TYPE,
23461  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DDATA_SPRAM_BANK3_ECC_SVBUS_ECC_TYPE,
23462  0u,
23463  NULL },
23464  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DDATA_SPRAM_BANK4_ECC_SVBUS_RAM_ID,
23465  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DDATA_SPRAM_BANK4_ECC_SVBUS_INJECT_TYPE,
23466  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DDATA_SPRAM_BANK4_ECC_SVBUS_ECC_TYPE,
23467  0u,
23468  NULL },
23469  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DDATA_SPRAM_BANK5_ECC_SVBUS_RAM_ID,
23470  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DDATA_SPRAM_BANK5_ECC_SVBUS_INJECT_TYPE,
23471  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DDATA_SPRAM_BANK5_ECC_SVBUS_ECC_TYPE,
23472  0u,
23473  NULL },
23474  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DDATA_SPRAM_BANK6_ECC_SVBUS_RAM_ID,
23475  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DDATA_SPRAM_BANK6_ECC_SVBUS_INJECT_TYPE,
23476  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DDATA_SPRAM_BANK6_ECC_SVBUS_ECC_TYPE,
23477  0u,
23478  NULL },
23479  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DDATA_SPRAM_BANK7_ECC_SVBUS_RAM_ID,
23480  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DDATA_SPRAM_BANK7_ECC_SVBUS_INJECT_TYPE,
23481  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DDATA_SPRAM_BANK7_ECC_SVBUS_ECC_TYPE,
23482  0u,
23483  NULL },
23484  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DTAG_SPRAM_BANK0_ECC_SVBUS_RAM_ID,
23485  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DTAG_SPRAM_BANK0_ECC_SVBUS_INJECT_TYPE,
23486  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DTAG_SPRAM_BANK0_ECC_SVBUS_ECC_TYPE,
23487  0u,
23488  NULL },
23489  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DTAG_SPRAM_BANK1_ECC_SVBUS_RAM_ID,
23490  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DTAG_SPRAM_BANK1_ECC_SVBUS_INJECT_TYPE,
23491  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DTAG_SPRAM_BANK1_ECC_SVBUS_ECC_TYPE,
23492  0u,
23493  NULL },
23494  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DTAG_SPRAM_BANK2_ECC_SVBUS_RAM_ID,
23495  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DTAG_SPRAM_BANK2_ECC_SVBUS_INJECT_TYPE,
23496  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DTAG_SPRAM_BANK2_ECC_SVBUS_ECC_TYPE,
23497  0u,
23498  NULL },
23499  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DTAG_SPRAM_BANK3_ECC_SVBUS_RAM_ID,
23500  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DTAG_SPRAM_BANK3_ECC_SVBUS_INJECT_TYPE,
23501  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DTAG_SPRAM_BANK3_ECC_SVBUS_ECC_TYPE,
23502  0u,
23503  NULL },
23504  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DDIRTY_SPRAM_ECC_SVBUS_RAM_ID,
23505  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DDIRTY_SPRAM_ECC_SVBUS_INJECT_TYPE,
23506  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DDIRTY_SPRAM_ECC_SVBUS_ECC_TYPE,
23507  0u,
23508  NULL },
23509  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_TLB_SPRAM_BANK0_ECC_SVBUS_RAM_ID,
23510  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_TLB_SPRAM_BANK0_ECC_SVBUS_INJECT_TYPE,
23511  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_TLB_SPRAM_BANK0_ECC_SVBUS_ECC_TYPE,
23512  0u,
23513  NULL },
23514  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_TLB_SPRAM_BANK1_ECC_SVBUS_RAM_ID,
23515  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_TLB_SPRAM_BANK1_ECC_SVBUS_INJECT_TYPE,
23516  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_TLB_SPRAM_BANK1_ECC_SVBUS_ECC_TYPE,
23517  0u,
23518  NULL },
23519  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_TLB_SPRAM_BANK2_ECC_SVBUS_RAM_ID,
23520  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_TLB_SPRAM_BANK2_ECC_SVBUS_INJECT_TYPE,
23521  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_TLB_SPRAM_BANK2_ECC_SVBUS_ECC_TYPE,
23522  0u,
23523  NULL },
23524  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_TLB_SPRAM_BANK3_ECC_SVBUS_RAM_ID,
23525  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_TLB_SPRAM_BANK3_ECC_SVBUS_INJECT_TYPE,
23526  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_TLB_SPRAM_BANK3_ECC_SVBUS_ECC_TYPE,
23527  0u,
23528  NULL },
23529  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY0_ECC_SVBUS_RAM_ID,
23530  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY0_ECC_SVBUS_INJECT_TYPE,
23531  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY0_ECC_SVBUS_ECC_TYPE,
23532  0u,
23533  NULL },
23534  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY1_ECC_SVBUS_RAM_ID,
23535  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY1_ECC_SVBUS_INJECT_TYPE,
23536  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY1_ECC_SVBUS_ECC_TYPE,
23537  0u,
23538  NULL },
23539  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY2_ECC_SVBUS_RAM_ID,
23540  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY2_ECC_SVBUS_INJECT_TYPE,
23541  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY2_ECC_SVBUS_ECC_TYPE,
23542  0u,
23543  NULL },
23544  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY3_ECC_SVBUS_RAM_ID,
23545  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY3_ECC_SVBUS_INJECT_TYPE,
23546  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY3_ECC_SVBUS_ECC_TYPE,
23547  0u,
23548  NULL },
23549 };
23550 
23555 static const SDL_RAMIdEntry_t SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_RamIdTable[SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_NUM_RAMS] =
23556 {
23557  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_IDATA_SPRAM_BANK0_LO_ECC_SVBUS_RAM_ID,
23558  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_IDATA_SPRAM_BANK0_LO_ECC_SVBUS_INJECT_TYPE,
23559  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_IDATA_SPRAM_BANK0_LO_ECC_SVBUS_ECC_TYPE,
23560  0u,
23561  NULL },
23562  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_IDATA_SPRAM_BANK0_HI_ECC_SVBUS_RAM_ID,
23563  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_IDATA_SPRAM_BANK0_HI_ECC_SVBUS_INJECT_TYPE,
23564  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_IDATA_SPRAM_BANK0_HI_ECC_SVBUS_ECC_TYPE,
23565  0u,
23566  NULL },
23567  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_IDATA_SPRAM_BANK1_LO_ECC_SVBUS_RAM_ID,
23568  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_IDATA_SPRAM_BANK1_LO_ECC_SVBUS_INJECT_TYPE,
23569  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_IDATA_SPRAM_BANK1_LO_ECC_SVBUS_ECC_TYPE,
23570  0u,
23571  NULL },
23572  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_IDATA_SPRAM_BANK1_HI_ECC_SVBUS_RAM_ID,
23573  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_IDATA_SPRAM_BANK1_HI_ECC_SVBUS_INJECT_TYPE,
23574  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_IDATA_SPRAM_BANK1_HI_ECC_SVBUS_ECC_TYPE,
23575  0u,
23576  NULL },
23577  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_ITAG_SPRAM_RAM0_ECC_SVBUS_RAM_ID,
23578  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_ITAG_SPRAM_RAM0_ECC_SVBUS_INJECT_TYPE,
23579  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_ITAG_SPRAM_RAM0_ECC_SVBUS_ECC_TYPE,
23580  0u,
23581  NULL },
23582  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_ITAG_SPRAM_RAM1_ECC_SVBUS_RAM_ID,
23583  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_ITAG_SPRAM_RAM1_ECC_SVBUS_INJECT_TYPE,
23584  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_ITAG_SPRAM_RAM1_ECC_SVBUS_ECC_TYPE,
23585  0u,
23586  NULL },
23587  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DDATA_SPRAM_BANK0_ECC_SVBUS_RAM_ID,
23588  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DDATA_SPRAM_BANK0_ECC_SVBUS_INJECT_TYPE,
23589  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DDATA_SPRAM_BANK0_ECC_SVBUS_ECC_TYPE,
23590  0u,
23591  NULL },
23592  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DDATA_SPRAM_BANK1_ECC_SVBUS_RAM_ID,
23593  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DDATA_SPRAM_BANK1_ECC_SVBUS_INJECT_TYPE,
23594  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DDATA_SPRAM_BANK1_ECC_SVBUS_ECC_TYPE,
23595  0u,
23596  NULL },
23597  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DDATA_SPRAM_BANK2_ECC_SVBUS_RAM_ID,
23598  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DDATA_SPRAM_BANK2_ECC_SVBUS_INJECT_TYPE,
23599  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DDATA_SPRAM_BANK2_ECC_SVBUS_ECC_TYPE,
23600  0u,
23601  NULL },
23602  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DDATA_SPRAM_BANK3_ECC_SVBUS_RAM_ID,
23603  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DDATA_SPRAM_BANK3_ECC_SVBUS_INJECT_TYPE,
23604  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DDATA_SPRAM_BANK3_ECC_SVBUS_ECC_TYPE,
23605  0u,
23606  NULL },
23607  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DDATA_SPRAM_BANK4_ECC_SVBUS_RAM_ID,
23608  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DDATA_SPRAM_BANK4_ECC_SVBUS_INJECT_TYPE,
23609  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DDATA_SPRAM_BANK4_ECC_SVBUS_ECC_TYPE,
23610  0u,
23611  NULL },
23612  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DDATA_SPRAM_BANK5_ECC_SVBUS_RAM_ID,
23613  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DDATA_SPRAM_BANK5_ECC_SVBUS_INJECT_TYPE,
23614  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DDATA_SPRAM_BANK5_ECC_SVBUS_ECC_TYPE,
23615  0u,
23616  NULL },
23617  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DDATA_SPRAM_BANK6_ECC_SVBUS_RAM_ID,
23618  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DDATA_SPRAM_BANK6_ECC_SVBUS_INJECT_TYPE,
23619  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DDATA_SPRAM_BANK6_ECC_SVBUS_ECC_TYPE,
23620  0u,
23621  NULL },
23622  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DDATA_SPRAM_BANK7_ECC_SVBUS_RAM_ID,
23623  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DDATA_SPRAM_BANK7_ECC_SVBUS_INJECT_TYPE,
23624  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DDATA_SPRAM_BANK7_ECC_SVBUS_ECC_TYPE,
23625  0u,
23626  NULL },
23627  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DTAG_SPRAM_BANK0_ECC_SVBUS_RAM_ID,
23628  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DTAG_SPRAM_BANK0_ECC_SVBUS_INJECT_TYPE,
23629  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DTAG_SPRAM_BANK0_ECC_SVBUS_ECC_TYPE,
23630  0u,
23631  NULL },
23632  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DTAG_SPRAM_BANK1_ECC_SVBUS_RAM_ID,
23633  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DTAG_SPRAM_BANK1_ECC_SVBUS_INJECT_TYPE,
23634  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DTAG_SPRAM_BANK1_ECC_SVBUS_ECC_TYPE,
23635  0u,
23636  NULL },
23637  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DTAG_SPRAM_BANK2_ECC_SVBUS_RAM_ID,
23638  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DTAG_SPRAM_BANK2_ECC_SVBUS_INJECT_TYPE,
23639  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DTAG_SPRAM_BANK2_ECC_SVBUS_ECC_TYPE,
23640  0u,
23641  NULL },
23642  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DTAG_SPRAM_BANK3_ECC_SVBUS_RAM_ID,
23643  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DTAG_SPRAM_BANK3_ECC_SVBUS_INJECT_TYPE,
23644  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DTAG_SPRAM_BANK3_ECC_SVBUS_ECC_TYPE,
23645  0u,
23646  NULL },
23647  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DDIRTY_SPRAM_ECC_SVBUS_RAM_ID,
23648  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DDIRTY_SPRAM_ECC_SVBUS_INJECT_TYPE,
23649  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DDIRTY_SPRAM_ECC_SVBUS_ECC_TYPE,
23650  0u,
23651  NULL },
23652  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_TLB_SPRAM_BANK0_ECC_SVBUS_RAM_ID,
23653  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_TLB_SPRAM_BANK0_ECC_SVBUS_INJECT_TYPE,
23654  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_TLB_SPRAM_BANK0_ECC_SVBUS_ECC_TYPE,
23655  0u,
23656  NULL },
23657  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_TLB_SPRAM_BANK1_ECC_SVBUS_RAM_ID,
23658  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_TLB_SPRAM_BANK1_ECC_SVBUS_INJECT_TYPE,
23659  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_TLB_SPRAM_BANK1_ECC_SVBUS_ECC_TYPE,
23660  0u,
23661  NULL },
23662  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_TLB_SPRAM_BANK2_ECC_SVBUS_RAM_ID,
23663  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_TLB_SPRAM_BANK2_ECC_SVBUS_INJECT_TYPE,
23664  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_TLB_SPRAM_BANK2_ECC_SVBUS_ECC_TYPE,
23665  0u,
23666  NULL },
23667  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_TLB_SPRAM_BANK3_ECC_SVBUS_RAM_ID,
23668  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_TLB_SPRAM_BANK3_ECC_SVBUS_INJECT_TYPE,
23669  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_TLB_SPRAM_BANK3_ECC_SVBUS_ECC_TYPE,
23670  0u,
23671  NULL },
23672  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY0_ECC_SVBUS_RAM_ID,
23673  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY0_ECC_SVBUS_INJECT_TYPE,
23674  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY0_ECC_SVBUS_ECC_TYPE,
23675  0u,
23676  NULL },
23677  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY1_ECC_SVBUS_RAM_ID,
23678  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY1_ECC_SVBUS_INJECT_TYPE,
23679  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY1_ECC_SVBUS_ECC_TYPE,
23680  0u,
23681  NULL },
23682  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY2_ECC_SVBUS_RAM_ID,
23683  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY2_ECC_SVBUS_INJECT_TYPE,
23684  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY2_ECC_SVBUS_ECC_TYPE,
23685  0u,
23686  NULL },
23687  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY3_ECC_SVBUS_RAM_ID,
23688  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY3_ECC_SVBUS_INJECT_TYPE,
23689  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY3_ECC_SVBUS_ECC_TYPE,
23690  0u,
23691  NULL },
23692 };
23693 
23698 static const SDL_RAMIdEntry_t SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_RamIdTable[SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_NUM_RAMS] =
23699 {
23700  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_IDATA_SPRAM_BANK0_LO_ECC_SVBUS_RAM_ID,
23701  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_IDATA_SPRAM_BANK0_LO_ECC_SVBUS_INJECT_TYPE,
23702  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_IDATA_SPRAM_BANK0_LO_ECC_SVBUS_ECC_TYPE,
23703  0u,
23704  NULL },
23705  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_IDATA_SPRAM_BANK0_HI_ECC_SVBUS_RAM_ID,
23706  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_IDATA_SPRAM_BANK0_HI_ECC_SVBUS_INJECT_TYPE,
23707  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_IDATA_SPRAM_BANK0_HI_ECC_SVBUS_ECC_TYPE,
23708  0u,
23709  NULL },
23710  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_IDATA_SPRAM_BANK1_LO_ECC_SVBUS_RAM_ID,
23711  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_IDATA_SPRAM_BANK1_LO_ECC_SVBUS_INJECT_TYPE,
23712  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_IDATA_SPRAM_BANK1_LO_ECC_SVBUS_ECC_TYPE,
23713  0u,
23714  NULL },
23715  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_IDATA_SPRAM_BANK1_HI_ECC_SVBUS_RAM_ID,
23716  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_IDATA_SPRAM_BANK1_HI_ECC_SVBUS_INJECT_TYPE,
23717  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_IDATA_SPRAM_BANK1_HI_ECC_SVBUS_ECC_TYPE,
23718  0u,
23719  NULL },
23720  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_ITAG_SPRAM_RAM0_ECC_SVBUS_RAM_ID,
23721  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_ITAG_SPRAM_RAM0_ECC_SVBUS_INJECT_TYPE,
23722  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_ITAG_SPRAM_RAM0_ECC_SVBUS_ECC_TYPE,
23723  0u,
23724  NULL },
23725  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_ITAG_SPRAM_RAM1_ECC_SVBUS_RAM_ID,
23726  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_ITAG_SPRAM_RAM1_ECC_SVBUS_INJECT_TYPE,
23727  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_ITAG_SPRAM_RAM1_ECC_SVBUS_ECC_TYPE,
23728  0u,
23729  NULL },
23730  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DDATA_SPRAM_BANK0_ECC_SVBUS_RAM_ID,
23731  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DDATA_SPRAM_BANK0_ECC_SVBUS_INJECT_TYPE,
23732  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DDATA_SPRAM_BANK0_ECC_SVBUS_ECC_TYPE,
23733  0u,
23734  NULL },
23735  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DDATA_SPRAM_BANK1_ECC_SVBUS_RAM_ID,
23736  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DDATA_SPRAM_BANK1_ECC_SVBUS_INJECT_TYPE,
23737  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DDATA_SPRAM_BANK1_ECC_SVBUS_ECC_TYPE,
23738  0u,
23739  NULL },
23740  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DDATA_SPRAM_BANK2_ECC_SVBUS_RAM_ID,
23741  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DDATA_SPRAM_BANK2_ECC_SVBUS_INJECT_TYPE,
23742  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DDATA_SPRAM_BANK2_ECC_SVBUS_ECC_TYPE,
23743  0u,
23744  NULL },
23745  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DDATA_SPRAM_BANK3_ECC_SVBUS_RAM_ID,
23746  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DDATA_SPRAM_BANK3_ECC_SVBUS_INJECT_TYPE,
23747  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DDATA_SPRAM_BANK3_ECC_SVBUS_ECC_TYPE,
23748  0u,
23749  NULL },
23750  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DDATA_SPRAM_BANK4_ECC_SVBUS_RAM_ID,
23751  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DDATA_SPRAM_BANK4_ECC_SVBUS_INJECT_TYPE,
23752  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DDATA_SPRAM_BANK4_ECC_SVBUS_ECC_TYPE,
23753  0u,
23754  NULL },
23755  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DDATA_SPRAM_BANK5_ECC_SVBUS_RAM_ID,
23756  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DDATA_SPRAM_BANK5_ECC_SVBUS_INJECT_TYPE,
23757  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DDATA_SPRAM_BANK5_ECC_SVBUS_ECC_TYPE,
23758  0u,
23759  NULL },
23760  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DDATA_SPRAM_BANK6_ECC_SVBUS_RAM_ID,
23761  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DDATA_SPRAM_BANK6_ECC_SVBUS_INJECT_TYPE,
23762  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DDATA_SPRAM_BANK6_ECC_SVBUS_ECC_TYPE,
23763  0u,
23764  NULL },
23765  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DDATA_SPRAM_BANK7_ECC_SVBUS_RAM_ID,
23766  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DDATA_SPRAM_BANK7_ECC_SVBUS_INJECT_TYPE,
23767  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DDATA_SPRAM_BANK7_ECC_SVBUS_ECC_TYPE,
23768  0u,
23769  NULL },
23770  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DTAG_SPRAM_BANK0_ECC_SVBUS_RAM_ID,
23771  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DTAG_SPRAM_BANK0_ECC_SVBUS_INJECT_TYPE,
23772  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DTAG_SPRAM_BANK0_ECC_SVBUS_ECC_TYPE,
23773  0u,
23774  NULL },
23775  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DTAG_SPRAM_BANK1_ECC_SVBUS_RAM_ID,
23776  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DTAG_SPRAM_BANK1_ECC_SVBUS_INJECT_TYPE,
23777  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DTAG_SPRAM_BANK1_ECC_SVBUS_ECC_TYPE,
23778  0u,
23779  NULL },
23780  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DTAG_SPRAM_BANK2_ECC_SVBUS_RAM_ID,
23781  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DTAG_SPRAM_BANK2_ECC_SVBUS_INJECT_TYPE,
23782  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DTAG_SPRAM_BANK2_ECC_SVBUS_ECC_TYPE,
23783  0u,
23784  NULL },
23785  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DTAG_SPRAM_BANK3_ECC_SVBUS_RAM_ID,
23786  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DTAG_SPRAM_BANK3_ECC_SVBUS_INJECT_TYPE,
23787  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DTAG_SPRAM_BANK3_ECC_SVBUS_ECC_TYPE,
23788  0u,
23789  NULL },
23790  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DDIRTY_SPRAM_ECC_SVBUS_RAM_ID,
23791  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DDIRTY_SPRAM_ECC_SVBUS_INJECT_TYPE,
23792  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DDIRTY_SPRAM_ECC_SVBUS_ECC_TYPE,
23793  0u,
23794  NULL },
23795  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_TLB_SPRAM_BANK0_ECC_SVBUS_RAM_ID,
23796  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_TLB_SPRAM_BANK0_ECC_SVBUS_INJECT_TYPE,
23797  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_TLB_SPRAM_BANK0_ECC_SVBUS_ECC_TYPE,
23798  0u,
23799  NULL },
23800  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_TLB_SPRAM_BANK1_ECC_SVBUS_RAM_ID,
23801  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_TLB_SPRAM_BANK1_ECC_SVBUS_INJECT_TYPE,
23802  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_TLB_SPRAM_BANK1_ECC_SVBUS_ECC_TYPE,
23803  0u,
23804  NULL },
23805  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_TLB_SPRAM_BANK2_ECC_SVBUS_RAM_ID,
23806  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_TLB_SPRAM_BANK2_ECC_SVBUS_INJECT_TYPE,
23807  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_TLB_SPRAM_BANK2_ECC_SVBUS_ECC_TYPE,
23808  0u,
23809  NULL },
23810  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_TLB_SPRAM_BANK3_ECC_SVBUS_RAM_ID,
23811  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_TLB_SPRAM_BANK3_ECC_SVBUS_INJECT_TYPE,
23812  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_TLB_SPRAM_BANK3_ECC_SVBUS_ECC_TYPE,
23813  0u,
23814  NULL },
23815  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY0_ECC_SVBUS_RAM_ID,
23816  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY0_ECC_SVBUS_INJECT_TYPE,
23817  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY0_ECC_SVBUS_ECC_TYPE,
23818  0u,
23819  NULL },
23820  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY1_ECC_SVBUS_RAM_ID,
23821  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY1_ECC_SVBUS_INJECT_TYPE,
23822  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY1_ECC_SVBUS_ECC_TYPE,
23823  0u,
23824  NULL },
23825  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY2_ECC_SVBUS_RAM_ID,
23826  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY2_ECC_SVBUS_INJECT_TYPE,
23827  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY2_ECC_SVBUS_ECC_TYPE,
23828  0u,
23829  NULL },
23830  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY3_ECC_SVBUS_RAM_ID,
23831  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY3_ECC_SVBUS_INJECT_TYPE,
23832  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY3_ECC_SVBUS_ECC_TYPE,
23833  0u,
23834  NULL },
23835 };
23836 
23841 static const SDL_RAMIdEntry_t SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_RamIdTable[SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_NUM_RAMS] =
23842 {
23843  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_IDATA_SPRAM_BANK0_LO_ECC_SVBUS_RAM_ID,
23844  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_IDATA_SPRAM_BANK0_LO_ECC_SVBUS_INJECT_TYPE,
23845  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_IDATA_SPRAM_BANK0_LO_ECC_SVBUS_ECC_TYPE,
23846  0u,
23847  NULL },
23848  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_IDATA_SPRAM_BANK0_HI_ECC_SVBUS_RAM_ID,
23849  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_IDATA_SPRAM_BANK0_HI_ECC_SVBUS_INJECT_TYPE,
23850  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_IDATA_SPRAM_BANK0_HI_ECC_SVBUS_ECC_TYPE,
23851  0u,
23852  NULL },
23853  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_IDATA_SPRAM_BANK1_LO_ECC_SVBUS_RAM_ID,
23854  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_IDATA_SPRAM_BANK1_LO_ECC_SVBUS_INJECT_TYPE,
23855  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_IDATA_SPRAM_BANK1_LO_ECC_SVBUS_ECC_TYPE,
23856  0u,
23857  NULL },
23858  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_IDATA_SPRAM_BANK1_HI_ECC_SVBUS_RAM_ID,
23859  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_IDATA_SPRAM_BANK1_HI_ECC_SVBUS_INJECT_TYPE,
23860  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_IDATA_SPRAM_BANK1_HI_ECC_SVBUS_ECC_TYPE,
23861  0u,
23862  NULL },
23863  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_ITAG_SPRAM_RAM0_ECC_SVBUS_RAM_ID,
23864  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_ITAG_SPRAM_RAM0_ECC_SVBUS_INJECT_TYPE,
23865  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_ITAG_SPRAM_RAM0_ECC_SVBUS_ECC_TYPE,
23866  0u,
23867  NULL },
23868  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_ITAG_SPRAM_RAM1_ECC_SVBUS_RAM_ID,
23869  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_ITAG_SPRAM_RAM1_ECC_SVBUS_INJECT_TYPE,
23870  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_ITAG_SPRAM_RAM1_ECC_SVBUS_ECC_TYPE,
23871  0u,
23872  NULL },
23873  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DDATA_SPRAM_BANK0_ECC_SVBUS_RAM_ID,
23874  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DDATA_SPRAM_BANK0_ECC_SVBUS_INJECT_TYPE,
23875  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DDATA_SPRAM_BANK0_ECC_SVBUS_ECC_TYPE,
23876  0u,
23877  NULL },
23878  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DDATA_SPRAM_BANK1_ECC_SVBUS_RAM_ID,
23879  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DDATA_SPRAM_BANK1_ECC_SVBUS_INJECT_TYPE,
23880  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DDATA_SPRAM_BANK1_ECC_SVBUS_ECC_TYPE,
23881  0u,
23882  NULL },
23883  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DDATA_SPRAM_BANK2_ECC_SVBUS_RAM_ID,
23884  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DDATA_SPRAM_BANK2_ECC_SVBUS_INJECT_TYPE,
23885  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DDATA_SPRAM_BANK2_ECC_SVBUS_ECC_TYPE,
23886  0u,
23887  NULL },
23888  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DDATA_SPRAM_BANK3_ECC_SVBUS_RAM_ID,
23889  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DDATA_SPRAM_BANK3_ECC_SVBUS_INJECT_TYPE,
23890  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DDATA_SPRAM_BANK3_ECC_SVBUS_ECC_TYPE,
23891  0u,
23892  NULL },
23893  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DDATA_SPRAM_BANK4_ECC_SVBUS_RAM_ID,
23894  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DDATA_SPRAM_BANK4_ECC_SVBUS_INJECT_TYPE,
23895  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DDATA_SPRAM_BANK4_ECC_SVBUS_ECC_TYPE,
23896  0u,
23897  NULL },
23898  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DDATA_SPRAM_BANK5_ECC_SVBUS_RAM_ID,
23899  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DDATA_SPRAM_BANK5_ECC_SVBUS_INJECT_TYPE,
23900  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DDATA_SPRAM_BANK5_ECC_SVBUS_ECC_TYPE,
23901  0u,
23902  NULL },
23903  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DDATA_SPRAM_BANK6_ECC_SVBUS_RAM_ID,
23904  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DDATA_SPRAM_BANK6_ECC_SVBUS_INJECT_TYPE,
23905  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DDATA_SPRAM_BANK6_ECC_SVBUS_ECC_TYPE,
23906  0u,
23907  NULL },
23908  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DDATA_SPRAM_BANK7_ECC_SVBUS_RAM_ID,
23909  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DDATA_SPRAM_BANK7_ECC_SVBUS_INJECT_TYPE,
23910  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DDATA_SPRAM_BANK7_ECC_SVBUS_ECC_TYPE,
23911  0u,
23912  NULL },
23913  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DTAG_SPRAM_BANK0_ECC_SVBUS_RAM_ID,
23914  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DTAG_SPRAM_BANK0_ECC_SVBUS_INJECT_TYPE,
23915  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DTAG_SPRAM_BANK0_ECC_SVBUS_ECC_TYPE,
23916  0u,
23917  NULL },
23918  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DTAG_SPRAM_BANK1_ECC_SVBUS_RAM_ID,
23919  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DTAG_SPRAM_BANK1_ECC_SVBUS_INJECT_TYPE,
23920  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DTAG_SPRAM_BANK1_ECC_SVBUS_ECC_TYPE,
23921  0u,
23922  NULL },
23923  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DTAG_SPRAM_BANK2_ECC_SVBUS_RAM_ID,
23924  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DTAG_SPRAM_BANK2_ECC_SVBUS_INJECT_TYPE,
23925  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DTAG_SPRAM_BANK2_ECC_SVBUS_ECC_TYPE,
23926  0u,
23927  NULL },
23928  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DTAG_SPRAM_BANK3_ECC_SVBUS_RAM_ID,
23929  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DTAG_SPRAM_BANK3_ECC_SVBUS_INJECT_TYPE,
23930  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DTAG_SPRAM_BANK3_ECC_SVBUS_ECC_TYPE,
23931  0u,
23932  NULL },
23933  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DDIRTY_SPRAM_ECC_SVBUS_RAM_ID,
23934  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DDIRTY_SPRAM_ECC_SVBUS_INJECT_TYPE,
23935  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DDIRTY_SPRAM_ECC_SVBUS_ECC_TYPE,
23936  0u,
23937  NULL },
23938  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_TLB_SPRAM_BANK0_ECC_SVBUS_RAM_ID,
23939  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_TLB_SPRAM_BANK0_ECC_SVBUS_INJECT_TYPE,
23940  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_TLB_SPRAM_BANK0_ECC_SVBUS_ECC_TYPE,
23941  0u,
23942  NULL },
23943  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_TLB_SPRAM_BANK1_ECC_SVBUS_RAM_ID,
23944  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_TLB_SPRAM_BANK1_ECC_SVBUS_INJECT_TYPE,
23945  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_TLB_SPRAM_BANK1_ECC_SVBUS_ECC_TYPE,
23946  0u,
23947  NULL },
23948  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_TLB_SPRAM_BANK2_ECC_SVBUS_RAM_ID,
23949  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_TLB_SPRAM_BANK2_ECC_SVBUS_INJECT_TYPE,
23950  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_TLB_SPRAM_BANK2_ECC_SVBUS_ECC_TYPE,
23951  0u,
23952  NULL },
23953  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_TLB_SPRAM_BANK3_ECC_SVBUS_RAM_ID,
23954  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_TLB_SPRAM_BANK3_ECC_SVBUS_INJECT_TYPE,
23955  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_TLB_SPRAM_BANK3_ECC_SVBUS_ECC_TYPE,
23956  0u,
23957  NULL },
23958  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY0_ECC_SVBUS_RAM_ID,
23959  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY0_ECC_SVBUS_INJECT_TYPE,
23960  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY0_ECC_SVBUS_ECC_TYPE,
23961  0u,
23962  NULL },
23963  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY1_ECC_SVBUS_RAM_ID,
23964  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY1_ECC_SVBUS_INJECT_TYPE,
23965  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY1_ECC_SVBUS_ECC_TYPE,
23966  0u,
23967  NULL },
23968  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY2_ECC_SVBUS_RAM_ID,
23969  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY2_ECC_SVBUS_INJECT_TYPE,
23970  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY2_ECC_SVBUS_ECC_TYPE,
23971  0u,
23972  NULL },
23973  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY3_ECC_SVBUS_RAM_ID,
23974  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY3_ECC_SVBUS_INJECT_TYPE,
23975  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY3_ECC_SVBUS_ECC_TYPE,
23976  0u,
23977  NULL },
23978 };
23979 
23984 static const SDL_RAMIdEntry_t SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_RamIdTable[SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_NUM_RAMS] =
23985 {
23986  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY0_ECC_SVBUS_RAM_ID,
23987  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY0_ECC_SVBUS_INJECT_TYPE,
23988  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY0_ECC_SVBUS_ECC_TYPE,
23989  0u,
23990  NULL },
23991  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY1_ECC_SVBUS_RAM_ID,
23992  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY1_ECC_SVBUS_INJECT_TYPE,
23993  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY1_ECC_SVBUS_ECC_TYPE,
23994  0u,
23995  NULL },
23996  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY2_ECC_SVBUS_RAM_ID,
23997  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY2_ECC_SVBUS_INJECT_TYPE,
23998  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY2_ECC_SVBUS_ECC_TYPE,
23999  0u,
24000  NULL },
24001  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY3_ECC_SVBUS_RAM_ID,
24002  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY3_ECC_SVBUS_INJECT_TYPE,
24003  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY3_ECC_SVBUS_ECC_TYPE,
24004  0u,
24005  NULL },
24006  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY4_ECC_SVBUS_RAM_ID,
24007  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY4_ECC_SVBUS_INJECT_TYPE,
24008  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY4_ECC_SVBUS_ECC_TYPE,
24009  0u,
24010  NULL },
24011  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY5_ECC_SVBUS_RAM_ID,
24012  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY5_ECC_SVBUS_INJECT_TYPE,
24013  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY5_ECC_SVBUS_ECC_TYPE,
24014  0u,
24015  NULL },
24016  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY6_ECC_SVBUS_RAM_ID,
24017  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY6_ECC_SVBUS_INJECT_TYPE,
24018  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY6_ECC_SVBUS_ECC_TYPE,
24019  0u,
24020  NULL },
24021  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY7_ECC_SVBUS_RAM_ID,
24022  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY7_ECC_SVBUS_INJECT_TYPE,
24023  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY7_ECC_SVBUS_ECC_TYPE,
24024  0u,
24025  NULL },
24026  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY8_ECC_SVBUS_RAM_ID,
24027  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY8_ECC_SVBUS_INJECT_TYPE,
24028  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY8_ECC_SVBUS_ECC_TYPE,
24029  0u,
24030  NULL },
24031  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY9_ECC_SVBUS_RAM_ID,
24032  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY9_ECC_SVBUS_INJECT_TYPE,
24033  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY9_ECC_SVBUS_ECC_TYPE,
24034  0u,
24035  NULL },
24036  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY10_ECC_SVBUS_RAM_ID,
24037  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY10_ECC_SVBUS_INJECT_TYPE,
24038  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY10_ECC_SVBUS_ECC_TYPE,
24039  0u,
24040  NULL },
24041  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY11_ECC_SVBUS_RAM_ID,
24042  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY11_ECC_SVBUS_INJECT_TYPE,
24043  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY11_ECC_SVBUS_ECC_TYPE,
24044  0u,
24045  NULL },
24046  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY12_ECC_SVBUS_RAM_ID,
24047  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY12_ECC_SVBUS_INJECT_TYPE,
24048  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY12_ECC_SVBUS_ECC_TYPE,
24049  0u,
24050  NULL },
24051  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY13_ECC_SVBUS_RAM_ID,
24052  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY13_ECC_SVBUS_INJECT_TYPE,
24053  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY13_ECC_SVBUS_ECC_TYPE,
24054  0u,
24055  NULL },
24056  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY14_ECC_SVBUS_RAM_ID,
24057  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY14_ECC_SVBUS_INJECT_TYPE,
24058  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY14_ECC_SVBUS_ECC_TYPE,
24059  0u,
24060  NULL },
24061  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY15_ECC_SVBUS_RAM_ID,
24062  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY15_ECC_SVBUS_INJECT_TYPE,
24063  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY15_ECC_SVBUS_ECC_TYPE,
24064  0u,
24065  NULL },
24066  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_DATARAM_SPRAM_0_ECC_SVBUS_RAM_ID,
24067  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_DATARAM_SPRAM_0_ECC_SVBUS_INJECT_TYPE,
24068  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_DATARAM_SPRAM_0_ECC_SVBUS_ECC_TYPE,
24069  0u,
24070  NULL },
24071  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_DATARAM_SPRAM_1_ECC_SVBUS_RAM_ID,
24072  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_DATARAM_SPRAM_1_ECC_SVBUS_INJECT_TYPE,
24073  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_DATARAM_SPRAM_1_ECC_SVBUS_ECC_TYPE,
24074  0u,
24075  NULL },
24076  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_DATARAM_SPRAM_2_ECC_SVBUS_RAM_ID,
24077  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_DATARAM_SPRAM_2_ECC_SVBUS_INJECT_TYPE,
24078  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_DATARAM_SPRAM_2_ECC_SVBUS_ECC_TYPE,
24079  0u,
24080  NULL },
24081  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_DATARAM_SPRAM_3_ECC_SVBUS_RAM_ID,
24082  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_DATARAM_SPRAM_3_ECC_SVBUS_INJECT_TYPE,
24083  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_DATARAM_SPRAM_3_ECC_SVBUS_ECC_TYPE,
24084  0u,
24085  NULL },
24086  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_DATARAM_SPRAM_4_ECC_SVBUS_RAM_ID,
24087  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_DATARAM_SPRAM_4_ECC_SVBUS_INJECT_TYPE,
24088  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_DATARAM_SPRAM_4_ECC_SVBUS_ECC_TYPE,
24089  0u,
24090  NULL },
24091  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_DATARAM_SPRAM_5_ECC_SVBUS_RAM_ID,
24092  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_DATARAM_SPRAM_5_ECC_SVBUS_INJECT_TYPE,
24093  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_DATARAM_SPRAM_5_ECC_SVBUS_ECC_TYPE,
24094  0u,
24095  NULL },
24096  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_DATARAM_SPRAM_6_ECC_SVBUS_RAM_ID,
24097  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_DATARAM_SPRAM_6_ECC_SVBUS_INJECT_TYPE,
24098  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_DATARAM_SPRAM_6_ECC_SVBUS_ECC_TYPE,
24099  0u,
24100  NULL },
24101  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_DATARAM_SPRAM_7_ECC_SVBUS_RAM_ID,
24102  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_DATARAM_SPRAM_7_ECC_SVBUS_INJECT_TYPE,
24103  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_DATARAM_SPRAM_7_ECC_SVBUS_ECC_TYPE,
24104  0u,
24105  NULL },
24106 };
24107 
24112 static const SDL_RAMIdEntry_t SDL_MCU_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_RamIdTable[SDL_MCU_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_NUM_RAMS] =
24113 {
24114  { SDL_MCU_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_ID,
24115  SDL_MCU_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_INJECT_TYPE,
24116  SDL_MCU_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_ECC_TYPE,
24117  0u,
24118  NULL },
24119  { SDL_MCU_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_RAM_ID,
24120  SDL_MCU_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_INJECT_TYPE,
24121  SDL_MCU_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_ECC_TYPE,
24122  SDL_MCU_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_MAX_NUM_CHECKERS,
24123  SDL_MCU_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_groupEntries },
24124 };
24125 
24130 static const SDL_RAMIdEntry_t SDL_MCU_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_RamIdTable[SDL_MCU_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_NUM_RAMS] =
24131 {
24132  { SDL_MCU_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_ID,
24133  SDL_MCU_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_INJECT_TYPE,
24134  SDL_MCU_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_ECC_TYPE,
24135  0u,
24136  NULL },
24137  { SDL_MCU_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_RAM_ID,
24138  SDL_MCU_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_INJECT_TYPE,
24139  SDL_MCU_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_ECC_TYPE,
24140  SDL_MCU_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_MAX_NUM_CHECKERS,
24141  SDL_MCU_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_groupEntries },
24142 };
24143 
24148 static const SDL_RAMIdEntry_t SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_RamIdTable[SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_NUM_RAMS] =
24149 {
24150  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_IMAILBOX4_MAIN_0_RAMECC_RAM_ID,
24151  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_IMAILBOX4_MAIN_0_RAMECC_INJECT_TYPE,
24152  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_IMAILBOX4_MAIN_0_RAMECC_ECC_TYPE,
24153  0u,
24154  NULL },
24155  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_RAM_ID,
24156  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_INJECT_TYPE,
24157  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_ECC_TYPE,
24158  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_MAX_NUM_CHECKERS,
24159  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_groupEntries },
24160  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_HSM_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_HSM_VBUSP_S_BRIDGE_BUSECC_RAM_ID,
24161  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_HSM_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_HSM_VBUSP_S_BRIDGE_BUSECC_INJECT_TYPE,
24162  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_HSM_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_HSM_VBUSP_S_BRIDGE_BUSECC_ECC_TYPE,
24163  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_HSM_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_HSM_VBUSP_S_BRIDGE_BUSECC_MAX_NUM_CHECKERS,
24164  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_HSM_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_HSM_VBUSP_S_BRIDGE_BUSECC_groupEntries },
24165  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_TIFS_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_TIFS_VBUSP_S_BRIDGE_BUSECC_RAM_ID,
24166  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_TIFS_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_TIFS_VBUSP_S_BRIDGE_BUSECC_INJECT_TYPE,
24167  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_TIFS_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_TIFS_VBUSP_S_BRIDGE_BUSECC_ECC_TYPE,
24168  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_TIFS_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_TIFS_VBUSP_S_BRIDGE_BUSECC_MAX_NUM_CHECKERS,
24169  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_TIFS_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_TIFS_VBUSP_S_BRIDGE_BUSECC_groupEntries },
24170  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_RAM_ID,
24171  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_INJECT_TYPE,
24172  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_ECC_TYPE,
24173  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_MAX_NUM_CHECKERS,
24174  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_groupEntries },
24175  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_FW_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_RAM_ID,
24176  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_FW_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_INJECT_TYPE,
24177  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_FW_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_ECC_TYPE,
24178  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_FW_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_MAX_NUM_CHECKERS,
24179  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_FW_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_groupEntries },
24180  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_FW_CBASS_IAM62A_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM62A_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_RAM_ID,
24181  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_FW_CBASS_IAM62A_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM62A_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_INJECT_TYPE,
24182  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_FW_CBASS_IAM62A_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM62A_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_ECC_TYPE,
24183  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_FW_CBASS_IAM62A_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM62A_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS,
24184  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_FW_CBASS_IAM62A_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM62A_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_groupEntries },
24185  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_DST_BUSECC_RAM_ID,
24186  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_DST_BUSECC_INJECT_TYPE,
24187  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_DST_BUSECC_ECC_TYPE,
24188  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS,
24189  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_DST_BUSECC_groupEntries },
24190  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_SRC_BUSECC_RAM_ID,
24191  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_SRC_BUSECC_INJECT_TYPE,
24192  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_SRC_BUSECC_ECC_TYPE,
24193  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS,
24194  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_SRC_BUSECC_groupEntries },
24195  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_DMSS_CFG_DST_BUSECC_RAM_ID,
24196  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_DMSS_CFG_DST_BUSECC_INJECT_TYPE,
24197  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_DMSS_CFG_DST_BUSECC_ECC_TYPE,
24198  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_DMSS_CFG_DST_BUSECC_MAX_NUM_CHECKERS,
24199  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_DMSS_CFG_DST_BUSECC_groupEntries },
24200  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_DMSS_CFG_SRC_BUSECC_RAM_ID,
24201  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_DMSS_CFG_SRC_BUSECC_INJECT_TYPE,
24202  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_DMSS_CFG_SRC_BUSECC_ECC_TYPE,
24203  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_DMSS_CFG_SRC_BUSECC_MAX_NUM_CHECKERS,
24204  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_DMSS_CFG_SRC_BUSECC_groupEntries },
24205  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_PKTDMA_CRED_DST_BUSECC_RAM_ID,
24206  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_PKTDMA_CRED_DST_BUSECC_INJECT_TYPE,
24207  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_PKTDMA_CRED_DST_BUSECC_ECC_TYPE,
24208  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_PKTDMA_CRED_DST_BUSECC_MAX_NUM_CHECKERS,
24209  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_PKTDMA_CRED_DST_BUSECC_groupEntries },
24210  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_PKTDMA_CRED_SRC_BUSECC_RAM_ID,
24211  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_PKTDMA_CRED_SRC_BUSECC_INJECT_TYPE,
24212  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_PKTDMA_CRED_SRC_BUSECC_ECC_TYPE,
24213  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_PKTDMA_CRED_SRC_BUSECC_MAX_NUM_CHECKERS,
24214  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_PKTDMA_CRED_SRC_BUSECC_groupEntries },
24215 };
24216 
24217 static SDL_ecc_aggrRegs * const SDL_ECC_aggrBaseAddressTable[SDL_ECC_BASE_ADDRESS_TOTAL_ENTRIES] =
24218 {
24219  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_PSCSS0_REGS_BASE)),
24220  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_PSRAMECC0_ECC_AGGR_BASE)),
24221  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_PSRAMECC1_ECC_AGGR_BASE)),
24222  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_MSRAM_64K0_ECC_AGGR_REGS_BASE)),
24223  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_WKUP_ECC_AGGR1_ECC_AGGR_BASE)),
24224  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_DMASS1_ECCAGGR_BASE)),
24225  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_MCU_MSRAM_256K1_ECC_AGGR_REGS_BASE)),
24226  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_WKUP_VTM0_ECCAGGR_CFG_BASE)),
24227  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_FSS0_OSPI0_ECC_AGGR_BASE)),
24228  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_MCU_R5FSS0_CORE0_ECC_AGGR_BASE)),
24229  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_CPSW0_ECC_BASE)),
24230  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_MCU_MSRAM_256K0_ECC_AGGR_REGS_BASE )),
24231  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_GICSS0_REGS_BASE)),
24232  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_ECC_AGGR1_ECC_AGGR_BASE)),
24233  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_DMASS0_ECCAGGR_BASE)),
24234  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_MMCSD1_ECC_AGGR_RXMEM_BASE)),
24235  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_MMCSD1_ECC_AGGR_TXMEM_BASE)),
24236  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_MMCSD2_ECC_AGGR_RXMEM_BASE)),
24237  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_MMCSD2_ECC_AGGR_TXMEM_BASE )),
24238  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_MMCSD0_ECC_AGGR_TXMEM_BASE)),
24239  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_MMCSD0_ECC_AGGR_RXMEM_BASE)),
24240  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_MCU_ECC_AGGR0_ECC_AGGR_BASE )),
24241  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_SMS0_ECC_AGGR_BASE )),
24242  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_SA3_SS0_ECCAGGR_CFG_BASE)),
24243  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_WKUP_ECC_AGGR2_ECC_AGGR_BASE )),
24244  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_WKUP_R5FSS0_CORE0_ECC_AGGR_BASE)),
24245  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_SMS0_HSM_ECC_BASE)),
24246  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_SMS0_TIFS_DMSS_HSM_ECC_BASE)),
24247  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_MCU_ECC_AGGR1_ECC_AGGR_BASE)),
24248  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_C7X256V0_ECC_AGGR_BASE)),
24249  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_USB1_ECC_AGGR_BASE )),
24250  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_USB0_ECC_AGGR_BASE)),
24251  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_WKUP_PSRAMECC_8K0_REGS_BASE)),
24252  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_PDMA0_BASE)),
24253  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_WKUP_ECC_AGGR0_ECC_AGGR_BASE)),
24254  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_PDMA1_BASE )),
24255  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_MCAN0_ECC_AGGR_BASE )),
24256  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_COMPUTE_CLUSTER0_CORE0_ECC_AGGR_BASE)),
24257  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_COMPUTE_CLUSTER0_CORE1_ECC_AGGR_BASE )),
24258  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_COMPUTE_CLUSTER0_CORE2_ECC_AGGR_BASE )),
24259  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_COMPUTE_CLUSTER0_CORE3_ECC_AGGR_BASE)),
24260  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_COMPUTE_CLUSTER0_SS_ECC_AGGR_BASE)),
24261  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_MCU_MCAN0_ECC_AGGR_BASE )),
24262  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_MCU_MCAN1_ECC_AGGR_BASE )),
24263  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_ECC_AGGR0_ECC_AGGR_BASE)),
24264 };
24265 
24266 extern SDL_ecc_aggrRegs * SDL_ECC_aggrTransBaseAddressTable[SDL_ECC_MEMTYPE_MAX];
24271 static const SDL_EccAggrEntry_t SDL_ECC_aggrTable[SDL_ECC_MEMTYPE_MAX] =
24272 {
24273 
24274  /* SDL_PSCSS0_SAM62A_MAIN_PSC_WRAP_ECC_AGGR (0) */
24275  {
24276  SDL_PSCSS0_SAM62A_MAIN_PSC_WRAP_ECC_AGGR_NUM_RAMS,
24277  SDL_PSCSS0_SAM62A_MAIN_PSC_WRAP_ECC_AGGR_RamIdTable,
24278  SDL_PSCSS0_SAM62A_MAIN_PSC_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES,
24279  SDL_PSCSS0_SAM62A_MAIN_PSC_WRAP_ECC_AGGR_MemEntries,
24280  SDL_ESM_INST_MAIN_ESM0,
24281  SDLR_ESM0_ESM_LVL_EVENT_PSC0_ECC_AGGR_0_FW_CH_BR_ECC_AGGR_CORR_LEVEL_0,
24282  SDLR_ESM0_ESM_LVL_EVENT_PSC0_ECC_AGGR_0_FW_CH_BR_ECC_AGGR_UNCORR_LEVEL_0
24283  },
24284  /* Index: SDL_PSRAMECC0_PSRAM256X32E_ECC_AGGR (1) */
24285  {
24286  SDL_PSRAMECC0_PSRAM256X32E_ECC_AGGR_NUM_RAMS,
24287  SDL_PSRAMECC0_PSRAM256X32E_ECC_AGGR_RamIdTable,
24288  SDL_PSRAMECC0_PSRAM256X32E_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES,
24289  SDL_PSRAMECC0_PSRAM256X32E_ECC_AGGR_MemEntries,
24290  SDL_ESM_INST_MAIN_ESM0,
24291  SDLR_ESM0_ESM_LVL_EVENT_PSRAMECC0_ECC_CORR_LEVEL_0,
24292  SDLR_ESM0_ESM_LVL_EVENT_PSRAMECC0_ECC_UNCORR_LEVEL_0
24293  },
24294  /* Index: SDL_PSRAMECC1_PSRAM256X32E_ECC_AGGR (2) */
24295  {
24296  SDL_PSRAMECC1_PSRAM256X32E_ECC_AGGR_NUM_RAMS,
24297  SDL_PSRAMECC1_PSRAM256X32E_ECC_AGGR_RamIdTable,
24298  SDL_PSRAMECC1_PSRAM256X32E_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES,
24299  SDL_PSRAMECC1_PSRAM256X32E_ECC_AGGR_MemEntries,
24300  SDL_ESM_INST_MAIN_ESM0,
24301  SDLR_ESM0_ESM_LVL_EVENT_PSRAMECC1_ECC_CORR_LEVEL_0,
24302  SDLR_ESM0_ESM_LVL_EVENT_PSRAMECC1_ECC_UNCORR_LEVEL_0
24303  },
24304  /* Index: SDL_MSRAM_64K0_MSRAM2KX256E_ECC_AGGR (3u) */
24305  {
24306  SDL_MSRAM_64K0_MSRAM2KX256E_ECC_AGGR_NUM_RAMS,
24307  SDL_MSRAM_64K0_MSRAM2KX256E_ECC_AGGR_RamIdTable,
24308  SDL_MSRAM_64K0_MSRAM2KX256E_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES,
24309  SDL_MSRAM_64K0_MSRAM2KX256E_ECC_AGGR_MemEntries,
24310  SDL_ESM_INST_MAIN_ESM0,
24311  SDLR_ESM0_ESM_LVL_EVENT_MSRAM_64K0_ECC_CORR_LEVEL_0,
24312  SDLR_ESM0_ESM_LVL_EVENT_MSRAM_64K0_ECC_UNCORR_LEVEL_0
24313  },
24314  /* Index: SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR (4u) */
24315  {
24316  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_NUM_RAMS,
24317  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_RamIdTable,
24318  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES,
24319  NULL,
24320  SDL_ESM_INST_MAIN_ESM0,
24321  SDLR_ESM0_ESM_LVL_EVENT_WKUP_ECC_AGGR1_CORR_LEVEL_0,
24322  SDLR_ESM0_ESM_LVL_EVENT_WKUP_ECC_AGGR1_UNCORR_LEVEL_0
24323  },
24324  /* Index: SDL_DMASS1_DMSS_CSI_AM62A_ECCAGGR (5u) */
24325  {
24326  SDL_DMASS1_DMSS_CSI_AM62A_ECCAGGR_NUM_RAMS,
24327  SDL_DMASS1_DMSS_CSI_AM62A_ECCAGGR_RamIdTable,
24328  SDL_DMASS1_DMSS_CSI_AM62A_ECCAGGR_RAM_IDS_TOTAL_ENTRIES,
24329  SDL_DMASS1_DMSS_CSI_AM62A_ECCAGGR_MemEntries,
24330  SDL_ESM_INST_MAIN_ESM0,
24331  SDLR_ESM0_ESM_LVL_EVENT_DMASS1_ECC_AGGR_0_ECC_CORRECTED_ERR_LEVEL_0,
24332  SDLR_ESM0_ESM_LVL_EVENT_DMASS1_ECC_AGGR_0_ECC_UNCORRECTED_ERR_LEVEL_0
24333  },
24334  /* Index: SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR (6u) */
24335  {
24336  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_NUM_RAMS,
24337  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_RamIdTable,
24338  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES,
24339  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MemEntries,
24340  SDL_ESM_INST_WKUP_ESM0,
24341  SDLR_WKUP_ESM0_ESM_LVL_EVENT_MCU_MSRAM_256K1_ECC_CORR_LEVEL_0,
24342  SDLR_WKUP_ESM0_ESM_LVL_EVENT_MCU_MSRAM_256K1_ECC_UNCORR_LEVEL_0
24343  },
24344  /*Index: SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR (7u) */
24345  {
24346  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_NUM_RAMS,
24347  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_RamIdTable,
24348  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_RAM_IDS_TOTAL_ENTRIES,
24349  NULL,
24350  SDL_ESM_INST_MAIN_ESM0,
24351  SDLR_ESM0_ESM_LVL_EVENT_WKUP_VTM0_CORR_LEVEL_0,
24352  SDLR_ESM0_ESM_LVL_EVENT_WKUP_VTM0_UNCORR_LEVEL_0
24353  },
24354  /* Index: SDL_FSS0_FSS_UL_OSPI0_OSPI_WRAP_ECC_AGGR (8) */
24355  {
24356  SDL_FSS0_FSS_UL_OSPI0_OSPI_WRAP_ECC_AGGR_NUM_RAMS,
24357  SDL_FSS0_FSS_UL_OSPI0_OSPI_WRAP_ECC_AGGR_RamIdTable,
24358  SDL_FSS0_FSS_UL_OSPI0_OSPI_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES,
24359  SDL_FSS0_FSS_UL_OSPI0_OSPI_WRAP_ECC_AGGR_MemEntries,
24360  SDL_ESM_INST_MAIN_ESM0,
24361  SDLR_ESM0_ESM_LVL_EVENT_FSS0_OSPI_0_OSPI_ECC_CORR_LVL_INTR_0,
24362  SDLR_ESM0_ESM_LVL_EVENT_FSS0_OSPI_0_OSPI_ECC_UNCORR_LVL_INTR_0
24363  },
24364  /* Index: SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR (9u) */
24365  {
24366  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_NUM_RAMS,
24367  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_RamIdTable,
24368  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES,
24369  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_MemEntries,
24370  SDL_ESM_INST_WKUP_ESM0,
24371  SDLR_WKUP_ESM0_ESM_LVL_EVENT_MCU_R5FSS0_CPU0_ECC_AGGR_0_CPU0_ECC_CORRECTED_LEVEL_0,
24372  SDLR_WKUP_ESM0_ESM_LVL_EVENT_MCU_R5FSS0_CPU0_ECC_AGGR_0_CPU0_ECC_UNCORRECTED_LEVEL_0
24373  },
24374  /* Index: SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR (10u) */
24375  {
24376  SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR_NUM_RAMS,
24377  SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR_RamIdTable,
24378  SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES,
24379  SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR_MemEntries,
24380  SDL_ESM_INST_MAIN_ESM0,
24381  SDLR_ESM0_ESM_LVL_EVENT_CPSW0_ECC_SEC_PEND_0,
24382  SDLR_ESM0_ESM_LVL_EVENT_CPSW0_ECC_DED_PEND_0
24383  },
24384  /* Index: SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR (11u) */
24385  {
24386  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_NUM_RAMS,
24387  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_RamIdTable,
24388  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES,
24389  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MemEntries,
24390  SDL_ESM_INST_WKUP_ESM0,
24391  SDLR_WKUP_ESM0_ESM_LVL_EVENT_MCU_MSRAM_256K0_ECC_CORR_LEVEL_0,
24392  SDLR_WKUP_ESM0_ESM_LVL_EVENT_MCU_MSRAM_256K0_ECC_UNCORR_LEVEL_0
24393  },
24394  /* Index: SDL_GICSS0_GIC500SS_1_4_ECC_AGGR (12u) */
24395  {
24396  SDL_GICSS0_GIC500SS_1_4_ECC_AGGR_NUM_RAMS,
24397  SDL_GICSS0_GIC500SS_1_4_ECC_AGGR_RamIdTable,
24398  SDL_GICSS0_GIC500SS_1_4_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES,
24399  SDL_GICSS0_GIC500SS_1_4_ECC_AGGR_MemEntries,
24400  SDL_ESM_INST_MAIN_ESM0,
24401  SDLR_ESM0_ESM_LVL_EVENT_GICSS0_ECC_AGGR_CORR_LEVEL_0,
24402  SDLR_ESM0_ESM_LVL_EVENT_GICSS0_ECC_AGGR_UNCORR_LEVEL_0
24403  },
24404  /* Index: SDL_ECC_AGGR1_SAM62A_SEC_MCU_ECC_AGGR (13u) */
24405  {
24406  SDL_ECC_AGGR1_SAM62A_SEC_MCU_ECC_AGGR_NUM_RAMS,
24407  SDL_ECC_AGGR1_SAM62A_SEC_MCU_ECC_AGGR_RamIdTable,
24408  SDL_ECC_AGGR1_SAM62A_SEC_MCU_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES,
24409  NULL,
24410  SDL_ESM_INST_MAIN_ESM0,
24411  SDLR_ESM0_ESM_LVL_EVENT_ECC_AGGR1_CORR_LEVEL_0,
24412  SDLR_ESM0_ESM_LVL_EVENT_ECC_AGGR1_UNCORR_LEVEL_0
24413  },
24414  /* Index: SDL_DMASS0_DMSS_AM62A_ECCAGGR (14u) */
24415  {
24416  SDL_DMASS0_DMSS_AM62A_ECCAGGR_NUM_RAMS,
24417  SDL_DMASS0_DMSS_AM62A_ECCAGGR_RamIdTable,
24418  SDL_DMASS0_DMSS_AM62A_ECCAGGR_RAM_IDS_TOTAL_ENTRIES,
24419  SDL_DMASS0_DMSS_AM62A_ECCAGGR_MemEntries,
24420  SDL_ESM_INST_MAIN_ESM0,
24421  SDLR_ESM0_ESM_LVL_EVENT_DMASS0_ECC_AGGR_0_ECC_CORRECTED_ERR_LEVEL_0,
24422  SDLR_ESM0_ESM_LVL_EVENT_DMASS0_ECC_AGGR_0_ECC_UNCORRECTED_ERR_LEVEL_0
24423  },
24424  /* Index: SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_RXMEM (15u) */
24425  {
24426  SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_RXMEM_NUM_RAMS,
24427  SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_RXMEM_RamIdTable,
24428  SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_RXMEM_RAM_IDS_TOTAL_ENTRIES,
24429  SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_RXMEM_MemEntries,
24430  SDL_ESM_INST_MAIN_ESM0,
24431  SDLR_ESM0_ESM_LVL_EVENT_MMCSD1_EMMCSDSS_RXMEM_CORR_ERR_LVL_0,
24432  SDLR_ESM0_ESM_LVL_EVENT_MMCSD1_EMMCSDSS_RXMEM_UNCORR_ERR_LVL_0
24433  },
24434  /* Index: SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_TXMEM (16u) */
24435  {
24436  SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_TXMEM_NUM_RAMS,
24437  SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_TXMEM_RamIdTable,
24438  SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_TXMEM_RAM_IDS_TOTAL_ENTRIES,
24439  SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_TXMEM_MemEntries,
24440  SDL_ESM_INST_MAIN_ESM0,
24441  SDLR_ESM0_ESM_LVL_EVENT_MMCSD1_EMMCSDSS_TXMEM_CORR_ERR_LVL_0,
24442  SDLR_ESM0_ESM_LVL_EVENT_MMCSD1_EMMCSDSS_TXMEM_UNCORR_ERR_LVL_0
24443  },
24444 
24445  /* Index: SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_RXMEM (17u) */
24446  {
24447  SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_RXMEM_NUM_RAMS,
24448  SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_RXMEM_RamIdTable,
24449  SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_RXMEM_RAM_IDS_TOTAL_ENTRIES,
24450  SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_RXMEM_MemEntries,
24451  SDL_ESM_INST_MAIN_ESM0,
24452  SDLR_ESM0_ESM_LVL_EVENT_MMCSD2_EMMCSDSS_RXMEM_CORR_ERR_LVL_0,
24453  SDLR_ESM0_ESM_LVL_EVENT_MMCSD2_EMMCSDSS_RXMEM_UNCORR_ERR_LVL_0
24454  },
24455 
24456  /* Index: SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_TXMEM (18u) */
24457  {
24458  SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_TXMEM_NUM_RAMS,
24459  SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_TXMEM_RamIdTable,
24460  SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_TXMEM_RAM_IDS_TOTAL_ENTRIES,
24461  SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_TXMEM_MemEntries,
24462  SDL_ESM_INST_MAIN_ESM0,
24463  SDLR_ESM0_ESM_LVL_EVENT_MMCSD2_EMMCSDSS_TXMEM_CORR_ERR_LVL_0,
24464  SDLR_ESM0_ESM_LVL_EVENT_MMCSD2_EMMCSDSS_TXMEM_UNCORR_ERR_LVL_0
24465  },
24466 
24467  /* Index: SDL_MMCSD0_EMMCSD8SS_ECC_AGGR_TXMEM (19u) */
24468  {
24469  SDL_MMCSD0_EMMCSD8SS_ECC_AGGR_TXMEM_NUM_RAMS,
24470  SDL_MMCSD0_EMMCSD8SS_ECC_AGGR_TXMEM_RamIdTable,
24471  SDL_MMCSD0_EMMCSD8SS_ECC_AGGR_TXMEM_RAM_IDS_TOTAL_ENTRIES,
24472  SDL_MMCSD0_EMMCSD8SS_ECC_AGGR_TXMEM_MemEntries,
24473  SDL_ESM_INST_MAIN_ESM0,
24474  SDLR_ESM0_ESM_LVL_EVENT_MMCSD0_EMMCSDSS_TXMEM_CORR_ERR_LVL_0,
24475  SDLR_ESM0_ESM_LVL_EVENT_MMCSD0_EMMCSDSS_TXMEM_UNCORR_ERR_LVL_0
24476  },
24477 
24478  /* Index: SDL_MMCSD0_EMMCSD8SS_ECC_AGGR_RXMEM (20u) */
24479  {
24480  SDL_MMCSD0_EMMCSD8SS_ECC_AGGR_RXMEM_NUM_RAMS,
24481  SDL_MMCSD0_EMMCSD8SS_ECC_AGGR_RXMEM_RamIdTable,
24482  SDL_MMCSD0_EMMCSD8SS_ECC_AGGR_RXMEM_RAM_IDS_TOTAL_ENTRIES,
24483  SDL_MMCSD0_EMMCSD8SS_ECC_AGGR_RXMEM_MemEntries,
24484  SDL_ESM_INST_MAIN_ESM0,
24485  SDLR_ESM0_ESM_LVL_EVENT_MMCSD0_EMMCSDSS_RXMEM_CORR_ERR_LVL_0,
24486  SDLR_ESM0_ESM_LVL_EVENT_MMCSD0_EMMCSDSS_RXMEM_UNCORR_ERR_LVL_0
24487  },
24488 
24489  /* Index: SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR (21u) */
24490  {
24491  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_NUM_RAMS,
24492  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_RamIdTable,
24493  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES,
24494  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_MemEntries,
24495  SDL_ESM_INST_WKUP_ESM0,
24496  SDLR_WKUP_ESM0_ESM_LVL_EVENT_MCU_ECC_AGGR0_CORR_LEVEL_0,
24497  SDLR_WKUP_ESM0_ESM_LVL_EVENT_MCU_ECC_AGGR0_UNCORR_LEVEL_0
24498  },
24499 
24500  /* Index: SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR (22u) */
24501  {
24502  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_NUM_RAMS,
24503  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_RamIdTable,
24504  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_RAM_IDS_TOTAL_ENTRIES,
24505  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_MemEntries,
24506  SDL_ESM_INST_MAIN_ESM0,
24507  SDLR_ESM0_ESM_LVL_EVENT_SA3_SS0_DMSS_ECCAGGR_0_DMSS_ECC_DED_PEND_0,
24508  SDLR_ESM0_ESM_LVL_EVENT_SA3_SS0_DMSS_ECCAGGR_0_DMSS_ECC_SEC_PEND_0
24509  },
24510  /* Index: SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR (23u) */
24511  {
24512  SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_NUM_RAMS,
24513  SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_RamIdTable,
24514  SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES,
24515  SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_MemEntries,
24516  SDL_ESM_INST_MAIN_ESM0,
24517  SDLR_ESM0_ESM_LVL_EVENT_SA3_SS0_SA_UL_0_SA_UL_ECC_CORR_LEVEL_0,
24518  SDLR_ESM0_ESM_LVL_EVENT_SA3_SS0_SA_UL_0_SA_UL_ECC_UNCORR_LEVEL_0
24519  },
24520  /* Index: SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR (24u) */
24521  {
24522  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_NUM_RAMS,
24523  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_RamIdTable,
24524  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES,
24525  NULL,
24526  SDL_ESM_INST_WKUP_ESM0,
24527  SDLR_WKUP_ESM0_ESM_LVL_EVENT_WKUP_ECC_AGGR2_CORR_LEVEL_0,
24528  SDLR_WKUP_ESM0_ESM_LVL_EVENT_WKUP_ECC_AGGR2_UNCORR_LEVEL_0
24529  },
24530  /* Index: SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR (25u) */
24531  {
24532  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_NUM_RAMS,
24533  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_RamIdTable,
24534  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES,
24535  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_MemEntries,
24536  SDL_ESM_INST_MAIN_ESM0,
24537  SDLR_ESM0_ESM_LVL_EVENT_WKUP_R5FSS0_CORE0_ECC_CORRECTED_LEVEL_0,
24538  SDLR_ESM0_ESM_LVL_EVENT_WKUP_R5FSS0_CORE0_ECC_UNCORRECTED_LEVEL_0
24539  },
24540  /* Index: SDL_SMS0_SMS_HSM_ECC (26u) */
24541  {
24542  SDL_SMS0_SMS_HSM_ECC_NUM_RAMS,
24543  SDL_SMS0_SMS_HSM_ECC_RamIdTable,
24544  SDL_SMS0_SMS_HSM_ECC_RAM_IDS_TOTAL_ENTRIES,
24545  SDL_SMS0_SMS_HSM_ECC_MemEntries,
24546  SDL_ESM_INST_MAIN_ESM0,
24547  SDLR_ESM0_ESM_LVL_EVENT_SMS0_HSM_ECC_AGGR_0_ECC_CORRECTED_LEVEL_0,
24548  SDLR_ESM0_ESM_LVL_EVENT_SMS0_HSM_ECC_AGGR_0_ECC_UNCORRECTED_LEVEL_0
24549  },
24550  /* Index: SDL_SMS0_SMS_TIFS_ECC (27u) */
24551  {
24552  SDL_SMS0_SMS_TIFS_ECC_NUM_RAMS,
24553  SDL_SMS0_SMS_TIFS_ECC_RamIdTable,
24554  SDL_SMS0_SMS_TIFS_ECC_RAM_IDS_TOTAL_ENTRIES,
24555  SDL_SMS0_SMS_TIFS_ECC_MemEntries,
24556  SDL_ESM_INST_MAIN_ESM0,
24557  SDLR_ESM0_ESM_LVL_EVENT_SMS0_TIFS_ECC_AGGR_0_ECC_CORRECTED_LEVEL_0,
24558  SDLR_ESM0_ESM_LVL_EVENT_SMS0_TIFS_ECC_AGGR_0_ECC_UNCORRECTED_LEVEL_0
24559  },
24560 
24561  /* SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR (28u) */
24562  {
24563  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_NUM_RAMS,
24564  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_RamIdTable,
24565  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES,
24566  NULL,
24567  SDL_ESM_INST_WKUP_ESM0,
24568  SDLR_WKUP_ESM0_ESM_LVL_EVENT_MCU_ECC_AGGR1_CORR_LEVEL_0,
24569  SDLR_WKUP_ESM0_ESM_LVL_EVENT_MCU_ECC_AGGR1_UNCORR_LEVEL_0
24570  },
24571  /* SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR (29u) */
24572  {
24573  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_NUM_RAMS,
24574  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_RamIdTable,
24575  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES,
24576  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_MemEntries,
24577  SDL_ESM_INST_MAIN_ESM0,
24578  SDLR_ESM0_ESM_LVL_EVENT_C7X256V0_CLEC_ESM_EVENTS_OUT_LEVEL_1,
24579  SDLR_ESM0_ESM_LVL_EVENT_C7X256V0_CLEC_ESM_EVENTS_OUT_LEVEL_0
24580  },
24581  /* SDL_USB1_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR (30u) */
24582  {
24583  SDL_USB1_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_NUM_RAMS,
24584  SDL_USB1_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_RamIdTable,
24585  SDL_USB1_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES,
24586  SDL_USB1_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_MemEntries,
24587  SDL_ESM_INST_MAIN_ESM0,
24588  SDLR_ESM0_ESM_LVL_EVENT_USB1_A_ECC_AGGR_CORRECTED_ERR_LEVEL_0,
24589  SDLR_ESM0_ESM_LVL_EVENT_USB1_A_ECC_AGGR_UNCORRECTED_ERR_LEVEL_0
24590  },
24591  /* SDL_USB0_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR (31u) */
24592  {
24593  SDL_USB0_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_NUM_RAMS,
24594  SDL_USB0_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_RamIdTable,
24595  SDL_USB0_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES,
24596  SDL_USB0_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_MemEntries,
24597  SDL_ESM_INST_MAIN_ESM0,
24598  SDLR_ESM0_ESM_LVL_EVENT_USB0_A_ECC_AGGR_CORRECTED_ERR_LEVEL_0,
24599  SDLR_ESM0_ESM_LVL_EVENT_USB0_A_ECC_AGGR_UNCORRECTED_ERR_LEVEL_0
24600  },
24601  /* SDL_WKUP_PSRAMECC_8K0_PSRAM8KX32E_ECC_AGGR (32u) */
24602  {
24603  SDL_WKUP_PSRAMECC_8K0_PSRAM8KX32E_ECC_AGGR_NUM_RAMS,
24604  SDL_WKUP_PSRAMECC_8K0_PSRAM8KX32E_ECC_AGGR_RamIdTable,
24605  SDL_WKUP_PSRAMECC_8K0_PSRAM8KX32E_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES,
24606  SDL_WKUP_PSRAMECC_8K0_PSRAM8KX32E_ECC_AGGR_MemEntries,
24607  SDL_ESM_INST_MAIN_ESM0,
24608  SDLR_ESM0_ESM_LVL_EVENT_WKUP_PSRAMECC_8K0_ECC_CORR_LEVEL_0,
24609  SDLR_ESM0_ESM_LVL_EVENT_WKUP_PSRAMECC_8K0_ECC_UNCORR_LEVEL_0
24610  },
24611  /* SDL_PDMA0_SAM62_PDMA_SPI_ECCAGGR (33u) */
24612  {
24613  SDL_PDMA0_SAM62_PDMA_SPI_ECCAGGR_NUM_RAMS,
24614  SDL_PDMA0_SAM62_PDMA_SPI_ECCAGGR_RamIdTable,
24615  SDL_PDMA0_SAM62_PDMA_SPI_ECCAGGR_RAM_IDS_TOTAL_ENTRIES,
24616  SDL_PDMA0_SAM62_PDMA_SPI_ECCAGGR_MemEntries,
24617  SDL_ESM_INST_MAIN_ESM0,
24618  SDLR_ESM0_ESM_LVL_EVENT_PDMA0_ECC_SEC_PEND_0,
24619  SDLR_ESM0_ESM_LVL_EVENT_PDMA0_ECC_DED_PEND_0
24620  },
24621  /* SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR (34u) */
24622  {
24623  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_NUM_RAMS,
24624  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_RamIdTable,
24625  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES,
24626  NULL,
24627  SDL_ESM_INST_MAIN_ESM0,
24628  SDLR_ESM0_ESM_LVL_EVENT_WKUP_ECC_AGGR0_CORR_LEVEL_0,
24629  SDLR_ESM0_ESM_LVL_EVENT_WKUP_ECC_AGGR0_UNCORR_LEVEL_0
24630  },
24631  /* SDL_PDMA1_SAM62_PDMA_UART_ECCAGGR (35u) */
24632  {
24633  SDL_PDMA1_SAM62_PDMA_UART_ECCAGGR_NUM_RAMS,
24634  SDL_PDMA1_SAM62_PDMA_UART_ECCAGGR_RamIdTable,
24635  SDL_PDMA1_SAM62_PDMA_UART_ECCAGGR_RAM_IDS_TOTAL_ENTRIES,
24636  SDL_PDMA1_SAM62_PDMA_UART_ECCAGGR_MemEntries,
24637  SDL_ESM_INST_MAIN_ESM0,
24638  SDLR_ESM0_ESM_LVL_EVENT_PDMA1_ECC_SEC_PEND_0,
24639  SDLR_ESM0_ESM_LVL_EVENT_PDMA1_ECC_DED_PEND_0
24640  },
24641  /* SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR (36u) */
24642  {
24643  SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_NUM_RAMS,
24644  SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_RamIdTable,
24645  SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES,
24646  SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_MemEntries,
24647  SDL_ESM_INST_MAIN_ESM0,
24648  SDLR_ESM0_ESM_LVL_EVENT_MCAN0_MCANSS_ECC_CORR_LVL_INT_0,
24649  SDLR_ESM0_ESM_LVL_EVENT_MCAN0_MCANSS_ECC_UNCORR_LVL_INT_0
24650  },
24651  /* SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0 (37u) */
24652  {
24653  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_NUM_RAMS,
24654  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_RamIdTable,
24655  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_RAM_IDS_TOTAL_ENTRIES,
24656  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_MemEntries,
24657  SDL_ESM_INST_MAIN_ESM0,
24658  SDLR_ESM0_ESM_LVL_EVENT_A53SS0_ECC_ECCAGGR0_CORRECTED_ERR_LEVEL_0,
24659  SDLR_ESM0_ESM_LVL_EVENT_A53SS0_ECC_ECCAGGR0_UNCORRECTED_ERR_LEVEL_0
24660  },
24661  /* SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1 (38u) */
24662  {
24663  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_NUM_RAMS,
24664  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_RamIdTable,
24665  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_RAM_IDS_TOTAL_ENTRIES,
24666  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_MemEntries,
24667  SDL_ESM_INST_MAIN_ESM0,
24668  SDLR_ESM0_ESM_LVL_EVENT_A53SS0_ECC_ECCAGGR1_CORRECTED_ERR_LEVEL_0,
24669  SDLR_ESM0_ESM_LVL_EVENT_A53SS0_ECC_ECCAGGR1_UNCORRECTED_ERR_LEVEL_0
24670  },
24671  /* SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2 (39u) */
24672  {
24673  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_NUM_RAMS,
24674  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_RamIdTable,
24675  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_RAM_IDS_TOTAL_ENTRIES,
24676  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_MemEntries,
24677  SDL_ESM_INST_MAIN_ESM0,
24678  SDLR_ESM0_ESM_LVL_EVENT_A53SS0_ECC_ECCAGGR2_CORRECTED_ERR_LEVEL_0,
24679  SDLR_ESM0_ESM_LVL_EVENT_A53SS0_ECC_ECCAGGR2_UNCORRECTED_ERR_LEVEL_0
24680  },
24681  /* SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3 (40u) */
24682  {
24683  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_NUM_RAMS,
24684  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_RamIdTable,
24685  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_RAM_IDS_TOTAL_ENTRIES,
24686  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_MemEntries,
24687  SDL_ESM_INST_MAIN_ESM0,
24688  SDLR_ESM0_ESM_LVL_EVENT_A53SS0_ECC_ECCAGGR3_CORRECTED_ERR_LEVEL_0,
24689  SDLR_ESM0_ESM_LVL_EVENT_A53SS0_ECC_ECCAGGR3_CORRECTED_ERR_LEVEL_0
24690  },
24691  /* SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC (41u) */
24692  {
24693  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_NUM_RAMS,
24694  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_RamIdTable,
24695  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_RAM_IDS_TOTAL_ENTRIES,
24696  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_MemEntries,
24697  SDL_ESM_INST_MAIN_ESM0,
24698  SDLR_ESM0_ESM_LVL_EVENT_A53SS0_ECC_ECCAGGR_COREPAC_CORRECTED_ERR_LEVEL_0,
24699  SDLR_ESM0_ESM_LVL_EVENT_A53SS0_ECC_ECCAGGR_COREPAC_UNCORRECTED_ERR_LEVEL_0
24700  },
24701  /* SDL_MCU_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR (42u) */
24702  {
24703  SDL_MCU_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_NUM_RAMS,
24704  SDL_MCU_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_RamIdTable,
24705  SDL_MCU_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES,
24706  SDL_MCU_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_MemEntries,
24707  SDL_ESM_INST_WKUP_ESM0,
24708  SDLR_WKUP_ESM0_ESM_LVL_EVENT_MCU_MCAN0_MCANSS_ECC_CORR_LVL_INT_0,
24709  SDLR_WKUP_ESM0_ESM_LVL_EVENT_MCU_MCAN0_MCANSS_ECC_UNCORR_LVL_INT_0
24710  },
24711  /* SDL_MCU_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR (43u) */
24712  {
24713  SDL_MCU_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_NUM_RAMS,
24714  SDL_MCU_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_RamIdTable,
24715  SDL_MCU_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES,
24716  SDL_MCU_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_MemEntries,
24717  SDL_ESM_INST_WKUP_ESM0,
24718  SDLR_WKUP_ESM0_ESM_LVL_EVENT_MCU_MCAN1_MCANSS_ECC_CORR_LVL_INT_0,
24719  SDLR_WKUP_ESM0_ESM_LVL_EVENT_MCU_MCAN1_MCANSS_ECC_UNCORR_LVL_INT_0
24720  },
24721  /* SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR (44u) */
24722  {
24723  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_NUM_RAMS,
24724  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_RamIdTable,
24725  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES,
24726  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_MemEntries,
24727  SDL_ESM_INST_MAIN_ESM0,
24728  SDLR_ESM0_ESM_LVL_EVENT_ECC_AGGR0_CORR_LEVEL_0,
24729  SDLR_ESM0_ESM_LVL_EVENT_ECC_AGGR0_UNCORR_LEVEL_0
24730  },
24731 };
24732 
24733  #endif /* INCLUDE_SDL_ECC_SOC_H_ */
SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
#define SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:84
SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IPULSAR_ULS_MCU_0_CPU0_CFG_SLV_P2P_BRIDGE_IPULSAR_ULS_MCU_0_CPU0_CFG_SLV_BRIDGE_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IPULSAR_ULS_MCU_0_CPU0_CFG_SLV_P2P_BRIDGE_IPULSAR_ULS_MCU_0_CPU0_CFG_SLV_BRIDGE_BUSECC_groupEntries[SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IPULSAR_ULS_MCU_0_CPU0_CFG_SLV_P2P_BRIDGE_IPULSAR_ULS_MCU_0_CPU0_CFG_SLV_BRIDGE_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:2932
SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISAM62A_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM62A_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_DST_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISAM62A_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM62A_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_DST_BUSECC_groupEntries[SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISAM62A_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM62A_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:19995
SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
#define SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:83
SDL_PDMA0_SAM62_PDMA_SPI_ECCAGGR_MemEntries
static const SDL_MemConfig_t SDL_PDMA0_SAM62_PDMA_SPI_ECCAGGR_MemEntries[SDL_PDMA0_SAM62_PDMA_SPI_ECCAGGR_RAM_IDS_TOTAL_ENTRIES]
Definition: sdl_ecc_soc.h:19391
SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_DEFAULT_MMRS_SMS_TIFS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_DEFAULT_MMRS_SMS_TIFS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_groupEntries[SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_DEFAULT_MMRS_SMS_TIFS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:17813
SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_MemEntries
static const SDL_MemConfig_t SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_MemEntries[SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
Definition: sdl_ecc_soc.h:1205
SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR_MemEntries
static const SDL_MemConfig_t SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR_MemEntries[SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
Definition: sdl_ecc_soc.h:1700
SDL_MMCSD0_EMMCSD8SS_ECC_AGGR_RXMEM_RAM_IDS_TOTAL_ENTRIES
#define SDL_MMCSD0_EMMCSD8SS_ECC_AGGR_RXMEM_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:79
SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
#define SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:93
SDL_WKUP_PSRAMECC_8K0_PSRAM8KX32E_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
#define SDL_WKUP_PSRAMECC_8K0_PSRAM8KX32E_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:91
SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
#define SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:87
SDL_ESM_INST_MAIN_ESM0
@ SDL_ESM_INST_MAIN_ESM0
Definition: sdl_esm_soc.h:63
SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IAM62A_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM62A_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IAM62A_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM62A_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_groupEntries[SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IAM62A_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM62A_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:2819
SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_RamIdTable
static const SDL_RAMIdEntry_t SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_RamIdTable[SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_NUM_RAMS]
Definition: sdl_ecc_soc.h:23841
SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_RamIdTable
static const SDL_RAMIdEntry_t SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_RamIdTable[SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_NUM_RAMS]
Definition: sdl_ecc_soc.h:22796
SDL_SMS0_SMS_HSM_ECC_RamIdTable
static const SDL_RAMIdEntry_t SDL_SMS0_SMS_HSM_ECC_RamIdTable[SDL_SMS0_SMS_HSM_ECC_NUM_RAMS]
Definition: sdl_ecc_soc.h:22949
SDL_DMASS1_DMSS_CSI_AM62A_ECCAGGR_MemEntries
static const SDL_MemConfig_t SDL_DMASS1_DMSS_CSI_AM62A_ECCAGGR_MemEntries[SDL_DMASS1_DMSS_CSI_AM62A_ECCAGGR_RAM_IDS_TOTAL_ENTRIES]
Definition: sdl_ecc_soc.h:492
SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_RXMEM_RAM_IDS_TOTAL_ENTRIES
#define SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_RXMEM_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:76
SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_groupEntries[SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:19412
SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_groupEntries[SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:7074
SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_groupEntries[SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:15575
SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_CFG_SLV_SRC_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_CFG_SLV_SRC_BUSECC_groupEntries[SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_CFG_SLV_SRC_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:2543
SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_INTAGGR_EVT_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_INTAGGR_EVT_EDC_CTRL_0_groupEntries[SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_INTAGGR_EVT_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:9582
SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_groupEntries[SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:6616
SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_TIFS_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_TIFS_VBUSP_S_BRIDGE_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_TIFS_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_TIFS_VBUSP_S_BRIDGE_BUSECC_groupEntries[SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_TIFS_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_TIFS_VBUSP_S_BRIDGE_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:21116
SDL_ECC_aggrTable
static const SDL_EccAggrEntry_t SDL_ECC_aggrTable[SDL_ECC_MEMTYPE_MAX]
Definition: sdl_ecc_soc.h:24271
SDL_ECC_AGGR1_SAM62A_SEC_MCU_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
#define SDL_ECC_AGGR1_SAM62A_SEC_MCU_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:72
SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_TXMEM_RamIdTable
static const SDL_RAMIdEntry_t SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_TXMEM_RamIdTable[SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_TXMEM_NUM_RAMS]
Definition: sdl_ecc_soc.h:22104
SDL_PSCSS0_SAM62A_MAIN_PSC_WRAP_ECC_AGGR_RamIdTable
static const SDL_RAMIdEntry_t SDL_PSCSS0_SAM62A_MAIN_PSC_WRAP_ECC_AGGR_RamIdTable[SDL_PSCSS0_SAM62A_MAIN_PSC_WRAP_ECC_AGGR_NUM_RAMS]
Definition: sdl_ecc_soc.h:21456
SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_groupEntries[SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:18928
SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_groupEntries
static const SDL_GrpChkConfig_t SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_groupEntries[SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:17062
SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_groupEntries[SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:18360
SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_SRC_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_SRC_BUSECC_groupEntries[SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:6933
SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_groupEntries[SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:15074
SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_RamIdTable
static const SDL_RAMIdEntry_t SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_RamIdTable[SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_NUM_RAMS]
Definition: sdl_ecc_soc.h:21589
SDL_PDMA1_SAM62_PDMA_UART_ECCAGGR_MemEntries
static const SDL_MemConfig_t SDL_PDMA1_SAM62_PDMA_UART_ECCAGGR_MemEntries[SDL_PDMA1_SAM62_PDMA_UART_ECCAGGR_RAM_IDS_TOTAL_ENTRIES]
Definition: sdl_ecc_soc.h:20414
SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_RamIdTable
static const SDL_RAMIdEntry_t SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_RamIdTable[SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_NUM_RAMS]
Definition: sdl_ecc_soc.h:21508
SDL_USB1_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
#define SDL_USB1_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:89
SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_groupEntries[SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:10151
SDL_DMASS0_DMSS_AM62A_ECCAGGR_MemEntries
static const SDL_MemConfig_t SDL_DMASS0_DMSS_AM62A_ECCAGGR_MemEntries[SDL_DMASS0_DMSS_AM62A_ECCAGGR_RAM_IDS_TOTAL_ENTRIES]
Definition: sdl_ecc_soc.h:1937
SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_CBASS_DEFAULT_ERR_AM62A_WKUP_SAFE_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_CBASS_DEFAULT_ERR_AM62A_WKUP_SAFE_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_groupEntries[SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_CBASS_DEFAULT_ERR_AM62A_WKUP_SAFE_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:14200
SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_RamIdTable
static const SDL_RAMIdEntry_t SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_RamIdTable[SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_NUM_RAMS]
Definition: sdl_ecc_soc.h:23303
SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_MemEntries
static const SDL_MemConfig_t SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_MemEntries[SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
Definition: sdl_ecc_soc.h:20936
SDL_FSS0_FSS_UL_OSPI0_OSPI_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
#define SDL_FSS0_FSS_UL_OSPI0_OSPI_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:67
sdl_esm_soc.h
SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_RamIdTable
static const SDL_RAMIdEntry_t SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_RamIdTable[SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_NUM_RAMS]
Definition: sdl_ecc_soc.h:23984
SDL_PDMA1_SAM62_PDMA_UART_ECCAGGR_RamIdTable
static const SDL_RAMIdEntry_t SDL_PDMA1_SAM62_PDMA_UART_ECCAGGR_RamIdTable[SDL_PDMA1_SAM62_PDMA_UART_ECCAGGR_NUM_RAMS]
Definition: sdl_ecc_soc.h:23366
SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_DMSS_CFG_SRC_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_DMSS_CFG_SRC_BUSECC_groupEntries[SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_DMSS_CFG_SRC_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:21363
SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ISAM62A_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM62A_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_BRIDGE_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ISAM62A_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM62A_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_BRIDGE_BUSECC_groupEntries[SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ISAM62A_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM62A_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_BRIDGE_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:13076
SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_ECC_AGGR_EDC_CTRL_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_ECC_AGGR_EDC_CTRL_groupEntries[SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_ECC_AGGR_EDC_CTRL_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:1883
SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_RXMEM_RamIdTable
static const SDL_RAMIdEntry_t SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_RXMEM_RamIdTable[SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_RXMEM_NUM_RAMS]
Definition: sdl_ecc_soc.h:22091
SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_RAM_IDS_TOTAL_ENTRIES
#define SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:99
SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_P2P_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_BRIDGE_SRC_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_P2P_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_BRIDGE_SRC_BUSECC_groupEntries[SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_P2P_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:6529
SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_groupEntries[SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:17931
SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_groupEntries[SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:17838
SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
#define SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:95
SDL_SMS0_SMS_HSM_ECC_SMS_HSM_WWRTI_CM_EDC_CTRL_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_SMS0_SMS_HSM_ECC_SMS_HSM_WWRTI_CM_EDC_CTRL_BUSECC_groupEntries[SDL_SMS0_SMS_HSM_ECC_SMS_HSM_WWRTI_CM_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:15715
SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_TXMEM_RAM_IDS_TOTAL_ENTRIES
#define SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_TXMEM_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:77
SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_SAM62A_MCU_MCU_ECC_AGGR_EDC_CTRL_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_SAM62A_MCU_MCU_ECC_AGGR_EDC_CTRL_groupEntries[SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_SAM62A_MCU_MCU_ECC_AGGR_EDC_CTRL_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:6976
SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_groupEntries
static const SDL_GrpChkConfig_t SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_groupEntries[SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:10842
SDL_PSRAMECC0_PSRAM256X32E_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
#define SDL_PSRAMECC0_PSRAM256X32E_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:60
SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_groupEntries[SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:9134
SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
#define SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:88
SDL_ecc_aggrRegs
Definition: V0/sdlr_ecc.h:54
SDL_PSRAMECC0_PSRAM256X32E_ECC_AGGR_RamIdTable
static const SDL_RAMIdEntry_t SDL_PSRAMECC0_PSRAM256X32E_ECC_AGGR_RamIdTable[SDL_PSRAMECC0_PSRAM256X32E_ECC_AGGR_NUM_RAMS]
Definition: sdl_ecc_soc.h:21469
SDL_PSRAMECC0_PSRAM256X32E_ECC_AGGR_MemEntries
static const SDL_MemConfig_t SDL_PSRAMECC0_PSRAM256X32E_ECC_AGGR_MemEntries[SDL_PSRAMECC0_PSRAM256X32E_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
Definition: sdl_ecc_soc.h:121
SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_SAM62A_DM_DM_ECC_AGGR_EDC_CTRL_groupEntries
static const SDL_GrpChkConfig_t SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_SAM62A_DM_DM_ECC_AGGR_EDC_CTRL_groupEntries[SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_SAM62A_DM_DM_ECC_AGGR_EDC_CTRL_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:20394
SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_groupEntries[SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:5915
SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ISAM62A_MCU_MCU_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM62A_MCU_MCU_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ISAM62A_MCU_MCU_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM62A_MCU_MCU_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_groupEntries[SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ISAM62A_MCU_MCU_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM62A_MCU_MCU_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:3033
SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISAM62A_DM_MCU_ECC_AGGR_WKUP_1_CFG_P2P_BRIDGE_ISAM62A_DM_MCU_ECC_AGGR_WKUP_1_CFG_BRIDGE_DST_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISAM62A_DM_MCU_ECC_AGGR_WKUP_1_CFG_P2P_BRIDGE_ISAM62A_DM_MCU_ECC_AGGR_WKUP_1_CFG_BRIDGE_DST_BUSECC_groupEntries[SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISAM62A_DM_MCU_ECC_AGGR_WKUP_1_CFG_P2P_BRIDGE_ISAM62A_DM_MCU_ECC_AGGR_WKUP_1_CFG_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:155
SDL_MMCSD0_EMMCSD8SS_ECC_AGGR_TXMEM_MemEntries
static const SDL_MemConfig_t SDL_MMCSD0_EMMCSD8SS_ECC_AGGR_TXMEM_MemEntries[SDL_MMCSD0_EMMCSD8SS_ECC_AGGR_TXMEM_RAM_IDS_TOTAL_ENTRIES]
Definition: sdl_ecc_soc.h:2073
SDL_PDMA1_SAM62_PDMA_UART_ECCAGGR_RAM_IDS_TOTAL_ENTRIES
#define SDL_PDMA1_SAM62_PDMA_UART_ECCAGGR_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:94
SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_groupEntries[SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:7272
SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_TAG_CTL_TOP_DMC_TAG_CTL_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_TAG_CTL_TOP_DMC_TAG_CTL_EDC_CTRL_0_groupEntries[SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_TAG_CTL_TOP_DMC_TAG_CTL_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:18915
SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_DM2MCU_VBUSM_GASKET_MCU_0_EDC_CTRL_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_DM2MCU_VBUSM_GASKET_MCU_0_EDC_CTRL_groupEntries[SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_DM2MCU_VBUSM_GASKET_MCU_0_EDC_CTRL_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:2638
SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ISAM62A_MCU_PULSAR_UL_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM62A_MCU_PULSAR_UL_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ISAM62A_MCU_PULSAR_UL_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM62A_MCU_PULSAR_UL_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_groupEntries[SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ISAM62A_MCU_PULSAR_UL_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM62A_MCU_PULSAR_UL_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:3068
SDL_SMS0_SMS_TIFS_ECC_RAM_IDS_TOTAL_ENTRIES
#define SDL_SMS0_SMS_TIFS_ECC_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:86
SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_groupEntries[SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:2257
SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_groupEntries
static const SDL_GrpChkConfig_t SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_groupEntries[SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:13883
SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_groupEntries[SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:9936
SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_groupEntries
static const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_groupEntries[SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:7793
SDL_USB0_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_RamIdTable
static const SDL_RAMIdEntry_t SDL_USB0_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_RamIdTable[SDL_USB0_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_NUM_RAMS]
Definition: sdl_ecc_soc.h:23244
SDL_MSRAM_64K0_MSRAM2KX256E_ECC_AGGR_RamIdTable
static const SDL_RAMIdEntry_t SDL_MSRAM_64K0_MSRAM2KX256E_ECC_AGGR_RamIdTable[SDL_MSRAM_64K0_MSRAM2KX256E_ECC_AGGR_NUM_RAMS]
Definition: sdl_ecc_soc.h:21495
SDL_PDMA0_SAM62_PDMA_SPI_ECCAGGR_RamIdTable
static const SDL_RAMIdEntry_t SDL_PDMA0_SAM62_PDMA_SPI_ECCAGGR_RamIdTable[SDL_PDMA0_SAM62_PDMA_SPI_ECCAGGR_NUM_RAMS]
Definition: sdl_ecc_soc.h:23275
SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_groupEntries[SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:14359
SDL_PSCSS0_SAM62A_MAIN_PSC_WRAP_ECC_AGGR_MemEntries
static const SDL_MemConfig_t SDL_PSCSS0_SAM62A_MAIN_PSC_WRAP_ECC_AGGR_MemEntries[SDL_PSCSS0_SAM62A_MAIN_PSC_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
Definition: sdl_ecc_soc.h:110
SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_CBASS_DEFAULT_ERR_AM62A_MCU_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_CBASS_DEFAULT_ERR_AM62A_MCU_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_groupEntries[SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_CBASS_DEFAULT_ERR_AM62A_MCU_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:6572
SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_RXMEM_RamIdTable
static const SDL_RAMIdEntry_t SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_RXMEM_RamIdTable[SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_RXMEM_NUM_RAMS]
Definition: sdl_ecc_soc.h:22117
SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_EDC_CTRL_0_groupEntries[SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:7227
SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_P2M_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_BRIDGE_DST_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_P2M_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_BRIDGE_DST_BUSECC_groupEntries[SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_P2M_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:6436
SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_groupEntries[SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:10474
SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_groupEntries[SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:8212
SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_CFG_P2P_BRIDGE_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_CFG_BRIDGE_SRC_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_CFG_P2P_BRIDGE_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_CFG_BRIDGE_SRC_BUSECC_groupEntries[SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_CFG_P2P_BRIDGE_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_CFG_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:2990
SDL_PSRAMECC1_PSRAM256X32E_ECC_AGGR_MemEntries
static const SDL_MemConfig_t SDL_PSRAMECC1_PSRAM256X32E_ECC_AGGR_MemEntries[SDL_PSRAMECC1_PSRAM256X32E_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
Definition: sdl_ecc_soc.h:132
SDL_ECC_BASE_ADDRESS_TOTAL_ENTRIES
#define SDL_ECC_BASE_ADDRESS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:104
SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_IAM62A_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM62A_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_BRIDGE_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_IAM62A_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM62A_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_BRIDGE_BUSECC_groupEntries[SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_IAM62A_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM62A_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_BRIDGE_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:13041
SDL_MCU_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_groupEntries[SDL_MCU_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:20926
SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_RamIdTable
static const SDL_RAMIdEntry_t SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_RamIdTable[SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_NUM_RAMS]
Definition: sdl_ecc_soc.h:21612
SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_groupEntries[SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:325
SDL_ECC_AGGR1_SAM62A_SEC_MCU_ECC_AGGR_RamIdTable
static const SDL_RAMIdEntry_t SDL_ECC_AGGR1_SAM62A_SEC_MCU_ECC_AGGR_RamIdTable[SDL_ECC_AGGR1_SAM62A_SEC_MCU_ECC_AGGR_NUM_RAMS]
Definition: sdl_ecc_soc.h:21930
SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_groupEntries[SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:1535
SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_AC71_PMC_WRAP_PMC_PMC_MEMWRAP_EDC_CTRL_PARITY_0_groupEntries
static const SDL_GrpChkConfig_t SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_AC71_PMC_WRAP_PMC_PMC_MEMWRAP_EDC_CTRL_PARITY_0_groupEntries[SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_AC71_PMC_WRAP_PMC_PMC_MEMWRAP_EDC_CTRL_PARITY_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:18898
SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__IECC_AGGR_CFG_SRC_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__IECC_AGGR_CFG_SRC_BUSECC_groupEntries[SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__IECC_AGGR_CFG_SRC_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:2599
SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_MemEntries
static const SDL_MemConfig_t SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_MemEntries[SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
Definition: sdl_ecc_soc.h:2095
SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_IK3VTM_N16FFC_WKUP_0_VBUSP_P2P_BRIDGE_IK3VTM_N16FFC_WKUP_0_VBUSP_BRIDGE_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_IK3VTM_N16FFC_WKUP_0_VBUSP_P2P_BRIDGE_IK3VTM_N16FFC_WKUP_0_VBUSP_BRIDGE_BUSECC_groupEntries[SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_IK3VTM_N16FFC_WKUP_0_VBUSP_P2P_BRIDGE_IK3VTM_N16FFC_WKUP_0_VBUSP_BRIDGE_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:19652
SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_groupEntries[SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:3485
SDL_MCU_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_RamIdTable
static const SDL_RAMIdEntry_t SDL_MCU_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_RamIdTable[SDL_MCU_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_NUM_RAMS]
Definition: sdl_ecc_soc.h:24112
SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_groupEntries[SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:2110
SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_groupEntries[SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:9621
SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
#define SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:63
SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_MemEntries
static const SDL_MemConfig_t SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_MemEntries[SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
Definition: sdl_ecc_soc.h:20434
SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_0_groupEntries[SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:1465
SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_RamIdTable
static const SDL_RAMIdEntry_t SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_RamIdTable[SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_NUM_RAMS]
Definition: sdl_ecc_soc.h:23178
SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_groupEntries[SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:14219
SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IMSRAM32KX64E_MCU_1_CFG_P2P_BRIDGE_IMSRAM32KX64E_MCU_1_CFG_BRIDGE_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IMSRAM32KX64E_MCU_1_CFG_P2P_BRIDGE_IMSRAM32KX64E_MCU_1_CFG_BRIDGE_BUSECC_groupEntries[SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IMSRAM32KX64E_MCU_1_CFG_P2P_BRIDGE_IMSRAM32KX64E_MCU_1_CFG_BRIDGE_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:2897
SDL_WKUP_PSRAMECC_8K0_PSRAM8KX32E_ECC_AGGR_MemEntries
static const SDL_MemConfig_t SDL_WKUP_PSRAMECC_8K0_PSRAM8KX32E_ECC_AGGR_MemEntries[SDL_WKUP_PSRAMECC_8K0_PSRAM8KX32E_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
Definition: sdl_ecc_soc.h:19380
SDL_GICSS0_GIC500SS_1_4_ECC_AGGR_RamIdTable
static const SDL_RAMIdEntry_t SDL_GICSS0_GIC500SS_1_4_ECC_AGGR_RamIdTable[SDL_GICSS0_GIC500SS_1_4_ECC_AGGR_NUM_RAMS]
Definition: sdl_ecc_soc.h:21907
SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_DST_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_DST_BUSECC_groupEntries[SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:21290
SDL_ECC_aggrTransBaseAddressTable
SDL_ecc_aggrRegs * SDL_ECC_aggrTransBaseAddressTable[SDL_ECC_MEMTYPE_MAX]
SDL_GICSS0_GIC500SS_1_4_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
#define SDL_GICSS0_GIC500SS_1_4_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:71
SDL_PSCSS0_SAM62A_MAIN_PSC_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
#define SDL_PSCSS0_SAM62A_MAIN_PSC_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:59
SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_RamIdTable
static const SDL_RAMIdEntry_t SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_RamIdTable[SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_NUM_RAMS]
Definition: sdl_ecc_soc.h:23412
SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_groupEntries[SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:4285
SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_MemEntries
static const SDL_MemConfig_t SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_MemEntries[SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_RAM_IDS_TOTAL_ENTRIES]
Definition: sdl_ecc_soc.h:20456
SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_groupEntries
static const SDL_GrpChkConfig_t SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_groupEntries[SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:12156
SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_HSM_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_HSM_VBUSP_S_BRIDGE_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_HSM_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_HSM_VBUSP_S_BRIDGE_BUSECC_groupEntries[SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_HSM_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_HSM_VBUSP_S_BRIDGE_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:21081
SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_RAM_IDS_TOTAL_ENTRIES
#define SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:96
SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_groupEntries[SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:8500
SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_SAM62A_WKUP_SAFE_ECC_AGGR_EDC_CTRL_groupEntries
static const SDL_GrpChkConfig_t SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_SAM62A_WKUP_SAFE_ECC_AGGR_EDC_CTRL_groupEntries[SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_SAM62A_WKUP_SAFE_ECC_AGGR_EDC_CTRL_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:14430
SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
#define SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:68
SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_groupEntries
static const SDL_GrpChkConfig_t SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_groupEntries[SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:16410
SDL_USB1_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_RamIdTable
static const SDL_RAMIdEntry_t SDL_USB1_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_RamIdTable[SDL_USB1_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_NUM_RAMS]
Definition: sdl_ecc_soc.h:23226
SDL_USB0_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_MemEntries
static const SDL_MemConfig_t SDL_USB0_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_MemEntries[SDL_USB0_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
Definition: sdl_ecc_soc.h:19366
SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_PLL_MMR_EDC_CTRL_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_PLL_MMR_EDC_CTRL_BUSECC_groupEntries[SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_PLL_MMR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:11520
SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_SCRP_EDC_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_SCRP_EDC_groupEntries[SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_SCRP_EDC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:1504
SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_SEC_CM_EDC_CTRL_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_SEC_CM_EDC_CTRL_BUSECC_groupEntries[SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_SEC_CM_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:18256
SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_RamIdTable
static const SDL_RAMIdEntry_t SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_RamIdTable[SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_NUM_RAMS]
Definition: sdl_ecc_soc.h:23135
SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_RAM_IDS_TOTAL_ENTRIES
#define SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:100
SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR_RamIdTable
static const SDL_RAMIdEntry_t SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR_RamIdTable[SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR_NUM_RAMS]
Definition: sdl_ecc_soc.h:21836
SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ERR_SCR_AM62A_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ERR_SCR_AM62A_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_groupEntries[SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ERR_SCR_AM62A_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:6756
SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IFWMGR_M_P2P_BRIDGE_IFWMGR_M_BRIDGE_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IFWMGR_M_P2P_BRIDGE_IFWMGR_M_BRIDGE_BUSECC_groupEntries[SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IFWMGR_M_P2P_BRIDGE_IFWMGR_M_BRIDGE_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:17027
SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_MemEntries
static const SDL_MemConfig_t SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_MemEntries[SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
Definition: sdl_ecc_soc.h:14450
SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_groupEntries[SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:539
SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_INTAGGR_CEVT_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_INTAGGR_CEVT_EDC_CTRL_0_groupEntries[SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_INTAGGR_CEVT_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:9595
SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_groupEntries[SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:17978
SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_groupEntries[SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:19687
SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IAM62A_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM62A_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IAM62A_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM62A_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_groupEntries[SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IAM62A_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM62A_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:2796
SDL_SMS0_SMS_TIFS_ECC_RamIdTable
static const SDL_RAMIdEntry_t SDL_SMS0_SMS_TIFS_ECC_RamIdTable[SDL_SMS0_SMS_TIFS_ECC_NUM_RAMS]
Definition: sdl_ecc_soc.h:23022
SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_PKTDMA_CRED_SRC_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_PKTDMA_CRED_SRC_BUSECC_groupEntries[SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_PKTDMA_CRED_SRC_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:21419
SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_MemEntries
static const SDL_MemConfig_t SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_MemEntries[SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_RAM_IDS_TOTAL_ENTRIES]
Definition: sdl_ecc_soc.h:20545
SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_2_groupEntries
static const SDL_GrpChkConfig_t SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_2_groupEntries[SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_2_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:16931
SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_groupEntries[SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:4562
SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_RAM_IDS_TOTAL_ENTRIES
#define SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:97
SDL_DMASS0_DMSS_AM62A_ECCAGGR_RAM_IDS_TOTAL_ENTRIES
#define SDL_DMASS0_DMSS_AM62A_ECCAGGR_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:73
SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_RAM_IDS_TOTAL_ENTRIES
#define SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:98
SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_groupEntries[SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:15668
SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries[SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:8059
SDL_SMS0_SMS_TIFS_ECC_ISRAM1_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_SMS0_SMS_TIFS_ECC_ISRAM1_BUSECC_groupEntries[SDL_SMS0_SMS_TIFS_ECC_ISRAM1_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:15840
SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_DMSS_CFG_P2P_BRIDGE_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_DMSS_CFG_P2P_BRIDGE_EDC_CTRL_0_groupEntries[SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_DMSS_CFG_P2P_BRIDGE_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:10451
SDL_GICSS0_GIC500SS_1_4_ECC_AGGR_MemEntries
static const SDL_MemConfig_t SDL_GICSS0_GIC500SS_1_4_ECC_AGGR_MemEntries[SDL_GICSS0_GIC500SS_1_4_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
Definition: sdl_ecc_soc.h:1903
SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_groupEntries[SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:9503
SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
#define SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:69
SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_SAM62A_MCU_PULSAR_UL_ECC_AGGR_EDC_CTRL_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_SAM62A_MCU_PULSAR_UL_ECC_AGGR_EDC_CTRL_groupEntries[SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_SAM62A_MCU_PULSAR_UL_ECC_AGGR_EDC_CTRL_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:18866
SDL_SMS0_SMS_TIFS_ECC_MemEntries
static const SDL_MemConfig_t SDL_SMS0_SMS_TIFS_ECC_MemEntries[SDL_SMS0_SMS_TIFS_ECC_RAM_IDS_TOTAL_ENTRIES]
Definition: sdl_ecc_soc.h:15776
SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_ECCAGGR_EDC_CTRL_groupEntries
static const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_ECCAGGR_EDC_CTRL_groupEntries[SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_ECCAGGR_EDC_CTRL_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:7053
SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_DEFAULT_MMRS_SMS_HSM_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_DEFAULT_MMRS_SMS_HSM_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_groupEntries[SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_DEFAULT_MMRS_SMS_HSM_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:15550
SDL_MemConfig_t
Definition: sdl_ecc_priv.h:71
SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_CBASS_DEFAULT_MMRS_AM62A_MCU_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_CBASS_DEFAULT_MMRS_AM62A_MCU_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_groupEntries[SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_CBASS_DEFAULT_MMRS_AM62A_MCU_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:6591
SDL_WKUP_PSRAMECC_8K0_PSRAM8KX32E_ECC_AGGR_RamIdTable
static const SDL_RAMIdEntry_t SDL_WKUP_PSRAMECC_8K0_PSRAM8KX32E_ECC_AGGR_RamIdTable[SDL_WKUP_PSRAMECC_8K0_PSRAM8KX32E_ECC_AGGR_NUM_RAMS]
Definition: sdl_ecc_soc.h:23262
SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_groupEntries[SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:6849
SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_MemEntries
static const SDL_MemConfig_t SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_MemEntries[SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_RAM_IDS_TOTAL_ENTRIES]
Definition: sdl_ecc_soc.h:6996
SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_MemEntries
static const SDL_MemConfig_t SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_MemEntries[SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_RAM_IDS_TOTAL_ENTRIES]
Definition: sdl_ecc_soc.h:20723
SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_TXMEM_RamIdTable
static const SDL_RAMIdEntry_t SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_TXMEM_RamIdTable[SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_TXMEM_NUM_RAMS]
Definition: sdl_ecc_soc.h:22130
SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_groupEntries
static const SDL_GrpChkConfig_t SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_groupEntries[SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:13362
SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_RAM_IDS_TOTAL_ENTRIES
#define SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:81
SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_UMC_WRAP_C7XV_EL2_C7XV_EL2_CORE_C7XV_EL2_EDC_CTL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_UMC_WRAP_C7XV_EL2_C7XV_EL2_CORE_C7XV_EL2_EDC_CTL_0_groupEntries[SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_UMC_WRAP_C7XV_EL2_C7XV_EL2_CORE_C7XV_EL2_EDC_CTL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:19312
SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_TXMEM_MemEntries
static const SDL_MemConfig_t SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_TXMEM_MemEntries[SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_TXMEM_RAM_IDS_TOTAL_ENTRIES]
Definition: sdl_ecc_soc.h:2062
SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_DRU_R30_C_R_CORE_RD_BUFFER_CMD_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_DRU_R30_C_R_CORE_RD_BUFFER_CMD_EDC_CTRL_0_groupEntries[SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_DRU_R30_C_R_CORE_RD_BUFFER_CMD_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:19290
SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_groupEntries[SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:13111
SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_RXMEM_MemEntries
static const SDL_MemConfig_t SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_RXMEM_MemEntries[SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_RXMEM_RAM_IDS_TOTAL_ENTRIES]
Definition: sdl_ecc_soc.h:2029
SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
#define SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:70
SDL_DMASS1_DMSS_CSI_AM62A_ECCAGGR_RAM_IDS_TOTAL_ENTRIES
#define SDL_DMASS1_DMSS_CSI_AM62A_ECCAGGR_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:64
SDL_FSS0_FSS_UL_OSPI0_OSPI_WRAP_ECC_AGGR_RamIdTable
static const SDL_RAMIdEntry_t SDL_FSS0_FSS_UL_OSPI0_OSPI_WRAP_ECC_AGGR_RamIdTable[SDL_FSS0_FSS_UL_OSPI0_OSPI_WRAP_ECC_AGGR_NUM_RAMS]
Definition: sdl_ecc_soc.h:21640
SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_PKTDMA_CRED_DST_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_PKTDMA_CRED_DST_BUSECC_groupEntries[SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_PKTDMA_CRED_DST_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:21402
SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_groupEntries[SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:18646
sdl_ecc.h
Header file contains enumerations, structure definitions and function.
SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_FW_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_FW_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_groupEntries[SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_FW_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:21212
SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_RamIdTable
static const SDL_RAMIdEntry_t SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_RamIdTable[SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_NUM_RAMS]
Definition: sdl_ecc_soc.h:22169
SDL_SMS0_SMS_HSM_ECC_RAM_IDS_TOTAL_ENTRIES
#define SDL_SMS0_SMS_HSM_ECC_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:85
SDL_MMCSD0_EMMCSD8SS_ECC_AGGR_TXMEM_RamIdTable
static const SDL_RAMIdEntry_t SDL_MMCSD0_EMMCSD8SS_ECC_AGGR_TXMEM_RamIdTable[SDL_MMCSD0_EMMCSD8SS_ECC_AGGR_TXMEM_NUM_RAMS]
Definition: sdl_ecc_soc.h:22143
SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_CFG_P2P_BRIDGE_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_CFG_BRIDGE_DST_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_CFG_P2P_BRIDGE_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_CFG_BRIDGE_DST_BUSECC_groupEntries[SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_CFG_P2P_BRIDGE_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_CFG_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:2967
SDL_ECC_AGGR1_SAM62A_SEC_MCU_ECC_AGGR_AM62A_MAIN_FW_CBASS_IAM62A_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM62A_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_ECC_AGGR1_SAM62A_SEC_MCU_ECC_AGGR_AM62A_MAIN_FW_CBASS_IAM62A_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM62A_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_groupEntries[SDL_ECC_AGGR1_SAM62A_SEC_MCU_ECC_AGGR_AM62A_MAIN_FW_CBASS_IAM62A_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM62A_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:1921
SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_BRIDGE_DST_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_BRIDGE_DST_BUSECC_groupEntries[SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:6356
SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_groupEntries[SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:3764
SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISAM62A_DM_MCU_ECC_AGGR_WKUP_1_CFG_P2P_BRIDGE_ISAM62A_DM_MCU_ECC_AGGR_WKUP_1_CFG_BRIDGE_SRC_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISAM62A_DM_MCU_ECC_AGGR_WKUP_1_CFG_P2P_BRIDGE_ISAM62A_DM_MCU_ECC_AGGR_WKUP_1_CFG_BRIDGE_SRC_BUSECC_groupEntries[SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISAM62A_DM_MCU_ECC_AGGR_WKUP_1_CFG_P2P_BRIDGE_ISAM62A_DM_MCU_ECC_AGGR_WKUP_1_CFG_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:20061
SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_ECC_AGGR_EDC_CTRL_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_ECC_AGGR_EDC_CTRL_groupEntries[SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_ECC_AGGR_EDC_CTRL_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:678
SDL_MCU_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
#define SDL_MCU_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:102
SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_CFG_SLV_DST_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_CFG_SLV_DST_BUSECC_groupEntries[SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_CFG_SLV_DST_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:18793
SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_RamIdTable
static const SDL_RAMIdEntry_t SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_RamIdTable[SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_NUM_RAMS]
Definition: sdl_ecc_soc.h:21653
SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_groupEntries[SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:15039
SDL_SMS0_SMS_HSM_ECC_ISRAM0_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_SMS0_SMS_HSM_ECC_ISRAM0_BUSECC_groupEntries[SDL_SMS0_SMS_HSM_ECC_ISRAM0_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:14560
SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_TXMEM_RAM_IDS_TOTAL_ENTRIES
#define SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_TXMEM_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:75
SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MemEntries
static const SDL_MemConfig_t SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MemEntries[SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
Definition: sdl_ecc_soc.h:527
SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_groupEntries
static const SDL_GrpChkConfig_t SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_groupEntries[SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:15889
SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_groupEntries
static const SDL_GrpChkConfig_t SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_groupEntries[SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:11635
SDL_MCU_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_MemEntries
static const SDL_MemConfig_t SDL_MCU_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_MemEntries[SDL_MCU_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
Definition: sdl_ecc_soc.h:20914
SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_PMST_SRC_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_PMST_SRC_BUSECC_groupEntries[SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_PMST_SRC_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:18810
SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_groupEntries[SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:14658
SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_groupEntries[SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:178
SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_groupEntries[SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:8854
SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_MemEntries
static const SDL_MemConfig_t SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_MemEntries[SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_RAM_IDS_TOTAL_ENTRIES]
Definition: sdl_ecc_soc.h:20812
SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_RamIdTable
static const SDL_RAMIdEntry_t SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_RamIdTable[SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_NUM_RAMS]
Definition: sdl_ecc_soc.h:24148
SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_groupEntries[SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:6709
SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_groupEntries[SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:21151
SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_groupEntries[SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:9424
SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_WWRTI_CM_EDC_CTRL_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_WWRTI_CM_EDC_CTRL_BUSECC_groupEntries[SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_WWRTI_CM_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:18154
SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_DMSS_HSM_P2P_BRIDGE_SMS_DMSS_HSM_BRIDGE_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_DMSS_HSM_P2P_BRIDGE_SMS_DMSS_HSM_BRIDGE_BUSECC_groupEntries[SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_DMSS_HSM_P2P_BRIDGE_SMS_DMSS_HSM_BRIDGE_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:18119
SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_TXMEM_MemEntries
static const SDL_MemConfig_t SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_TXMEM_MemEntries[SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_TXMEM_RAM_IDS_TOTAL_ENTRIES]
Definition: sdl_ecc_soc.h:2040
SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_groupEntries[SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:17678
SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_groupEntries[SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:19577
SDL_MMCSD0_EMMCSD8SS_ECC_AGGR_RXMEM_RamIdTable
static const SDL_RAMIdEntry_t SDL_MMCSD0_EMMCSD8SS_ECC_AGGR_RXMEM_RamIdTable[SDL_MMCSD0_EMMCSD8SS_ECC_AGGR_RXMEM_NUM_RAMS]
Definition: sdl_ecc_soc.h:22156
SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_groupEntries[SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:9345
SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_groupEntries[SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:8785
SDL_SMS0_SMS_HSM_ECC_MemEntries
static const SDL_MemConfig_t SDL_SMS0_SMS_HSM_ECC_MemEntries[SDL_SMS0_SMS_HSM_ECC_RAM_IDS_TOTAL_ENTRIES]
Definition: sdl_ecc_soc.h:14545
SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:19842
SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_groupEntries[SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:10665
SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_SRC_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_SRC_BUSECC_groupEntries[SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:21307
SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MemEntries
static const SDL_MemConfig_t SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MemEntries[SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
Definition: sdl_ecc_soc.h:1732
SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_groupEntries[SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:5083
SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_groupEntries[SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:20948
SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_groupEntries
static const SDL_GrpChkConfig_t SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_groupEntries[SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:20446
SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:20104
SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_RamIdTable
static const SDL_RAMIdEntry_t SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_RamIdTable[SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_NUM_RAMS]
Definition: sdl_ecc_soc.h:23698
SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_groupEntries[SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:8710
SDL_MMCSD0_EMMCSD8SS_ECC_AGGR_RXMEM_MemEntries
static const SDL_MemConfig_t SDL_MMCSD0_EMMCSD8SS_ECC_AGGR_RXMEM_MemEntries[SDL_MMCSD0_EMMCSD8SS_ECC_AGGR_RXMEM_RAM_IDS_TOTAL_ENTRIES]
Definition: sdl_ecc_soc.h:2084
SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_BRIDGE_SRC_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_BRIDGE_SRC_BUSECC_groupEntries[SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:6393
SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_RamIdTable
static const SDL_RAMIdEntry_t SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_RamIdTable[SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_NUM_RAMS]
Definition: sdl_ecc_soc.h:21884
SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_MemEntries
static const SDL_MemConfig_t SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_MemEntries[SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
Definition: sdl_ecc_soc.h:10797
SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_RamIdTable
static const SDL_RAMIdEntry_t SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_RamIdTable[SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_NUM_RAMS]
Definition: sdl_ecc_soc.h:22703
SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_P2P_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_BRIDGE_DST_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_P2P_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_BRIDGE_DST_BUSECC_groupEntries[SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_P2P_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:6510
SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__IECC_AGGR_CFG_DST_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__IECC_AGGR_CFG_DST_BUSECC_groupEntries[SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__IECC_AGGR_CFG_DST_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:18849
SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_RXMEM_RAM_IDS_TOTAL_ENTRIES
#define SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_RXMEM_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:74
SDL_RAMIdEntry_t
Definition: sdl_ecc_priv.h:46
SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_RamIdTable
static const SDL_RAMIdEntry_t SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_RamIdTable[SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_NUM_RAMS]
Definition: sdl_ecc_soc.h:22392
SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_SAM62A_DM_MCU_ECC_AGGR_EDC_CTRL_groupEntries
static const SDL_GrpChkConfig_t SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_SAM62A_DM_MCU_ECC_AGGR_EDC_CTRL_groupEntries[SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_SAM62A_DM_MCU_ECC_AGGR_EDC_CTRL_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:472
SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_VD2GCLK_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_VD2GCLK_EDC_CTRL_0_groupEntries[SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_VD2GCLK_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:8485
SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_groupEntries[SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:8635
SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_RAM_IDS_TOTAL_ENTRIES
#define SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:66
SDL_MSRAM_64K0_MSRAM2KX256E_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
#define SDL_MSRAM_64K0_MSRAM2KX256E_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:62
SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_RamIdTable
static const SDL_RAMIdEntry_t SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_RamIdTable[SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_NUM_RAMS]
Definition: sdl_ecc_soc.h:22635
SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_ECCAGGR_EDC_CTRL_groupEntries
static const SDL_GrpChkConfig_t SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_ECCAGGR_EDC_CTRL_groupEntries[SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_ECCAGGR_EDC_CTRL_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:699
SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
#define SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:82
SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_MemEntries
static const SDL_MemConfig_t SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_MemEntries[SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_RAM_IDS_TOTAL_ENTRIES]
Definition: sdl_ecc_soc.h:20634
SDL_MCU_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_groupEntries[SDL_MCU_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:20904
SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_groupEntries[SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:1382
SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_groupEntries[SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:7916
SDL_PSRAMECC1_PSRAM256X32E_ECC_AGGR_RamIdTable
static const SDL_RAMIdEntry_t SDL_PSRAMECC1_PSRAM256X32E_ECC_AGGR_RamIdTable[SDL_PSRAMECC1_PSRAM256X32E_ECC_AGGR_NUM_RAMS]
Definition: sdl_ecc_soc.h:21482
SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
#define SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:80
SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_DMSS_CFG_DST_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_DMSS_CFG_DST_BUSECC_groupEntries[SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_DMSS_CFG_DST_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:21346
SDL_SMS0_SMS_HSM_ECC_ISRAM1_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_SMS0_SMS_HSM_ECC_ISRAM1_BUSECC_groupEntries[SDL_SMS0_SMS_HSM_ECC_ISRAM1_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:14609
SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_groupEntries[SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:18507
SDL_SMS0_SMS_TIFS_ECC_ISRAM0_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_SMS0_SMS_TIFS_ECC_ISRAM0_BUSECC_groupEntries[SDL_SMS0_SMS_TIFS_ECC_ISRAM0_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:15791
SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_groupEntries[SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:2649
SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_groupEntries[SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:720
SDL_SMS0_SMS_HSM_ECC_SMS_HSM_ECC_EDC_CTRL_groupEntries
static const SDL_GrpChkConfig_t SDL_SMS0_SMS_HSM_ECC_SMS_HSM_ECC_EDC_CTRL_groupEntries[SDL_SMS0_SMS_HSM_ECC_SMS_HSM_ECC_EDC_CTRL_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:15756
SDL_PSRAMECC1_PSRAM256X32E_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
#define SDL_PSRAMECC1_PSRAM256X32E_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:61
SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_DST_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_DST_BUSECC_groupEntries[SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:6896
SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:20253
SDL_DMASS1_DMSS_CSI_AM62A_ECCAGGR_RamIdTable
static const SDL_RAMIdEntry_t SDL_DMASS1_DMSS_CSI_AM62A_ECCAGGR_RamIdTable[SDL_DMASS1_DMSS_CSI_AM62A_ECCAGGR_NUM_RAMS]
Definition: sdl_ecc_soc.h:21536
SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_DRU_R30_C_R_CORE_CH_LOGIC_RING_MEM_RING_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_DRU_R30_C_R_CORE_CH_LOGIC_RING_MEM_RING_EDC_CTRL_0_groupEntries[SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_DRU_R30_C_R_CORE_CH_LOGIC_RING_MEM_RING_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:19301
SDL_MCU_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
#define SDL_MCU_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:101
SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_VD2GCLK_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_VD2GCLK_EDC_CTRL_0_groupEntries[SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_VD2GCLK_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:10422
SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_PMST_DST_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_PMST_DST_BUSECC_groupEntries[SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_PMST_DST_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:2582
SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_groupEntries[SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:5394
SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_RamIdTable
static const SDL_RAMIdEntry_t SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_RamIdTable[SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_NUM_RAMS]
Definition: sdl_ecc_soc.h:23394
SDL_EccAggrEntry_t
Definition: sdl_ecc_priv.h:87
SDL_FSS0_FSS_UL_OSPI0_OSPI_WRAP_ECC_AGGR_MemEntries
static const SDL_MemConfig_t SDL_FSS0_FSS_UL_OSPI0_OSPI_WRAP_ECC_AGGR_MemEntries[SDL_FSS0_FSS_UL_OSPI0_OSPI_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
Definition: sdl_ecc_soc.h:1194
SDL_DMASS0_DMSS_AM62A_ECCAGGR_RamIdTable
static const SDL_RAMIdEntry_t SDL_DMASS0_DMSS_AM62A_ECCAGGR_RamIdTable[SDL_DMASS0_DMSS_AM62A_ECCAGGR_NUM_RAMS]
Definition: sdl_ecc_soc.h:21943
SDL_MMCSD0_EMMCSD8SS_ECC_AGGR_TXMEM_RAM_IDS_TOTAL_ENTRIES
#define SDL_MMCSD0_EMMCSD8SS_ECC_AGGR_TXMEM_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:78
SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_groupEntries[SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:15415
SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISAM62A_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM62A_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_SRC_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISAM62A_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM62A_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_SRC_BUSECC_groupEntries[SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISAM62A_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM62A_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:20018
SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_RXMEM_MemEntries
static const SDL_MemConfig_t SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_RXMEM_MemEntries[SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_RXMEM_RAM_IDS_TOTAL_ENTRIES]
Definition: sdl_ecc_soc.h:2051
SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_ECC_EDC_CTRL_groupEntries
static const SDL_GrpChkConfig_t SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_ECC_EDC_CTRL_groupEntries[SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_ECC_EDC_CTRL_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:18339
SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_groupEntries[SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:1744
SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CM_EDC_CTRL_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CM_EDC_CTRL_BUSECC_groupEntries[SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CM_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:18175
SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_DRU_R30_C_R_CORE_QUEUE_CMD_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_DRU_R30_C_R_CORE_QUEUE_CMD_EDC_CTRL_0_groupEntries[SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_DRU_R30_C_R_CORE_QUEUE_CMD_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:19273
SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_groupEntries[SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:3103
SDL_USB1_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_MemEntries
static const SDL_MemConfig_t SDL_USB1_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_MemEntries[SDL_USB1_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
Definition: sdl_ecc_soc.h:19352
SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_VBUSM2AXI_EDC_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_VBUSM2AXI_EDC_groupEntries[SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_VBUSM2AXI_EDC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:1301
SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_INTAGGR_MEVT_IN_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_INTAGGR_MEVT_IN_EDC_CTRL_0_groupEntries[SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_INTAGGR_MEVT_IN_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:9608
SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_MemEntries
static const SDL_MemConfig_t SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_MemEntries[SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
Definition: sdl_ecc_soc.h:18886
SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_groupEntries
static const SDL_GrpChkConfig_t SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_groupEntries[SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:11363
SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
#define SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:103
SDL_MSRAM_64K0_MSRAM2KX256E_ECC_AGGR_MemEntries
static const SDL_MemConfig_t SDL_MSRAM_64K0_MSRAM2KX256E_ECC_AGGR_MemEntries[SDL_MSRAM_64K0_MSRAM2KX256E_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
Definition: sdl_ecc_soc.h:143
SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_ECC_AGGR_EDC_CTRL_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_ECC_AGGR_EDC_CTRL_groupEntries[SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_ECC_AGGR_EDC_CTRL_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:1680
SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_RamIdTable
static const SDL_RAMIdEntry_t SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_RamIdTable[SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_NUM_RAMS]
Definition: sdl_ecc_soc.h:23555
SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_VBUSP_P2P_BRIDGE_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_VBUSP_P2P_BRIDGE_EDC_CTRL_0_groupEntries[SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_VBUSP_P2P_BRIDGE_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:1071
sdl_ecc_priv.h
SDL_ESM_INST_WKUP_ESM0
@ SDL_ESM_INST_WKUP_ESM0
Definition: sdl_esm_soc.h:61
SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_groupEntries
static const SDL_GrpChkConfig_t SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_groupEntries[SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:12677
SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
#define SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:65
SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_groupEntries[SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:9715
SDL_PDMA0_SAM62_PDMA_SPI_ECCAGGR_RAM_IDS_TOTAL_ENTRIES
#define SDL_PDMA0_SAM62_PDMA_SPI_ECCAGGR_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:92
SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_groupEntries[SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:3274
SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_groupEntries[SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:14312
SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_P2M_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_BRIDGE_SRC_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_P2M_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_BRIDGE_SRC_BUSECC_groupEntries[SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_P2M_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:6467
SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_groupEntries[SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:1086
SDL_ECC_aggrBaseAddressTable
static SDL_ecc_aggrRegs *const SDL_ECC_aggrBaseAddressTable[SDL_ECC_BASE_ADDRESS_TOTAL_ENTRIES]
Definition: sdl_ecc_soc.h:24217
SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_groupEntries
static const SDL_GrpChkConfig_t SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_groupEntries[SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:17583
SDL_USB0_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
#define SDL_USB0_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:90
SDL_MCU_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_MemEntries
static const SDL_MemConfig_t SDL_MCU_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_MemEntries[SDL_MCU_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
Definition: sdl_ecc_soc.h:20892
SDL_MCU_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_RamIdTable
static const SDL_RAMIdEntry_t SDL_MCU_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_RamIdTable[SDL_MCU_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_NUM_RAMS]
Definition: sdl_ecc_soc.h:24130
SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_groupEntries[SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:16992
SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_ISAM62A_DM2WS_VBUSM_GASKET_MCU_0_EDC_CTRL_groupEntries
static const SDL_GrpChkConfig_t SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_ISAM62A_DM2WS_VBUSM_GASKET_MCU_0_EDC_CTRL_groupEntries[SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_ISAM62A_DM2WS_VBUSM_GASKET_MCU_0_EDC_CTRL_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:13030
SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IMSRAM32KX64E_MCU_0_CFG_P2P_BRIDGE_IMSRAM32KX64E_MCU_0_CFG_BRIDGE_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IMSRAM32KX64E_MCU_0_CFG_P2P_BRIDGE_IMSRAM32KX64E_MCU_0_CFG_BRIDGE_BUSECC_groupEntries[SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IMSRAM32KX64E_MCU_0_CFG_P2P_BRIDGE_IMSRAM32KX64E_MCU_0_CFG_BRIDGE_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:2862
SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_groupEntries[SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:8923
SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CFG_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CFG_EDC_CTRL_0_groupEntries[SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CFG_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:9700
SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_FW_CBASS_IAM62A_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM62A_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_FW_CBASS_IAM62A_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM62A_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_groupEntries[SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_FW_CBASS_IAM62A_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM62A_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:21251
SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_groupEntries[SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:2396