mcspi/v0/mcspi.h

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/*
 *  Copyright (C) 2021-22 Texas Instruments Incorporated
 *
 *  Redistribution and use in source and binary forms, with or without
 *  modification, are permitted provided that the following conditions
 *  are met:
 *
 *    Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 *
 *    Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the
 *    distribution.
 *
 *    Neither the name of Texas Instruments Incorporated nor the names of
 *    its contributors may be used to endorse or promote products derived
 *    from this software without specific prior written permission.
 *
 *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
 *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
 *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
 *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
 *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */
 
#ifndef MCSPI_H_
#define MCSPI_H_
 
/* ========================================================================== */
/*                             Include Files                                  */
/* ========================================================================== */
 
#include <stdint.h>
#include <kernel/dpl/SystemP.h>
#include <kernel/dpl/SemaphoreP.h>
#include <kernel/dpl/HwiP.h>
#include <drivers/hw_include/csl_types.h>
#include <drivers/hw_include/cslr_mcspi.h>
#include <drivers/hw_include/cslr.h>
 
#if defined (DMA_VERSION_MCSPI_UDMA)
#include <drivers/mcspi/v0/dma/udma/mcspi_dma_udma.h>
#endif
 
#if defined (DMA_VERSION_MCSPI_EDMA)
#include <drivers/mcspi/v0/dma/edma/mcspi_dma_edma.h>
#endif
 
#ifdef __cplusplus
extern "C" {
#endif
 
/* ========================================================================== */
/*                           Macros & Typedefs                                */
/* ========================================================================== */
 
#define MCSPI_MAX_TIMEOUT_VALUE       (1000000000U)
 
typedef void *MCSPI_Handle;
 
#define MCSPI_CHANNEL_0                 (0U)
#define MCSPI_CHANNEL_1                 (1U)
#define MCSPI_CHANNEL_2                 (2U)
#define MCSPI_CHANNEL_3                 (3U)
 
#define MCSPI_OPER_MODE_POLLED                 (0U)
#define MCSPI_OPER_MODE_INTERRUPT              (1U)
#define MCSPI_OPER_MODE_DMA                    (2U)
 
#define MCSPI_MAX_NUM_CHANNELS          (4U)
 
#define MCSPI_TRANSFER_COMPLETED        (0U)
#define MCSPI_TRANSFER_STARTED          (1U)
#define MCSPI_TRANSFER_CANCELLED        (2U)
#define MCSPI_TRANSFER_FAILED           (3U)
#define MCSPI_TRANSFER_CSN_DEASSERT     (4U)
#define MCSPI_TRANSFER_TIMEOUT          (5U)
 
#define MCSPI_TRANSFER_MODE_BLOCKING    (0U)
 
#define MCSPI_TRANSFER_MODE_CALLBACK    (1U)
 
#define MCSPI_MS_MODE_MASTER            (CSL_MCSPI_MODULCTRL_MS_MASTER)
 
#define MCSPI_MS_MODE_SLAVE             (CSL_MCSPI_MODULCTRL_MS_SLAVE)
 
#define MCSPI_FF_POL0_PHA0              (0U)
#define MCSPI_FF_POL0_PHA1              (1U)
#define MCSPI_FF_POL1_PHA0              (2U)
#define MCSPI_FF_POL1_PHA1              (3U)
 
#define MCSPI_CS_POL_HIGH               (CSL_MCSPI_CH0CONF_EPOL_ACTIVEHIGH)
 
#define MCSPI_CS_POL_LOW                (CSL_MCSPI_CH0CONF_EPOL_ACTIVELOW)
 
#define MCSPI_TR_MODE_TX_RX             (CSL_MCSPI_CH0CONF_TRM_TRANSRECEI)
#define MCSPI_TR_MODE_RX_ONLY           (CSL_MCSPI_CH0CONF_TRM_RECEIVONLY)
#define MCSPI_TR_MODE_TX_ONLY           (CSL_MCSPI_CH0CONF_TRM_TRANSONLY)
 
#define MCSPI_IS_D0                     (CSL_MCSPI_CH0CONF_IS_LINE0)
 
#define MCSPI_IS_D1                     (CSL_MCSPI_CH0CONF_IS_LINE1)
 
#define MCSPI_DPE_ENABLE                (CSL_MCSPI_CH0CONF_DPE0_ENABLED)
 
#define MCSPI_DPE_DISABLE               (CSL_MCSPI_CH0CONF_DPE0_DISABLED)
 
#define MCSPI_SLV_CS_SELECT_0           (CSL_MCSPI_CH0CONF_SPIENSLV_SPIEN0)
#define MCSPI_SLV_CS_SELECT_1           (CSL_MCSPI_CH0CONF_SPIENSLV_SPIEN1)
#define MCSPI_SLV_CS_SELECT_2           (CSL_MCSPI_CH0CONF_SPIENSLV_SPIEN2)
#define MCSPI_SLV_CS_SELECT_3           (CSL_MCSPI_CH0CONF_SPIENSLV_SPIEN3)
 
#define MCSPI_SB_POL_HIGH               (CSL_MCSPI_CH0CONF_SBPOL_HIGHLEVEL)
 
#define MCSPI_SB_POL_LOW                (CSL_MCSPI_CH0CONF_SBPOL_LOWLEVEL)
 
#define MCSPI_TCS0_0_CLK                (CSL_MCSPI_CH0CONF_TCS0_ZEROCYCLEDLY)
 
#define MCSPI_TCS0_1_CLK                (CSL_MCSPI_CH0CONF_TCS0_ONECYCLEDLY)
 
#define MCSPI_TCS0_2_CLK                (CSL_MCSPI_CH0CONF_TCS0_TWOCYCLEDLY)
 
#define MCSPI_TCS0_3_CLK                (CSL_MCSPI_CH0CONF_TCS0_THREECYCLEDLY)
 
#define MCSPI_CH_MODE_SINGLE            (CSL_MCSPI_MODULCTRL_SINGLE_SINGLE)
 
#define MCSPI_CH_MODE_MULTI             (CSL_MCSPI_MODULCTRL_SINGLE_MULTI)
 
#define MCSPI_PINMODE_3PIN              (CSL_MCSPI_MODULCTRL_PIN34_3PINMODE)
#define MCSPI_PINMODE_4PIN              (CSL_MCSPI_MODULCTRL_PIN34_4PINMODE)
 
#define MCSPI_INITDLY_0                 (CSL_MCSPI_MODULCTRL_INITDLY_NODELAY)
 
#define MCSPI_INITDLY_4                 (CSL_MCSPI_MODULCTRL_INITDLY_4CLKDLY)
 
#define MCSPI_INITDLY_8                 (CSL_MCSPI_MODULCTRL_INITDLY_8CLKDLY)
 
#define MCSPI_INITDLY_16                (CSL_MCSPI_MODULCTRL_INITDLY_16CLKDLY)
 
#define MCSPI_INITDLY_32                (CSL_MCSPI_MODULCTRL_INITDLY_32CLKDLY)
 
#define MCSPI_ERROR_TX_UNDERFLOW    (0x00000001U)
#define MCSPI_ERROR_RX_OVERFLOW     (0x00000002U)
 
/* ========================================================================== */
/*                         Structure Declarations                             */
/* ========================================================================== */
 
typedef struct
{
    uint32_t                channel;
    uint32_t                csDisable;
    uint32_t                dataSize;
    uint32_t                count;
    void                   *txBuf;
    void                   *rxBuf;
    void                   *args;
    uint32_t                status;
} MCSPI_Transaction;
 
typedef void (*MCSPI_CallbackFxn) (MCSPI_Handle handle,
                                   MCSPI_Transaction *transaction);
 
typedef struct
{
    uint32_t                transferMode;
    uint32_t                transferTimeout;
    MCSPI_CallbackFxn       transferCallbackFxn;
    uint32_t                msMode;
    int32_t                 mcspiDmaIndex;
} MCSPI_OpenParams;
 
typedef struct
{
    uint32_t                chNum;
    uint32_t                frameFormat;
    uint32_t                bitRate;
    uint32_t                csPolarity;
    uint32_t                trMode;
    uint32_t                inputSelect;
    uint32_t                dpe0;
    uint32_t                dpe1;
    uint32_t                slvCsSelect;
    uint32_t                startBitEnable;
    uint32_t                startBitPolarity;
    uint32_t                csIdleTime;
    uint32_t                defaultTxData;
    uint32_t                txFifoTrigLvl;
    uint32_t                rxFifoTrigLvl;
} MCSPI_ChConfig;
 
typedef struct
{
    /*
     * SOC configuration
     */
    uint32_t                baseAddr;
    uint32_t                inputClkFreq;
    /*
     * Driver configuration
     */
    uint32_t                intrNum;
    uint16_t                eventId;
    uint32_t                operMode;
    uint8_t                 intrPriority;
    /*
     * MCSPI instance configuration - common across all channels
     */
    uint32_t                chMode;
    uint32_t                pinMode;
    uint32_t                initDelay;
} MCSPI_Attrs;
 
/* ========================================================================== */
/*                  Internal/Private Structure Declarations                   */
/* ========================================================================== */
 
typedef struct
{
    /*
     * User parameters
     */
    MCSPI_ChConfig          chCfg;
    /*
     * State variables
     */
    uint32_t                isOpen;
    uint32_t                csDisable;
    uint32_t                csEnable;
    const uint8_t          *curTxBufPtr;
    uint8_t                *curRxBufPtr;
    uint32_t                curTxWords;
    uint32_t                curRxWords;
    /*
     * MCSPI derived variables
     */
    uint8_t                 bufWidthShift;
    uint32_t                dataWidthBitMask;
    uint32_t                effTxFifoDepth;
    uint32_t                effRxFifoDepth;
    uint32_t                intrMask;
    MCSPI_DmaChConfig       dmaChCfg;
    uint32_t                chConfRegVal;
    uint32_t                chCtrlRegVal;
    uint32_t                systRegVal;
} MCSPI_ChObject;
 
typedef struct
{
    /*
     * User parameters
     */
    MCSPI_Handle            handle;
    MCSPI_OpenParams        openPrms;
    uint32_t                baseAddr;
    MCSPI_ChObject          chObj[MCSPI_MAX_NUM_CHANNELS];
    uint32_t                errorFlag;
    /*
     * State variables
     */
    uint32_t                isOpen;
    void                   *transferSem;
    SemaphoreP_Object       transferSemObj;
    void                   *hwiHandle;
    HwiP_Object             hwiObj;
    MCSPI_Transaction      *currTransaction;
    void                   *mcspiDmaHandle;
} MCSPI_Object;
 
typedef struct
{
    const MCSPI_Attrs      *attrs;
    MCSPI_Object           *object;
} MCSPI_Config;
 
extern MCSPI_Config         gMcspiConfig[];
extern uint32_t             gMcspiConfigNum;
 
/* ========================================================================== */
/*                          Function Declarations                             */
/* ========================================================================== */
 
void MCSPI_init(void);
 
void MCSPI_deinit(void);
 
MCSPI_Handle MCSPI_open(uint32_t mcspiConfigIndex, const MCSPI_OpenParams *openPrms);
 
void MCSPI_close(MCSPI_Handle handle);
 
int32_t MCSPI_chConfig(MCSPI_Handle handle, const MCSPI_ChConfig *chCfg);
 
int32_t MCSPI_dmaChConfig(MCSPI_Handle handle,
                       const MCSPI_ChConfig *chCfg,
                       const MCSPI_DmaChConfig *dmaChCfg);
int32_t MCSPI_transfer(MCSPI_Handle handle, MCSPI_Transaction *transaction);
 
int32_t MCSPI_transferCancel(MCSPI_Handle handle);
 
static inline void MCSPI_OpenParams_init(MCSPI_OpenParams *openPrms);
 
static inline void MCSPI_ChConfig_init(MCSPI_ChConfig *chConfig);
 
static inline void MCSPI_Transaction_init(MCSPI_Transaction *trans);
/* ========================================================================== */
/*                       Static Function Definitions                          */
/* ========================================================================== */
 
static inline void MCSPI_OpenParams_init(MCSPI_OpenParams *openPrms)
{
    if(openPrms != NULL)
    {
        openPrms->transferMode        = MCSPI_TRANSFER_MODE_BLOCKING;
        openPrms->transferTimeout     = SystemP_WAIT_FOREVER;
        openPrms->transferCallbackFxn = NULL;
        openPrms->msMode              = MCSPI_MS_MODE_MASTER;
    }
}
 
static inline void MCSPI_ChConfig_init(MCSPI_ChConfig *chConfig)
{
    if(chConfig != NULL)
    {
        chConfig->chNum             = MCSPI_CHANNEL_0;
        chConfig->frameFormat       = MCSPI_FF_POL0_PHA0;
        chConfig->bitRate           = 1000000U;
        chConfig->csPolarity        = MCSPI_CS_POL_LOW;
        chConfig->trMode            = MCSPI_TR_MODE_TX_RX;
        chConfig->inputSelect       = MCSPI_IS_D1;
        chConfig->dpe0              = MCSPI_DPE_ENABLE;
        chConfig->dpe1              = MCSPI_DPE_DISABLE;
        chConfig->slvCsSelect       = MCSPI_SLV_CS_SELECT_0;
        chConfig->startBitEnable    = FALSE;
        chConfig->startBitPolarity  = MCSPI_SB_POL_LOW;
        chConfig->csIdleTime        = MCSPI_TCS0_0_CLK;
        chConfig->defaultTxData     = 0x00000000U;
        chConfig->txFifoTrigLvl     = 16;
        chConfig->rxFifoTrigLvl     = 16;
    }
}
 
static inline void MCSPI_Transaction_init(MCSPI_Transaction *trans)
{
    if(trans != NULL)
    {
        trans->channel   = 0U;
        trans->csDisable = TRUE;
        trans->dataSize  = 8U;
        trans->count     = 0U;
        trans->txBuf     = NULL;
        trans->rxBuf     = NULL;
        trans->args      = NULL;
        trans->status    = MCSPI_TRANSFER_COMPLETED;
    }
}
 
/* ========================================================================== */
/*                       Advanced Macros & Typedefs                           */
/* ========================================================================== */
#define MCSPI_FIFO_LENGTH           (64U)
 
#define MCSPI_RX_FIFO_ENABLE         ((uint32_t) CSL_MCSPI_CH0CONF_FFER_FFENABLED \
                                      <<                                      \
                                      CSL_MCSPI_CH0CONF_FFER_SHIFT)
 
#define MCSPI_RX_FIFO_DISABLE        ((uint32_t) CSL_MCSPI_CH0CONF_FFER_FFDISABLED \
                                      << CSL_MCSPI_CH0CONF_FFER_SHIFT)
 
#define MCSPI_TX_FIFO_ENABLE         ((uint32_t) CSL_MCSPI_CH0CONF_FFEW_FFENABLED \
                                      << CSL_MCSPI_CH0CONF_FFEW_SHIFT)
 
#define MCSPI_TX_FIFO_DISABLE        ((uint32_t) CSL_MCSPI_CH0CONF_FFEW_FFDISABLED \
                                      << CSL_MCSPI_CH0CONF_FFEW_SHIFT)
 
#define MCSPI_REG_OFFSET            (0x14U)
 
#define MCSPI_CHCONF(x)             ((uint32_t) CSL_MCSPI_CH0CONF +            \
                                     (uint32_t) ((uint32_t) MCSPI_REG_OFFSET * \
                                                 (uint32_t) (x)))
 
#define MCSPI_CHSTAT(x)             ((uint32_t) CSL_MCSPI_CH0STAT +            \
                                     (uint32_t) ((uint32_t) MCSPI_REG_OFFSET * \
                                                 (uint32_t) (x)))
 
#define MCSPI_CHCTRL(x)             ((uint32_t) CSL_MCSPI_CH0CTRL +            \
                                     (uint32_t) ((uint32_t) MCSPI_REG_OFFSET * \
                                                 (uint32_t) (x)))
 
#define MCSPI_CHTX(x)               ((uint32_t) CSL_MCSPI_TX0 +                \
                                     (uint32_t) ((uint32_t) MCSPI_REG_OFFSET * \
                                                 (uint32_t) (x)))
 
#define MCSPI_CHRX(x)               ((uint32_t) CSL_MCSPI_RX0 +                \
                                     (uint32_t) ((uint32_t) MCSPI_REG_OFFSET * \
                                                 (uint32_t) (x)))
 
#define MCSPI_CLKD_MASK             (0x0FU)
 
#define MCSPI_IRQSTATUS_CLEAR_ALL   (CSL_MCSPI_IRQSTATUS_EOW_MASK |            \
                                     CSL_MCSPI_IRQSTATUS_WKS_MASK |            \
                                     CSL_MCSPI_IRQSTATUS_RX3_FULL_MASK |       \
                                     CSL_MCSPI_IRQSTATUS_TX3_UNDERFLOW_MASK |  \
                                     CSL_MCSPI_IRQSTATUS_TX3_EMPTY_MASK |      \
                                     CSL_MCSPI_IRQSTATUS_RX2_FULL_MASK |       \
                                     CSL_MCSPI_IRQSTATUS_TX2_UNDERFLOW_MASK |  \
                                     CSL_MCSPI_IRQSTATUS_TX2_EMPTY_MASK |      \
                                     CSL_MCSPI_IRQSTATUS_RX1_FULL_MASK |       \
                                     CSL_MCSPI_IRQSTATUS_TX1_UNDERFLOW_MASK |  \
                                     CSL_MCSPI_IRQSTATUS_TX1_EMPTY_MASK |      \
                                     CSL_MCSPI_IRQSTATUS_RX0_OVERFLOW_MASK |   \
                                     CSL_MCSPI_IRQSTATUS_RX0_FULL_MASK |       \
                                     CSL_MCSPI_IRQSTATUS_TX0_UNDERFLOW_MASK |  \
                                     CSL_MCSPI_IRQSTATUS_TX0_EMPTY_MASK)
 
/* ========================================================================== */
/*                       Advanced Function Declarations                       */
/* ========================================================================== */
uint32_t MCSPI_getBaseAddr(MCSPI_Handle handle);
 
int32_t MCSPI_reConfigFifo(MCSPI_Handle handle,
                           uint32_t chNum,
                           uint32_t numWordsRxTx);
 
static inline uint32_t MCSPI_getBufWidthShift(uint32_t dataSize);
 
static inline uint32_t MCSPI_readChStatusReg(uint32_t baseAddr, uint32_t chNum);
 
static inline uint32_t MCSPI_readChCtrlReg(uint32_t baseAddr, uint32_t chNum);
 
static inline void MCSPI_writeChCtrlReg(uint32_t baseAddr, uint32_t chNum,
                       uint32_t regVal);
 
static inline uint32_t MCSPI_readChConf(uint32_t baseAddr, uint32_t chNum);
 
static inline void MCSPI_writeChConfReg(uint32_t baseAddr, uint32_t chNum,
                       uint32_t regVal);
 
static inline void MCSPI_writeTxDataReg(uint32_t baseAddr,
                       uint32_t txData,
                       uint32_t chNum);
 
static inline void MCSPI_enableTxFIFO(uint32_t baseAddr, uint32_t chNum,
                               uint32_t enableFlag);
 
static inline void MCSPI_enableRxFIFO(uint32_t baseAddr, uint32_t chNum,
                               uint32_t enableFlag);
 
static inline uint32_t MCSPI_readRxDataReg(uint32_t baseAddr,
                                           uint32_t chNum);
 
static inline void MCSPI_setDataWidth(uint32_t baseAddr, uint32_t chNum,
                                         uint32_t dataWidth);
 
/* ========================================================================== */
/*                       Advanced Function Definitions                        */
/* ========================================================================== */
static inline uint32_t MCSPI_getBufWidthShift(uint32_t dataSize)
{
    uint32_t bufWidthShift = 0U;
 
    if(dataSize <= 8U)
    {
        bufWidthShift = 0U;
    }
    else if(dataSize <= 16U)
    {
        bufWidthShift = 1U;
    }
    else
    {
        bufWidthShift = 2U;
    }
 
    return bufWidthShift;
}
 
static inline uint32_t MCSPI_readChStatusReg(uint32_t baseAddr, uint32_t chNum)
{
    /* Return the status from MCSPI_CHSTAT register. */
    return (CSL_REG32_RD(baseAddr + MCSPI_CHSTAT(chNum)));
}
 
static inline uint32_t MCSPI_readChCtrlReg(uint32_t baseAddr, uint32_t chNum)
{
    return CSL_REG32_RD(baseAddr + MCSPI_CHCTRL(chNum));
}
 
static inline void MCSPI_writeChCtrlReg(uint32_t baseAddr, uint32_t chNum,
                        uint32_t regVal)
{
    CSL_REG32_WR(baseAddr + MCSPI_CHCTRL(chNum), regVal);
}
 
static inline uint32_t MCSPI_readChConf(uint32_t baseAddr, uint32_t chNum)
{
    return CSL_REG32_RD(baseAddr + MCSPI_CHCONF(chNum));
}
 
static inline void MCSPI_writeChConfReg(uint32_t baseAddr, uint32_t chNum,
                        uint32_t regVal)
{
    CSL_REG32_WR(baseAddr + MCSPI_CHCONF(chNum), regVal);
}
 
static inline void MCSPI_writeTxDataReg(uint32_t baseAddr,
                       uint32_t txData,
                       uint32_t chNum)
{
    /* Load the MCSPI_TX register with the data to be transmitted */
    CSL_REG32_WR(baseAddr + MCSPI_CHTX(chNum), txData);
}
 
static inline void MCSPI_enableTxFIFO(uint32_t baseAddr,
                               uint32_t chNum,
                               uint32_t enableFlag)
{
    /* Set the FFEW field with user sent value. */
    CSL_REG32_FINS(
        baseAddr + MCSPI_CHCONF(chNum),
        MCSPI_CH0CONF_FFEW,
        enableFlag >> CSL_MCSPI_CH0CONF_FFEW_SHIFT);
}
 
static inline void MCSPI_enableRxFIFO(uint32_t baseAddr,
                               uint32_t chNum,
                               uint32_t enableFlag)
{
    /* Set the FFER field with the user sent value. */
    CSL_REG32_FINS(
        baseAddr + MCSPI_CHCONF(chNum),
        MCSPI_CH0CONF_FFER,
        enableFlag >> CSL_MCSPI_CH0CONF_FFER_SHIFT);
}
 
static inline uint32_t MCSPI_readRxDataReg(uint32_t baseAddr, uint32_t chNum)
{
    /* Return the data present in the MCSPI_RX register. */
    return (CSL_REG32_RD(baseAddr + MCSPI_CHRX(chNum)));
}
 
static inline void MCSPI_setDataWidth(uint32_t baseAddr, uint32_t chNum,
                                         uint32_t dataWidth)
{
    uint32_t regVal;
 
    regVal = CSL_REG32_RD(baseAddr + MCSPI_CHCONF(chNum));
    CSL_FINS(regVal, MCSPI_CH0CONF_WL, (dataWidth - 1U));
    CSL_REG32_WR(baseAddr + MCSPI_CHCONF(chNum), regVal);
}
 
/* ========================================================================== */
/*                  Internal/Private Structure Declarations                   */
/* ========================================================================== */
 
#ifdef __cplusplus
}
#endif
 
#endif /* #ifndef MCSPI_H_ */