AM62Ax MCU+ SDK  10.01.00
sdlr_pbist.h
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2  * Copyright (C) 2023 Texas Instruments Incorporated
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30  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31  *
32  * Name : sdlr_pbist.h
33 */
34 #ifndef SDLR_PBIST_H_
35 #define SDLR_PBIST_H_
36 
37 #ifdef __cplusplus
38 extern "C"
39 {
40 #endif
41 
42 #include <stdint.h>
43 
44 /**************************************************************************
45 * Hardware Region :
46 **************************************************************************/
47 
48 
49 /**************************************************************************
50 * Register Overlay Structure
51 **************************************************************************/
52 
53 typedef struct {
54  volatile uint32_t RF0L; /* Register Files / Instruction Registers */
55  volatile uint32_t RF1L; /* Register Files / Instruction Registers */
56  volatile uint32_t RF2L; /* Register Files / Instruction Registers */
57  volatile uint32_t RF3L; /* Register Files / Instruction Registers */
58  volatile uint32_t RF4L; /* Register Files / Instruction Registers */
59  volatile uint32_t RF5L; /* Register Files / Instruction Registers */
60  volatile uint32_t RF6L; /* Register Files / Instruction Registers */
61  volatile uint32_t RF7L; /* Register Files / Instruction Registers */
62  volatile uint32_t RF8L; /* Register Files / Instruction Registers */
63  volatile uint32_t RF9L; /* Register Files / Instruction Registers */
64  volatile uint32_t RF10L; /* Register Files / Instruction Registers */
65  volatile uint32_t RF11L; /* Register Files / Instruction Registers */
66  volatile uint32_t RF12L; /* Register Files / Instruction Registers */
67  volatile uint32_t RF13L; /* Register Files / Instruction Registers */
68  volatile uint32_t RF14L; /* Register Files / Instruction Registers */
69  volatile uint32_t RF15L; /* Register Files / Instruction Registers */
70  volatile uint32_t RF0U; /* Register Files / Instruction Registers */
71  volatile uint32_t RF1U; /* Register Files / Instruction Registers */
72  volatile uint32_t RF2U; /* Register Files / Instruction Registers */
73  volatile uint32_t RF3U; /* Register Files / Instruction Registers */
74  volatile uint32_t RF4U; /* Register Files / Instruction Registers */
75  volatile uint32_t RF5U; /* Register Files / Instruction Registers */
76  volatile uint32_t RF6U; /* Register Files / Instruction Registers */
77  volatile uint32_t RF7U; /* Register Files / Instruction Registers */
78  volatile uint32_t RF8U; /* Register Files / Instruction Registers */
79  volatile uint32_t RF9U; /* Register Files / Instruction Registers */
80  volatile uint32_t RF10U; /* Register Files / Instruction Registers */
81  volatile uint32_t RF11U; /* Register Files / Instruction Registers */
82  volatile uint32_t RF12U; /* Register Files / Instruction Registers */
83  volatile uint32_t RF13U; /* Register Files / Instruction Registers */
84  volatile uint32_t RF14U; /* Register Files / Instruction Registers */
85  volatile uint32_t RF15U; /* Register Files / Instruction Registers */
86  volatile uint8_t Resv_256[128];
87  volatile uint32_t A0; /* Variable Address Registers */
88  volatile uint32_t A1; /* Variable Address Registers */
89  volatile uint32_t A2; /* Variable Address Registers */
90  volatile uint32_t A3; /* Variable Address Registers */
91  volatile uint32_t L0; /* Variable Loop Count Registers */
92  volatile uint32_t L1; /* Variable Loop Count Registers */
93  volatile uint32_t L2; /* Variable Loop Count Registers */
94  volatile uint32_t L3; /* Variable Loop Count Registers */
95  volatile uint32_t D; /* Data Registers */
96  volatile uint32_t E; /* Data Registers */
97  volatile uint8_t Resv_304[8];
98  volatile uint32_t CA0; /* Constant Address Registers */
99  volatile uint32_t CA1; /* Constant Address Registers */
100  volatile uint32_t CA2; /* Constant Address Registers */
101  volatile uint32_t CA3; /* Constant Address Registers */
102  volatile uint32_t CL0; /* Constant Loop Count Registers */
103  volatile uint32_t CL1; /* Constant Loop Count Registers */
104  volatile uint32_t CL2; /* Constant Loop Count Registers */
105  volatile uint32_t CL3; /* Constant Loop Count Registers */
106  volatile uint32_t I0; /* Constant Increment Registers */
107  volatile uint32_t I1; /* Constant Increment Registers */
108  volatile uint32_t I2; /* Constant Increment Registers */
109  volatile uint32_t I3; /* Constant Increment Registers */
110  volatile uint32_t RAMT; /* RAM Configuration Register */
111  volatile uint32_t DLR; /* Datalogger Register */
112  volatile uint32_t CMS; /* Clock-Mux Select Register */
113  volatile uint32_t STR; /* Program Control Register */
114  volatile uint64_t SCR; /* Address Scrambling Register */
115  volatile uint32_t CSR; /* Chip Select Register */
116  volatile uint32_t FDLY; /* Fail Delay Register */
117  volatile uint32_t PACT; /* PACT Register */
118  volatile uint32_t PID; /* PBIST_ID Register */
119  volatile uint32_t OVER; /* Override Register */
120  volatile uint8_t Resv_400[4];
121  volatile uint64_t FSRF; /* Fail Status Fail Register */
122  volatile uint64_t FSRC; /* Fail Status Count Register */
123  volatile uint64_t FSRA; /* Fail Status Address Register */
124  volatile uint32_t FSRDL0; /* Fail Status Data Registers */
125  volatile uint8_t Resv_432[4];
126  volatile uint32_t FSRDL1; /* Fail Status Data Registers */
127  volatile uint32_t MARGIN_MODE; /* Fail Status Fail Register */
128  volatile uint32_t WRENZ; /* Fail Status Fail Register */
129  volatile uint32_t PAGE_PGS; /* Fail Status Fail Register */
130  volatile uint32_t ROM; /* ROM Mask Register */
131  volatile uint32_t ALGO; /* Algorithm Mask Register */
132  volatile uint64_t RINFO; /* RAM Info Mask Register */
133 } SDL_pbistRegs;
134 
135 
136 /**************************************************************************
137 * Register Macros
138 **************************************************************************/
139 
140 #define SDL_PBIST_RF0L (0x00000000U)
141 #define SDL_PBIST_RF1L (0x00000004U)
142 #define SDL_PBIST_RF2L (0x00000008U)
143 #define SDL_PBIST_RF3L (0x0000000CU)
144 #define SDL_PBIST_RF4L (0x00000010U)
145 #define SDL_PBIST_RF5L (0x00000014U)
146 #define SDL_PBIST_RF6L (0x00000018U)
147 #define SDL_PBIST_RF7L (0x0000001CU)
148 #define SDL_PBIST_RF8L (0x00000020U)
149 #define SDL_PBIST_RF9L (0x00000024U)
150 #define SDL_PBIST_RF10L (0x00000028U)
151 #define SDL_PBIST_RF11L (0x0000002CU)
152 #define SDL_PBIST_RF12L (0x00000030U)
153 #define SDL_PBIST_RF13L (0x00000034U)
154 #define SDL_PBIST_RF14L (0x00000038U)
155 #define SDL_PBIST_RF15L (0x0000003CU)
156 #define SDL_PBIST_RF0U (0x00000040U)
157 #define SDL_PBIST_RF1U (0x00000044U)
158 #define SDL_PBIST_RF2U (0x00000048U)
159 #define SDL_PBIST_RF3U (0x0000004CU)
160 #define SDL_PBIST_RF4U (0x00000050U)
161 #define SDL_PBIST_RF5U (0x00000054U)
162 #define SDL_PBIST_RF6U (0x00000058U)
163 #define SDL_PBIST_RF7U (0x0000005CU)
164 #define SDL_PBIST_RF8U (0x00000060U)
165 #define SDL_PBIST_RF9U (0x00000064U)
166 #define SDL_PBIST_RF10U (0x00000068U)
167 #define SDL_PBIST_RF11U (0x0000006CU)
168 #define SDL_PBIST_RF12U (0x00000070U)
169 #define SDL_PBIST_RF13U (0x00000074U)
170 #define SDL_PBIST_RF14U (0x00000078U)
171 #define SDL_PBIST_RF15U (0x0000007CU)
172 #define SDL_PBIST_A0 (0x00000100U)
173 #define SDL_PBIST_A1 (0x00000104U)
174 #define SDL_PBIST_A2 (0x00000108U)
175 #define SDL_PBIST_A3 (0x0000010CU)
176 #define SDL_PBIST_L0 (0x00000110U)
177 #define SDL_PBIST_L1 (0x00000114U)
178 #define SDL_PBIST_L2 (0x00000118U)
179 #define SDL_PBIST_L3 (0x0000011CU)
180 #define SDL_PBIST_D (0x00000120U)
181 #define SDL_PBIST_E (0x00000124U)
182 #define SDL_PBIST_CA0 (0x00000130U)
183 #define SDL_PBIST_CA1 (0x00000134U)
184 #define SDL_PBIST_CA2 (0x00000138U)
185 #define SDL_PBIST_CA3 (0x0000013CU)
186 #define SDL_PBIST_CL0 (0x00000140U)
187 #define SDL_PBIST_CL1 (0x00000144U)
188 #define SDL_PBIST_CL2 (0x00000148U)
189 #define SDL_PBIST_CL3 (0x0000014CU)
190 #define SDL_PBIST_I0 (0x00000150U)
191 #define SDL_PBIST_I1 (0x00000154U)
192 #define SDL_PBIST_I2 (0x00000158U)
193 #define SDL_PBIST_I3 (0x0000015CU)
194 #define SDL_PBIST_RAMT (0x00000160U)
195 #define SDL_PBIST_DLR (0x00000164U)
196 #define SDL_PBIST_CMS (0x00000168U)
197 #define SDL_PBIST_STR (0x0000016CU)
198 #define SDL_PBIST_SCR (0x00000170U)
199 #define SDL_PBIST_CSR (0x00000178U)
200 #define SDL_PBIST_FDLY (0x0000017CU)
201 #define SDL_PBIST_PACT (0x00000180U)
202 #define SDL_PBIST_PID (0x00000184U)
203 #define SDL_PBIST_OVER (0x00000188U)
204 #define SDL_PBIST_FSRF (0x00000190U)
205 #define SDL_PBIST_FSRC (0x00000198U)
206 #define SDL_PBIST_FSRA (0x000001A0U)
207 #define SDL_PBIST_FSRDL0 (0x000001A8U)
208 #define SDL_PBIST_FSRDL1 (0x000001B0U)
209 #define SDL_PBIST_MARGIN_MODE (0x000001B4U)
210 #define SDL_PBIST_WRENZ (0x000001B8U)
211 #define SDL_PBIST_PAGE_PGS (0x000001BCU)
212 #define SDL_PBIST_ROM (0x000001C0U)
213 #define SDL_PBIST_ALGO (0x000001C4U)
214 #define SDL_PBIST_RINFO (0x000001C8U)
215 
216 /**************************************************************************
217 * Field Definition Macros
218 **************************************************************************/
219 
220 
221 /* RF0L */
222 
223 #define SDL_PBIST_RF0L_RF0L_MASK (0xFFFFFFFFU)
224 #define SDL_PBIST_RF0L_RF0L_SHIFT (0x00000000U)
225 #define SDL_PBIST_RF0L_RF0L_MAX (0xFFFFFFFFU)
226 
227 /* RF1L */
228 
229 #define SDL_PBIST_RF1L_RF1L_MASK (0xFFFFFFFFU)
230 #define SDL_PBIST_RF1L_RF1L_SHIFT (0x00000000U)
231 #define SDL_PBIST_RF1L_RF1L_MAX (0xFFFFFFFFU)
232 
233 /* RF2L */
234 
235 #define SDL_PBIST_RF2L_RF2L_MASK (0xFFFFFFFFU)
236 #define SDL_PBIST_RF2L_RF2L_SHIFT (0x00000000U)
237 #define SDL_PBIST_RF2L_RF2L_MAX (0xFFFFFFFFU)
238 
239 /* RF3L */
240 
241 #define SDL_PBIST_RF3L_RF3L_MASK (0xFFFFFFFFU)
242 #define SDL_PBIST_RF3L_RF3L_SHIFT (0x00000000U)
243 #define SDL_PBIST_RF3L_RF3L_MAX (0xFFFFFFFFU)
244 
245 /* RF4L */
246 
247 #define SDL_PBIST_RF4L_RF4L_MASK (0xFFFFFFFFU)
248 #define SDL_PBIST_RF4L_RF4L_SHIFT (0x00000000U)
249 #define SDL_PBIST_RF4L_RF4L_MAX (0xFFFFFFFFU)
250 
251 /* RF5L */
252 
253 #define SDL_PBIST_RF5L_RF5L_MASK (0xFFFFFFFFU)
254 #define SDL_PBIST_RF5L_RF5L_SHIFT (0x00000000U)
255 #define SDL_PBIST_RF5L_RF5L_MAX (0xFFFFFFFFU)
256 
257 /* RF6L */
258 
259 #define SDL_PBIST_RF6L_RF6L_MASK (0xFFFFFFFFU)
260 #define SDL_PBIST_RF6L_RF6L_SHIFT (0x00000000U)
261 #define SDL_PBIST_RF6L_RF6L_MAX (0xFFFFFFFFU)
262 
263 /* RF7L */
264 
265 #define SDL_PBIST_RF7L_RF7L_MASK (0xFFFFFFFFU)
266 #define SDL_PBIST_RF7L_RF7L_SHIFT (0x00000000U)
267 #define SDL_PBIST_RF7L_RF7L_MAX (0xFFFFFFFFU)
268 
269 /* RF8L */
270 
271 #define SDL_PBIST_RF8L_RF8L_MASK (0xFFFFFFFFU)
272 #define SDL_PBIST_RF8L_RF8L_SHIFT (0x00000000U)
273 #define SDL_PBIST_RF8L_RF8L_MAX (0xFFFFFFFFU)
274 
275 /* RF9L */
276 
277 #define SDL_PBIST_RF9L_RF9L_MASK (0xFFFFFFFFU)
278 #define SDL_PBIST_RF9L_RF9L_SHIFT (0x00000000U)
279 #define SDL_PBIST_RF9L_RF9L_MAX (0xFFFFFFFFU)
280 
281 /* RF10L */
282 
283 #define SDL_PBIST_RF10L_RF10L_MASK (0xFFFFFFFFU)
284 #define SDL_PBIST_RF10L_RF10L_SHIFT (0x00000000U)
285 #define SDL_PBIST_RF10L_RF10L_MAX (0xFFFFFFFFU)
286 
287 /* RF11L */
288 
289 #define SDL_PBIST_RF11L_RF11L_MASK (0xFFFFFFFFU)
290 #define SDL_PBIST_RF11L_RF11L_SHIFT (0x00000000U)
291 #define SDL_PBIST_RF11L_RF11L_MAX (0xFFFFFFFFU)
292 
293 /* RF12L */
294 
295 #define SDL_PBIST_RF12L_RF12L_MASK (0xFFFFFFFFU)
296 #define SDL_PBIST_RF12L_RF12L_SHIFT (0x00000000U)
297 #define SDL_PBIST_RF12L_RF12L_MAX (0xFFFFFFFFU)
298 
299 /* RF13L */
300 
301 #define SDL_PBIST_RF13L_RF13L_MASK (0xFFFFFFFFU)
302 #define SDL_PBIST_RF13L_RF13L_SHIFT (0x00000000U)
303 #define SDL_PBIST_RF13L_RF13L_MAX (0xFFFFFFFFU)
304 
305 /* RF14L */
306 
307 #define SDL_PBIST_RF14L_RF14L_MASK (0xFFFFFFFFU)
308 #define SDL_PBIST_RF14L_RF14L_SHIFT (0x00000000U)
309 #define SDL_PBIST_RF14L_RF14L_MAX (0xFFFFFFFFU)
310 
311 /* RF15L */
312 
313 #define SDL_PBIST_RF15L_RF15L_MASK (0xFFFFFFFFU)
314 #define SDL_PBIST_RF15L_RF15L_SHIFT (0x00000000U)
315 #define SDL_PBIST_RF15L_RF15L_MAX (0xFFFFFFFFU)
316 
317 /* RF0U */
318 
319 #define SDL_PBIST_RF0U_RF0U_MASK (0xFFFFFFFFU)
320 #define SDL_PBIST_RF0U_RF0U_SHIFT (0x00000000U)
321 #define SDL_PBIST_RF0U_RF0U_MAX (0xFFFFFFFFU)
322 
323 /* RF1U */
324 
325 #define SDL_PBIST_RF1U_RF1U_MASK (0xFFFFFFFFU)
326 #define SDL_PBIST_RF1U_RF1U_SHIFT (0x00000000U)
327 #define SDL_PBIST_RF1U_RF1U_MAX (0xFFFFFFFFU)
328 
329 /* RF2U */
330 
331 #define SDL_PBIST_RF2U_RF2U_MASK (0xFFFFFFFFU)
332 #define SDL_PBIST_RF2U_RF2U_SHIFT (0x00000000U)
333 #define SDL_PBIST_RF2U_RF2U_MAX (0xFFFFFFFFU)
334 
335 /* RF3U */
336 
337 #define SDL_PBIST_RF3U_RF3U_MASK (0xFFFFFFFFU)
338 #define SDL_PBIST_RF3U_RF3U_SHIFT (0x00000000U)
339 #define SDL_PBIST_RF3U_RF3U_MAX (0xFFFFFFFFU)
340 
341 /* RF4U */
342 
343 #define SDL_PBIST_RF4U_RF4U_MASK (0xFFFFFFFFU)
344 #define SDL_PBIST_RF4U_RF4U_SHIFT (0x00000000U)
345 #define SDL_PBIST_RF4U_RF4U_MAX (0xFFFFFFFFU)
346 
347 /* RF5U */
348 
349 #define SDL_PBIST_RF5U_RF5U_MASK (0xFFFFFFFFU)
350 #define SDL_PBIST_RF5U_RF5U_SHIFT (0x00000000U)
351 #define SDL_PBIST_RF5U_RF5U_MAX (0xFFFFFFFFU)
352 
353 /* RF6U */
354 
355 #define SDL_PBIST_RF6U_RF6U_MASK (0xFFFFFFFFU)
356 #define SDL_PBIST_RF6U_RF6U_SHIFT (0x00000000U)
357 #define SDL_PBIST_RF6U_RF6U_MAX (0xFFFFFFFFU)
358 
359 /* RF7U */
360 
361 #define SDL_PBIST_RF7U_RF7U_MASK (0xFFFFFFFFU)
362 #define SDL_PBIST_RF7U_RF7U_SHIFT (0x00000000U)
363 #define SDL_PBIST_RF7U_RF7U_MAX (0xFFFFFFFFU)
364 
365 /* RF8U */
366 
367 #define SDL_PBIST_RF8U_RF8U_MASK (0xFFFFFFFFU)
368 #define SDL_PBIST_RF8U_RF8U_SHIFT (0x00000000U)
369 #define SDL_PBIST_RF8U_RF8U_MAX (0xFFFFFFFFU)
370 
371 /* RF9U */
372 
373 #define SDL_PBIST_RF9U_RF9U_MASK (0xFFFFFFFFU)
374 #define SDL_PBIST_RF9U_RF9U_SHIFT (0x00000000U)
375 #define SDL_PBIST_RF9U_RF9U_MAX (0xFFFFFFFFU)
376 
377 /* RF10U */
378 
379 #define SDL_PBIST_RF10U_RF10U_MASK (0xFFFFFFFFU)
380 #define SDL_PBIST_RF10U_RF10U_SHIFT (0x00000000U)
381 #define SDL_PBIST_RF10U_RF10U_MAX (0xFFFFFFFFU)
382 
383 /* RF11U */
384 
385 #define SDL_PBIST_RF11U_RF11U_MASK (0xFFFFFFFFU)
386 #define SDL_PBIST_RF11U_RF11U_SHIFT (0x00000000U)
387 #define SDL_PBIST_RF11U_RF11U_MAX (0xFFFFFFFFU)
388 
389 /* RF12U */
390 
391 #define SDL_PBIST_RF12U_RF12U_MASK (0xFFFFFFFFU)
392 #define SDL_PBIST_RF12U_RF12U_SHIFT (0x00000000U)
393 #define SDL_PBIST_RF12U_RF12U_MAX (0xFFFFFFFFU)
394 
395 /* RF13U */
396 
397 #define SDL_PBIST_RF13U_RF13U_MASK (0xFFFFFFFFU)
398 #define SDL_PBIST_RF13U_RF13U_SHIFT (0x00000000U)
399 #define SDL_PBIST_RF13U_RF13U_MAX (0xFFFFFFFFU)
400 
401 /* RF14U */
402 
403 #define SDL_PBIST_RF14U_RF14U_MASK (0xFFFFFFFFU)
404 #define SDL_PBIST_RF14U_RF14U_SHIFT (0x00000000U)
405 #define SDL_PBIST_RF14U_RF14U_MAX (0xFFFFFFFFU)
406 
407 /* RF15U */
408 
409 #define SDL_PBIST_RF15U_RF15U_MASK (0xFFFFFFFFU)
410 #define SDL_PBIST_RF15U_RF15U_SHIFT (0x00000000U)
411 #define SDL_PBIST_RF15U_RF15U_MAX (0xFFFFFFFFU)
412 
413 /* A0 */
414 
415 #define SDL_PBIST_A0_A0_MASK (0x0000FFFFU)
416 #define SDL_PBIST_A0_A0_SHIFT (0x00000000U)
417 #define SDL_PBIST_A0_A0_MAX (0x0000FFFFU)
418 
419 /* A1 */
420 
421 #define SDL_PBIST_A1_A1_MASK (0x0000FFFFU)
422 #define SDL_PBIST_A1_A1_SHIFT (0x00000000U)
423 #define SDL_PBIST_A1_A1_MAX (0x0000FFFFU)
424 
425 /* A2 */
426 
427 #define SDL_PBIST_A2_A2_MASK (0x0000FFFFU)
428 #define SDL_PBIST_A2_A2_SHIFT (0x00000000U)
429 #define SDL_PBIST_A2_A2_MAX (0x0000FFFFU)
430 
431 /* A3 */
432 
433 #define SDL_PBIST_A3_A3_MASK (0x0000FFFFU)
434 #define SDL_PBIST_A3_A3_SHIFT (0x00000000U)
435 #define SDL_PBIST_A3_A3_MAX (0x0000FFFFU)
436 
437 /* L0 */
438 
439 #define SDL_PBIST_L0_L0_MASK (0x0000FFFFU)
440 #define SDL_PBIST_L0_L0_SHIFT (0x00000000U)
441 #define SDL_PBIST_L0_L0_MAX (0x0000FFFFU)
442 
443 /* L1 */
444 
445 #define SDL_PBIST_L1_L1_MASK (0x0000FFFFU)
446 #define SDL_PBIST_L1_L1_SHIFT (0x00000000U)
447 #define SDL_PBIST_L1_L1_MAX (0x0000FFFFU)
448 
449 /* L2 */
450 
451 #define SDL_PBIST_L2_L2_MASK (0x0000FFFFU)
452 #define SDL_PBIST_L2_L2_SHIFT (0x00000000U)
453 #define SDL_PBIST_L2_L2_MAX (0x0000FFFFU)
454 
455 /* L3 */
456 
457 #define SDL_PBIST_L3_L3_MASK (0x0000FFFFU)
458 #define SDL_PBIST_L3_L3_SHIFT (0x00000000U)
459 #define SDL_PBIST_L3_L3_MAX (0x0000FFFFU)
460 
461 /* D */
462 
463 #define SDL_PBIST_D_D0_MASK (0x0000FFFFU)
464 #define SDL_PBIST_D_D0_SHIFT (0x00000000U)
465 #define SDL_PBIST_D_D0_MAX (0x0000FFFFU)
466 
467 #define SDL_PBIST_D_D1_MASK (0xFFFF0000U)
468 #define SDL_PBIST_D_D1_SHIFT (0x00000010U)
469 #define SDL_PBIST_D_D1_MAX (0x0000FFFFU)
470 
471 /* E */
472 
473 #define SDL_PBIST_E_E0_MASK (0x0000FFFFU)
474 #define SDL_PBIST_E_E0_SHIFT (0x00000000U)
475 #define SDL_PBIST_E_E0_MAX (0x0000FFFFU)
476 
477 #define SDL_PBIST_E_E1_MASK (0xFFFF0000U)
478 #define SDL_PBIST_E_E1_SHIFT (0x00000010U)
479 #define SDL_PBIST_E_E1_MAX (0x0000FFFFU)
480 
481 /* CA0 */
482 
483 #define SDL_PBIST_CA0_CA0_MASK (0x0000FFFFU)
484 #define SDL_PBIST_CA0_CA0_SHIFT (0x00000000U)
485 #define SDL_PBIST_CA0_CA0_MAX (0x0000FFFFU)
486 
487 /* CA1 */
488 
489 #define SDL_PBIST_CA1_CA1_MASK (0x0000FFFFU)
490 #define SDL_PBIST_CA1_CA1_SHIFT (0x00000000U)
491 #define SDL_PBIST_CA1_CA1_MAX (0x0000FFFFU)
492 
493 /* CA2 */
494 
495 #define SDL_PBIST_CA2_CA2_MASK (0x0000FFFFU)
496 #define SDL_PBIST_CA2_CA2_SHIFT (0x00000000U)
497 #define SDL_PBIST_CA2_CA2_MAX (0x0000FFFFU)
498 
499 /* CA3 */
500 
501 #define SDL_PBIST_CA3_CA3_MASK (0x0000FFFFU)
502 #define SDL_PBIST_CA3_CA3_SHIFT (0x00000000U)
503 #define SDL_PBIST_CA3_CA3_MAX (0x0000FFFFU)
504 
505 /* CL0 */
506 
507 #define SDL_PBIST_CL0_CL0_MASK (0x0000FFFFU)
508 #define SDL_PBIST_CL0_CL0_SHIFT (0x00000000U)
509 #define SDL_PBIST_CL0_CL0_MAX (0x0000FFFFU)
510 
511 /* CL1 */
512 
513 #define SDL_PBIST_CL1_CL1_MASK (0x0000FFFFU)
514 #define SDL_PBIST_CL1_CL1_SHIFT (0x00000000U)
515 #define SDL_PBIST_CL1_CL1_MAX (0x0000FFFFU)
516 
517 /* CL2 */
518 
519 #define SDL_PBIST_CL2_CL2_MASK (0x0000FFFFU)
520 #define SDL_PBIST_CL2_CL2_SHIFT (0x00000000U)
521 #define SDL_PBIST_CL2_CL2_MAX (0x0000FFFFU)
522 
523 /* CL3 */
524 
525 #define SDL_PBIST_CL3_CL3_MASK (0x0000FFFFU)
526 #define SDL_PBIST_CL3_CL3_SHIFT (0x00000000U)
527 #define SDL_PBIST_CL3_CL3_MAX (0x0000FFFFU)
528 
529 /* I0 */
530 
531 #define SDL_PBIST_I0_I0_MASK (0x0000FFFFU)
532 #define SDL_PBIST_I0_I0_SHIFT (0x00000000U)
533 #define SDL_PBIST_I0_I0_MAX (0x0000FFFFU)
534 
535 /* I1 */
536 
537 #define SDL_PBIST_I1_I0_MASK (0x0000FFFFU)
538 #define SDL_PBIST_I1_I0_SHIFT (0x00000000U)
539 #define SDL_PBIST_I1_I0_MAX (0x0000FFFFU)
540 
541 /* I2 */
542 
543 #define SDL_PBIST_I2_I0_MASK (0x0000FFFFU)
544 #define SDL_PBIST_I2_I0_SHIFT (0x00000000U)
545 #define SDL_PBIST_I2_I0_MAX (0x0000FFFFU)
546 
547 /* I3 */
548 
549 #define SDL_PBIST_I3_I0_MASK (0x0000FFFFU)
550 #define SDL_PBIST_I3_I0_SHIFT (0x00000000U)
551 #define SDL_PBIST_I3_I0_MAX (0x0000FFFFU)
552 
553 /* RAMT */
554 
555 #define SDL_PBIST_RAMT_RLS_MASK (0x00000003U)
556 #define SDL_PBIST_RAMT_RLS_SHIFT (0x00000000U)
557 #define SDL_PBIST_RAMT_RLS_MAX (0x00000003U)
558 
559 #define SDL_PBIST_RAMT_PLS_MASK (0x0000003CU)
560 #define SDL_PBIST_RAMT_PLS_SHIFT (0x00000002U)
561 #define SDL_PBIST_RAMT_PLS_MAX (0x0000000FU)
562 
563 #define SDL_PBIST_RAMT_DWR_MASK (0x0000FF00U)
564 #define SDL_PBIST_RAMT_DWR_SHIFT (0x00000008U)
565 #define SDL_PBIST_RAMT_DWR_MAX (0x000000FFU)
566 
567 #define SDL_PBIST_RAMT_RDS_MASK (0x00FF0000U)
568 #define SDL_PBIST_RAMT_RDS_SHIFT (0x00000010U)
569 #define SDL_PBIST_RAMT_RDS_MAX (0x000000FFU)
570 
571 #define SDL_PBIST_RAMT_RGS_MASK (0xFF000000U)
572 #define SDL_PBIST_RAMT_RGS_SHIFT (0x00000018U)
573 #define SDL_PBIST_RAMT_RGS_MAX (0x000000FFU)
574 
575 /* DLR */
576 
577 #define SDL_PBIST_DLR_DLR0_DCM_MASK (0x00000001U)
578 #define SDL_PBIST_DLR_DLR0_DCM_SHIFT (0x00000000U)
579 #define SDL_PBIST_DLR_DLR0_DCM_MAX (0x00000001U)
580 
581 #define SDL_PBIST_DLR_DLR0_IDDQ_MASK (0x00000002U)
582 #define SDL_PBIST_DLR_DLR0_IDDQ_SHIFT (0x00000001U)
583 #define SDL_PBIST_DLR_DLR0_IDDQ_MAX (0x00000001U)
584 
585 #define SDL_PBIST_DLR_DLR0_ROM_MASK (0x00000004U)
586 #define SDL_PBIST_DLR_DLR0_ROM_SHIFT (0x00000002U)
587 #define SDL_PBIST_DLR_DLR0_ROM_MAX (0x00000001U)
588 
589 #define SDL_PBIST_DLR_DLR0_TCK_MASK (0x00000008U)
590 #define SDL_PBIST_DLR_DLR0_TCK_SHIFT (0x00000003U)
591 #define SDL_PBIST_DLR_DLR0_TCK_MAX (0x00000001U)
592 
593 #define SDL_PBIST_DLR_DLR0_CAM_MASK (0x00000010U)
594 #define SDL_PBIST_DLR_DLR0_CAM_SHIFT (0x00000004U)
595 #define SDL_PBIST_DLR_DLR0_CAM_MAX (0x00000001U)
596 
597 #define SDL_PBIST_DLR_DLR0_ECAM_MASK (0x00000020U)
598 #define SDL_PBIST_DLR_DLR0_ECAM_SHIFT (0x00000005U)
599 #define SDL_PBIST_DLR_DLR0_ECAM_MAX (0x00000001U)
600 
601 #define SDL_PBIST_DLR_DLR0_CFMM_MASK (0x00000040U)
602 #define SDL_PBIST_DLR_DLR0_CFMM_SHIFT (0x00000006U)
603 #define SDL_PBIST_DLR_DLR0_CFMM_MAX (0x00000001U)
604 
605 #define SDL_PBIST_DLR_DLR0_TSM_MASK (0x00000080U)
606 #define SDL_PBIST_DLR_DLR0_TSM_SHIFT (0x00000007U)
607 #define SDL_PBIST_DLR_DLR0_TSM_MAX (0x00000001U)
608 
609 #define SDL_PBIST_DLR_DLR1_MISR_MASK (0x00000100U)
610 #define SDL_PBIST_DLR_DLR1_MISR_SHIFT (0x00000008U)
611 #define SDL_PBIST_DLR_DLR1_MISR_MAX (0x00000001U)
612 
613 #define SDL_PBIST_DLR_DLR1_GNG_MASK (0x00000200U)
614 #define SDL_PBIST_DLR_DLR1_GNG_SHIFT (0x00000009U)
615 #define SDL_PBIST_DLR_DLR1_GNG_MAX (0x00000001U)
616 
617 #define SDL_PBIST_DLR_DLR1_RTM_MASK (0x00000400U)
618 #define SDL_PBIST_DLR_DLR1_RTM_SHIFT (0x0000000AU)
619 #define SDL_PBIST_DLR_DLR1_RTM_MAX (0x00000001U)
620 
621 #define SDL_PBIST_DLR_BRP_MASK (0x00FF0000U)
622 #define SDL_PBIST_DLR_BRP_SHIFT (0x00000010U)
623 #define SDL_PBIST_DLR_BRP_MAX (0x000000FFU)
624 
625 /* CMS */
626 
627 #define SDL_PBIST_CMS_CMS_MASK (0x0000000FU)
628 #define SDL_PBIST_CMS_CMS_SHIFT (0x00000000U)
629 #define SDL_PBIST_CMS_CMS_MAX (0x0000000FU)
630 
631 /* STR */
632 
633 #define SDL_PBIST_STR_START_MASK (0x00000001U)
634 #define SDL_PBIST_STR_START_SHIFT (0x00000000U)
635 #define SDL_PBIST_STR_START_MAX (0x00000001U)
636 
637 #define SDL_PBIST_STR_RES_MASK (0x00000002U)
638 #define SDL_PBIST_STR_RES_SHIFT (0x00000001U)
639 #define SDL_PBIST_STR_RES_MAX (0x00000001U)
640 
641 #define SDL_PBIST_STR_STOP_MASK (0x00000004U)
642 #define SDL_PBIST_STR_STOP_SHIFT (0x00000002U)
643 #define SDL_PBIST_STR_STOP_MAX (0x00000001U)
644 
645 #define SDL_PBIST_STR_STEP_MASK (0x00000008U)
646 #define SDL_PBIST_STR_STEP_SHIFT (0x00000003U)
647 #define SDL_PBIST_STR_STEP_MAX (0x00000001U)
648 
649 #define SDL_PBIST_STR_CHK_MASK (0x00000010U)
650 #define SDL_PBIST_STR_CHK_SHIFT (0x00000004U)
651 #define SDL_PBIST_STR_CHK_MAX (0x00000001U)
652 
653 /* SCR */
654 
655 #define SDL_PBIST_SCR_SCR0_MASK (0x00000000000000FFU)
656 #define SDL_PBIST_SCR_SCR0_SHIFT (0x0000000000000000U)
657 #define SDL_PBIST_SCR_SCR0_MAX (0x00000000000000FFU)
658 
659 #define SDL_PBIST_SCR_SCR1_MASK (0x000000000000FF00U)
660 #define SDL_PBIST_SCR_SCR1_SHIFT (0x0000000000000008U)
661 #define SDL_PBIST_SCR_SCR1_MAX (0x00000000000000FFU)
662 
663 #define SDL_PBIST_SCR_SCR2_MASK (0x0000000000FF0000U)
664 #define SDL_PBIST_SCR_SCR2_SHIFT (0x0000000000000010U)
665 #define SDL_PBIST_SCR_SCR2_MAX (0x00000000000000FFU)
666 
667 #define SDL_PBIST_SCR_SCR3_MASK (0x00000000FF000000U)
668 #define SDL_PBIST_SCR_SCR3_SHIFT (0x0000000000000018U)
669 #define SDL_PBIST_SCR_SCR3_MAX (0x00000000000000FFU)
670 
671 #define SDL_PBIST_SCR_SCR4_MASK (0x000000FF00000000U)
672 #define SDL_PBIST_SCR_SCR4_SHIFT (0x0000000000000020U)
673 #define SDL_PBIST_SCR_SCR4_MAX (0x00000000000000FFU)
674 
675 #define SDL_PBIST_SCR_SCR5_MASK (0x0000FF0000000000U)
676 #define SDL_PBIST_SCR_SCR5_SHIFT (0x0000000000000028U)
677 #define SDL_PBIST_SCR_SCR5_MAX (0x00000000000000FFU)
678 
679 #define SDL_PBIST_SCR_SCR6_MASK (0x00FF000000000000U)
680 #define SDL_PBIST_SCR_SCR6_SHIFT (0x0000000000000030U)
681 #define SDL_PBIST_SCR_SCR6_MAX (0x00000000000000FFU)
682 
683 #define SDL_PBIST_SCR_SCR7_MASK (0xFF00000000000000U)
684 #define SDL_PBIST_SCR_SCR7_SHIFT (0x0000000000000038U)
685 #define SDL_PBIST_SCR_SCR7_MAX (0x00000000000000FFU)
686 
687 /* CSR */
688 
689 #define SDL_PBIST_CSR_CSR0_MASK (0x000000FFU)
690 #define SDL_PBIST_CSR_CSR0_SHIFT (0x00000000U)
691 #define SDL_PBIST_CSR_CSR0_MAX (0x000000FFU)
692 
693 #define SDL_PBIST_CSR_CSR1_MASK (0x0000FF00U)
694 #define SDL_PBIST_CSR_CSR1_SHIFT (0x00000008U)
695 #define SDL_PBIST_CSR_CSR1_MAX (0x000000FFU)
696 
697 #define SDL_PBIST_CSR_CSR2_MASK (0x00FF0000U)
698 #define SDL_PBIST_CSR_CSR2_SHIFT (0x00000010U)
699 #define SDL_PBIST_CSR_CSR2_MAX (0x000000FFU)
700 
701 #define SDL_PBIST_CSR_CSR3_MASK (0xFF000000U)
702 #define SDL_PBIST_CSR_CSR3_SHIFT (0x00000018U)
703 #define SDL_PBIST_CSR_CSR3_MAX (0x000000FFU)
704 
705 /* FDLY */
706 
707 #define SDL_PBIST_FDLY_FDLY_MASK (0x000000FFU)
708 #define SDL_PBIST_FDLY_FDLY_SHIFT (0x00000000U)
709 #define SDL_PBIST_FDLY_FDLY_MAX (0x000000FFU)
710 
711 /* PACT */
712 
713 #define SDL_PBIST_PACT_PACT_MASK (0x00000001U)
714 #define SDL_PBIST_PACT_PACT_SHIFT (0x00000000U)
715 #define SDL_PBIST_PACT_PACT_MAX (0x00000001U)
716 
717 /* PID */
718 
719 #define SDL_PBIST_PID_PID_MASK (0x0000001FU)
720 #define SDL_PBIST_PID_PID_SHIFT (0x00000000U)
721 #define SDL_PBIST_PID_PID_MAX (0x0000001FU)
722 
723 /* OVER */
724 
725 #define SDL_PBIST_OVER_RINFO_MASK (0x00000001U)
726 #define SDL_PBIST_OVER_RINFO_SHIFT (0x00000000U)
727 #define SDL_PBIST_OVER_RINFO_MAX (0x00000001U)
728 
729 #define SDL_PBIST_OVER_READ_MASK (0x00000002U)
730 #define SDL_PBIST_OVER_READ_SHIFT (0x00000001U)
731 #define SDL_PBIST_OVER_READ_MAX (0x00000001U)
732 
733 #define SDL_PBIST_OVER_MM_MASK (0x00000004U)
734 #define SDL_PBIST_OVER_MM_SHIFT (0x00000002U)
735 #define SDL_PBIST_OVER_MM_MAX (0x00000001U)
736 
737 #define SDL_PBIST_OVER_ALGO_MASK (0x00000008U)
738 #define SDL_PBIST_OVER_ALGO_SHIFT (0x00000003U)
739 #define SDL_PBIST_OVER_ALGO_MAX (0x00000001U)
740 
741 /* FSRF */
742 
743 #define SDL_PBIST_FSRF_FRSF0_MASK (0x0000000000000001U)
744 #define SDL_PBIST_FSRF_FRSF0_SHIFT (0x0000000000000000U)
745 #define SDL_PBIST_FSRF_FRSF0_MAX (0x0000000000000001U)
746 
747 #define SDL_PBIST_FSRF_FRSF1_MASK (0x0000000100000000U)
748 #define SDL_PBIST_FSRF_FRSF1_SHIFT (0x0000000000000020U)
749 #define SDL_PBIST_FSRF_FRSF1_MAX (0x0000000000000001U)
750 
751 /* FSRC */
752 
753 #define SDL_PBIST_FSRC_FSRC0_MASK (0x000000000000000FU)
754 #define SDL_PBIST_FSRC_FSRC0_SHIFT (0x0000000000000000U)
755 #define SDL_PBIST_FSRC_FSRC0_MAX (0x000000000000000FU)
756 
757 #define SDL_PBIST_FSRC_FSRC1_MASK (0x0000000F00000000U)
758 #define SDL_PBIST_FSRC_FSRC1_SHIFT (0x0000000000000020U)
759 #define SDL_PBIST_FSRC_FSRC1_MAX (0x000000000000000FU)
760 
761 /* FSRA */
762 
763 #define SDL_PBIST_FSRA_FSRA0_MASK (0x000000000000FFFFU)
764 #define SDL_PBIST_FSRA_FSRA0_SHIFT (0x0000000000000000U)
765 #define SDL_PBIST_FSRA_FSRA0_MAX (0x000000000000FFFFU)
766 
767 #define SDL_PBIST_FSRA_FSRA1_MASK (0x0000FFFF00000000U)
768 #define SDL_PBIST_FSRA_FSRA1_SHIFT (0x0000000000000020U)
769 #define SDL_PBIST_FSRA_FSRA1_MAX (0x000000000000FFFFU)
770 
771 /* FSRDL0 */
772 
773 #define SDL_PBIST_FSRDL0_FSRDL0_MASK (0xFFFFFFFFU)
774 #define SDL_PBIST_FSRDL0_FSRDL0_SHIFT (0x00000000U)
775 #define SDL_PBIST_FSRDL0_FSRDL0_MAX (0xFFFFFFFFU)
776 
777 /* FSRDL1 */
778 
779 #define SDL_PBIST_FSRDL1_FSRDL1_MASK (0xFFFFFFFFU)
780 #define SDL_PBIST_FSRDL1_FSRDL1_SHIFT (0x00000000U)
781 #define SDL_PBIST_FSRDL1_FSRDL1_MAX (0xFFFFFFFFU)
782 
783 /* MARGIN_MODE */
784 
785 #define SDL_PBIST_MARGIN_MODE_PBIST_DFT_WRITE_MASK (0x00000003U)
786 #define SDL_PBIST_MARGIN_MODE_PBIST_DFT_WRITE_SHIFT (0x00000000U)
787 #define SDL_PBIST_MARGIN_MODE_PBIST_DFT_WRITE_MAX (0x00000003U)
788 
789 #define SDL_PBIST_MARGIN_MODE_PBIST_DFT_READ_MASK (0x0000000CU)
790 #define SDL_PBIST_MARGIN_MODE_PBIST_DFT_READ_SHIFT (0x00000002U)
791 #define SDL_PBIST_MARGIN_MODE_PBIST_DFT_READ_MAX (0x00000003U)
792 
793 /* WRENZ */
794 
795 #define SDL_PBIST_WRENZ_WRENZ_MASK (0x00000003U)
796 #define SDL_PBIST_WRENZ_WRENZ_SHIFT (0x00000000U)
797 #define SDL_PBIST_WRENZ_WRENZ_MAX (0x00000003U)
798 
799 /* PAGE_PGS */
800 
801 #define SDL_PBIST_PAGE_PGS_PGS_MASK (0x00000003U)
802 #define SDL_PBIST_PAGE_PGS_PGS_SHIFT (0x00000000U)
803 #define SDL_PBIST_PAGE_PGS_PGS_MAX (0x00000003U)
804 
805 /* ROM */
806 
807 #define SDL_PBIST_ROM_ROM_MASK (0x00000003U)
808 #define SDL_PBIST_ROM_ROM_SHIFT (0x00000000U)
809 #define SDL_PBIST_ROM_ROM_MAX (0x00000003U)
810 
811 /* ALGO */
812 
813 #define SDL_PBIST_ALGO_ALGO_0_MASK (0x000000FFU)
814 #define SDL_PBIST_ALGO_ALGO_0_SHIFT (0x00000000U)
815 #define SDL_PBIST_ALGO_ALGO_0_MAX (0x000000FFU)
816 
817 #define SDL_PBIST_ALGO_ALGO_1_MASK (0x0000FF00U)
818 #define SDL_PBIST_ALGO_ALGO_1_SHIFT (0x00000008U)
819 #define SDL_PBIST_ALGO_ALGO_1_MAX (0x000000FFU)
820 
821 #define SDL_PBIST_ALGO_ALGO_2_MASK (0x00FF0000U)
822 #define SDL_PBIST_ALGO_ALGO_2_SHIFT (0x00000010U)
823 #define SDL_PBIST_ALGO_ALGO_2_MAX (0x000000FFU)
824 
825 #define SDL_PBIST_ALGO_ALGO_3_MASK (0xFF000000U)
826 #define SDL_PBIST_ALGO_ALGO_3_SHIFT (0x00000018U)
827 #define SDL_PBIST_ALGO_ALGO_3_MAX (0x000000FFU)
828 
829 /* RINFO */
830 
831 #define SDL_PBIST_RINFO_L0_MASK (0x00000000000000FFU)
832 #define SDL_PBIST_RINFO_L0_SHIFT (0x0000000000000000U)
833 #define SDL_PBIST_RINFO_L0_MAX (0x00000000000000FFU)
834 
835 #define SDL_PBIST_RINFO_L1_MASK (0x000000000000FF00U)
836 #define SDL_PBIST_RINFO_L1_SHIFT (0x0000000000000008U)
837 #define SDL_PBIST_RINFO_L1_MAX (0x00000000000000FFU)
838 
839 #define SDL_PBIST_RINFO_L2_MASK (0x0000000000FF0000U)
840 #define SDL_PBIST_RINFO_L2_SHIFT (0x0000000000000010U)
841 #define SDL_PBIST_RINFO_L2_MAX (0x00000000000000FFU)
842 
843 #define SDL_PBIST_RINFO_L3_MASK (0x00000000FF000000U)
844 #define SDL_PBIST_RINFO_L3_SHIFT (0x0000000000000018U)
845 #define SDL_PBIST_RINFO_L3_MAX (0x00000000000000FFU)
846 
847 #define SDL_PBIST_RINFO_U0_MASK (0x000000FF00000000U)
848 #define SDL_PBIST_RINFO_U0_SHIFT (0x0000000000000020U)
849 #define SDL_PBIST_RINFO_U0_MAX (0x00000000000000FFU)
850 
851 #define SDL_PBIST_RINFO_U1_MASK (0x0000FF0000000000U)
852 #define SDL_PBIST_RINFO_U1_SHIFT (0x0000000000000028U)
853 #define SDL_PBIST_RINFO_U1_MAX (0x00000000000000FFU)
854 
855 #define SDL_PBIST_RINFO_U2_MASK (0x00FF000000000000U)
856 #define SDL_PBIST_RINFO_U2_SHIFT (0x0000000000000030U)
857 #define SDL_PBIST_RINFO_U2_MAX (0x00000000000000FFU)
858 
859 #define SDL_PBIST_RINFO_U3_MASK (0xFF00000000000000U)
860 #define SDL_PBIST_RINFO_U3_SHIFT (0x0000000000000038U)
861 #define SDL_PBIST_RINFO_U3_MAX (0x00000000000000FFU)
862 
863 #ifdef __cplusplus
864 }
865 #endif
866 #endif
SDL_pbistRegs::RF5U
volatile uint32_t RF5U
Definition: sdlr_pbist.h:75
SDL_pbistRegs::PACT
volatile uint32_t PACT
Definition: sdlr_pbist.h:117
SDL_pbistRegs::FSRF
volatile uint64_t FSRF
Definition: sdlr_pbist.h:121
SDL_pbistRegs
Definition: sdlr_pbist.h:53
SDL_pbistRegs::I0
volatile uint32_t I0
Definition: sdlr_pbist.h:106
SDL_pbistRegs::PAGE_PGS
volatile uint32_t PAGE_PGS
Definition: sdlr_pbist.h:129
SDL_pbistRegs::RF1U
volatile uint32_t RF1U
Definition: sdlr_pbist.h:71
SDL_pbistRegs::FSRC
volatile uint64_t FSRC
Definition: sdlr_pbist.h:122
SDL_pbistRegs::A2
volatile uint32_t A2
Definition: sdlr_pbist.h:89
SDL_pbistRegs::RF12U
volatile uint32_t RF12U
Definition: sdlr_pbist.h:82
SDL_pbistRegs::CA3
volatile uint32_t CA3
Definition: sdlr_pbist.h:101
SDL_pbistRegs::I3
volatile uint32_t I3
Definition: sdlr_pbist.h:109
SDL_pbistRegs::ALGO
volatile uint32_t ALGO
Definition: sdlr_pbist.h:131
SDL_pbistRegs::DLR
volatile uint32_t DLR
Definition: sdlr_pbist.h:111
SDL_pbistRegs::RINFO
volatile uint64_t RINFO
Definition: sdlr_pbist.h:132
SDL_pbistRegs::I1
volatile uint32_t I1
Definition: sdlr_pbist.h:107
SDL_pbistRegs::A0
volatile uint32_t A0
Definition: sdlr_pbist.h:87
SDL_pbistRegs::CL0
volatile uint32_t CL0
Definition: sdlr_pbist.h:102
SDL_pbistRegs::RF12L
volatile uint32_t RF12L
Definition: sdlr_pbist.h:66
SDL_pbistRegs::CL1
volatile uint32_t CL1
Definition: sdlr_pbist.h:103
SDL_pbistRegs::CMS
volatile uint32_t CMS
Definition: sdlr_pbist.h:112
SDL_pbistRegs::RF4L
volatile uint32_t RF4L
Definition: sdlr_pbist.h:58
SDL_pbistRegs::FSRDL0
volatile uint32_t FSRDL0
Definition: sdlr_pbist.h:124
SDL_pbistRegs::CL2
volatile uint32_t CL2
Definition: sdlr_pbist.h:104
SDL_pbistRegs::FDLY
volatile uint32_t FDLY
Definition: sdlr_pbist.h:116
SDL_pbistRegs::RF15U
volatile uint32_t RF15U
Definition: sdlr_pbist.h:85
SDL_pbistRegs::RF3U
volatile uint32_t RF3U
Definition: sdlr_pbist.h:73
SDL_pbistRegs::RF9L
volatile uint32_t RF9L
Definition: sdlr_pbist.h:63
SDL_pbistRegs::RF8L
volatile uint32_t RF8L
Definition: sdlr_pbist.h:62
SDL_pbistRegs::CA0
volatile uint32_t CA0
Definition: sdlr_pbist.h:98
SDL_pbistRegs::ROM
volatile uint32_t ROM
Definition: sdlr_pbist.h:130
SDL_pbistRegs::I2
volatile uint32_t I2
Definition: sdlr_pbist.h:108
SDL_pbistRegs::RF13L
volatile uint32_t RF13L
Definition: sdlr_pbist.h:67
SDL_pbistRegs::CA2
volatile uint32_t CA2
Definition: sdlr_pbist.h:100
SDL_pbistRegs::RF14U
volatile uint32_t RF14U
Definition: sdlr_pbist.h:84
SDL_pbistRegs::MARGIN_MODE
volatile uint32_t MARGIN_MODE
Definition: sdlr_pbist.h:127
SDL_pbistRegs::CA1
volatile uint32_t CA1
Definition: sdlr_pbist.h:99
SDL_pbistRegs::RF13U
volatile uint32_t RF13U
Definition: sdlr_pbist.h:83
SDL_pbistRegs::RF0U
volatile uint32_t RF0U
Definition: sdlr_pbist.h:70
SDL_pbistRegs::RF7L
volatile uint32_t RF7L
Definition: sdlr_pbist.h:61
SDL_pbistRegs::RF2U
volatile uint32_t RF2U
Definition: sdlr_pbist.h:72
SDL_pbistRegs::CL3
volatile uint32_t CL3
Definition: sdlr_pbist.h:105
SDL_pbistRegs::RF9U
volatile uint32_t RF9U
Definition: sdlr_pbist.h:79
SDL_pbistRegs::RF8U
volatile uint32_t RF8U
Definition: sdlr_pbist.h:78
SDL_pbistRegs::L1
volatile uint32_t L1
Definition: sdlr_pbist.h:92
SDL_pbistRegs::RF5L
volatile uint32_t RF5L
Definition: sdlr_pbist.h:59
SDL_pbistRegs::D
volatile uint32_t D
Definition: sdlr_pbist.h:95
SDL_pbistRegs::A1
volatile uint32_t A1
Definition: sdlr_pbist.h:88
SDL_pbistRegs::RF10L
volatile uint32_t RF10L
Definition: sdlr_pbist.h:64
SDL_pbistRegs::RF4U
volatile uint32_t RF4U
Definition: sdlr_pbist.h:74
SDL_pbistRegs::PID
volatile uint32_t PID
Definition: sdlr_pbist.h:118
SDL_pbistRegs::L0
volatile uint32_t L0
Definition: sdlr_pbist.h:91
SDL_pbistRegs::L2
volatile uint32_t L2
Definition: sdlr_pbist.h:93
SDL_pbistRegs::SCR
volatile uint64_t SCR
Definition: sdlr_pbist.h:114
SDL_pbistRegs::RF6L
volatile uint32_t RF6L
Definition: sdlr_pbist.h:60
SDL_pbistRegs::RF15L
volatile uint32_t RF15L
Definition: sdlr_pbist.h:69
SDL_pbistRegs::RF7U
volatile uint32_t RF7U
Definition: sdlr_pbist.h:77
SDL_pbistRegs::FSRA
volatile uint64_t FSRA
Definition: sdlr_pbist.h:123
SDL_pbistRegs::RF3L
volatile uint32_t RF3L
Definition: sdlr_pbist.h:57
SDL_pbistRegs::STR
volatile uint32_t STR
Definition: sdlr_pbist.h:113
SDL_pbistRegs::RF6U
volatile uint32_t RF6U
Definition: sdlr_pbist.h:76
SDL_pbistRegs::RF10U
volatile uint32_t RF10U
Definition: sdlr_pbist.h:80
SDL_pbistRegs::RF2L
volatile uint32_t RF2L
Definition: sdlr_pbist.h:56
SDL_pbistRegs::RAMT
volatile uint32_t RAMT
Definition: sdlr_pbist.h:110
SDL_pbistRegs::RF0L
volatile uint32_t RF0L
Definition: sdlr_pbist.h:54
SDL_pbistRegs::FSRDL1
volatile uint32_t FSRDL1
Definition: sdlr_pbist.h:126
SDL_pbistRegs::WRENZ
volatile uint32_t WRENZ
Definition: sdlr_pbist.h:128
SDL_pbistRegs::A3
volatile uint32_t A3
Definition: sdlr_pbist.h:90
SDL_pbistRegs::RF1L
volatile uint32_t RF1L
Definition: sdlr_pbist.h:55
SDL_pbistRegs::RF11U
volatile uint32_t RF11U
Definition: sdlr_pbist.h:81
SDL_pbistRegs::RF11L
volatile uint32_t RF11L
Definition: sdlr_pbist.h:65
SDL_pbistRegs::RF14L
volatile uint32_t RF14L
Definition: sdlr_pbist.h:68
SDL_pbistRegs::E
volatile uint32_t E
Definition: sdlr_pbist.h:96
SDL_pbistRegs::OVER
volatile uint32_t OVER
Definition: sdlr_pbist.h:119
SDL_pbistRegs::CSR
volatile uint32_t CSR
Definition: sdlr_pbist.h:115
SDL_pbistRegs::L3
volatile uint32_t L3
Definition: sdlr_pbist.h:94