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AM62Ax MCU+ SDK
10.01.00
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Go to the documentation of this file.
86 volatile uint8_t Resv_256[128];
97 volatile uint8_t Resv_304[8];
98 volatile uint32_t
CA0;
99 volatile uint32_t
CA1;
106 volatile uint32_t
I0;
107 volatile uint32_t
I1;
108 volatile uint32_t
I2;
109 volatile uint32_t
I3;
120 volatile uint8_t Resv_400[4];
125 volatile uint8_t Resv_432[4];
140 #define SDL_PBIST_RF0L (0x00000000U)
141 #define SDL_PBIST_RF1L (0x00000004U)
142 #define SDL_PBIST_RF2L (0x00000008U)
143 #define SDL_PBIST_RF3L (0x0000000CU)
144 #define SDL_PBIST_RF4L (0x00000010U)
145 #define SDL_PBIST_RF5L (0x00000014U)
146 #define SDL_PBIST_RF6L (0x00000018U)
147 #define SDL_PBIST_RF7L (0x0000001CU)
148 #define SDL_PBIST_RF8L (0x00000020U)
149 #define SDL_PBIST_RF9L (0x00000024U)
150 #define SDL_PBIST_RF10L (0x00000028U)
151 #define SDL_PBIST_RF11L (0x0000002CU)
152 #define SDL_PBIST_RF12L (0x00000030U)
153 #define SDL_PBIST_RF13L (0x00000034U)
154 #define SDL_PBIST_RF14L (0x00000038U)
155 #define SDL_PBIST_RF15L (0x0000003CU)
156 #define SDL_PBIST_RF0U (0x00000040U)
157 #define SDL_PBIST_RF1U (0x00000044U)
158 #define SDL_PBIST_RF2U (0x00000048U)
159 #define SDL_PBIST_RF3U (0x0000004CU)
160 #define SDL_PBIST_RF4U (0x00000050U)
161 #define SDL_PBIST_RF5U (0x00000054U)
162 #define SDL_PBIST_RF6U (0x00000058U)
163 #define SDL_PBIST_RF7U (0x0000005CU)
164 #define SDL_PBIST_RF8U (0x00000060U)
165 #define SDL_PBIST_RF9U (0x00000064U)
166 #define SDL_PBIST_RF10U (0x00000068U)
167 #define SDL_PBIST_RF11U (0x0000006CU)
168 #define SDL_PBIST_RF12U (0x00000070U)
169 #define SDL_PBIST_RF13U (0x00000074U)
170 #define SDL_PBIST_RF14U (0x00000078U)
171 #define SDL_PBIST_RF15U (0x0000007CU)
172 #define SDL_PBIST_A0 (0x00000100U)
173 #define SDL_PBIST_A1 (0x00000104U)
174 #define SDL_PBIST_A2 (0x00000108U)
175 #define SDL_PBIST_A3 (0x0000010CU)
176 #define SDL_PBIST_L0 (0x00000110U)
177 #define SDL_PBIST_L1 (0x00000114U)
178 #define SDL_PBIST_L2 (0x00000118U)
179 #define SDL_PBIST_L3 (0x0000011CU)
180 #define SDL_PBIST_D (0x00000120U)
181 #define SDL_PBIST_E (0x00000124U)
182 #define SDL_PBIST_CA0 (0x00000130U)
183 #define SDL_PBIST_CA1 (0x00000134U)
184 #define SDL_PBIST_CA2 (0x00000138U)
185 #define SDL_PBIST_CA3 (0x0000013CU)
186 #define SDL_PBIST_CL0 (0x00000140U)
187 #define SDL_PBIST_CL1 (0x00000144U)
188 #define SDL_PBIST_CL2 (0x00000148U)
189 #define SDL_PBIST_CL3 (0x0000014CU)
190 #define SDL_PBIST_I0 (0x00000150U)
191 #define SDL_PBIST_I1 (0x00000154U)
192 #define SDL_PBIST_I2 (0x00000158U)
193 #define SDL_PBIST_I3 (0x0000015CU)
194 #define SDL_PBIST_RAMT (0x00000160U)
195 #define SDL_PBIST_DLR (0x00000164U)
196 #define SDL_PBIST_CMS (0x00000168U)
197 #define SDL_PBIST_STR (0x0000016CU)
198 #define SDL_PBIST_SCR (0x00000170U)
199 #define SDL_PBIST_CSR (0x00000178U)
200 #define SDL_PBIST_FDLY (0x0000017CU)
201 #define SDL_PBIST_PACT (0x00000180U)
202 #define SDL_PBIST_PID (0x00000184U)
203 #define SDL_PBIST_OVER (0x00000188U)
204 #define SDL_PBIST_FSRF (0x00000190U)
205 #define SDL_PBIST_FSRC (0x00000198U)
206 #define SDL_PBIST_FSRA (0x000001A0U)
207 #define SDL_PBIST_FSRDL0 (0x000001A8U)
208 #define SDL_PBIST_FSRDL1 (0x000001B0U)
209 #define SDL_PBIST_MARGIN_MODE (0x000001B4U)
210 #define SDL_PBIST_WRENZ (0x000001B8U)
211 #define SDL_PBIST_PAGE_PGS (0x000001BCU)
212 #define SDL_PBIST_ROM (0x000001C0U)
213 #define SDL_PBIST_ALGO (0x000001C4U)
214 #define SDL_PBIST_RINFO (0x000001C8U)
223 #define SDL_PBIST_RF0L_RF0L_MASK (0xFFFFFFFFU)
224 #define SDL_PBIST_RF0L_RF0L_SHIFT (0x00000000U)
225 #define SDL_PBIST_RF0L_RF0L_MAX (0xFFFFFFFFU)
229 #define SDL_PBIST_RF1L_RF1L_MASK (0xFFFFFFFFU)
230 #define SDL_PBIST_RF1L_RF1L_SHIFT (0x00000000U)
231 #define SDL_PBIST_RF1L_RF1L_MAX (0xFFFFFFFFU)
235 #define SDL_PBIST_RF2L_RF2L_MASK (0xFFFFFFFFU)
236 #define SDL_PBIST_RF2L_RF2L_SHIFT (0x00000000U)
237 #define SDL_PBIST_RF2L_RF2L_MAX (0xFFFFFFFFU)
241 #define SDL_PBIST_RF3L_RF3L_MASK (0xFFFFFFFFU)
242 #define SDL_PBIST_RF3L_RF3L_SHIFT (0x00000000U)
243 #define SDL_PBIST_RF3L_RF3L_MAX (0xFFFFFFFFU)
247 #define SDL_PBIST_RF4L_RF4L_MASK (0xFFFFFFFFU)
248 #define SDL_PBIST_RF4L_RF4L_SHIFT (0x00000000U)
249 #define SDL_PBIST_RF4L_RF4L_MAX (0xFFFFFFFFU)
253 #define SDL_PBIST_RF5L_RF5L_MASK (0xFFFFFFFFU)
254 #define SDL_PBIST_RF5L_RF5L_SHIFT (0x00000000U)
255 #define SDL_PBIST_RF5L_RF5L_MAX (0xFFFFFFFFU)
259 #define SDL_PBIST_RF6L_RF6L_MASK (0xFFFFFFFFU)
260 #define SDL_PBIST_RF6L_RF6L_SHIFT (0x00000000U)
261 #define SDL_PBIST_RF6L_RF6L_MAX (0xFFFFFFFFU)
265 #define SDL_PBIST_RF7L_RF7L_MASK (0xFFFFFFFFU)
266 #define SDL_PBIST_RF7L_RF7L_SHIFT (0x00000000U)
267 #define SDL_PBIST_RF7L_RF7L_MAX (0xFFFFFFFFU)
271 #define SDL_PBIST_RF8L_RF8L_MASK (0xFFFFFFFFU)
272 #define SDL_PBIST_RF8L_RF8L_SHIFT (0x00000000U)
273 #define SDL_PBIST_RF8L_RF8L_MAX (0xFFFFFFFFU)
277 #define SDL_PBIST_RF9L_RF9L_MASK (0xFFFFFFFFU)
278 #define SDL_PBIST_RF9L_RF9L_SHIFT (0x00000000U)
279 #define SDL_PBIST_RF9L_RF9L_MAX (0xFFFFFFFFU)
283 #define SDL_PBIST_RF10L_RF10L_MASK (0xFFFFFFFFU)
284 #define SDL_PBIST_RF10L_RF10L_SHIFT (0x00000000U)
285 #define SDL_PBIST_RF10L_RF10L_MAX (0xFFFFFFFFU)
289 #define SDL_PBIST_RF11L_RF11L_MASK (0xFFFFFFFFU)
290 #define SDL_PBIST_RF11L_RF11L_SHIFT (0x00000000U)
291 #define SDL_PBIST_RF11L_RF11L_MAX (0xFFFFFFFFU)
295 #define SDL_PBIST_RF12L_RF12L_MASK (0xFFFFFFFFU)
296 #define SDL_PBIST_RF12L_RF12L_SHIFT (0x00000000U)
297 #define SDL_PBIST_RF12L_RF12L_MAX (0xFFFFFFFFU)
301 #define SDL_PBIST_RF13L_RF13L_MASK (0xFFFFFFFFU)
302 #define SDL_PBIST_RF13L_RF13L_SHIFT (0x00000000U)
303 #define SDL_PBIST_RF13L_RF13L_MAX (0xFFFFFFFFU)
307 #define SDL_PBIST_RF14L_RF14L_MASK (0xFFFFFFFFU)
308 #define SDL_PBIST_RF14L_RF14L_SHIFT (0x00000000U)
309 #define SDL_PBIST_RF14L_RF14L_MAX (0xFFFFFFFFU)
313 #define SDL_PBIST_RF15L_RF15L_MASK (0xFFFFFFFFU)
314 #define SDL_PBIST_RF15L_RF15L_SHIFT (0x00000000U)
315 #define SDL_PBIST_RF15L_RF15L_MAX (0xFFFFFFFFU)
319 #define SDL_PBIST_RF0U_RF0U_MASK (0xFFFFFFFFU)
320 #define SDL_PBIST_RF0U_RF0U_SHIFT (0x00000000U)
321 #define SDL_PBIST_RF0U_RF0U_MAX (0xFFFFFFFFU)
325 #define SDL_PBIST_RF1U_RF1U_MASK (0xFFFFFFFFU)
326 #define SDL_PBIST_RF1U_RF1U_SHIFT (0x00000000U)
327 #define SDL_PBIST_RF1U_RF1U_MAX (0xFFFFFFFFU)
331 #define SDL_PBIST_RF2U_RF2U_MASK (0xFFFFFFFFU)
332 #define SDL_PBIST_RF2U_RF2U_SHIFT (0x00000000U)
333 #define SDL_PBIST_RF2U_RF2U_MAX (0xFFFFFFFFU)
337 #define SDL_PBIST_RF3U_RF3U_MASK (0xFFFFFFFFU)
338 #define SDL_PBIST_RF3U_RF3U_SHIFT (0x00000000U)
339 #define SDL_PBIST_RF3U_RF3U_MAX (0xFFFFFFFFU)
343 #define SDL_PBIST_RF4U_RF4U_MASK (0xFFFFFFFFU)
344 #define SDL_PBIST_RF4U_RF4U_SHIFT (0x00000000U)
345 #define SDL_PBIST_RF4U_RF4U_MAX (0xFFFFFFFFU)
349 #define SDL_PBIST_RF5U_RF5U_MASK (0xFFFFFFFFU)
350 #define SDL_PBIST_RF5U_RF5U_SHIFT (0x00000000U)
351 #define SDL_PBIST_RF5U_RF5U_MAX (0xFFFFFFFFU)
355 #define SDL_PBIST_RF6U_RF6U_MASK (0xFFFFFFFFU)
356 #define SDL_PBIST_RF6U_RF6U_SHIFT (0x00000000U)
357 #define SDL_PBIST_RF6U_RF6U_MAX (0xFFFFFFFFU)
361 #define SDL_PBIST_RF7U_RF7U_MASK (0xFFFFFFFFU)
362 #define SDL_PBIST_RF7U_RF7U_SHIFT (0x00000000U)
363 #define SDL_PBIST_RF7U_RF7U_MAX (0xFFFFFFFFU)
367 #define SDL_PBIST_RF8U_RF8U_MASK (0xFFFFFFFFU)
368 #define SDL_PBIST_RF8U_RF8U_SHIFT (0x00000000U)
369 #define SDL_PBIST_RF8U_RF8U_MAX (0xFFFFFFFFU)
373 #define SDL_PBIST_RF9U_RF9U_MASK (0xFFFFFFFFU)
374 #define SDL_PBIST_RF9U_RF9U_SHIFT (0x00000000U)
375 #define SDL_PBIST_RF9U_RF9U_MAX (0xFFFFFFFFU)
379 #define SDL_PBIST_RF10U_RF10U_MASK (0xFFFFFFFFU)
380 #define SDL_PBIST_RF10U_RF10U_SHIFT (0x00000000U)
381 #define SDL_PBIST_RF10U_RF10U_MAX (0xFFFFFFFFU)
385 #define SDL_PBIST_RF11U_RF11U_MASK (0xFFFFFFFFU)
386 #define SDL_PBIST_RF11U_RF11U_SHIFT (0x00000000U)
387 #define SDL_PBIST_RF11U_RF11U_MAX (0xFFFFFFFFU)
391 #define SDL_PBIST_RF12U_RF12U_MASK (0xFFFFFFFFU)
392 #define SDL_PBIST_RF12U_RF12U_SHIFT (0x00000000U)
393 #define SDL_PBIST_RF12U_RF12U_MAX (0xFFFFFFFFU)
397 #define SDL_PBIST_RF13U_RF13U_MASK (0xFFFFFFFFU)
398 #define SDL_PBIST_RF13U_RF13U_SHIFT (0x00000000U)
399 #define SDL_PBIST_RF13U_RF13U_MAX (0xFFFFFFFFU)
403 #define SDL_PBIST_RF14U_RF14U_MASK (0xFFFFFFFFU)
404 #define SDL_PBIST_RF14U_RF14U_SHIFT (0x00000000U)
405 #define SDL_PBIST_RF14U_RF14U_MAX (0xFFFFFFFFU)
409 #define SDL_PBIST_RF15U_RF15U_MASK (0xFFFFFFFFU)
410 #define SDL_PBIST_RF15U_RF15U_SHIFT (0x00000000U)
411 #define SDL_PBIST_RF15U_RF15U_MAX (0xFFFFFFFFU)
415 #define SDL_PBIST_A0_A0_MASK (0x0000FFFFU)
416 #define SDL_PBIST_A0_A0_SHIFT (0x00000000U)
417 #define SDL_PBIST_A0_A0_MAX (0x0000FFFFU)
421 #define SDL_PBIST_A1_A1_MASK (0x0000FFFFU)
422 #define SDL_PBIST_A1_A1_SHIFT (0x00000000U)
423 #define SDL_PBIST_A1_A1_MAX (0x0000FFFFU)
427 #define SDL_PBIST_A2_A2_MASK (0x0000FFFFU)
428 #define SDL_PBIST_A2_A2_SHIFT (0x00000000U)
429 #define SDL_PBIST_A2_A2_MAX (0x0000FFFFU)
433 #define SDL_PBIST_A3_A3_MASK (0x0000FFFFU)
434 #define SDL_PBIST_A3_A3_SHIFT (0x00000000U)
435 #define SDL_PBIST_A3_A3_MAX (0x0000FFFFU)
439 #define SDL_PBIST_L0_L0_MASK (0x0000FFFFU)
440 #define SDL_PBIST_L0_L0_SHIFT (0x00000000U)
441 #define SDL_PBIST_L0_L0_MAX (0x0000FFFFU)
445 #define SDL_PBIST_L1_L1_MASK (0x0000FFFFU)
446 #define SDL_PBIST_L1_L1_SHIFT (0x00000000U)
447 #define SDL_PBIST_L1_L1_MAX (0x0000FFFFU)
451 #define SDL_PBIST_L2_L2_MASK (0x0000FFFFU)
452 #define SDL_PBIST_L2_L2_SHIFT (0x00000000U)
453 #define SDL_PBIST_L2_L2_MAX (0x0000FFFFU)
457 #define SDL_PBIST_L3_L3_MASK (0x0000FFFFU)
458 #define SDL_PBIST_L3_L3_SHIFT (0x00000000U)
459 #define SDL_PBIST_L3_L3_MAX (0x0000FFFFU)
463 #define SDL_PBIST_D_D0_MASK (0x0000FFFFU)
464 #define SDL_PBIST_D_D0_SHIFT (0x00000000U)
465 #define SDL_PBIST_D_D0_MAX (0x0000FFFFU)
467 #define SDL_PBIST_D_D1_MASK (0xFFFF0000U)
468 #define SDL_PBIST_D_D1_SHIFT (0x00000010U)
469 #define SDL_PBIST_D_D1_MAX (0x0000FFFFU)
473 #define SDL_PBIST_E_E0_MASK (0x0000FFFFU)
474 #define SDL_PBIST_E_E0_SHIFT (0x00000000U)
475 #define SDL_PBIST_E_E0_MAX (0x0000FFFFU)
477 #define SDL_PBIST_E_E1_MASK (0xFFFF0000U)
478 #define SDL_PBIST_E_E1_SHIFT (0x00000010U)
479 #define SDL_PBIST_E_E1_MAX (0x0000FFFFU)
483 #define SDL_PBIST_CA0_CA0_MASK (0x0000FFFFU)
484 #define SDL_PBIST_CA0_CA0_SHIFT (0x00000000U)
485 #define SDL_PBIST_CA0_CA0_MAX (0x0000FFFFU)
489 #define SDL_PBIST_CA1_CA1_MASK (0x0000FFFFU)
490 #define SDL_PBIST_CA1_CA1_SHIFT (0x00000000U)
491 #define SDL_PBIST_CA1_CA1_MAX (0x0000FFFFU)
495 #define SDL_PBIST_CA2_CA2_MASK (0x0000FFFFU)
496 #define SDL_PBIST_CA2_CA2_SHIFT (0x00000000U)
497 #define SDL_PBIST_CA2_CA2_MAX (0x0000FFFFU)
501 #define SDL_PBIST_CA3_CA3_MASK (0x0000FFFFU)
502 #define SDL_PBIST_CA3_CA3_SHIFT (0x00000000U)
503 #define SDL_PBIST_CA3_CA3_MAX (0x0000FFFFU)
507 #define SDL_PBIST_CL0_CL0_MASK (0x0000FFFFU)
508 #define SDL_PBIST_CL0_CL0_SHIFT (0x00000000U)
509 #define SDL_PBIST_CL0_CL0_MAX (0x0000FFFFU)
513 #define SDL_PBIST_CL1_CL1_MASK (0x0000FFFFU)
514 #define SDL_PBIST_CL1_CL1_SHIFT (0x00000000U)
515 #define SDL_PBIST_CL1_CL1_MAX (0x0000FFFFU)
519 #define SDL_PBIST_CL2_CL2_MASK (0x0000FFFFU)
520 #define SDL_PBIST_CL2_CL2_SHIFT (0x00000000U)
521 #define SDL_PBIST_CL2_CL2_MAX (0x0000FFFFU)
525 #define SDL_PBIST_CL3_CL3_MASK (0x0000FFFFU)
526 #define SDL_PBIST_CL3_CL3_SHIFT (0x00000000U)
527 #define SDL_PBIST_CL3_CL3_MAX (0x0000FFFFU)
531 #define SDL_PBIST_I0_I0_MASK (0x0000FFFFU)
532 #define SDL_PBIST_I0_I0_SHIFT (0x00000000U)
533 #define SDL_PBIST_I0_I0_MAX (0x0000FFFFU)
537 #define SDL_PBIST_I1_I0_MASK (0x0000FFFFU)
538 #define SDL_PBIST_I1_I0_SHIFT (0x00000000U)
539 #define SDL_PBIST_I1_I0_MAX (0x0000FFFFU)
543 #define SDL_PBIST_I2_I0_MASK (0x0000FFFFU)
544 #define SDL_PBIST_I2_I0_SHIFT (0x00000000U)
545 #define SDL_PBIST_I2_I0_MAX (0x0000FFFFU)
549 #define SDL_PBIST_I3_I0_MASK (0x0000FFFFU)
550 #define SDL_PBIST_I3_I0_SHIFT (0x00000000U)
551 #define SDL_PBIST_I3_I0_MAX (0x0000FFFFU)
555 #define SDL_PBIST_RAMT_RLS_MASK (0x00000003U)
556 #define SDL_PBIST_RAMT_RLS_SHIFT (0x00000000U)
557 #define SDL_PBIST_RAMT_RLS_MAX (0x00000003U)
559 #define SDL_PBIST_RAMT_PLS_MASK (0x0000003CU)
560 #define SDL_PBIST_RAMT_PLS_SHIFT (0x00000002U)
561 #define SDL_PBIST_RAMT_PLS_MAX (0x0000000FU)
563 #define SDL_PBIST_RAMT_DWR_MASK (0x0000FF00U)
564 #define SDL_PBIST_RAMT_DWR_SHIFT (0x00000008U)
565 #define SDL_PBIST_RAMT_DWR_MAX (0x000000FFU)
567 #define SDL_PBIST_RAMT_RDS_MASK (0x00FF0000U)
568 #define SDL_PBIST_RAMT_RDS_SHIFT (0x00000010U)
569 #define SDL_PBIST_RAMT_RDS_MAX (0x000000FFU)
571 #define SDL_PBIST_RAMT_RGS_MASK (0xFF000000U)
572 #define SDL_PBIST_RAMT_RGS_SHIFT (0x00000018U)
573 #define SDL_PBIST_RAMT_RGS_MAX (0x000000FFU)
577 #define SDL_PBIST_DLR_DLR0_DCM_MASK (0x00000001U)
578 #define SDL_PBIST_DLR_DLR0_DCM_SHIFT (0x00000000U)
579 #define SDL_PBIST_DLR_DLR0_DCM_MAX (0x00000001U)
581 #define SDL_PBIST_DLR_DLR0_IDDQ_MASK (0x00000002U)
582 #define SDL_PBIST_DLR_DLR0_IDDQ_SHIFT (0x00000001U)
583 #define SDL_PBIST_DLR_DLR0_IDDQ_MAX (0x00000001U)
585 #define SDL_PBIST_DLR_DLR0_ROM_MASK (0x00000004U)
586 #define SDL_PBIST_DLR_DLR0_ROM_SHIFT (0x00000002U)
587 #define SDL_PBIST_DLR_DLR0_ROM_MAX (0x00000001U)
589 #define SDL_PBIST_DLR_DLR0_TCK_MASK (0x00000008U)
590 #define SDL_PBIST_DLR_DLR0_TCK_SHIFT (0x00000003U)
591 #define SDL_PBIST_DLR_DLR0_TCK_MAX (0x00000001U)
593 #define SDL_PBIST_DLR_DLR0_CAM_MASK (0x00000010U)
594 #define SDL_PBIST_DLR_DLR0_CAM_SHIFT (0x00000004U)
595 #define SDL_PBIST_DLR_DLR0_CAM_MAX (0x00000001U)
597 #define SDL_PBIST_DLR_DLR0_ECAM_MASK (0x00000020U)
598 #define SDL_PBIST_DLR_DLR0_ECAM_SHIFT (0x00000005U)
599 #define SDL_PBIST_DLR_DLR0_ECAM_MAX (0x00000001U)
601 #define SDL_PBIST_DLR_DLR0_CFMM_MASK (0x00000040U)
602 #define SDL_PBIST_DLR_DLR0_CFMM_SHIFT (0x00000006U)
603 #define SDL_PBIST_DLR_DLR0_CFMM_MAX (0x00000001U)
605 #define SDL_PBIST_DLR_DLR0_TSM_MASK (0x00000080U)
606 #define SDL_PBIST_DLR_DLR0_TSM_SHIFT (0x00000007U)
607 #define SDL_PBIST_DLR_DLR0_TSM_MAX (0x00000001U)
609 #define SDL_PBIST_DLR_DLR1_MISR_MASK (0x00000100U)
610 #define SDL_PBIST_DLR_DLR1_MISR_SHIFT (0x00000008U)
611 #define SDL_PBIST_DLR_DLR1_MISR_MAX (0x00000001U)
613 #define SDL_PBIST_DLR_DLR1_GNG_MASK (0x00000200U)
614 #define SDL_PBIST_DLR_DLR1_GNG_SHIFT (0x00000009U)
615 #define SDL_PBIST_DLR_DLR1_GNG_MAX (0x00000001U)
617 #define SDL_PBIST_DLR_DLR1_RTM_MASK (0x00000400U)
618 #define SDL_PBIST_DLR_DLR1_RTM_SHIFT (0x0000000AU)
619 #define SDL_PBIST_DLR_DLR1_RTM_MAX (0x00000001U)
621 #define SDL_PBIST_DLR_BRP_MASK (0x00FF0000U)
622 #define SDL_PBIST_DLR_BRP_SHIFT (0x00000010U)
623 #define SDL_PBIST_DLR_BRP_MAX (0x000000FFU)
627 #define SDL_PBIST_CMS_CMS_MASK (0x0000000FU)
628 #define SDL_PBIST_CMS_CMS_SHIFT (0x00000000U)
629 #define SDL_PBIST_CMS_CMS_MAX (0x0000000FU)
633 #define SDL_PBIST_STR_START_MASK (0x00000001U)
634 #define SDL_PBIST_STR_START_SHIFT (0x00000000U)
635 #define SDL_PBIST_STR_START_MAX (0x00000001U)
637 #define SDL_PBIST_STR_RES_MASK (0x00000002U)
638 #define SDL_PBIST_STR_RES_SHIFT (0x00000001U)
639 #define SDL_PBIST_STR_RES_MAX (0x00000001U)
641 #define SDL_PBIST_STR_STOP_MASK (0x00000004U)
642 #define SDL_PBIST_STR_STOP_SHIFT (0x00000002U)
643 #define SDL_PBIST_STR_STOP_MAX (0x00000001U)
645 #define SDL_PBIST_STR_STEP_MASK (0x00000008U)
646 #define SDL_PBIST_STR_STEP_SHIFT (0x00000003U)
647 #define SDL_PBIST_STR_STEP_MAX (0x00000001U)
649 #define SDL_PBIST_STR_CHK_MASK (0x00000010U)
650 #define SDL_PBIST_STR_CHK_SHIFT (0x00000004U)
651 #define SDL_PBIST_STR_CHK_MAX (0x00000001U)
655 #define SDL_PBIST_SCR_SCR0_MASK (0x00000000000000FFU)
656 #define SDL_PBIST_SCR_SCR0_SHIFT (0x0000000000000000U)
657 #define SDL_PBIST_SCR_SCR0_MAX (0x00000000000000FFU)
659 #define SDL_PBIST_SCR_SCR1_MASK (0x000000000000FF00U)
660 #define SDL_PBIST_SCR_SCR1_SHIFT (0x0000000000000008U)
661 #define SDL_PBIST_SCR_SCR1_MAX (0x00000000000000FFU)
663 #define SDL_PBIST_SCR_SCR2_MASK (0x0000000000FF0000U)
664 #define SDL_PBIST_SCR_SCR2_SHIFT (0x0000000000000010U)
665 #define SDL_PBIST_SCR_SCR2_MAX (0x00000000000000FFU)
667 #define SDL_PBIST_SCR_SCR3_MASK (0x00000000FF000000U)
668 #define SDL_PBIST_SCR_SCR3_SHIFT (0x0000000000000018U)
669 #define SDL_PBIST_SCR_SCR3_MAX (0x00000000000000FFU)
671 #define SDL_PBIST_SCR_SCR4_MASK (0x000000FF00000000U)
672 #define SDL_PBIST_SCR_SCR4_SHIFT (0x0000000000000020U)
673 #define SDL_PBIST_SCR_SCR4_MAX (0x00000000000000FFU)
675 #define SDL_PBIST_SCR_SCR5_MASK (0x0000FF0000000000U)
676 #define SDL_PBIST_SCR_SCR5_SHIFT (0x0000000000000028U)
677 #define SDL_PBIST_SCR_SCR5_MAX (0x00000000000000FFU)
679 #define SDL_PBIST_SCR_SCR6_MASK (0x00FF000000000000U)
680 #define SDL_PBIST_SCR_SCR6_SHIFT (0x0000000000000030U)
681 #define SDL_PBIST_SCR_SCR6_MAX (0x00000000000000FFU)
683 #define SDL_PBIST_SCR_SCR7_MASK (0xFF00000000000000U)
684 #define SDL_PBIST_SCR_SCR7_SHIFT (0x0000000000000038U)
685 #define SDL_PBIST_SCR_SCR7_MAX (0x00000000000000FFU)
689 #define SDL_PBIST_CSR_CSR0_MASK (0x000000FFU)
690 #define SDL_PBIST_CSR_CSR0_SHIFT (0x00000000U)
691 #define SDL_PBIST_CSR_CSR0_MAX (0x000000FFU)
693 #define SDL_PBIST_CSR_CSR1_MASK (0x0000FF00U)
694 #define SDL_PBIST_CSR_CSR1_SHIFT (0x00000008U)
695 #define SDL_PBIST_CSR_CSR1_MAX (0x000000FFU)
697 #define SDL_PBIST_CSR_CSR2_MASK (0x00FF0000U)
698 #define SDL_PBIST_CSR_CSR2_SHIFT (0x00000010U)
699 #define SDL_PBIST_CSR_CSR2_MAX (0x000000FFU)
701 #define SDL_PBIST_CSR_CSR3_MASK (0xFF000000U)
702 #define SDL_PBIST_CSR_CSR3_SHIFT (0x00000018U)
703 #define SDL_PBIST_CSR_CSR3_MAX (0x000000FFU)
707 #define SDL_PBIST_FDLY_FDLY_MASK (0x000000FFU)
708 #define SDL_PBIST_FDLY_FDLY_SHIFT (0x00000000U)
709 #define SDL_PBIST_FDLY_FDLY_MAX (0x000000FFU)
713 #define SDL_PBIST_PACT_PACT_MASK (0x00000001U)
714 #define SDL_PBIST_PACT_PACT_SHIFT (0x00000000U)
715 #define SDL_PBIST_PACT_PACT_MAX (0x00000001U)
719 #define SDL_PBIST_PID_PID_MASK (0x0000001FU)
720 #define SDL_PBIST_PID_PID_SHIFT (0x00000000U)
721 #define SDL_PBIST_PID_PID_MAX (0x0000001FU)
725 #define SDL_PBIST_OVER_RINFO_MASK (0x00000001U)
726 #define SDL_PBIST_OVER_RINFO_SHIFT (0x00000000U)
727 #define SDL_PBIST_OVER_RINFO_MAX (0x00000001U)
729 #define SDL_PBIST_OVER_READ_MASK (0x00000002U)
730 #define SDL_PBIST_OVER_READ_SHIFT (0x00000001U)
731 #define SDL_PBIST_OVER_READ_MAX (0x00000001U)
733 #define SDL_PBIST_OVER_MM_MASK (0x00000004U)
734 #define SDL_PBIST_OVER_MM_SHIFT (0x00000002U)
735 #define SDL_PBIST_OVER_MM_MAX (0x00000001U)
737 #define SDL_PBIST_OVER_ALGO_MASK (0x00000008U)
738 #define SDL_PBIST_OVER_ALGO_SHIFT (0x00000003U)
739 #define SDL_PBIST_OVER_ALGO_MAX (0x00000001U)
743 #define SDL_PBIST_FSRF_FRSF0_MASK (0x0000000000000001U)
744 #define SDL_PBIST_FSRF_FRSF0_SHIFT (0x0000000000000000U)
745 #define SDL_PBIST_FSRF_FRSF0_MAX (0x0000000000000001U)
747 #define SDL_PBIST_FSRF_FRSF1_MASK (0x0000000100000000U)
748 #define SDL_PBIST_FSRF_FRSF1_SHIFT (0x0000000000000020U)
749 #define SDL_PBIST_FSRF_FRSF1_MAX (0x0000000000000001U)
753 #define SDL_PBIST_FSRC_FSRC0_MASK (0x000000000000000FU)
754 #define SDL_PBIST_FSRC_FSRC0_SHIFT (0x0000000000000000U)
755 #define SDL_PBIST_FSRC_FSRC0_MAX (0x000000000000000FU)
757 #define SDL_PBIST_FSRC_FSRC1_MASK (0x0000000F00000000U)
758 #define SDL_PBIST_FSRC_FSRC1_SHIFT (0x0000000000000020U)
759 #define SDL_PBIST_FSRC_FSRC1_MAX (0x000000000000000FU)
763 #define SDL_PBIST_FSRA_FSRA0_MASK (0x000000000000FFFFU)
764 #define SDL_PBIST_FSRA_FSRA0_SHIFT (0x0000000000000000U)
765 #define SDL_PBIST_FSRA_FSRA0_MAX (0x000000000000FFFFU)
767 #define SDL_PBIST_FSRA_FSRA1_MASK (0x0000FFFF00000000U)
768 #define SDL_PBIST_FSRA_FSRA1_SHIFT (0x0000000000000020U)
769 #define SDL_PBIST_FSRA_FSRA1_MAX (0x000000000000FFFFU)
773 #define SDL_PBIST_FSRDL0_FSRDL0_MASK (0xFFFFFFFFU)
774 #define SDL_PBIST_FSRDL0_FSRDL0_SHIFT (0x00000000U)
775 #define SDL_PBIST_FSRDL0_FSRDL0_MAX (0xFFFFFFFFU)
779 #define SDL_PBIST_FSRDL1_FSRDL1_MASK (0xFFFFFFFFU)
780 #define SDL_PBIST_FSRDL1_FSRDL1_SHIFT (0x00000000U)
781 #define SDL_PBIST_FSRDL1_FSRDL1_MAX (0xFFFFFFFFU)
785 #define SDL_PBIST_MARGIN_MODE_PBIST_DFT_WRITE_MASK (0x00000003U)
786 #define SDL_PBIST_MARGIN_MODE_PBIST_DFT_WRITE_SHIFT (0x00000000U)
787 #define SDL_PBIST_MARGIN_MODE_PBIST_DFT_WRITE_MAX (0x00000003U)
789 #define SDL_PBIST_MARGIN_MODE_PBIST_DFT_READ_MASK (0x0000000CU)
790 #define SDL_PBIST_MARGIN_MODE_PBIST_DFT_READ_SHIFT (0x00000002U)
791 #define SDL_PBIST_MARGIN_MODE_PBIST_DFT_READ_MAX (0x00000003U)
795 #define SDL_PBIST_WRENZ_WRENZ_MASK (0x00000003U)
796 #define SDL_PBIST_WRENZ_WRENZ_SHIFT (0x00000000U)
797 #define SDL_PBIST_WRENZ_WRENZ_MAX (0x00000003U)
801 #define SDL_PBIST_PAGE_PGS_PGS_MASK (0x00000003U)
802 #define SDL_PBIST_PAGE_PGS_PGS_SHIFT (0x00000000U)
803 #define SDL_PBIST_PAGE_PGS_PGS_MAX (0x00000003U)
807 #define SDL_PBIST_ROM_ROM_MASK (0x00000003U)
808 #define SDL_PBIST_ROM_ROM_SHIFT (0x00000000U)
809 #define SDL_PBIST_ROM_ROM_MAX (0x00000003U)
813 #define SDL_PBIST_ALGO_ALGO_0_MASK (0x000000FFU)
814 #define SDL_PBIST_ALGO_ALGO_0_SHIFT (0x00000000U)
815 #define SDL_PBIST_ALGO_ALGO_0_MAX (0x000000FFU)
817 #define SDL_PBIST_ALGO_ALGO_1_MASK (0x0000FF00U)
818 #define SDL_PBIST_ALGO_ALGO_1_SHIFT (0x00000008U)
819 #define SDL_PBIST_ALGO_ALGO_1_MAX (0x000000FFU)
821 #define SDL_PBIST_ALGO_ALGO_2_MASK (0x00FF0000U)
822 #define SDL_PBIST_ALGO_ALGO_2_SHIFT (0x00000010U)
823 #define SDL_PBIST_ALGO_ALGO_2_MAX (0x000000FFU)
825 #define SDL_PBIST_ALGO_ALGO_3_MASK (0xFF000000U)
826 #define SDL_PBIST_ALGO_ALGO_3_SHIFT (0x00000018U)
827 #define SDL_PBIST_ALGO_ALGO_3_MAX (0x000000FFU)
831 #define SDL_PBIST_RINFO_L0_MASK (0x00000000000000FFU)
832 #define SDL_PBIST_RINFO_L0_SHIFT (0x0000000000000000U)
833 #define SDL_PBIST_RINFO_L0_MAX (0x00000000000000FFU)
835 #define SDL_PBIST_RINFO_L1_MASK (0x000000000000FF00U)
836 #define SDL_PBIST_RINFO_L1_SHIFT (0x0000000000000008U)
837 #define SDL_PBIST_RINFO_L1_MAX (0x00000000000000FFU)
839 #define SDL_PBIST_RINFO_L2_MASK (0x0000000000FF0000U)
840 #define SDL_PBIST_RINFO_L2_SHIFT (0x0000000000000010U)
841 #define SDL_PBIST_RINFO_L2_MAX (0x00000000000000FFU)
843 #define SDL_PBIST_RINFO_L3_MASK (0x00000000FF000000U)
844 #define SDL_PBIST_RINFO_L3_SHIFT (0x0000000000000018U)
845 #define SDL_PBIST_RINFO_L3_MAX (0x00000000000000FFU)
847 #define SDL_PBIST_RINFO_U0_MASK (0x000000FF00000000U)
848 #define SDL_PBIST_RINFO_U0_SHIFT (0x0000000000000020U)
849 #define SDL_PBIST_RINFO_U0_MAX (0x00000000000000FFU)
851 #define SDL_PBIST_RINFO_U1_MASK (0x0000FF0000000000U)
852 #define SDL_PBIST_RINFO_U1_SHIFT (0x0000000000000028U)
853 #define SDL_PBIST_RINFO_U1_MAX (0x00000000000000FFU)
855 #define SDL_PBIST_RINFO_U2_MASK (0x00FF000000000000U)
856 #define SDL_PBIST_RINFO_U2_SHIFT (0x0000000000000030U)
857 #define SDL_PBIST_RINFO_U2_MAX (0x00000000000000FFU)
859 #define SDL_PBIST_RINFO_U3_MASK (0xFF00000000000000U)
860 #define SDL_PBIST_RINFO_U3_SHIFT (0x0000000000000038U)
861 #define SDL_PBIST_RINFO_U3_MAX (0x00000000000000FFU)
volatile uint32_t RF5U
Definition: sdlr_pbist.h:75
volatile uint32_t PACT
Definition: sdlr_pbist.h:117
volatile uint64_t FSRF
Definition: sdlr_pbist.h:121
Definition: sdlr_pbist.h:53
volatile uint32_t I0
Definition: sdlr_pbist.h:106
volatile uint32_t PAGE_PGS
Definition: sdlr_pbist.h:129
volatile uint32_t RF1U
Definition: sdlr_pbist.h:71
volatile uint64_t FSRC
Definition: sdlr_pbist.h:122
volatile uint32_t A2
Definition: sdlr_pbist.h:89
volatile uint32_t RF12U
Definition: sdlr_pbist.h:82
volatile uint32_t CA3
Definition: sdlr_pbist.h:101
volatile uint32_t I3
Definition: sdlr_pbist.h:109
volatile uint32_t ALGO
Definition: sdlr_pbist.h:131
volatile uint32_t DLR
Definition: sdlr_pbist.h:111
volatile uint64_t RINFO
Definition: sdlr_pbist.h:132
volatile uint32_t I1
Definition: sdlr_pbist.h:107
volatile uint32_t A0
Definition: sdlr_pbist.h:87
volatile uint32_t CL0
Definition: sdlr_pbist.h:102
volatile uint32_t RF12L
Definition: sdlr_pbist.h:66
volatile uint32_t CL1
Definition: sdlr_pbist.h:103
volatile uint32_t CMS
Definition: sdlr_pbist.h:112
volatile uint32_t RF4L
Definition: sdlr_pbist.h:58
volatile uint32_t FSRDL0
Definition: sdlr_pbist.h:124
volatile uint32_t CL2
Definition: sdlr_pbist.h:104
volatile uint32_t FDLY
Definition: sdlr_pbist.h:116
volatile uint32_t RF15U
Definition: sdlr_pbist.h:85
volatile uint32_t RF3U
Definition: sdlr_pbist.h:73
volatile uint32_t RF9L
Definition: sdlr_pbist.h:63
volatile uint32_t RF8L
Definition: sdlr_pbist.h:62
volatile uint32_t CA0
Definition: sdlr_pbist.h:98
volatile uint32_t ROM
Definition: sdlr_pbist.h:130
volatile uint32_t I2
Definition: sdlr_pbist.h:108
volatile uint32_t RF13L
Definition: sdlr_pbist.h:67
volatile uint32_t CA2
Definition: sdlr_pbist.h:100
volatile uint32_t RF14U
Definition: sdlr_pbist.h:84
volatile uint32_t MARGIN_MODE
Definition: sdlr_pbist.h:127
volatile uint32_t CA1
Definition: sdlr_pbist.h:99
volatile uint32_t RF13U
Definition: sdlr_pbist.h:83
volatile uint32_t RF0U
Definition: sdlr_pbist.h:70
volatile uint32_t RF7L
Definition: sdlr_pbist.h:61
volatile uint32_t RF2U
Definition: sdlr_pbist.h:72
volatile uint32_t CL3
Definition: sdlr_pbist.h:105
volatile uint32_t RF9U
Definition: sdlr_pbist.h:79
volatile uint32_t RF8U
Definition: sdlr_pbist.h:78
volatile uint32_t L1
Definition: sdlr_pbist.h:92
volatile uint32_t RF5L
Definition: sdlr_pbist.h:59
volatile uint32_t D
Definition: sdlr_pbist.h:95
volatile uint32_t A1
Definition: sdlr_pbist.h:88
volatile uint32_t RF10L
Definition: sdlr_pbist.h:64
volatile uint32_t RF4U
Definition: sdlr_pbist.h:74
volatile uint32_t PID
Definition: sdlr_pbist.h:118
volatile uint32_t L0
Definition: sdlr_pbist.h:91
volatile uint32_t L2
Definition: sdlr_pbist.h:93
volatile uint64_t SCR
Definition: sdlr_pbist.h:114
volatile uint32_t RF6L
Definition: sdlr_pbist.h:60
volatile uint32_t RF15L
Definition: sdlr_pbist.h:69
volatile uint32_t RF7U
Definition: sdlr_pbist.h:77
volatile uint64_t FSRA
Definition: sdlr_pbist.h:123
volatile uint32_t RF3L
Definition: sdlr_pbist.h:57
volatile uint32_t STR
Definition: sdlr_pbist.h:113
volatile uint32_t RF6U
Definition: sdlr_pbist.h:76
volatile uint32_t RF10U
Definition: sdlr_pbist.h:80
volatile uint32_t RF2L
Definition: sdlr_pbist.h:56
volatile uint32_t RAMT
Definition: sdlr_pbist.h:110
volatile uint32_t RF0L
Definition: sdlr_pbist.h:54
volatile uint32_t FSRDL1
Definition: sdlr_pbist.h:126
volatile uint32_t WRENZ
Definition: sdlr_pbist.h:128
volatile uint32_t A3
Definition: sdlr_pbist.h:90
volatile uint32_t RF1L
Definition: sdlr_pbist.h:55
volatile uint32_t RF11U
Definition: sdlr_pbist.h:81
volatile uint32_t RF11L
Definition: sdlr_pbist.h:65
volatile uint32_t RF14L
Definition: sdlr_pbist.h:68
volatile uint32_t E
Definition: sdlr_pbist.h:96
volatile uint32_t OVER
Definition: sdlr_pbist.h:119
volatile uint32_t CSR
Definition: sdlr_pbist.h:115
volatile uint32_t L3
Definition: sdlr_pbist.h:94