SMP FreeRTOS kernel support is added in the DPL layer for A53 core. This makes use of all the four A53 cores for running applications by using the FreeRTOS SMP kernel for scheduling tasks on all the four cores.
SMP application uses SGI interrupt interrupt number 0 for communication between A53 cores. So care must be taken not to use this interrupt in user applications.
SMP applications can be loaded via SBL as well as CCS. A53 cores must be run as sync group in CCS when running SMP applications.
When runnig SMP application using CCS, the cores needs to be run as sync group.
A sync group can be created as follows. This ensures the same binary is executed on all the four cores from the same entry point.
Connect the Target Group
An SMP example for A53 can be imported and build just as a single core A53 application. But all the four a53 cores must be selected and sync group must be created when launching the debug session.
Connect to target and load the .out file then run
The dhrystone values can be used to compare the performance between single core FreeRTOS on A53 and SMP FreeRTOS on A53.
No of Threads | No of Iterations | Dhrystone per second for Single Core FreeRTOS on A53 | Dhrystone per second for SMP FreeRTOS on A53 |
---|---|---|---|
1 | 30000000 | 7602697.5 | 7692834.5 |
2 | 30000000 | 7623452.5 | 15385641.0 |
5 | 30000000 | 7652666.5 | 19074966.0 |
10 | 30000000 | 7656853.0 | 25470718.0 |
For more details on debugging an SMP application using CCS, see here