NO RTOS

Table of Contents

• Introduction
• Features Supported
• SysConfig Features
• Features Not Supported
• Important files and directory structure
• Additional References
• See also

Introduction

NORTOS is a SW module that implements APIs which allow the upper layers of SW to run in no-RTOS mode. i.e without any RTOS. The NO RTOS APIs are implemented underneath the Driver Porting Layer (DPL) APIs. This allows the device drivers to run either in no-RTOS mode or with a RTOS.

Features Supported

Common across all CPUs,

• Clock APIs to initialize a system tick ISR and allow SW to create multiple SW timers using a single underlying HW timer. || SOC_AM62DX
• Address translate APIs to translate system address to local address, needed for MCU_R5F
• Heap APIs to create arbitrary heaps at user defined memory locations
• Semaphore APIs to model a semaphore in no-RTOS environment
• HW Timer APIs to setup user defined HW timers beyond the system tick timer.
• Logging APIs to log to different consoles like UART, CCS, shared memory, CPU local memory, including logging zones to enable/disable logging.

|| SOC_AM62DX DM_R5F features,

• CPU start up code
• Cache APIs to enable, disable, invalidate, write back caches
• Memory protection unit (MPU) APIs to enable, disable multiple regions in the MPU
• Interrupt controller APIs to register ISRs, enable/disable interrupts
• ISR handlers and exception handlers
• Performance counter APIs
• DM_R5F ISRs,
  • IRQ mode,
    • nested interrupts supported
    • FPU save/restore supported

|| SOC_AM62DX MCU_R5F features,

• CPU start up code
• Memory protection unit (MPU) APIs to enable, disable multiple regions in the MPU
• Interrupt controller APIs to register ISRs, enable/disable interrupts
• ISR handlers and exception handlers
• Performance counter APIs
• SysTick timer APIs
• MCU_R5F ISRs
  • Nested interrupts

A53 features,

• Single Core A53
• CPU start up code
• Memory management unit (MMU) APIs to enable, disable multiple regions in the MMU
• Interrupt controller APIs to register ISRs, enable/disable interrupts
• ISR handlers and exception handlers
• Performance counter APIs
• A53 ISRs
  • IRQ mode
    • nested interrupt supported
    • FPU save/restore supported

SysConfig Features

Note

It is strongly recommend to use SysConfig where it is available instead of using direct SW API calls. This will help simplify the SW application and also catch common mistakes early in the development cycle.

SysConfig can be used to configure below modules with NORTOS

• Clock module to setup system tick timer including the tick duration
• Debug Log module to select the console to use for logging as well as enable/disable logging zones || SOC_AM62DX
• RAT to setup address translation regions, needed for MCU_R5F and DM_R5F
• MPU ARMv7 to setup different MPU regions for DM_R5F and MCU_R5F CPUs
• MMU ARMV8 to setup different MMU regions for A53 CPU
• Timer to setup HW timer available on the SOC, including enabling timer interrupt and ISR registration

Features Not Supported

• Task APIs are not supported in NORTOS mode. Task APIs necessarily need a RTOS and cannot be used in no-RTOS mode || SOC_AM62DX
• DM_R5F ISRs,
  • FIQ mode,
    • nested interrupts not supported.
    • FPU save/restore not supported.
• MCU_R5F ISRs,
  • FPU save/restore not supported.
• A53 ISRs,
  • FIQ mode ISRs not supported.
• A53 multi-core SMP mode is not supported.

Important files and directory structure

Folder/Files	Description
${SDK_INSTALL_PATH}/source/kernel/
dpl/	APIs to access NORTOS features
${SDK_INSTALL_PATH}/source/kernel/nortos
lib/	NORTOS library to link against. Linking to the library in this path enables the application to operate in no-RTOS mode
dpl/common/	NORTOS APIs that are common across all CPUs
dpl/a53/	NORTOS APIs that are specific to A53 CPUs

Additional References

Note

Precise web links are not provided since these can change, search for the document title in google to download the documents

Please also refer to below documents from ARM Ltd. to understand more about R5F, M4F, A53 CPUs including features like MPU, MMU, cache and interrupts.

Document Title	Description
ARM v7R Architecture Reference Manual	Information about ARM architecture that is implemented by R5F. Should be used in conjunction with R5F TRM to understand R5F architecture details.
ARM Cortex R5F Technical Reference Manual	Information about R5F CPU architecture.

See also

Driver Porting Layer (DPL)