AM62Ax MCU+ SDK  11.01.00
SDL ECC SEC

Introduction

This example takes an aggregator index as input from the user and performs single bit error test for the corresponding aggregator. It involves the following steps:

  • Setup of an ESM application callback to receive Single Error Correction (SEC) and setup of ECC Aggregators in general
  • Triggering of ECC events for all the RAM IDs, including Interconnect type and Wrapper type
  • Printing out error information within the ECC callback upon reception of ECC events

Aggregators Supported

The following aggregators can be tested using this example.

Aggregator Index ECC Aggregator
0 SDL_PSCSS0_SAM62A_MAIN_PSC_WRAP_ECC_AGGR
1 SDL_PSRAMECC0_PSRAM256X32E_ECC_AGGR
2 SDL_PSRAMECC1_PSRAM256X32E_ECC_AGGR
3 SDL_MSRAM_64K0_MSRAM2KX256E_ECC_AGGR
4 SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR
5 SDL_DMASS1_DMSS_CSI_AM62A_ECCAGGR
6 SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR
7 SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR
8 SDL_FSS0_FSS_UL_OSPI0_OSPI_WRAP_ECC_AGGR
9 SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR
10 SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR
11 SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR
12 SDL_GICSS0_GIC500SS_1_4_ECC_AGGR
13 SDL_ECC_AGGR1_SAM62A_SEC_MCU_ECC_AGGR
14 SDL_DMASS0_DMSS_AM62A_ECCAGGR
15 SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR
16 SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_RXMEM
17 SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_TXMEM
18 SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_RXMEM
19 SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_TXMEM
20 SDL_MMCSD0_EMMCSD8SS_ECC_AGGR_TXMEM
21 SDL_MMCSD0_EMMCSD8SS_ECC_AGGR_RXMEM
22 SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR
23 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR
24 SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR
25 SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR
26 SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR
27 SDL_SMS0_SMS_HSM_ECC
28 SDL_SMS0_SMS_TIFS_ECC
29 SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_PAC_BASE_KSDW_ECC_AGGR
30 SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_LDC0_KSDW_ECC_AGGR
31 SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR
32 SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR
33 SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR
34 SDL_USB1_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR
35 SDL_USB0_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR
36 SDL_WKUP_PSRAMECC_8K0_PSRAM8KX32E_ECC_AGGR
37 SDL_PDMA0_SAM62_PDMA_SPI_ECCAGGR
38 SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR
39 SDL_PDMA1_SAM62_PDMA_UART_ECCAGGR
40 SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR
41 SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0
42 SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1
43 SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2
44 SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3
45 SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC
46 SDL_MCU_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR
47 SDL_MCU_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR
48 SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR

Supported Combinations

Parameter Value
CPU + OS mcu-r5fss0-0 nortos
Toolchain ti-arm-clang
Board am62ax-sk
Example folder examples/sdl/ecc_sec/

Steps to Run the Example

Sample Output

Shown below is a sample output when the application is run for a couple of aggregators,

ECC Example Application
ECC_Test_init: Init MCU ESM complete
ECC_Test_init: Init MAIN ESM complete
ECC_Test_init: ECC Callback Init complete for MCU ESM
ECC_Test_init: ECC Callback Init complete for Main ESM
ECC SDL API tests: starting
Select the memory to test...
0
...selected 0
ecc_aggrtest: [0] single bit error self test: SDL_PSCSS0_SAM62A_MAIN_PSC_WRAP_ECC_AGGR starting
ECC_Memory_init: [0] SDL_PSCSS0_SAM62A_MAIN_PSC_WRAP_ECC_AGGR ECC Init complete
Inject test started not accessable RamId 0 starting
Injected ECC error and got ESM Interrupt
Select the memory to test...
4
...selected 4
ecc_aggrtest: [4] single bit error self test: SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR starting
ECC_Memory_init: [4] SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR ECC Init complete
Self test started RamId 0 starting
Self test started RamId 0 completed
Self test started RamId 1 starting
Self test started RamId 1 completed
Self test started RamId 2 starting
Self test started RamId 2 completed
Self test started RamId 3 starting
Self test started RamId 3 completed
Select the memory to test...