Introduction
This datasheet provides the performance numbers of various device drivers in MCU PLUS SDK for AM62AX
Generic Setup details
SOC Details | Values |
Core | R5F |
Core Operating Speed | 800 MHz |
Cache Status | Enabled |
Optimization Details | Values |
Build Profile | Release |
R5F Compiler flags | -mcpu=cortex-r5 -mfloat-abi=hard -mfpu=vfpv3-d16 -Wall -Werror -g -mthumb -Wno-gnu-variable-sized-type-not-at-end -Wno-unused-function |
R5F Linker flags | -Wl,–diag_suppress=10063 -Wl,–ram_model -Wl,–reread_libs |
Code Placement | HSM RAM (For SBL Stage1), DDR (SBL Stage2 and others) |
Data Placement | HSM RAM (For SBL Stage1), DDR (SBL Stage2 and others) |
Performance Numbers
SBL OSPI NAND performance (HS-FS)
- Software/Application used : sbl_ospi_nand_linux_multistage, ipc_rpmsg_echo_linux, linux and HSM App Images
- Cores booted by stage1 SBL : mcu-r5f0-0 r5f0-0
- Cores booted by stage2 SBL : hsm-m4f0-0 r5f0-0 a530-0 c75ss0
- Size of images loaded by stage1 : 193 KB
- Size of images loaded by stage2 : 1202 KB
- Boot Media Clock : 166.667 MHz
- Mode : PHY enabled, DMA enabled
- Protocol : 1S-8S-8S
SBL Stage1 boot time breakdown | Time (ms) |
SBL Stage1: System_init | 37.426 |
SBL Stage1: Board_init | 0.000 |
SBL Stage1: Drivers_open | 0.194 |
SBL Stage1: Board_driversOpen | 26.726 |
SBL Stage1: Sciclient Get Version | 10.170 |
SBL Stage1: App_waitForMcuPbist | 0.002 |
SBL Stage1: MCU R5 Image Load | 3.401 |
SBL Stage1: DM R5 Image Load | 6.749 |
-------------------------------------— | -----------— |
SBL Stage2: Total time taken | 84.672 |
SBL Stage2 boot time breakdown | Time (ms) |
SBL Stage2: System_init | 1.772 |
SBL Stage2: Board_init | 0.001 |
SBL Stage2: Drivers_open | 0.222 |
SBL Stage2: Board_driversOpen | 26.590 |
SBL Stage2: Sciclient Get Version | 10.219 |
SBL Stage2: HSM Image Load | 2.041 |
SBL Stage2: DM R5 Image Load | 8.078 |
SBL Stage2: A53 Image Load | 29.494 |
SBL Stage2: DSP Image Load | 13.070 |
-------------------------------------— | -----------— |
SBL Stage2: Total time taken | 91.490 |
- Here the CPU load or section copy takes place from the OSPI memory to DDR, this would be slower that mem to mem copy.
- The time taken for Sciclient Get Version can be avoided if the version check is disabled
- MCU PBIST is started before the DDR init/ It is done in HW in parallel while the DDR init is completed. Due to this MCU PBIST wait time is low.
- Out of the ~39 ms taken for System Init is mostly attributed to DDR initialization.
SBL OSPI NAND performance (HS)
- Software/Application used : sbl_ospi_nand_linux_multistage, ipc_rpmsg_echo_linux, linux and HSM App Images
- Cores booted by stage1 SBL : mcu-r5f0-0 r5f0-0
- Cores booted by stage2 SBL : hsm-m4f0-0 r5f0-0 a530-0 c75ss0
- Size of images loaded by stage1 : 193 KB
- Size of images loaded by stage2 : 1202 KB
- Boot Media Clock : 166.667 MHz
- Mode : PHY enabled, DMA enabled
- Protocol : 1S-8S-8S
SBL Stage1 boot time breakdown | Time (ms) |
SBL Stage1: System_init | 36.716 |
SBL Stage1: Board_init | 0.000 |
SBL Stage1: Drivers_open | 0.192 |
SBL Stage1: Board_driversOpen | 26.694 |
SBL Stage1: Sciclient Get Version | 10.169 |
SBL Stage1: App_waitForMcuPbist | 0.002 |
SBL Stage1: MCU R5 Image Load | 3.482 |
SBL Stage1: DM R5 Image Load | 6.749 |
-------------------------------------— | -----------— |
SBL Stage2: Total time taken | 84.094 |
SBL Stage2 boot time breakdown | Time (ms) |
SBL Stage2: System_init | 1.767 |
SBL Stage2: Board_init | 0.001 |
SBL Stage2: Drivers_open | 0.221 |
SBL Stage2: Board_driversOpen | 26.583 |
SBL Stage2: Sciclient Get Version | 10.219 |
SBL Stage2: HSM Image Load | 2.127 |
SBL Stage2: DM R5 Image Load | 8.164 |
SBL Stage2: A53 Image Load | 29.568 |
SBL Stage2: DSP Image Load | 13.147 |
-------------------------------------— | -----------— |
SBL Stage2: Total time taken | 91.801 |
- Here the CPU load or section copy takes place from the OSPI memory to DDR, this would be slower that mem to mem copy.
- The time taken for Sciclient Get Version can be avoided if the version check is disabled
- MCU PBIST is started before the DDR init/ It is done in HW in parallel while the DDR init is completed. Due to this MCU PBIST wait time is low.
- Out of the ~39 ms taken for System Init is mostly attributed to DDR initialization.
SBL EMMC performance (HS-FS)
- Software/Application used : sbl_emmc_linux_multistage, ipc_rpmsg_echo_linux, linux and HSM App Images
- Cores booted by stage1 SBL : mcu-r5f0-0 r5f0-0
- Cores booted by stage2 SBL : hsm-m4f0-0 r5f0-0 a530-0 c75ss0
- Size of images loaded by stage1 : 163 KB
- Size of images loaded by stage2 : 1202 KB
- Boot Media Clock : 200.000 MHz
- Mode : HS200
SBL Stage1 boot time breakdown | Time (ms) |
SBL Stage1: System_init | 37.396 |
SBL Stage1: Board_init | 0.000 |
SBL Stage1: Drivers_open | 20.620 |
SBL Stage1: Board_driversOpen | 0.000 |
SBL Stage1: Sciclient Get Version | 10.170 |
SBL Stage1: MCU R5 Image Load | 6.897 |
SBL Stage1: DM R5 Image Load | 8.247 |
-------------------------------------— | -----------— |
SBL Stage1: Total time taken | 83.333 |
SBL Stage2 boot time breakdown | Time (ms) |
SBL Stage2: System_init | 1.644 |
SBL Stage2: Board_init | 0.000 |
SBL Stage2: Drivers_open | 20.526 |
SBL Stage2: Board_driversOpen | 0.000 |
SBL Stage2: Sciclient Get Version | 10.266 |
SBL Stage2: HSM Image Load | 5.371 |
SBL Stage2: DM R5 Image Load | 8.619 |
SBL Stage2: A53 Image Load | 20.915 |
SBL Stage2: DSP Image Load | 15.007 |
-------------------------------------— | -----------— |
SBL Stage2: Total time taken | 82.352 |
- The emmc driver initialization is done as part of Drivers_open.
- The time taken for Sciclient Get Version can be avoided if the version check is disabled
- Out of the ~39 ms taken for System Init is mostly attributed to DDR initialization.
SBL EMMC performance (HS)
- Software/Application used : sbl_emmc_linux_multistage, ipc_rpmsg_echo_linux, linux and HSM App Images
- Cores booted by stage1 SBL : mcu-r5f0-0 r5f0-0
- Cores booted by stage2 SBL : hsm-m4f0-0 r5f0-0 a530-0 c75ss0
- Size of images loaded by stage1 : 163 KB
- Size of images loaded by stage2 : 1202 KB
- Boot Media Clock : 200.000 MHz
- Mode : HS200
SBL Stage1 boot time breakdown | Time (ms) |
SBL Stage1: System_init | 36.606 |
SBL Stage1: Board_init | 0.000 |
SBL Stage1: Drivers_open | 20.604 |
SBL Stage1: Board_driversOpen | 0.000 |
SBL Stage1: Sciclient Get Version | 10.170 |
SBL Stage1: MCU R5 Image Load | 6.893 |
SBL Stage1: DM R5 Image Load | 7.611 |
-------------------------------------— | -----------— |
SBL Stage1: Total time taken | 81.887 |
SBL Stage2 boot time breakdown | Time (ms) |
SBL Stage2: System_init | 1.645 |
SBL Stage2: Board_init | 0.000 |
SBL Stage2: Drivers_open | 20.583 |
SBL Stage2: Board_driversOpen | 0.000 |
SBL Stage2: Sciclient Get Version | 10.227 |
SBL Stage2: HSM Image Load | 5.442 |
SBL Stage2: DM R5 Image Load | 9.257 |
SBL Stage2: A53 Image Load | 20.985 |
SBL Stage2: DSP Image Load | 14.385 |
-------------------------------------— | -----------— |
SBL Stage2: Total time taken | 82.527 |
- The emmc driver initialization is done as part of Drivers_open.
- The time taken for Sciclient Get Version can be avoided if the version check is disabled
- Out of the ~39 ms taken for System Init is mostly attributed to DDR initialization.
IPC performance
IPC NOTIFY
- 10000 messages are sent and average one way message latency is measured
Local Core | Remote Core | Average Message Latency (us) |
r5f0-0 | mcu-r5f0-0 | 1.22 |
r5f0-0 | a530-0 | 6.79 |
r5f0-0 | c75ss0 | 15.56 |
IPC RPMSG
- 1000 messages are sent and average one way message latency is measured
Local Core | Remote Core | Message Size | Average Message Latency (us) | Max Latency (us) | Message Count |
r5f0-0 | a530-0 | 4 | 7.105 | 10 | 1000 |
r5f0-0 | a530-0 | 32 | 9.702 | 13 | 1000 |
r5f0-0 | a530-0 | 64 | 12.795 | 17 | 1000 |
r5f0-0 | a530-0 | 112 | 17.505 | 22 | 1000 |
r5f0-0 | mcu-r5f0-0 | 4 | 9.002 | 12 | 1000 |
r5f0-0 | mcu-r5f0-0 | 32 | 14.783 | 17 | 1000 |
r5f0-0 | mcu-r5f0-0 | 64 | 21.340 | 24 | 1000 |
r5f0-0 | mcu-r5f0-0 | 112 | 31.204 | 38 | 1000 |
r5f0-0 | c75ss0 | 32 | 79.382 | 93 | 1000 |
r5f0-0 | c75ss0 | 32 | 88.238 | 102 | 1000 |
r5f0-0 | c75ss0 | 64 | 101.240 | 125 | 1000 |
r5f0-0 | c75ss0 | 112 | 111.027 | 126 | 1000 |
EMMC Performance
r5f0-0:
Mode | Data size(MiB) | Write speed(MiBps) | Read speed(MiBps) |
SDR50 | 1 | 37.59 | 45.15 |
SDR50 | 4 | 40.36 | 44.48 |
SDR50 | 6 | 42.69 | 44.93 |
DDR50 | 1 | 53.27 | 82.31 |
DDR50 | 4 | 61.31 | 80.10 |
DDR50 | 6 | 59.49 | 81.50 |
HS200 | 1 | 56.30 | 164.22 |
HS200 | 4 | 62.93 | 155.52 |
HS200 | 6 | 61.54 | 161.17 |
a53ss0-0_freertos:
Mode | Data size(MiB) | Write speed(MiBps) | Read speed(MiBps) |
SDR50 | 1 | 37.38 | 45.96 |
SDR50 | 4 | 42.35 | 46.50 |
SDR50 | 6 | 42.42 | 46.54 |
DDR50 | 1 | 71.59 | 84.90 |
DDR50 | 4 | 54.20 | 86.93 |
DDR50 | 6 | 73.54 | 87.03 |
HS200 | 1 | 98.74 | 171.25 |
HS200 | 4 | 113.31 | 183.62 |
HS200 | 6 | 77.47 | 184.07 |
OSPI NAND Performance
r5f0-0:
- Flash protocol: FLASH_CFG_PROTO_1S_8S_8S
- PHY : enabled
- DMA : enabled
Data size(MiB) | Write speed(MiBps) | Read speed(MiBps) |
1 | 2.33 | 49.77 |
5 | 2.33 | 49.78 |
10 | 2.33 | 49.77 |
Non-DQS Tuning Algorithm | Tuning Time (ms) |
Default Tuning Window | 1.13 ms |
Fast Tuning Window | 0.64 ms |
mcu-r5f0-0:
- Flash protocol: FLASH_CFG_PROTO_1S_8S_8S
- PHY : enabled
- DMA : enabled
Data size(MiB) | Write speed(MiBps) | Read speed(MiBps) |
1 | 2.02 | 49.32 |
5 | 2.02 | 49.33 |
10 | 2.02 | 49.33 |
Non-DQS Tuning Algorithm | Tuning Time (ms) |
Default Tuning Window | 1.30 ms |
Fast Tuning Window | 0.74 ms |
GPIO latency
GPIO latency is measured by connecting 2 GPIOs externaly and configuring one GPIO as input and the other as output. Then 1 is written to GPIO output and measure the time between writing 1 to GPIO output to rececving the interrupt at GPIO input.
Core | GPIO In | GPIO Out | Latency (us) |
mcu-r5f | MCU_GPIO0_15 | MCU_GPIO0_16 | 2 |