Introduction
This example simulates a 1b and 2b ECC error for DDR and waits for interrupt via the MAIN ESM instance. On receiving the interrupt, the handler clears the ECC error bit and restore the original value. If the interrupt is not received the test fails.
Supported Combinations
Parameter | Value |
CPU + OS | mcu-r5fss0-0 freertos |
Toolchain | ti-arm-clang |
Board | am62ax-sk |
Example folder | examples/drivers/ddr/ddr_ecc_test_main_esm/ |
Steps to Run the Example
- Note
- DDR inline ECC can be configured in the sysconfig of other SBLs as well. If you are configuring ECC for different address region, change the DDR_ECC_REGION0_START macro in the example file for testing.
See Also
DDR
Sample Output
Shown below is a sample output when the application is run,
Waiting on Single bit Error Correction Interrupt...
1b ECC error detected
Waiting on Dual bit error detection Interrupt...
2b ECC error detected
All tests have passed!!